2 * Copyright 2021 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
27 #include "dm_services.h"
30 #include "dcn31/dcn31_init.h"
33 #include "include/irq_service_interface.h"
34 #include "dcn316_resource.h"
36 #include "dcn20/dcn20_resource.h"
37 #include "dcn30/dcn30_resource.h"
38 #include "dcn31/dcn31_resource.h"
40 #include "dcn10/dcn10_ipp.h"
41 #include "dcn30/dcn30_hubbub.h"
42 #include "dcn31/dcn31_hubbub.h"
43 #include "dcn30/dcn30_mpc.h"
44 #include "dcn31/dcn31_hubp.h"
45 #include "irq/dcn31/irq_service_dcn31.h"
46 #include "dcn30/dcn30_dpp.h"
47 #include "dcn31/dcn31_optc.h"
48 #include "dcn20/dcn20_hwseq.h"
49 #include "dcn30/dcn30_hwseq.h"
50 #include "dce110/dce110_hw_sequencer.h"
51 #include "dcn30/dcn30_opp.h"
52 #include "dcn20/dcn20_dsc.h"
53 #include "dcn30/dcn30_vpg.h"
54 #include "dcn30/dcn30_afmt.h"
55 #include "dcn30/dcn30_dio_stream_encoder.h"
56 #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
57 #include "dcn31/dcn31_hpo_dp_link_encoder.h"
58 #include "dcn31/dcn31_apg.h"
59 #include "dcn31/dcn31_dio_link_encoder.h"
60 #include "dcn31/dcn31_vpg.h"
61 #include "dcn31/dcn31_afmt.h"
62 #include "dce/dce_clock_source.h"
63 #include "dce/dce_audio.h"
64 #include "dce/dce_hwseq.h"
66 #include "virtual/virtual_stream_encoder.h"
67 #include "dce110/dce110_resource.h"
68 #include "dml/display_mode_vba.h"
69 #include "dml/dcn31/dcn31_fpu.h"
70 #include "dcn31/dcn31_dccg.h"
71 #include "dcn10/dcn10_resource.h"
72 #include "dcn31/dcn31_panel_cntl.h"
74 #include "dcn30/dcn30_dwb.h"
75 #include "dcn30/dcn30_mmhubbub.h"
77 #include "dcn/dcn_3_1_6_offset.h"
78 #include "dcn/dcn_3_1_6_sh_mask.h"
79 #include "dpcs/dpcs_4_2_3_offset.h"
80 #include "dpcs/dpcs_4_2_3_sh_mask.h"
82 #define regBIF_BX1_BIOS_SCRATCH_2 0x003a
83 #define regBIF_BX1_BIOS_SCRATCH_2_BASE_IDX 1
84 #define regBIF_BX1_BIOS_SCRATCH_3 0x003b
85 #define regBIF_BX1_BIOS_SCRATCH_3_BASE_IDX 1
86 #define regBIF_BX1_BIOS_SCRATCH_6 0x003e
87 #define regBIF_BX1_BIOS_SCRATCH_6_BASE_IDX 1
89 #define regDCHUBBUB_DEBUG_CTRL_0 0x04d6
90 #define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX 2
91 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT 0x10
92 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK 0x01FF0000L
94 #define DCN_BASE__INST0_SEG0 0x00000012
95 #define DCN_BASE__INST0_SEG1 0x000000C0
96 #define DCN_BASE__INST0_SEG2 0x000034C0
97 #define DCN_BASE__INST0_SEG3 0x00009000
98 #define DCN_BASE__INST0_SEG4 0x02403C00
99 #define DCN_BASE__INST0_SEG5 0
101 #define DPCS_BASE__INST0_SEG0 0x00000012
102 #define DPCS_BASE__INST0_SEG1 0x000000C0
103 #define DPCS_BASE__INST0_SEG2 0x000034C0
104 #define DPCS_BASE__INST0_SEG3 0x00009000
105 #define DPCS_BASE__INST0_SEG4 0x02403C00
106 #define DPCS_BASE__INST0_SEG5 0
108 #define NBIO_BASE__INST0_SEG0 0x00000000
109 #define NBIO_BASE__INST0_SEG1 0x00000014
110 #define NBIO_BASE__INST0_SEG2 0x00000D20
111 #define NBIO_BASE__INST0_SEG3 0x00010400
112 #define NBIO_BASE__INST0_SEG4 0x0241B000
113 #define NBIO_BASE__INST0_SEG5 0x04040000
115 #include "reg_helper.h"
116 #include "dce/dmub_abm.h"
117 #include "dce/dmub_psr.h"
118 #include "dce/dce_aux.h"
119 #include "dce/dce_i2c.h"
121 #include "dml/dcn30/display_mode_vba_30.h"
122 #include "vm_helper.h"
123 #include "dcn20/dcn20_vmid.h"
125 #include "link_enc_cfg.h"
127 #define DCN3_16_MAX_DET_SIZE 384
128 #define DCN3_16_MIN_COMPBUF_SIZE_KB 128
129 #define DCN3_16_CRB_SEGMENT_SIZE_KB 64
131 enum dcn31_clk_src_array_id {
140 /* begin *********************
141 * macros to expend register list macro defined in HW object header file
145 /* TODO awful hack. fixup dcn20_dwb.h */
147 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
149 #define BASE(seg) BASE_INNER(seg)
151 #define SR(reg_name)\
152 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
155 #define SRI(reg_name, block, id)\
156 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
157 reg ## block ## id ## _ ## reg_name
159 #define SRI2(reg_name, block, id)\
160 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
163 #define SRIR(var_name, reg_name, block, id)\
164 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
165 reg ## block ## id ## _ ## reg_name
167 #define SRII(reg_name, block, id)\
168 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
169 reg ## block ## id ## _ ## reg_name
171 #define SRII_MPC_RMU(reg_name, block, id)\
172 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
173 reg ## block ## id ## _ ## reg_name
175 #define SRII_DWB(reg_name, temp_name, block, id)\
176 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
177 reg ## block ## id ## _ ## temp_name
179 #define DCCG_SRII(reg_name, block, id)\
180 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
181 reg ## block ## id ## _ ## reg_name
183 #define VUPDATE_SRII(reg_name, block, id)\
184 .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
185 reg ## reg_name ## _ ## block ## id
188 #define NBIO_BASE_INNER(seg) \
189 NBIO_BASE__INST0_SEG ## seg
191 #define NBIO_BASE(seg) \
194 #define NBIO_SR(reg_name)\
195 .reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \
196 regBIF_BX1_ ## reg_name
198 static const struct bios_registers bios_regs = {
199 NBIO_SR(BIOS_SCRATCH_3),
200 NBIO_SR(BIOS_SCRATCH_6)
203 #define clk_src_regs(index, pllid)\
205 CS_COMMON_REG_LIST_DCN3_0(index, pllid),\
208 static const struct dce110_clk_src_regs clk_src_regs[] = {
216 static const struct dce110_clk_src_shift cs_shift = {
217 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
220 static const struct dce110_clk_src_mask cs_mask = {
221 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
224 #define abm_regs(id)\
226 ABM_DCN302_REG_LIST(id)\
229 static const struct dce_abm_registers abm_regs[] = {
236 static const struct dce_abm_shift abm_shift = {
237 ABM_MASK_SH_LIST_DCN30(__SHIFT)
240 static const struct dce_abm_mask abm_mask = {
241 ABM_MASK_SH_LIST_DCN30(_MASK)
244 #define audio_regs(id)\
246 AUD_COMMON_REG_LIST(id)\
249 static const struct dce_audio_registers audio_regs[] = {
259 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
260 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
261 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
262 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
264 static const struct dce_audio_shift audio_shift = {
265 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
268 static const struct dce_audio_mask audio_mask = {
269 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
272 #define vpg_regs(id)\
274 VPG_DCN31_REG_LIST(id)\
277 static const struct dcn31_vpg_registers vpg_regs[] = {
290 static const struct dcn31_vpg_shift vpg_shift = {
291 DCN31_VPG_MASK_SH_LIST(__SHIFT)
294 static const struct dcn31_vpg_mask vpg_mask = {
295 DCN31_VPG_MASK_SH_LIST(_MASK)
298 #define afmt_regs(id)\
300 AFMT_DCN31_REG_LIST(id)\
303 static const struct dcn31_afmt_registers afmt_regs[] = {
312 static const struct dcn31_afmt_shift afmt_shift = {
313 DCN31_AFMT_MASK_SH_LIST(__SHIFT)
316 static const struct dcn31_afmt_mask afmt_mask = {
317 DCN31_AFMT_MASK_SH_LIST(_MASK)
321 #define apg_regs(id)\
323 APG_DCN31_REG_LIST(id)\
326 static const struct dcn31_apg_registers apg_regs[] = {
333 static const struct dcn31_apg_shift apg_shift = {
334 DCN31_APG_MASK_SH_LIST(__SHIFT)
337 static const struct dcn31_apg_mask apg_mask = {
338 DCN31_APG_MASK_SH_LIST(_MASK)
342 #define stream_enc_regs(id)\
344 SE_DCN3_REG_LIST(id)\
347 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
355 static const struct dcn10_stream_encoder_shift se_shift = {
356 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
359 static const struct dcn10_stream_encoder_mask se_mask = {
360 SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
364 #define aux_regs(id)\
366 DCN2_AUX_REG_LIST(id)\
369 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
377 #define hpd_regs(id)\
382 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
390 #define link_regs(id, phyid)\
392 LE_DCN31_REG_LIST(id), \
393 UNIPHY_DCN2_REG_LIST(phyid), \
394 DPCS_DCN31_REG_LIST(id), \
397 static const struct dce110_aux_registers_shift aux_shift = {
398 DCN_AUX_MASK_SH_LIST(__SHIFT)
401 static const struct dce110_aux_registers_mask aux_mask = {
402 DCN_AUX_MASK_SH_LIST(_MASK)
405 static const struct dcn10_link_enc_registers link_enc_regs[] = {
413 static const struct dcn10_link_enc_shift le_shift = {
414 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \
415 DPCS_DCN31_MASK_SH_LIST(__SHIFT)
418 static const struct dcn10_link_enc_mask le_mask = {
419 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \
420 DPCS_DCN31_MASK_SH_LIST(_MASK)
425 #define hpo_dp_stream_encoder_reg_list(id)\
427 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\
430 static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = {
431 hpo_dp_stream_encoder_reg_list(0),
432 hpo_dp_stream_encoder_reg_list(1),
433 hpo_dp_stream_encoder_reg_list(2),
434 hpo_dp_stream_encoder_reg_list(3),
437 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
438 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
441 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
442 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
446 #define hpo_dp_link_encoder_reg_list(id)\
448 DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\
449 DCN3_1_RDPCSTX_REG_LIST(0),\
450 DCN3_1_RDPCSTX_REG_LIST(1),\
451 DCN3_1_RDPCSTX_REG_LIST(2),\
452 DCN3_1_RDPCSTX_REG_LIST(3),\
453 DCN3_1_RDPCSTX_REG_LIST(4)\
456 static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = {
457 hpo_dp_link_encoder_reg_list(0),
458 hpo_dp_link_encoder_reg_list(1),
461 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
462 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)
465 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
466 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)
470 #define dpp_regs(id)\
472 DPP_REG_LIST_DCN30(id),\
475 static const struct dcn3_dpp_registers dpp_regs[] = {
482 static const struct dcn3_dpp_shift tf_shift = {
483 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
486 static const struct dcn3_dpp_mask tf_mask = {
487 DPP_REG_LIST_SH_MASK_DCN30(_MASK)
490 #define opp_regs(id)\
492 OPP_REG_LIST_DCN30(id),\
495 static const struct dcn20_opp_registers opp_regs[] = {
502 static const struct dcn20_opp_shift opp_shift = {
503 OPP_MASK_SH_LIST_DCN20(__SHIFT)
506 static const struct dcn20_opp_mask opp_mask = {
507 OPP_MASK_SH_LIST_DCN20(_MASK)
510 #define aux_engine_regs(id)\
512 AUX_COMMON_REG_LIST0(id), \
515 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
518 static const struct dce110_aux_registers aux_engine_regs[] = {
526 #define dwbc_regs_dcn3(id)\
528 DWBC_COMMON_REG_LIST_DCN30(id),\
531 static const struct dcn30_dwbc_registers dwbc30_regs[] = {
535 static const struct dcn30_dwbc_shift dwbc30_shift = {
536 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
539 static const struct dcn30_dwbc_mask dwbc30_mask = {
540 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
543 #define mcif_wb_regs_dcn3(id)\
545 MCIF_WB_COMMON_REG_LIST_DCN30(id),\
548 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
552 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
553 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
556 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
557 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
560 #define dsc_regsDCN20(id)\
562 DSC_REG_LIST_DCN20(id)\
565 static const struct dcn20_dsc_registers dsc_regs[] = {
571 static const struct dcn20_dsc_shift dsc_shift = {
572 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
575 static const struct dcn20_dsc_mask dsc_mask = {
576 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
579 static const struct dcn30_mpc_registers mpc_regs = {
580 MPC_REG_LIST_DCN3_0(0),
581 MPC_REG_LIST_DCN3_0(1),
582 MPC_REG_LIST_DCN3_0(2),
583 MPC_REG_LIST_DCN3_0(3),
584 MPC_OUT_MUX_REG_LIST_DCN3_0(0),
585 MPC_OUT_MUX_REG_LIST_DCN3_0(1),
586 MPC_OUT_MUX_REG_LIST_DCN3_0(2),
587 MPC_OUT_MUX_REG_LIST_DCN3_0(3),
588 MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
589 MPC_RMU_REG_LIST_DCN3AG(0),
590 MPC_RMU_REG_LIST_DCN3AG(1),
591 //MPC_RMU_REG_LIST_DCN3AG(2),
592 MPC_DWB_MUX_REG_LIST_DCN3_0(0),
595 static const struct dcn30_mpc_shift mpc_shift = {
596 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
599 static const struct dcn30_mpc_mask mpc_mask = {
600 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
603 #define optc_regs(id)\
604 [id] = {OPTC_COMMON_REG_LIST_DCN3_1(id)}
606 static const struct dcn_optc_registers optc_regs[] = {
613 static const struct dcn_optc_shift optc_shift = {
614 OPTC_COMMON_MASK_SH_LIST_DCN3_1(__SHIFT)
617 static const struct dcn_optc_mask optc_mask = {
618 OPTC_COMMON_MASK_SH_LIST_DCN3_1(_MASK)
621 #define hubp_regs(id)\
623 HUBP_REG_LIST_DCN30(id)\
626 static const struct dcn_hubp2_registers hubp_regs[] = {
634 static const struct dcn_hubp2_shift hubp_shift = {
635 HUBP_MASK_SH_LIST_DCN31(__SHIFT)
638 static const struct dcn_hubp2_mask hubp_mask = {
639 HUBP_MASK_SH_LIST_DCN31(_MASK)
641 static const struct dcn_hubbub_registers hubbub_reg = {
642 HUBBUB_REG_LIST_DCN31(0)
645 static const struct dcn_hubbub_shift hubbub_shift = {
646 HUBBUB_MASK_SH_LIST_DCN31(__SHIFT)
649 static const struct dcn_hubbub_mask hubbub_mask = {
650 HUBBUB_MASK_SH_LIST_DCN31(_MASK)
653 static const struct dccg_registers dccg_regs = {
654 DCCG_REG_LIST_DCN31()
657 static const struct dccg_shift dccg_shift = {
658 DCCG_MASK_SH_LIST_DCN31(__SHIFT)
661 static const struct dccg_mask dccg_mask = {
662 DCCG_MASK_SH_LIST_DCN31(_MASK)
666 #define SRII2(reg_name_pre, reg_name_post, id)\
667 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \
668 ## id ## _ ## reg_name_post ## _BASE_IDX) + \
669 reg ## reg_name_pre ## id ## _ ## reg_name_post
672 #define HWSEQ_DCN31_REG_LIST()\
673 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
674 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
675 SR(DIO_MEM_PWR_CTRL), \
676 SR(ODM_MEM_PWR_CTRL3), \
677 SR(DMU_MEM_PWR_CNTL), \
678 SR(MMHUBBUB_MEM_PWR_CNTL), \
679 SR(DCCG_GATE_DISABLE_CNTL), \
680 SR(DCCG_GATE_DISABLE_CNTL2), \
682 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
683 SRII(PIXEL_RATE_CNTL, OTG, 0), \
684 SRII(PIXEL_RATE_CNTL, OTG, 1),\
685 SRII(PIXEL_RATE_CNTL, OTG, 2),\
686 SRII(PIXEL_RATE_CNTL, OTG, 3),\
687 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
688 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
689 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
690 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
691 SR(MICROSECOND_TIME_BASE_DIV), \
692 SR(MILLISECOND_TIME_BASE_DIV), \
693 SR(DISPCLK_FREQ_CHANGE_CNTL), \
694 SR(RBBMIF_TIMEOUT_DIS), \
695 SR(RBBMIF_TIMEOUT_DIS_2), \
696 SR(DCHUBBUB_CRC_CTRL), \
697 SR(DPP_TOP0_DPP_CRC_CTRL), \
698 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
699 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
701 SR(MPC_CRC_RESULT_GB), \
702 SR(MPC_CRC_RESULT_C), \
703 SR(MPC_CRC_RESULT_AR), \
704 SR(DOMAIN0_PG_CONFIG), \
705 SR(DOMAIN1_PG_CONFIG), \
706 SR(DOMAIN2_PG_CONFIG), \
707 SR(DOMAIN3_PG_CONFIG), \
708 SR(DOMAIN16_PG_CONFIG), \
709 SR(DOMAIN17_PG_CONFIG), \
710 SR(DOMAIN18_PG_CONFIG), \
711 SR(DOMAIN0_PG_STATUS), \
712 SR(DOMAIN1_PG_STATUS), \
713 SR(DOMAIN2_PG_STATUS), \
714 SR(DOMAIN3_PG_STATUS), \
715 SR(DOMAIN16_PG_STATUS), \
716 SR(DOMAIN17_PG_STATUS), \
717 SR(DOMAIN18_PG_STATUS), \
724 SR(DC_IP_REQUEST_CNTL), \
725 SR(AZALIA_AUDIO_DTO), \
726 SR(AZALIA_CONTROLLER_CLOCK_GATING), \
727 SR(HPO_TOP_HW_CONTROL)
729 static const struct dce_hwseq_registers hwseq_reg = {
730 HWSEQ_DCN31_REG_LIST()
733 #define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\
734 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
735 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
736 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \
737 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
738 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
739 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
740 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
741 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
742 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
743 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
744 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
745 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
746 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
747 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
748 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
749 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
750 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
751 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
752 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
753 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
754 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
755 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
756 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
757 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
758 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
759 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
760 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
761 HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \
762 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
763 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
764 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \
765 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \
766 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh)
768 static const struct dce_hwseq_shift hwseq_shift = {
769 HWSEQ_DCN31_MASK_SH_LIST(__SHIFT)
772 static const struct dce_hwseq_mask hwseq_mask = {
773 HWSEQ_DCN31_MASK_SH_LIST(_MASK)
775 #define vmid_regs(id)\
777 DCN20_VMID_REG_LIST(id)\
780 static const struct dcn_vmid_registers vmid_regs[] = {
799 static const struct dcn20_vmid_shift vmid_shifts = {
800 DCN20_VMID_MASK_SH_LIST(__SHIFT)
803 static const struct dcn20_vmid_mask vmid_masks = {
804 DCN20_VMID_MASK_SH_LIST(_MASK)
807 static const struct resource_caps res_cap_dcn31 = {
808 .num_timing_generator = 4,
810 .num_video_plane = 4,
812 .num_stream_encoder = 5,
813 .num_dig_link_enc = 5,
814 .num_hpo_dp_stream_encoder = 4,
815 .num_hpo_dp_link_encoder = 2,
824 static const struct dc_plane_cap plane_cap = {
825 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
826 .blends_with_above = true,
827 .blends_with_below = true,
828 .per_pixel_alpha = true,
830 .pixel_format_support = {
838 .max_upscale_factor = {
844 // 6:1 downscaling ratio: 1000/6 = 166.666
845 .max_downscale_factor = {
854 static const struct dc_debug_options debug_defaults_drv = {
855 .disable_z10 = true, /*hw not support it*/
856 .disable_dmcu = true,
857 .force_abm_enable = false,
858 .timing_trace = false,
860 .disable_pplib_clock_request = false,
861 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
862 .force_single_disp_pipe_split = false,
863 .disable_dcc = DCC_ENABLE,
865 .performance_trace = false,
866 .max_downscale_src_width = 4096,/*upto true 4k*/
867 .disable_pplib_wm_range = false,
868 .scl_reset_length10 = true,
869 .sanity_checks = false,
870 .underflow_assert_delay_us = 0xFFFFFFFF,
871 .dwb_fi_phase = -1, // -1 = disable,
872 .dmub_command_table = true,
873 .pstate_enabled = true,
875 .enable_mem_low_power = {
879 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
890 static const struct dc_debug_options debug_defaults_diags = {
891 .disable_dmcu = true,
892 .force_abm_enable = false,
893 .timing_trace = true,
895 .disable_dpp_power_gate = true,
896 .disable_hubp_power_gate = true,
897 .disable_clock_gate = true,
898 .disable_pplib_clock_request = true,
899 .disable_pplib_wm_range = true,
900 .disable_stutter = false,
901 .scl_reset_length10 = true,
902 .dwb_fi_phase = -1, // -1 = disable
903 .dmub_command_table = true,
904 .enable_tri_buf = true,
908 static const struct dc_panel_config panel_config_defaults = {
910 .disable_psr = false,
911 .disallow_psrsu = false,
914 .optimize_edp_link_rate = true,
918 static void dcn31_dpp_destroy(struct dpp **dpp)
920 kfree(TO_DCN20_DPP(*dpp));
924 static struct dpp *dcn31_dpp_create(
925 struct dc_context *ctx,
928 struct dcn3_dpp *dpp =
929 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
934 if (dpp3_construct(dpp, ctx, inst,
935 &dpp_regs[inst], &tf_shift, &tf_mask))
943 static struct output_pixel_processor *dcn31_opp_create(
944 struct dc_context *ctx, uint32_t inst)
946 struct dcn20_opp *opp =
947 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
954 dcn20_opp_construct(opp, ctx, inst,
955 &opp_regs[inst], &opp_shift, &opp_mask);
959 static struct dce_aux *dcn31_aux_engine_create(
960 struct dc_context *ctx,
963 struct aux_engine_dce110 *aux_engine =
964 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
969 dce110_aux_engine_construct(aux_engine, ctx, inst,
970 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
971 &aux_engine_regs[inst],
974 ctx->dc->caps.extended_aux_timeout_support);
976 return &aux_engine->base;
978 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
980 static const struct dce_i2c_registers i2c_hw_regs[] = {
988 static const struct dce_i2c_shift i2c_shifts = {
989 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
992 static const struct dce_i2c_mask i2c_masks = {
993 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
996 static struct dce_i2c_hw *dcn31_i2c_hw_create(
997 struct dc_context *ctx,
1000 struct dce_i2c_hw *dce_i2c_hw =
1001 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
1006 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
1007 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
1011 static struct mpc *dcn31_mpc_create(
1012 struct dc_context *ctx,
1016 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
1022 dcn30_mpc_construct(mpc30, ctx,
1029 return &mpc30->base;
1032 static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx)
1036 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
1042 hubbub31_construct(hubbub3, ctx,
1046 dcn3_16_ip.det_buffer_size_kbytes,
1047 dcn3_16_ip.pixel_chunk_size_kbytes,
1048 dcn3_16_ip.config_return_buffer_size_in_kbytes);
1051 for (i = 0; i < res_cap_dcn31.num_vmid; i++) {
1052 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
1056 vmid->regs = &vmid_regs[i];
1057 vmid->shifts = &vmid_shifts;
1058 vmid->masks = &vmid_masks;
1061 return &hubbub3->base;
1064 static struct timing_generator *dcn31_timing_generator_create(
1065 struct dc_context *ctx,
1068 struct optc *tgn10 =
1069 kzalloc(sizeof(struct optc), GFP_KERNEL);
1074 tgn10->base.inst = instance;
1075 tgn10->base.ctx = ctx;
1077 tgn10->tg_regs = &optc_regs[instance];
1078 tgn10->tg_shift = &optc_shift;
1079 tgn10->tg_mask = &optc_mask;
1081 dcn31_timing_generator_init(tgn10);
1083 return &tgn10->base;
1086 static const struct encoder_feature_support link_enc_feature = {
1087 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1088 .max_hdmi_pixel_clock = 600000,
1089 .hdmi_ycbcr420_supported = true,
1090 .dp_ycbcr420_supported = true,
1091 .fec_supported = true,
1092 .flags.bits.IS_HBR2_CAPABLE = true,
1093 .flags.bits.IS_HBR3_CAPABLE = true,
1094 .flags.bits.IS_TPS3_CAPABLE = true,
1095 .flags.bits.IS_TPS4_CAPABLE = true
1098 static struct link_encoder *dcn31_link_encoder_create(
1099 struct dc_context *ctx,
1100 const struct encoder_init_data *enc_init_data)
1102 struct dcn20_link_encoder *enc20 =
1103 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1108 dcn31_link_encoder_construct(enc20,
1111 &link_enc_regs[enc_init_data->transmitter],
1112 &link_enc_aux_regs[enc_init_data->channel - 1],
1113 &link_enc_hpd_regs[enc_init_data->hpd_source],
1117 return &enc20->enc10.base;
1120 /* Create a minimal link encoder object not associated with a particular
1121 * physical connector.
1122 * resource_funcs.link_enc_create_minimal
1124 static struct link_encoder *dcn31_link_enc_create_minimal(
1125 struct dc_context *ctx, enum engine_id eng_id)
1127 struct dcn20_link_encoder *enc20;
1129 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
1132 enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1136 dcn31_link_encoder_construct_minimal(
1140 &link_enc_regs[eng_id - ENGINE_ID_DIGA],
1143 return &enc20->enc10.base;
1146 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1148 struct dcn31_panel_cntl *panel_cntl =
1149 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL);
1154 dcn31_panel_cntl_construct(panel_cntl, init_data);
1156 return &panel_cntl->base;
1159 static void read_dce_straps(
1160 struct dc_context *ctx,
1161 struct resource_straps *straps)
1163 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
1164 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1168 static struct audio *dcn31_create_audio(
1169 struct dc_context *ctx, unsigned int inst)
1171 return dce_audio_create(ctx, inst,
1172 &audio_regs[inst], &audio_shift, &audio_mask);
1175 static struct vpg *dcn31_vpg_create(
1176 struct dc_context *ctx,
1179 struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL);
1184 vpg31_construct(vpg31, ctx, inst,
1189 return &vpg31->base;
1192 static struct afmt *dcn31_afmt_create(
1193 struct dc_context *ctx,
1196 struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL);
1201 afmt31_construct(afmt31, ctx, inst,
1206 // Light sleep by default, no need to power down here
1208 return &afmt31->base;
1212 static struct apg *dcn31_apg_create(
1213 struct dc_context *ctx,
1216 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL);
1221 apg31_construct(apg31, ctx, inst,
1226 return &apg31->base;
1230 static struct stream_encoder *dcn316_stream_encoder_create(
1231 enum engine_id eng_id,
1232 struct dc_context *ctx)
1234 struct dcn10_stream_encoder *enc1;
1240 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1241 if (eng_id <= ENGINE_ID_DIGF) {
1247 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1248 vpg = dcn31_vpg_create(ctx, vpg_inst);
1249 afmt = dcn31_afmt_create(ctx, afmt_inst);
1251 if (!enc1 || !vpg || !afmt) {
1258 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1260 &stream_enc_regs[eng_id],
1261 &se_shift, &se_mask);
1267 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create(
1268 enum engine_id eng_id,
1269 struct dc_context *ctx)
1271 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1274 uint32_t hpo_dp_inst;
1278 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1279 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1281 /* Mapping of VPG register blocks to HPO DP block instance:
1282 * VPG[6] -> HPO_DP[0]
1283 * VPG[7] -> HPO_DP[1]
1284 * VPG[8] -> HPO_DP[2]
1285 * VPG[9] -> HPO_DP[3]
1287 vpg_inst = hpo_dp_inst + 6;
1289 /* Mapping of APG register blocks to HPO DP block instance:
1290 * APG[0] -> HPO_DP[0]
1291 * APG[1] -> HPO_DP[1]
1292 * APG[2] -> HPO_DP[2]
1293 * APG[3] -> HPO_DP[3]
1295 apg_inst = hpo_dp_inst;
1297 /* allocate HPO stream encoder and create VPG sub-block */
1298 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);
1299 vpg = dcn31_vpg_create(ctx, vpg_inst);
1300 apg = dcn31_apg_create(ctx, apg_inst);
1302 if (!hpo_dp_enc31 || !vpg || !apg) {
1303 kfree(hpo_dp_enc31);
1309 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1310 hpo_dp_inst, eng_id, vpg, apg,
1311 &hpo_dp_stream_enc_regs[hpo_dp_inst],
1312 &hpo_dp_se_shift, &hpo_dp_se_mask);
1314 return &hpo_dp_enc31->base;
1317 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create(
1319 struct dc_context *ctx)
1321 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1323 /* allocate HPO link encoder */
1324 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);
1326 hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,
1327 &hpo_dp_link_enc_regs[inst],
1328 &hpo_dp_le_shift, &hpo_dp_le_mask);
1330 return &hpo_dp_enc31->base;
1334 static struct dce_hwseq *dcn31_hwseq_create(
1335 struct dc_context *ctx)
1337 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1341 hws->regs = &hwseq_reg;
1342 hws->shifts = &hwseq_shift;
1343 hws->masks = &hwseq_mask;
1344 /* DCN3.1 FPGA Workaround
1345 * Need to enable HPO DP Stream Encoder before setting OTG master enable.
1346 * To do so, move calling function enable_stream_timing to only be done AFTER calling
1347 * function core_link_enable_stream
1349 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
1350 hws->wa.dp_hpo_and_otg_sequence = true;
1354 static const struct resource_create_funcs res_create_funcs = {
1355 .read_dce_straps = read_dce_straps,
1356 .create_audio = dcn31_create_audio,
1357 .create_stream_encoder = dcn316_stream_encoder_create,
1358 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
1359 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
1360 .create_hwseq = dcn31_hwseq_create,
1363 static const struct resource_create_funcs res_create_maximus_funcs = {
1364 .read_dce_straps = NULL,
1365 .create_audio = NULL,
1366 .create_stream_encoder = NULL,
1367 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
1368 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
1369 .create_hwseq = dcn31_hwseq_create,
1372 static void dcn316_resource_destruct(struct dcn316_resource_pool *pool)
1376 for (i = 0; i < pool->base.stream_enc_count; i++) {
1377 if (pool->base.stream_enc[i] != NULL) {
1378 if (pool->base.stream_enc[i]->vpg != NULL) {
1379 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1380 pool->base.stream_enc[i]->vpg = NULL;
1382 if (pool->base.stream_enc[i]->afmt != NULL) {
1383 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1384 pool->base.stream_enc[i]->afmt = NULL;
1386 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1387 pool->base.stream_enc[i] = NULL;
1391 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1392 if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1393 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1394 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1395 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1397 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1398 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1399 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1401 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1402 pool->base.hpo_dp_stream_enc[i] = NULL;
1406 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1407 if (pool->base.hpo_dp_link_enc[i] != NULL) {
1408 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1409 pool->base.hpo_dp_link_enc[i] = NULL;
1413 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1414 if (pool->base.dscs[i] != NULL)
1415 dcn20_dsc_destroy(&pool->base.dscs[i]);
1418 if (pool->base.mpc != NULL) {
1419 kfree(TO_DCN20_MPC(pool->base.mpc));
1420 pool->base.mpc = NULL;
1422 if (pool->base.hubbub != NULL) {
1423 kfree(pool->base.hubbub);
1424 pool->base.hubbub = NULL;
1426 for (i = 0; i < pool->base.pipe_count; i++) {
1427 if (pool->base.dpps[i] != NULL)
1428 dcn31_dpp_destroy(&pool->base.dpps[i]);
1430 if (pool->base.ipps[i] != NULL)
1431 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1433 if (pool->base.hubps[i] != NULL) {
1434 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1435 pool->base.hubps[i] = NULL;
1438 if (pool->base.irqs != NULL) {
1439 dal_irq_service_destroy(&pool->base.irqs);
1443 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1444 if (pool->base.engines[i] != NULL)
1445 dce110_engine_destroy(&pool->base.engines[i]);
1446 if (pool->base.hw_i2cs[i] != NULL) {
1447 kfree(pool->base.hw_i2cs[i]);
1448 pool->base.hw_i2cs[i] = NULL;
1450 if (pool->base.sw_i2cs[i] != NULL) {
1451 kfree(pool->base.sw_i2cs[i]);
1452 pool->base.sw_i2cs[i] = NULL;
1456 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1457 if (pool->base.opps[i] != NULL)
1458 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1461 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1462 if (pool->base.timing_generators[i] != NULL) {
1463 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1464 pool->base.timing_generators[i] = NULL;
1468 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1469 if (pool->base.dwbc[i] != NULL) {
1470 kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1471 pool->base.dwbc[i] = NULL;
1473 if (pool->base.mcif_wb[i] != NULL) {
1474 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1475 pool->base.mcif_wb[i] = NULL;
1479 for (i = 0; i < pool->base.audio_count; i++) {
1480 if (pool->base.audios[i])
1481 dce_aud_destroy(&pool->base.audios[i]);
1484 for (i = 0; i < pool->base.clk_src_count; i++) {
1485 if (pool->base.clock_sources[i] != NULL) {
1486 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1487 pool->base.clock_sources[i] = NULL;
1491 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1492 if (pool->base.mpc_lut[i] != NULL) {
1493 dc_3dlut_func_release(pool->base.mpc_lut[i]);
1494 pool->base.mpc_lut[i] = NULL;
1496 if (pool->base.mpc_shaper[i] != NULL) {
1497 dc_transfer_func_release(pool->base.mpc_shaper[i]);
1498 pool->base.mpc_shaper[i] = NULL;
1502 if (pool->base.dp_clock_source != NULL) {
1503 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1504 pool->base.dp_clock_source = NULL;
1507 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1508 if (pool->base.multiple_abms[i] != NULL)
1509 dce_abm_destroy(&pool->base.multiple_abms[i]);
1512 if (pool->base.psr != NULL)
1513 dmub_psr_destroy(&pool->base.psr);
1515 if (pool->base.dccg != NULL)
1516 dcn_dccg_destroy(&pool->base.dccg);
1519 static struct hubp *dcn31_hubp_create(
1520 struct dc_context *ctx,
1523 struct dcn20_hubp *hubp2 =
1524 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1529 if (hubp31_construct(hubp2, ctx, inst,
1530 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1531 return &hubp2->base;
1533 BREAK_TO_DEBUGGER();
1538 static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1541 uint32_t pipe_count = pool->res_cap->num_dwb;
1543 for (i = 0; i < pipe_count; i++) {
1544 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1548 dm_error("DC: failed to create dwbc30!\n");
1552 dcn30_dwbc_construct(dwbc30, ctx,
1558 pool->dwbc[i] = &dwbc30->base;
1563 static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1566 uint32_t pipe_count = pool->res_cap->num_dwb;
1568 for (i = 0; i < pipe_count; i++) {
1569 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1573 dm_error("DC: failed to create mcif_wb30!\n");
1577 dcn30_mmhubbub_construct(mcif_wb30, ctx,
1583 pool->mcif_wb[i] = &mcif_wb30->base;
1588 static struct display_stream_compressor *dcn31_dsc_create(
1589 struct dc_context *ctx, uint32_t inst)
1591 struct dcn20_dsc *dsc =
1592 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1595 BREAK_TO_DEBUGGER();
1599 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1603 static void dcn316_destroy_resource_pool(struct resource_pool **pool)
1605 struct dcn316_resource_pool *dcn31_pool = TO_DCN316_RES_POOL(*pool);
1607 dcn316_resource_destruct(dcn31_pool);
1612 static struct clock_source *dcn31_clock_source_create(
1613 struct dc_context *ctx,
1614 struct dc_bios *bios,
1615 enum clock_source_id id,
1616 const struct dce110_clk_src_regs *regs,
1619 struct dce110_clk_src *clk_src =
1620 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1625 if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
1626 regs, &cs_shift, &cs_mask)) {
1627 clk_src->base.dp_clk_src = dp_clk_src;
1628 return &clk_src->base;
1633 BREAK_TO_DEBUGGER();
1637 static bool is_dual_plane(enum surface_pixel_format format)
1639 return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA;
1642 static int dcn316_populate_dml_pipes_from_context(
1643 struct dc *dc, struct dc_state *context,
1644 display_e2e_pipe_params_st *pipes,
1648 struct resource_context *res_ctx = &context->res_ctx;
1649 struct pipe_ctx *pipe;
1650 const int max_usable_det = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes - DCN3_16_MIN_COMPBUF_SIZE_KB;
1653 dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
1656 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1657 struct dc_crtc_timing *timing;
1659 if (!res_ctx->pipe_ctx[i].stream)
1661 pipe = &res_ctx->pipe_ctx[i];
1662 timing = &pipe->stream->timing;
1665 * Immediate flip can be set dynamically after enabling the plane.
1666 * We need to require support for immediate flip or underflow can be
1667 * intermittently experienced depending on peak b/w requirements.
1669 pipes[pipe_cnt].pipe.src.immediate_flip = true;
1671 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
1672 pipes[pipe_cnt].pipe.src.gpuvm = true;
1673 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;
1674 pipes[pipe_cnt].pipe.src.dcc_rate = 3;
1675 pipes[pipe_cnt].dout.dsc_input_bpc = 0;
1677 dcn31_zero_pipe_dcc_fraction(pipes, pipe_cnt);
1680 if (pipes[pipe_cnt].dout.dsc_enable) {
1681 switch (timing->display_color_depth) {
1682 case COLOR_DEPTH_888:
1683 pipes[pipe_cnt].dout.dsc_input_bpc = 8;
1685 case COLOR_DEPTH_101010:
1686 pipes[pipe_cnt].dout.dsc_input_bpc = 10;
1688 case COLOR_DEPTH_121212:
1689 pipes[pipe_cnt].dout.dsc_input_bpc = 12;
1701 context->bw_ctx.dml.ip.det_buffer_size_kbytes =
1702 (max_usable_det / DCN3_16_CRB_SEGMENT_SIZE_KB / pipe_cnt) * DCN3_16_CRB_SEGMENT_SIZE_KB;
1703 if (context->bw_ctx.dml.ip.det_buffer_size_kbytes > DCN3_16_MAX_DET_SIZE)
1704 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_16_MAX_DET_SIZE;
1705 ASSERT(context->bw_ctx.dml.ip.det_buffer_size_kbytes >= DCN3_16_DEFAULT_DET_SIZE);
1706 dc->config.enable_4to1MPC = false;
1707 if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {
1708 if (is_dual_plane(pipe->plane_state->format)
1709 && pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) {
1710 dc->config.enable_4to1MPC = true;
1711 context->bw_ctx.dml.ip.det_buffer_size_kbytes =
1712 (max_usable_det / DCN3_16_CRB_SEGMENT_SIZE_KB / 4) * DCN3_16_CRB_SEGMENT_SIZE_KB;
1713 } else if (!is_dual_plane(pipe->plane_state->format)) {
1714 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;
1715 pipes[0].pipe.src.unbounded_req_mode = true;
1722 static void dcn316_get_panel_config_defaults(struct dc_panel_config *panel_config)
1724 *panel_config = panel_config_defaults;
1727 static struct dc_cap_funcs cap_funcs = {
1728 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1731 static struct resource_funcs dcn316_res_pool_funcs = {
1732 .destroy = dcn316_destroy_resource_pool,
1733 .link_enc_create = dcn31_link_encoder_create,
1734 .link_enc_create_minimal = dcn31_link_enc_create_minimal,
1735 .link_encs_assign = link_enc_cfg_link_encs_assign,
1736 .link_enc_unassign = link_enc_cfg_link_enc_unassign,
1737 .panel_cntl_create = dcn31_panel_cntl_create,
1738 .validate_bandwidth = dcn31_validate_bandwidth,
1739 .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg,
1740 .update_soc_for_wm_a = dcn31_update_soc_for_wm_a,
1741 .populate_dml_pipes = dcn316_populate_dml_pipes_from_context,
1742 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
1743 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1744 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1745 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1746 .populate_dml_writeback_from_context = dcn31_populate_dml_writeback_from_context,
1747 .set_mcif_arb_params = dcn31_set_mcif_arb_params,
1748 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1749 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1750 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1751 .update_bw_bounding_box = dcn316_update_bw_bounding_box,
1752 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1753 .get_panel_config_defaults = dcn316_get_panel_config_defaults,
1756 static bool dcn316_resource_construct(
1757 uint8_t num_virtual_links,
1759 struct dcn316_resource_pool *pool)
1762 struct dc_context *ctx = dc->ctx;
1763 struct irq_service_init_data init_data;
1765 ctx->dc_bios->regs = &bios_regs;
1767 pool->base.res_cap = &res_cap_dcn31;
1769 pool->base.funcs = &dcn316_res_pool_funcs;
1771 /*************************************************
1772 * Resource + asic cap harcoding *
1773 *************************************************/
1774 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1775 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1776 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
1777 dc->caps.max_downscale_ratio = 600;
1778 dc->caps.i2c_speed_in_khz = 100;
1779 dc->caps.i2c_speed_in_khz_hdcp = 100;
1780 dc->caps.max_cursor_size = 256;
1781 dc->caps.min_horizontal_blanking_period = 80;
1782 dc->caps.dmdata_alloc_size = 2048;
1783 dc->caps.max_slave_planes = 2;
1784 dc->caps.max_slave_yuv_planes = 2;
1785 dc->caps.max_slave_rgb_planes = 2;
1786 dc->caps.post_blend_color_processing = true;
1787 dc->caps.force_dp_tps4_for_cp2520 = true;
1788 if (dc->config.forceHBR2CP2520)
1789 dc->caps.force_dp_tps4_for_cp2520 = false;
1790 dc->caps.dp_hpo = true;
1791 dc->caps.dp_hdmi21_pcon_support = true;
1792 dc->caps.edp_dsc_support = true;
1793 dc->caps.extended_aux_timeout_support = true;
1794 dc->caps.dmcub_support = true;
1795 dc->caps.is_apu = true;
1797 /* Color pipeline capabilities */
1798 dc->caps.color.dpp.dcn_arch = 1;
1799 dc->caps.color.dpp.input_lut_shared = 0;
1800 dc->caps.color.dpp.icsc = 1;
1801 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1802 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1803 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1804 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1805 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1806 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1807 dc->caps.color.dpp.post_csc = 1;
1808 dc->caps.color.dpp.gamma_corr = 1;
1809 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1811 dc->caps.color.dpp.hw_3d_lut = 1;
1812 dc->caps.color.dpp.ogam_ram = 1;
1813 // no OGAM ROM on DCN301
1814 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1815 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1816 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1817 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1818 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1819 dc->caps.color.dpp.ocsc = 0;
1821 dc->caps.color.mpc.gamut_remap = 1;
1822 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
1823 dc->caps.color.mpc.ogam_ram = 1;
1824 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1825 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1826 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1827 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1828 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1829 dc->caps.color.mpc.ocsc = 1;
1831 /* read VBIOS LTTPR caps */
1833 if (ctx->dc_bios->funcs->get_lttpr_caps) {
1834 enum bp_result bp_query_result;
1835 uint8_t is_vbios_lttpr_enable = 0;
1837 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1838 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1841 /* interop bit is implicit */
1843 dc->caps.vbios_lttpr_aware = true;
1847 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1848 dc->debug = debug_defaults_drv;
1849 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
1850 dc->debug = debug_defaults_diags;
1852 dc->debug = debug_defaults_diags;
1853 // Init the vm_helper
1855 vm_helper_init(dc->vm_helper, 16);
1857 /*************************************************
1858 * Create resources *
1859 *************************************************/
1861 /* Clock Sources for Pixel Clock*/
1862 pool->base.clock_sources[DCN31_CLK_SRC_PLL0] =
1863 dcn31_clock_source_create(ctx, ctx->dc_bios,
1864 CLOCK_SOURCE_COMBO_PHY_PLL0,
1865 &clk_src_regs[0], false);
1866 pool->base.clock_sources[DCN31_CLK_SRC_PLL1] =
1867 dcn31_clock_source_create(ctx, ctx->dc_bios,
1868 CLOCK_SOURCE_COMBO_PHY_PLL1,
1869 &clk_src_regs[1], false);
1870 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =
1871 dcn31_clock_source_create(ctx, ctx->dc_bios,
1872 CLOCK_SOURCE_COMBO_PHY_PLL2,
1873 &clk_src_regs[2], false);
1874 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =
1875 dcn31_clock_source_create(ctx, ctx->dc_bios,
1876 CLOCK_SOURCE_COMBO_PHY_PLL3,
1877 &clk_src_regs[3], false);
1878 pool->base.clock_sources[DCN31_CLK_SRC_PLL4] =
1879 dcn31_clock_source_create(ctx, ctx->dc_bios,
1880 CLOCK_SOURCE_COMBO_PHY_PLL4,
1881 &clk_src_regs[4], false);
1883 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL;
1885 /* todo: not reuse phy_pll registers */
1886 pool->base.dp_clock_source =
1887 dcn31_clock_source_create(ctx, ctx->dc_bios,
1888 CLOCK_SOURCE_ID_DP_DTO,
1889 &clk_src_regs[0], true);
1891 for (i = 0; i < pool->base.clk_src_count; i++) {
1892 if (pool->base.clock_sources[i] == NULL) {
1893 dm_error("DC: failed to create clock sources!\n");
1894 BREAK_TO_DEBUGGER();
1900 pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1901 if (pool->base.dccg == NULL) {
1902 dm_error("DC: failed to create dccg!\n");
1903 BREAK_TO_DEBUGGER();
1908 init_data.ctx = dc->ctx;
1909 pool->base.irqs = dal_irq_service_dcn31_create(&init_data);
1910 if (!pool->base.irqs)
1914 pool->base.hubbub = dcn31_hubbub_create(ctx);
1915 if (pool->base.hubbub == NULL) {
1916 BREAK_TO_DEBUGGER();
1917 dm_error("DC: failed to create hubbub!\n");
1921 /* HUBPs, DPPs, OPPs and TGs */
1922 for (i = 0; i < pool->base.pipe_count; i++) {
1923 pool->base.hubps[i] = dcn31_hubp_create(ctx, i);
1924 if (pool->base.hubps[i] == NULL) {
1925 BREAK_TO_DEBUGGER();
1927 "DC: failed to create hubps!\n");
1931 pool->base.dpps[i] = dcn31_dpp_create(ctx, i);
1932 if (pool->base.dpps[i] == NULL) {
1933 BREAK_TO_DEBUGGER();
1935 "DC: failed to create dpps!\n");
1940 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1941 pool->base.opps[i] = dcn31_opp_create(ctx, i);
1942 if (pool->base.opps[i] == NULL) {
1943 BREAK_TO_DEBUGGER();
1945 "DC: failed to create output pixel processor!\n");
1950 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1951 pool->base.timing_generators[i] = dcn31_timing_generator_create(
1953 if (pool->base.timing_generators[i] == NULL) {
1954 BREAK_TO_DEBUGGER();
1955 dm_error("DC: failed to create tg!\n");
1959 pool->base.timing_generator_count = i;
1962 pool->base.psr = dmub_psr_create(ctx);
1963 if (pool->base.psr == NULL) {
1964 dm_error("DC: failed to create psr obj!\n");
1965 BREAK_TO_DEBUGGER();
1970 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1971 pool->base.multiple_abms[i] = dmub_abm_create(ctx,
1975 if (pool->base.multiple_abms[i] == NULL) {
1976 dm_error("DC: failed to create abm for pipe %d!\n", i);
1977 BREAK_TO_DEBUGGER();
1983 pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
1984 if (pool->base.mpc == NULL) {
1985 BREAK_TO_DEBUGGER();
1986 dm_error("DC: failed to create mpc!\n");
1990 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1991 pool->base.dscs[i] = dcn31_dsc_create(ctx, i);
1992 if (pool->base.dscs[i] == NULL) {
1993 BREAK_TO_DEBUGGER();
1994 dm_error("DC: failed to create display stream compressor %d!\n", i);
1999 /* DWB and MMHUBBUB */
2000 if (!dcn31_dwbc_create(ctx, &pool->base)) {
2001 BREAK_TO_DEBUGGER();
2002 dm_error("DC: failed to create dwbc!\n");
2006 if (!dcn31_mmhubbub_create(ctx, &pool->base)) {
2007 BREAK_TO_DEBUGGER();
2008 dm_error("DC: failed to create mcif_wb!\n");
2013 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2014 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);
2015 if (pool->base.engines[i] == NULL) {
2016 BREAK_TO_DEBUGGER();
2018 "DC:failed to create aux engine!!\n");
2021 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);
2022 if (pool->base.hw_i2cs[i] == NULL) {
2023 BREAK_TO_DEBUGGER();
2025 "DC:failed to create hw i2c!!\n");
2028 pool->base.sw_i2cs[i] = NULL;
2031 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2032 if (!resource_construct(num_virtual_links, dc, &pool->base,
2033 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
2034 &res_create_funcs : &res_create_maximus_funcs)))
2037 /* HW Sequencer and Plane caps */
2038 dcn31_hw_sequencer_construct(dc);
2040 dc->caps.max_planes = pool->base.pipe_count;
2042 for (i = 0; i < dc->caps.max_planes; ++i)
2043 dc->caps.planes[i] = plane_cap;
2045 dc->cap_funcs = cap_funcs;
2047 dc->dcn_ip->max_num_dpp = dcn3_16_ip.max_num_dpp;
2053 dcn316_resource_destruct(pool);
2058 struct resource_pool *dcn316_create_resource_pool(
2059 const struct dc_init_data *init_data,
2062 struct dcn316_resource_pool *pool =
2063 kzalloc(sizeof(struct dcn316_resource_pool), GFP_KERNEL);
2068 if (dcn316_resource_construct(init_data->num_virtual_links, dc, pool))
2071 BREAK_TO_DEBUGGER();