2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
27 #include "dm_services.h"
28 #include "dm_helpers.h"
29 #include "core_types.h"
32 #include "dce/dce_hwseq.h"
34 #include "reg_helper.h"
38 #include "timing_generator.h"
43 #include "dc_dmub_srv.h"
44 #include "dcn31_hwseq.h"
45 #include "link_hwss.h"
46 #include "dpcd_defs.h"
47 #include "dce/dmub_outbox.h"
48 #include "dc_link_dp.h"
49 #include "inc/link_dpcd.h"
50 #include "dcn10/dcn10_hw_sequencer.h"
52 #define DC_LOGGER_INIT(logger)
63 #define FN(reg_name, field_name) \
64 hws->shifts->field_name, hws->masks->field_name
66 void dcn31_init_hw(struct dc *dc)
68 struct abm **abms = dc->res_pool->multiple_abms;
69 struct dce_hwseq *hws = dc->hwseq;
70 struct dc_bios *dcb = dc->ctx->dc_bios;
71 struct resource_pool *res_pool = dc->res_pool;
72 uint32_t backlight = MAX_BACKLIGHT_LEVEL;
76 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
77 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
79 // Initialize the dccg
80 if (res_pool->dccg->funcs->dccg_init)
81 res_pool->dccg->funcs->dccg_init(res_pool->dccg);
83 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
85 REG_WRITE(REFCLK_CNTL, 0);
86 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
87 REG_WRITE(DIO_MEM_PWR_CTRL, 0);
89 if (!dc->debug.disable_clock_gate) {
90 /* enable all DCN clock gating */
91 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
93 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
95 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
98 //Enable ability to power gate / don't force power on permanently
99 if (hws->funcs.enable_power_gating_plane)
100 hws->funcs.enable_power_gating_plane(hws, true);
105 if (!dcb->funcs->is_accelerated_mode(dcb)) {
106 hws->funcs.bios_golden_init(dc);
107 hws->funcs.disable_vga(dc->hwseq);
110 if (dc->debug.enable_mem_low_power.bits.dmcu) {
111 // Force ERAM to shutdown if DMCU is not enabled
112 if (dc->debug.disable_dmcu || dc->config.disable_dmcu) {
113 REG_UPDATE(DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, 3);
117 // Set default OPTC memory power states
118 if (dc->debug.enable_mem_low_power.bits.optc) {
119 // Shutdown when unassigned and light sleep in VBLANK
120 REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1);
123 if (dc->debug.enable_mem_low_power.bits.vga) {
124 // Power down VGA memory
125 REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1);
128 if (dc->ctx->dc_bios->fw_info_valid) {
129 res_pool->ref_clocks.xtalin_clock_inKhz =
130 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
132 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
133 if (res_pool->dccg && res_pool->hubbub) {
135 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
136 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
137 &res_pool->ref_clocks.dccg_ref_clock_inKhz);
139 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
140 res_pool->ref_clocks.dccg_ref_clock_inKhz,
141 &res_pool->ref_clocks.dchub_ref_clock_inKhz);
143 // Not all ASICs have DCCG sw component
144 res_pool->ref_clocks.dccg_ref_clock_inKhz =
145 res_pool->ref_clocks.xtalin_clock_inKhz;
146 res_pool->ref_clocks.dchub_ref_clock_inKhz =
147 res_pool->ref_clocks.xtalin_clock_inKhz;
151 ASSERT_CRITICAL(false);
153 for (i = 0; i < dc->link_count; i++) {
154 /* Power up AND update implementation according to the
155 * required signal (which may be different from the
156 * default signal on connector).
158 struct dc_link *link = dc->links[i];
160 link->link_enc->funcs->hw_init(link->link_enc);
162 /* Check for enabled DIG to identify enabled display */
163 if (link->link_enc->funcs->is_dig_enabled &&
164 link->link_enc->funcs->is_dig_enabled(link->link_enc))
165 link->link_status.link_active = true;
168 /* Power gate DSCs */
169 for (i = 0; i < res_pool->res_cap->num_dsc; i++)
170 if (hws->funcs.dsc_pg_control != NULL)
171 hws->funcs.dsc_pg_control(hws, res_pool->dscs[i]->inst, false);
173 /* we want to turn off all dp displays before doing detection */
174 if (dc->config.power_down_display_on_boot) {
175 uint8_t dpcd_power_state = '\0';
176 enum dc_status status = DC_ERROR_UNEXPECTED;
178 for (i = 0; i < dc->link_count; i++) {
179 if (dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT)
182 /* if any of the displays are lit up turn them off */
183 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER,
184 &dpcd_power_state, sizeof(dpcd_power_state));
185 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) {
186 /* blank dp stream before power off receiver*/
187 if (dc->links[i]->link_enc->funcs->get_dig_frontend) {
190 fe = dc->links[i]->link_enc->funcs->get_dig_frontend(
191 dc->links[i]->link_enc);
192 if (fe == ENGINE_ID_UNKNOWN)
195 for (j = 0; j < dc->res_pool->stream_enc_count; j++) {
196 if (fe == dc->res_pool->stream_enc[j]->id) {
197 dc->res_pool->stream_enc[j]->funcs->dp_blank(
198 dc->res_pool->stream_enc[j]);
203 dp_receiver_power_ctrl(dc->links[i], false);
208 /* If taking control over from VBIOS, we may want to optimize our first
209 * mode set, so we need to skip powering down pipes until we know which
210 * pipes we want to use.
211 * Otherwise, if taking control is not possible, we need to power
214 if (dcb->funcs->is_accelerated_mode(dcb) || dc->config.power_down_display_on_boot) {
215 hws->funcs.init_pipes(dc, dc->current_state);
216 if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)
217 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,
218 !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);
221 /* In headless boot cases, DIG may be turned
222 * on which causes HW/SW discrepancies.
223 * To avoid this, power down hardware on boot
224 * if DIG is turned on and seamless boot not enabled
226 if (dc->config.power_down_display_on_boot) {
227 struct dc_link *edp_links[MAX_NUM_EDP];
228 struct dc_link *edp_link;
230 get_edp_links(dc, edp_links, &edp_num);
232 for (i = 0; i < edp_num; i++) {
233 edp_link = edp_links[i];
234 if (edp_link->link_enc->funcs->is_dig_enabled &&
235 edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) &&
236 dc->hwss.edp_backlight_control &&
237 dc->hwss.power_down &&
238 dc->hwss.edp_power_control) {
239 dc->hwss.edp_backlight_control(edp_link, false);
240 dc->hwss.power_down(dc);
241 dc->hwss.edp_power_control(edp_link, false);
245 for (i = 0; i < dc->link_count; i++) {
246 struct dc_link *link = dc->links[i];
248 if (link->link_enc->funcs->is_dig_enabled &&
249 link->link_enc->funcs->is_dig_enabled(link->link_enc) &&
250 dc->hwss.power_down) {
251 dc->hwss.power_down(dc);
259 for (i = 0; i < res_pool->audio_count; i++) {
260 struct audio *audio = res_pool->audios[i];
262 audio->funcs->hw_init(audio);
265 for (i = 0; i < dc->link_count; i++) {
266 struct dc_link *link = dc->links[i];
268 if (link->panel_cntl)
269 backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl);
272 for (i = 0; i < dc->res_pool->pipe_count; i++) {
274 abms[i]->funcs->abm_init(abms[i], backlight);
277 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/
278 REG_WRITE(DIO_MEM_PWR_CTRL, 0);
280 if (!dc->debug.disable_clock_gate) {
281 /* enable all DCN clock gating */
282 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
284 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
286 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
288 if (hws->funcs.enable_power_gating_plane)
289 hws->funcs.enable_power_gating_plane(dc->hwseq, true);
291 if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)
292 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);
294 if (dc->clk_mgr->funcs->notify_wm_ranges)
295 dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);
297 if (dc->clk_mgr->funcs->set_hard_max_memclk)
298 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
300 if (dc->res_pool->hubbub->funcs->force_pstate_change_control)
301 dc->res_pool->hubbub->funcs->force_pstate_change_control(
302 dc->res_pool->hubbub, false, false);
303 if (dc->res_pool->hubbub->funcs->init_crb)
304 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);
307 void dcn31_dsc_pg_control(
308 struct dce_hwseq *hws,
309 unsigned int dsc_inst,
312 uint32_t power_gate = power_on ? 0 : 1;
313 uint32_t pwr_status = power_on ? 0 : 2;
314 uint32_t org_ip_request_cntl = 0;
316 if (hws->ctx->dc->debug.disable_dsc_power_gate)
319 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
320 if (org_ip_request_cntl == 0)
321 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
325 REG_UPDATE(DOMAIN16_PG_CONFIG,
326 DOMAIN_POWER_GATE, power_gate);
328 REG_WAIT(DOMAIN16_PG_STATUS,
329 DOMAIN_PGFSM_PWR_STATUS, pwr_status,
333 REG_UPDATE(DOMAIN17_PG_CONFIG,
334 DOMAIN_POWER_GATE, power_gate);
336 REG_WAIT(DOMAIN17_PG_STATUS,
337 DOMAIN_PGFSM_PWR_STATUS, pwr_status,
341 REG_UPDATE(DOMAIN18_PG_CONFIG,
342 DOMAIN_POWER_GATE, power_gate);
344 REG_WAIT(DOMAIN18_PG_STATUS,
345 DOMAIN_PGFSM_PWR_STATUS, pwr_status,
353 if (org_ip_request_cntl == 0)
354 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
358 void dcn31_enable_power_gating_plane(
359 struct dce_hwseq *hws,
362 bool force_on = true; /* disable power gating */
367 /* DCHUBP0/1/2/3/4/5 */
368 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
369 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
372 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
373 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
376 REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
377 REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
378 REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
381 void dcn31_update_info_frame(struct pipe_ctx *pipe_ctx)
386 ASSERT(pipe_ctx->stream);
388 if (pipe_ctx->stream_res.stream_enc == NULL)
389 return; /* this is not root pipe */
391 is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal);
392 is_dp = dc_is_dp_signal(pipe_ctx->stream->signal);
394 if (!is_hdmi_tmds && !is_dp)
398 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(
399 pipe_ctx->stream_res.stream_enc,
400 &pipe_ctx->stream_res.encoder_info_frame);
402 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(
403 pipe_ctx->stream_res.stream_enc,
404 &pipe_ctx->stream_res.encoder_info_frame);
408 void dcn31_z10_restore(struct dc *dc)
410 union dmub_rb_cmd cmd;
413 * DMUB notifies whether restore is required.
414 * Optimization to avoid sending commands when not required.
416 if (!dc_dmub_srv_is_restore_required(dc->ctx->dmub_srv))
419 memset(&cmd, 0, sizeof(cmd));
420 cmd.dcn_restore.header.type = DMUB_CMD__IDLE_OPT;
421 cmd.dcn_restore.header.sub_type = DMUB_CMD__IDLE_OPT_DCN_RESTORE;
423 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
424 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
425 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
428 void dcn31_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on)
430 uint32_t power_gate = power_on ? 0 : 1;
431 uint32_t pwr_status = power_on ? 0 : 2;
433 if (hws->ctx->dc->debug.disable_hubp_power_gate)
436 if (REG(DOMAIN0_PG_CONFIG) == 0)
441 REG_SET(DOMAIN0_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
442 REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
445 REG_SET(DOMAIN1_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
446 REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
449 REG_SET(DOMAIN2_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
450 REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
453 REG_SET(DOMAIN3_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
454 REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
462 int dcn31_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)
464 struct dcn_hubbub_phys_addr_config config;
466 config.system_aperture.fb_top = pa_config->system_aperture.fb_top;
467 config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset;
468 config.system_aperture.fb_base = pa_config->system_aperture.fb_base;
469 config.system_aperture.agp_top = pa_config->system_aperture.agp_top;
470 config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot;
471 config.system_aperture.agp_base = pa_config->system_aperture.agp_base;
472 config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr;
473 config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr;
475 if (pa_config->gart_config.base_addr_is_mc_addr) {
476 /* Convert from MC address to offset into FB */
477 config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr -
478 pa_config->system_aperture.fb_base +
479 pa_config->system_aperture.fb_offset;
481 config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr;
483 return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config);
486 static void dcn31_reset_back_end_for_pipe(
488 struct pipe_ctx *pipe_ctx,
489 struct dc_state *context)
491 struct dc_link *link;
493 DC_LOGGER_INIT(dc->ctx->logger);
494 if (pipe_ctx->stream_res.stream_enc == NULL) {
495 pipe_ctx->stream = NULL;
498 ASSERT(!pipe_ctx->top_pipe);
500 dc->hwss.set_abm_immediate_disable(pipe_ctx);
502 pipe_ctx->stream_res.tg->funcs->set_dsc_config(
503 pipe_ctx->stream_res.tg,
504 OPTC_DSC_DISABLED, 0, 0);
505 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
507 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
508 if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass)
509 pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
510 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
512 if (pipe_ctx->stream_res.tg->funcs->set_drr)
513 pipe_ctx->stream_res.tg->funcs->set_drr(
514 pipe_ctx->stream_res.tg, NULL);
516 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
517 link = pipe_ctx->stream->link;
518 /* DPMS may already disable or */
519 /* dpms_off status is incorrect due to fastboot
520 * feature. When system resume from S4 with second
521 * screen only, the dpms_off would be true but
522 * VBIOS lit up eDP, so check link status too.
524 if (!pipe_ctx->stream->dpms_off || link->link_status.link_active)
525 core_link_disable_stream(pipe_ctx);
526 else if (pipe_ctx->stream_res.audio)
527 dc->hwss.disable_audio_stream(pipe_ctx);
529 /* free acquired resources */
530 if (pipe_ctx->stream_res.audio) {
531 /*disable az_endpoint*/
532 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
535 if (dc->caps.dynamic_audio == true) {
536 /*we have to dynamic arbitrate the audio endpoints*/
537 /*we free the resource, need reset is_audio_acquired*/
538 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
539 pipe_ctx->stream_res.audio, false);
540 pipe_ctx->stream_res.audio = NULL;
543 } else if (pipe_ctx->stream_res.dsc) {
544 dp_set_dsc_enable(pipe_ctx, false);
547 pipe_ctx->stream = NULL;
548 DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n",
549 pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
552 void dcn31_reset_hw_ctx_wrap(
554 struct dc_state *context)
557 struct dce_hwseq *hws = dc->hwseq;
560 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
561 struct pipe_ctx *pipe_ctx_old =
562 &dc->current_state->res_ctx.pipe_ctx[i];
563 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
565 if (!pipe_ctx_old->stream)
568 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe)
571 if (!pipe_ctx->stream ||
572 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
573 struct clock_source *old_clk = pipe_ctx_old->clock_source;
575 dcn31_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
576 if (hws->funcs.enable_stream_gating)
577 hws->funcs.enable_stream_gating(dc, pipe_ctx);
579 old_clk->funcs->cs_power_down(old_clk);
584 bool dcn31_is_abm_supported(struct dc *dc,
585 struct dc_state *context, struct dc_stream_state *stream)
589 for (i = 0; i < dc->res_pool->pipe_count; i++) {
590 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
592 if (pipe_ctx->stream == stream &&
593 (pipe_ctx->prev_odm_pipe == NULL && pipe_ctx->next_odm_pipe == NULL))
599 static void apply_riommu_invalidation_wa(struct dc *dc)
601 struct dce_hwseq *hws = dc->hwseq;
603 if (!hws->wa.early_riommu_invalidation)
606 REG_UPDATE(DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, 0);
609 void dcn31_init_pipes(struct dc *dc, struct dc_state *context)
611 dcn10_init_pipes(dc, context);
612 apply_riommu_invalidation_wa(dc);