drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26
  27 #include "dm_services.h"
  28 #include "dm_helpers.h"
  29 #include "core_types.h"
  30 #include "resource.h"
  31 #include "dccg.h"
  32 #include "dce/dce_hwseq.h"
  33 #include "clk_mgr.h"
  34 #include "reg_helper.h"
  35 #include "abm.h"
  36 #include "hubp.h"
  37 #include "dchubbub.h"
  38 #include "timing_generator.h"
  39 #include "opp.h"
  40 #include "ipp.h"
  41 #include "mpc.h"
  42 #include "mcif_wb.h"
  43 #include "dc_dmub_srv.h"
  44 #include "dcn31_hwseq.h"
  45 #include "link_hwss.h"
  46 #include "dpcd_defs.h"
  47 #include "dce/dmub_outbox.h"
  48 #include "dc_link_dp.h"
  49 #include "inc/link_dpcd.h"
  50
  51 #define DC_LOGGER_INIT(logger)
  52
  53 #define CTX \
  54         hws->ctx
  55 #define REG(reg)\
  56         hws->regs->reg
  57 #define DC_LOGGER \
  58                 dc->ctx->logger
  59
  60
  61 #undef FN
  62 #define FN(reg_name, field_name) \
  63         hws->shifts->field_name, hws->masks->field_name
  64
  65 void dcn31_init_hw(struct dc *dc)
  66 {
  67         struct abm **abms = dc->res_pool->multiple_abms;
  68         struct dce_hwseq *hws = dc->hwseq;
  69         struct dc_bios *dcb = dc->ctx->dc_bios;
  70         struct resource_pool *res_pool = dc->res_pool;
  71         uint32_t backlight = MAX_BACKLIGHT_LEVEL;
  72         int i, j;
  73         int edp_num;
  74
  75         if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
  76                 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
  77
  78         // Initialize the dccg
  79         if (res_pool->dccg->funcs->dccg_init)
  80                 res_pool->dccg->funcs->dccg_init(res_pool->dccg);
  81
  82         if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
  83
  84                 REG_WRITE(REFCLK_CNTL, 0);
  85                 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
  86                 REG_WRITE(DIO_MEM_PWR_CTRL, 0);
  87
  88                 if (!dc->debug.disable_clock_gate) {
  89                         /* enable all DCN clock gating */
  90                         REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
  91
  92                         REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
  93
  94                         REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
  95                 }
  96
  97                 //Enable ability to power gate / don't force power on permanently
  98                 if (hws->funcs.enable_power_gating_plane)
  99                         hws->funcs.enable_power_gating_plane(hws, true);
 100
 101                 return;
 102         }
 103
 104         if (!dcb->funcs->is_accelerated_mode(dcb)) {
 105                 hws->funcs.bios_golden_init(dc);
 106                 hws->funcs.disable_vga(dc->hwseq);
 107         }
 108
 109         if (dc->debug.enable_mem_low_power.bits.dmcu) {
 110                 // Force ERAM to shutdown if DMCU is not enabled
 111                 if (dc->debug.disable_dmcu || dc->config.disable_dmcu) {
 112                         REG_UPDATE(DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, 3);
 113                 }
 114         }
 115
 116         // Set default OPTC memory power states
 117         if (dc->debug.enable_mem_low_power.bits.optc) {
 118                 // Shutdown when unassigned and light sleep in VBLANK
 119                 REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1);
 120         }
 121
 122         if (dc->debug.enable_mem_low_power.bits.vga) {
 123                 // Power down VGA memory
 124                 REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1);
 125         }
 126
 127         if (dc->ctx->dc_bios->fw_info_valid) {
 128                 res_pool->ref_clocks.xtalin_clock_inKhz =
 129                                 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
 130
 131                 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
 132                         if (res_pool->dccg && res_pool->hubbub) {
 133
 134                                 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
 135                                                 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
 136                                                 &res_pool->ref_clocks.dccg_ref_clock_inKhz);
 137
 138                                 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
 139                                                 res_pool->ref_clocks.dccg_ref_clock_inKhz,
 140                                                 &res_pool->ref_clocks.dchub_ref_clock_inKhz);
 141                         } else {
 142                                 // Not all ASICs have DCCG sw component
 143                                 res_pool->ref_clocks.dccg_ref_clock_inKhz =
 144                                                 res_pool->ref_clocks.xtalin_clock_inKhz;
 145                                 res_pool->ref_clocks.dchub_ref_clock_inKhz =
 146                                                 res_pool->ref_clocks.xtalin_clock_inKhz;
 147                         }
 148                 }
 149         } else
 150                 ASSERT_CRITICAL(false);
 151
 152         for (i = 0; i < dc->link_count; i++) {
 153                 /* Power up AND update implementation according to the
 154                  * required signal (which may be different from the
 155                  * default signal on connector).
 156                  */
 157                 struct dc_link *link = dc->links[i];
 158
 159                 link->link_enc->funcs->hw_init(link->link_enc);
 160
 161                 /* Check for enabled DIG to identify enabled display */
 162                 if (link->link_enc->funcs->is_dig_enabled &&
 163                         link->link_enc->funcs->is_dig_enabled(link->link_enc))
 164                         link->link_status.link_active = true;
 165         }
 166
 167         /* Power gate DSCs */
 168         for (i = 0; i < res_pool->res_cap->num_dsc; i++)
 169                 if (hws->funcs.dsc_pg_control != NULL)
 170                         hws->funcs.dsc_pg_control(hws, res_pool->dscs[i]->inst, false);
 171
 172         /* we want to turn off all dp displays before doing detection */
 173         if (dc->config.power_down_display_on_boot) {
 174                 uint8_t dpcd_power_state = '\0';
 175                 enum dc_status status = DC_ERROR_UNEXPECTED;
 176
 177                 for (i = 0; i < dc->link_count; i++) {
 178                         if (dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT)
 179                                 continue;
 180
 181                         /* if any of the displays are lit up turn them off */
 182                         status = core_link_read_dpcd(dc->links[i], DP_SET_POWER,
 183                                                      &dpcd_power_state, sizeof(dpcd_power_state));
 184                         if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) {
 185                                 /* blank dp stream before power off receiver*/
 186                                 if (dc->links[i]->link_enc->funcs->get_dig_frontend) {
 187                                         unsigned int fe;
 188
 189                                         fe = dc->links[i]->link_enc->funcs->get_dig_frontend(
 190                                                                                 dc->links[i]->link_enc);
 191                                         if (fe == ENGINE_ID_UNKNOWN)
 192                                                 continue;
 193
 194                                         for (j = 0; j < dc->res_pool->stream_enc_count; j++) {
 195                                                 if (fe == dc->res_pool->stream_enc[j]->id) {
 196                                                         dc->res_pool->stream_enc[j]->funcs->dp_blank(
 197                                                                                 dc->res_pool->stream_enc[j]);
 198                                                         break;
 199                                                 }
 200                                         }
 201                                 }
 202                                 dp_receiver_power_ctrl(dc->links[i], false);
 203                         }
 204                 }
 205         }
 206
 207         /* If taking control over from VBIOS, we may want to optimize our first
 208          * mode set, so we need to skip powering down pipes until we know which
 209          * pipes we want to use.
 210          * Otherwise, if taking control is not possible, we need to power
 211          * everything down.
 212          */
 213         if (dcb->funcs->is_accelerated_mode(dcb) || dc->config.power_down_display_on_boot) {
 214                 hws->funcs.init_pipes(dc, dc->current_state);
 215                 if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)
 216                         dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,
 217                                         !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);
 218         }
 219
 220         /* In headless boot cases, DIG may be turned
 221          * on which causes HW/SW discrepancies.
 222          * To avoid this, power down hardware on boot
 223          * if DIG is turned on and seamless boot not enabled
 224          */
 225         if (dc->config.power_down_display_on_boot) {
 226                 struct dc_link *edp_links[MAX_NUM_EDP];
 227                 struct dc_link *edp_link;
 228
 229                 get_edp_links(dc, edp_links, &edp_num);
 230                 if (edp_num) {
 231                         for (i = 0; i < edp_num; i++) {
 232                                 edp_link = edp_links[i];
 233                                 if (edp_link->link_enc->funcs->is_dig_enabled &&
 234                                                 edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) &&
 235                                                 dc->hwss.edp_backlight_control &&
 236                                                 dc->hwss.power_down &&
 237                                                 dc->hwss.edp_power_control) {
 238                                         dc->hwss.edp_backlight_control(edp_link, false);
 239                                         dc->hwss.power_down(dc);
 240                                         dc->hwss.edp_power_control(edp_link, false);
 241                                 }
 242                         }
 243                 } else {
 244                         for (i = 0; i < dc->link_count; i++) {
 245                                 struct dc_link *link = dc->links[i];
 246
 247                                 if (link->link_enc->funcs->is_dig_enabled &&
 248                                                 link->link_enc->funcs->is_dig_enabled(link->link_enc) &&
 249                                                 dc->hwss.power_down) {
 250                                         dc->hwss.power_down(dc);
 251                                         break;
 252                                 }
 253
 254                         }
 255                 }
 256         }
 257
 258         for (i = 0; i < res_pool->audio_count; i++) {
 259                 struct audio *audio = res_pool->audios[i];
 260
 261                 audio->funcs->hw_init(audio);
 262         }
 263
 264         for (i = 0; i < dc->link_count; i++) {
 265                 struct dc_link *link = dc->links[i];
 266
 267                 if (link->panel_cntl)
 268                         backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl);
 269         }
 270
 271         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 272                 if (abms[i] != NULL)
 273                         abms[i]->funcs->abm_init(abms[i], backlight);
 274         }
 275
 276         /* power AFMT HDMI memory TODO: may move to dis/en output save power*/
 277         REG_WRITE(DIO_MEM_PWR_CTRL, 0);
 278
 279         if (!dc->debug.disable_clock_gate) {
 280                 /* enable all DCN clock gating */
 281                 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
 282
 283                 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
 284
 285                 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
 286         }
 287         if (hws->funcs.enable_power_gating_plane)
 288                 hws->funcs.enable_power_gating_plane(dc->hwseq, true);
 289
 290         if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)
 291                 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);
 292
 293         if (dc->clk_mgr->funcs->notify_wm_ranges)
 294                 dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);
 295
 296         if (dc->clk_mgr->funcs->set_hard_max_memclk)
 297                 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
 298
 299         if (dc->res_pool->hubbub->funcs->force_pstate_change_control)
 300                 dc->res_pool->hubbub->funcs->force_pstate_change_control(
 301                                 dc->res_pool->hubbub, false, false);
 302         if (dc->res_pool->hubbub->funcs->init_crb)
 303                 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);
 304 }
 305
 306 void dcn31_dsc_pg_control(
 307                 struct dce_hwseq *hws,
 308                 unsigned int dsc_inst,
 309                 bool power_on)
 310 {
 311         uint32_t power_gate = power_on ? 0 : 1;
 312         uint32_t pwr_status = power_on ? 0 : 2;
 313         uint32_t org_ip_request_cntl = 0;
 314
 315         if (hws->ctx->dc->debug.disable_dsc_power_gate)
 316                 return;
 317
 318         REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
 319         if (org_ip_request_cntl == 0)
 320                 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
 321
 322         switch (dsc_inst) {
 323         case 0: /* DSC0 */
 324                 REG_UPDATE(DOMAIN16_PG_CONFIG,
 325                                 DOMAIN_POWER_GATE, power_gate);
 326
 327                 REG_WAIT(DOMAIN16_PG_STATUS,
 328                                 DOMAIN_PGFSM_PWR_STATUS, pwr_status,
 329                                 1, 1000);
 330                 break;
 331         case 1: /* DSC1 */
 332                 REG_UPDATE(DOMAIN17_PG_CONFIG,
 333                                 DOMAIN_POWER_GATE, power_gate);
 334
 335                 REG_WAIT(DOMAIN17_PG_STATUS,
 336                                 DOMAIN_PGFSM_PWR_STATUS, pwr_status,
 337                                 1, 1000);
 338                 break;
 339         case 2: /* DSC2 */
 340                 REG_UPDATE(DOMAIN18_PG_CONFIG,
 341                                 DOMAIN_POWER_GATE, power_gate);
 342
 343                 REG_WAIT(DOMAIN18_PG_STATUS,
 344                                 DOMAIN_PGFSM_PWR_STATUS, pwr_status,
 345                                 1, 1000);
 346                 break;
 347         default:
 348                 BREAK_TO_DEBUGGER();
 349                 break;
 350         }
 351
 352         if (org_ip_request_cntl == 0)
 353                 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
 354 }
 355
 356
 357 void dcn31_enable_power_gating_plane(
 358         struct dce_hwseq *hws,
 359         bool enable)
 360 {
 361         bool force_on = true; /* disable power gating */
 362
 363         if (enable)
 364                 force_on = false;
 365
 366         /* DCHUBP0/1/2/3/4/5 */
 367         REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
 368         REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
 369
 370         /* DPP0/1/2/3/4/5 */
 371         REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
 372         REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
 373
 374         /* DCS0/1/2/3/4/5 */
 375         REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
 376         REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
 377         REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
 378 }
 379
 380 void dcn31_update_info_frame(struct pipe_ctx *pipe_ctx)
 381 {
 382         bool is_hdmi_tmds;
 383         bool is_dp;
 384
 385         ASSERT(pipe_ctx->stream);
 386
 387         if (pipe_ctx->stream_res.stream_enc == NULL)
 388                 return;  /* this is not root pipe */
 389
 390         is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal);
 391         is_dp = dc_is_dp_signal(pipe_ctx->stream->signal);
 392
 393         if (!is_hdmi_tmds)
 394                 return;
 395
 396         if (is_hdmi_tmds)
 397                 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(
 398                         pipe_ctx->stream_res.stream_enc,
 399                         &pipe_ctx->stream_res.encoder_info_frame);
 400         else {
 401                 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(
 402                         pipe_ctx->stream_res.stream_enc,
 403                         &pipe_ctx->stream_res.encoder_info_frame);
 404         }
 405 }
 406
 407 void dcn31_z10_restore(struct dc *dc)
 408 {
 409         union dmub_rb_cmd cmd;
 410
 411         /*
 412          * DMUB notifies whether restore is required.
 413          * Optimization to avoid sending commands when not required.
 414          */
 415         if (!dc_dmub_srv_is_restore_required(dc->ctx->dmub_srv))
 416                 return;
 417
 418         memset(&cmd, 0, sizeof(cmd));
 419         cmd.dcn_restore.header.type = DMUB_CMD__IDLE_OPT;
 420         cmd.dcn_restore.header.sub_type = DMUB_CMD__IDLE_OPT_DCN_RESTORE;
 421
 422         dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
 423         dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
 424         dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
 425 }
 426
 427 void dcn31_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on)
 428 {
 429         uint32_t power_gate = power_on ? 0 : 1;
 430         uint32_t pwr_status = power_on ? 0 : 2;
 431
 432         if (hws->ctx->dc->debug.disable_hubp_power_gate)
 433                 return;
 434
 435         if (REG(DOMAIN0_PG_CONFIG) == 0)
 436                 return;
 437
 438         switch (hubp_inst) {
 439         case 0:
 440                 REG_SET(DOMAIN0_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
 441                 REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
 442                 break;
 443         case 1:
 444                 REG_SET(DOMAIN1_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
 445                 REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
 446                 break;
 447         case 2:
 448                 REG_SET(DOMAIN2_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
 449                 REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
 450                 break;
 451         case 3:
 452                 REG_SET(DOMAIN3_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
 453                 REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
 454                 break;
 455         default:
 456                 BREAK_TO_DEBUGGER();
 457                 break;
 458         }
 459 }
 460
 461 int dcn31_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)
 462 {
 463         struct dcn_hubbub_phys_addr_config config;
 464
 465         config.system_aperture.fb_top = pa_config->system_aperture.fb_top;
 466         config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset;
 467         config.system_aperture.fb_base = pa_config->system_aperture.fb_base;
 468         config.system_aperture.agp_top = pa_config->system_aperture.agp_top;
 469         config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot;
 470         config.system_aperture.agp_base = pa_config->system_aperture.agp_base;
 471         config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr;
 472         config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr;
 473
 474         if (pa_config->gart_config.base_addr_is_mc_addr) {
 475                 /* Convert from MC address to offset into FB */
 476                 config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr -
 477                                 pa_config->system_aperture.fb_base +
 478                                 pa_config->system_aperture.fb_offset;
 479         } else
 480                 config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr;
 481
 482         return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config);
 483 }
 484
 485 static void dcn31_reset_back_end_for_pipe(
 486                 struct dc *dc,
 487                 struct pipe_ctx *pipe_ctx,
 488                 struct dc_state *context)
 489 {
 490         struct dc_link *link;
 491
 492         DC_LOGGER_INIT(dc->ctx->logger);
 493         if (pipe_ctx->stream_res.stream_enc == NULL) {
 494                 pipe_ctx->stream = NULL;
 495                 return;
 496         }
 497         ASSERT(!pipe_ctx->top_pipe);
 498
 499         dc->hwss.set_abm_immediate_disable(pipe_ctx);
 500
 501         pipe_ctx->stream_res.tg->funcs->set_dsc_config(
 502                         pipe_ctx->stream_res.tg,
 503                         OPTC_DSC_DISABLED, 0, 0);
 504         pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
 505
 506         pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
 507         if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass)
 508                 pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
 509                                 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
 510
 511         if (pipe_ctx->stream_res.tg->funcs->set_drr)
 512                 pipe_ctx->stream_res.tg->funcs->set_drr(
 513                                 pipe_ctx->stream_res.tg, NULL);
 514
 515         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
 516                 link = pipe_ctx->stream->link;
 517                 /* DPMS may already disable or */
 518                 /* dpms_off status is incorrect due to fastboot
 519                  * feature. When system resume from S4 with second
 520                  * screen only, the dpms_off would be true but
 521                  * VBIOS lit up eDP, so check link status too.
 522                  */
 523                 if (!pipe_ctx->stream->dpms_off || link->link_status.link_active)
 524                         core_link_disable_stream(pipe_ctx);
 525                 else if (pipe_ctx->stream_res.audio)
 526                         dc->hwss.disable_audio_stream(pipe_ctx);
 527
 528                 /* free acquired resources */
 529                 if (pipe_ctx->stream_res.audio) {
 530                         /*disable az_endpoint*/
 531                         pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
 532
 533                         /*free audio*/
 534                         if (dc->caps.dynamic_audio == true) {
 535                                 /*we have to dynamic arbitrate the audio endpoints*/
 536                                 /*we free the resource, need reset is_audio_acquired*/
 537                                 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
 538                                                 pipe_ctx->stream_res.audio, false);
 539                                 pipe_ctx->stream_res.audio = NULL;
 540                         }
 541                 }
 542         } else if (pipe_ctx->stream_res.dsc) {
 543                         dp_set_dsc_enable(pipe_ctx, false);
 544         }
 545
 546         pipe_ctx->stream = NULL;
 547         DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n",
 548                                         pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
 549 }
 550
 551 void dcn31_reset_hw_ctx_wrap(
 552                 struct dc *dc,
 553                 struct dc_state *context)
 554 {
 555         int i;
 556         struct dce_hwseq *hws = dc->hwseq;
 557
 558         /* Reset Back End*/
 559         for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
 560                 struct pipe_ctx *pipe_ctx_old =
 561                         &dc->current_state->res_ctx.pipe_ctx[i];
 562                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
 563
 564                 if (!pipe_ctx_old->stream)
 565                         continue;
 566
 567                 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe)
 568                         continue;
 569
 570                 if (!pipe_ctx->stream ||
 571                                 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
 572                         struct clock_source *old_clk = pipe_ctx_old->clock_source;
 573
 574                         dcn31_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
 575                         if (hws->funcs.enable_stream_gating)
 576                                 hws->funcs.enable_stream_gating(dc, pipe_ctx);
 577                         if (old_clk)
 578                                 old_clk->funcs->cs_power_down(old_clk);
 579                 }
 580         }
 581 }
 582
 583 bool dcn31_is_abm_supported(struct dc *dc,
 584                 struct dc_state *context, struct dc_stream_state *stream)
 585 {
 586         int i;
 587
 588         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 589                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
 590
 591                 if (pipe_ctx->stream == stream &&
 592                                 (pipe_ctx->prev_odm_pipe == NULL && pipe_ctx->next_odm_pipe == NULL))
 593                         return true;
 594         }
 595         return false;
 596 }