drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c

   1 /*
   2  * Copyright 2020 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dcn302_init.h"
  27 #include "dcn302_resource.h"
  28 #include "dcn302_dccg.h"
  29 #include "irq/dcn302/irq_service_dcn302.h"
  30
  31 #include "dcn30/dcn30_dio_link_encoder.h"
  32 #include "dcn30/dcn30_dio_stream_encoder.h"
  33 #include "dcn30/dcn30_dwb.h"
  34 #include "dcn30/dcn30_dpp.h"
  35 #include "dcn30/dcn30_hubbub.h"
  36 #include "dcn30/dcn30_hubp.h"
  37 #include "dcn30/dcn30_mmhubbub.h"
  38 #include "dcn30/dcn30_mpc.h"
  39 #include "dcn30/dcn30_opp.h"
  40 #include "dcn30/dcn30_optc.h"
  41 #include "dcn30/dcn30_resource.h"
  42
  43 #include "dcn20/dcn20_dsc.h"
  44 #include "dcn20/dcn20_resource.h"
  45
  46 #include "dcn10/dcn10_resource.h"
  47
  48 #include "dce/dce_abm.h"
  49 #include "dce/dce_audio.h"
  50 #include "dce/dce_aux.h"
  51 #include "dce/dce_clock_source.h"
  52 #include "dce/dce_hwseq.h"
  53 #include "dce/dce_i2c_hw.h"
  54 #include "dce/dce_panel_cntl.h"
  55 #include "dce/dmub_abm.h"
  56 #include "dce/dmub_psr.h"
  57
  58 #include "hw_sequencer_private.h"
  59 #include "reg_helper.h"
  60 #include "resource.h"
  61 #include "vm_helper.h"
  62
  63 #include "dimgrey_cavefish_ip_offset.h"
  64 #include "dcn/dcn_3_0_2_offset.h"
  65 #include "dcn/dcn_3_0_2_sh_mask.h"
  66 #include "dcn/dpcs_3_0_0_offset.h"
  67 #include "dcn/dpcs_3_0_0_sh_mask.h"
  68 #include "nbio/nbio_7_4_offset.h"
  69 #include "amdgpu_socbb.h"
  70
  71 #define DC_LOGGER_INIT(logger)
  72
  73 struct _vcs_dpi_ip_params_st dcn3_02_ip = {
  74                 .use_min_dcfclk = 0,
  75                 .clamp_min_dcfclk = 0,
  76                 .odm_capable = 1,
  77                 .gpuvm_enable = 1,
  78                 .hostvm_enable = 0,
  79                 .gpuvm_max_page_table_levels = 4,
  80                 .hostvm_max_page_table_levels = 4,
  81                 .hostvm_cached_page_table_levels = 0,
  82                 .pte_group_size_bytes = 2048,
  83                 .num_dsc = 5,
  84                 .rob_buffer_size_kbytes = 184,
  85                 .det_buffer_size_kbytes = 184,
  86                 .dpte_buffer_size_in_pte_reqs_luma = 64,
  87                 .dpte_buffer_size_in_pte_reqs_chroma = 34,
  88                 .pde_proc_buffer_size_64k_reqs = 48,
  89                 .dpp_output_buffer_pixels = 2560,
  90                 .opp_output_buffer_lines = 1,
  91                 .pixel_chunk_size_kbytes = 8,
  92                 .pte_enable = 1,
  93                 .max_page_table_levels = 2,
  94                 .pte_chunk_size_kbytes = 2,  // ?
  95                 .meta_chunk_size_kbytes = 2,
  96                 .writeback_chunk_size_kbytes = 8,
  97                 .line_buffer_size_bits = 789504,
  98                 .is_line_buffer_bpp_fixed = 0,  // ?
  99                 .line_buffer_fixed_bpp = 0,     // ?
 100                 .dcc_supported = true,
 101                 .writeback_interface_buffer_size_kbytes = 90,
 102                 .writeback_line_buffer_buffer_size = 0,
 103                 .max_line_buffer_lines = 12,
 104                 .writeback_luma_buffer_size_kbytes = 12,  // writeback_line_buffer_buffer_size = 656640
 105                 .writeback_chroma_buffer_size_kbytes = 8,
 106                 .writeback_chroma_line_buffer_width_pixels = 4,
 107                 .writeback_max_hscl_ratio = 1,
 108                 .writeback_max_vscl_ratio = 1,
 109                 .writeback_min_hscl_ratio = 1,
 110                 .writeback_min_vscl_ratio = 1,
 111                 .writeback_max_hscl_taps = 1,
 112                 .writeback_max_vscl_taps = 1,
 113                 .writeback_line_buffer_luma_buffer_size = 0,
 114                 .writeback_line_buffer_chroma_buffer_size = 14643,
 115                 .cursor_buffer_size = 8,
 116                 .cursor_chunk_size = 2,
 117                 .max_num_otg = 5,
 118                 .max_num_dpp = 5,
 119                 .max_num_wb = 1,
 120                 .max_dchub_pscl_bw_pix_per_clk = 4,
 121                 .max_pscl_lb_bw_pix_per_clk = 2,
 122                 .max_lb_vscl_bw_pix_per_clk = 4,
 123                 .max_vscl_hscl_bw_pix_per_clk = 4,
 124                 .max_hscl_ratio = 6,
 125                 .max_vscl_ratio = 6,
 126                 .hscl_mults = 4,
 127                 .vscl_mults = 4,
 128                 .max_hscl_taps = 8,
 129                 .max_vscl_taps = 8,
 130                 .dispclk_ramp_margin_percent = 1,
 131                 .underscan_factor = 1.11,
 132                 .min_vblank_lines = 32,
 133                 .dppclk_delay_subtotal = 46,
 134                 .dynamic_metadata_vm_enabled = true,
 135                 .dppclk_delay_scl_lb_only = 16,
 136                 .dppclk_delay_scl = 50,
 137                 .dppclk_delay_cnvc_formatter = 27,
 138                 .dppclk_delay_cnvc_cursor = 6,
 139                 .dispclk_delay_subtotal = 119,
 140                 .dcfclk_cstate_latency = 5.2, // SRExitTime
 141                 .max_inter_dcn_tile_repeaters = 8,
 142                 .max_num_hdmi_frl_outputs = 1,
 143                 .odm_combine_4to1_supported = true,
 144
 145                 .xfc_supported = false,
 146                 .xfc_fill_bw_overhead_percent = 10.0,
 147                 .xfc_fill_constant_bytes = 0,
 148                 .gfx7_compat_tiling_supported = 0,
 149                 .number_of_cursors = 1,
 150 };
 151
 152 struct _vcs_dpi_soc_bounding_box_st dcn3_02_soc = {
 153                 .clock_limits = {
 154                                 {
 155                                                 .state = 0,
 156                                                 .dispclk_mhz = 562.0,
 157                                                 .dppclk_mhz = 300.0,
 158                                                 .phyclk_mhz = 300.0,
 159                                                 .phyclk_d18_mhz = 667.0,
 160                                                 .dscclk_mhz = 405.6,
 161                                 },
 162                 },
 163
 164                 .min_dcfclk = 500.0, /* TODO: set this to actual min DCFCLK */
 165                 .num_states = 1,
 166                 .sr_exit_time_us = 5.20,
 167                 .sr_enter_plus_exit_time_us = 9.60,
 168                 .urgent_latency_us = 4.0,
 169                 .urgent_latency_pixel_data_only_us = 4.0,
 170                 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
 171                 .urgent_latency_vm_data_only_us = 4.0,
 172                 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
 173                 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
 174                 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
 175                 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0,
 176                 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0,
 177                 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
 178                 .max_avg_sdp_bw_use_normal_percent = 60.0,
 179                 .max_avg_dram_bw_use_normal_percent = 40.0,
 180                 .writeback_latency_us = 12.0,
 181                 .max_request_size_bytes = 256,
 182                 .fabric_datapath_to_dcn_data_return_bytes = 64,
 183                 .dcn_downspread_percent = 0.5,
 184                 .downspread_percent = 0.38,
 185                 .dram_page_open_time_ns = 50.0,
 186                 .dram_rw_turnaround_time_ns = 17.5,
 187                 .dram_return_buffer_per_channel_bytes = 8192,
 188                 .round_trip_ping_latency_dcfclk_cycles = 156,
 189                 .urgent_out_of_order_return_per_channel_bytes = 4096,
 190                 .channel_interleave_bytes = 256,
 191                 .num_banks = 8,
 192                 .gpuvm_min_page_size_bytes = 4096,
 193                 .hostvm_min_page_size_bytes = 4096,
 194                 .dram_clock_change_latency_us = 350,
 195                 .dummy_pstate_latency_us = 5,
 196                 .writeback_dram_clock_change_latency_us = 23.0,
 197                 .return_bus_width_bytes = 64,
 198                 .dispclk_dppclk_vco_speed_mhz = 3650,
 199                 .xfc_bus_transport_time_us = 20,      // ?
 200                 .xfc_xbuf_latency_tolerance_us = 4,  // ?
 201                 .use_urgent_burst_bw = 1,            // ?
 202                 .do_urgent_latency_adjustment = true,
 203                 .urgent_latency_adjustment_fabric_clock_component_us = 1.0,
 204                 .urgent_latency_adjustment_fabric_clock_reference_mhz = 1000,
 205 };
 206
 207 static const struct dc_debug_options debug_defaults_drv = {
 208                 .disable_dmcu = true,
 209                 .force_abm_enable = false,
 210                 .timing_trace = false,
 211                 .clock_trace = true,
 212                 .disable_pplib_clock_request = true,
 213                 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
 214                 .force_single_disp_pipe_split = false,
 215                 .disable_dcc = DCC_ENABLE,
 216                 .vsr_support = true,
 217                 .performance_trace = false,
 218                 .max_downscale_src_width = 7680,/*upto 8K*/
 219                 .disable_pplib_wm_range = false,
 220                 .scl_reset_length10 = true,
 221                 .sanity_checks = false,
 222                 .underflow_assert_delay_us = 0xFFFFFFFF,
 223                 .dwb_fi_phase = -1, // -1 = disable,
 224                 .dmub_command_table = true,
 225 };
 226
 227 static const struct dc_debug_options debug_defaults_diags = {
 228                 .disable_dmcu = true,
 229                 .force_abm_enable = false,
 230                 .timing_trace = true,
 231                 .clock_trace = true,
 232                 .disable_dpp_power_gate = true,
 233                 .disable_hubp_power_gate = true,
 234                 .disable_clock_gate = true,
 235                 .disable_pplib_clock_request = true,
 236                 .disable_pplib_wm_range = true,
 237                 .disable_stutter = false,
 238                 .scl_reset_length10 = true,
 239                 .dwb_fi_phase = -1, // -1 = disable
 240                 .dmub_command_table = true,
 241                 .enable_tri_buf = true,
 242                 .disable_psr = true,
 243 };
 244
 245 enum dcn302_clk_src_array_id {
 246         DCN302_CLK_SRC_PLL0,
 247         DCN302_CLK_SRC_PLL1,
 248         DCN302_CLK_SRC_PLL2,
 249         DCN302_CLK_SRC_PLL3,
 250         DCN302_CLK_SRC_PLL4,
 251         DCN302_CLK_SRC_TOTAL
 252 };
 253
 254 static const struct resource_caps res_cap_dcn302 = {
 255                 .num_timing_generator = 5,
 256                 .num_opp = 5,
 257                 .num_video_plane = 5,
 258                 .num_audio = 5,
 259                 .num_stream_encoder = 5,
 260                 .num_dwb = 1,
 261                 .num_ddc = 5,
 262                 .num_vmid = 16,
 263                 .num_mpc_3dlut = 2,
 264                 .num_dsc = 5,
 265 };
 266
 267 static const struct dc_plane_cap plane_cap = {
 268                 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
 269                 .blends_with_above = true,
 270                 .blends_with_below = true,
 271                 .per_pixel_alpha = true,
 272                 .pixel_format_support = {
 273                                 .argb8888 = true,
 274                                 .nv12 = true,
 275                                 .fp16 = true,
 276                                 .p010 = false,
 277                                 .ayuv = false,
 278                 },
 279                 .max_upscale_factor = {
 280                                 .argb8888 = 16000,
 281                                 .nv12 = 16000,
 282                                 .fp16 = 16000
 283                 },
 284                 .max_downscale_factor = {
 285                                 .argb8888 = 600,
 286                                 .nv12 = 600,
 287                                 .fp16 = 600
 288                 },
 289                 16,
 290                 16
 291 };
 292
 293 /* NBIO */
 294 #define NBIO_BASE_INNER(seg) \
 295                 NBIO_BASE__INST0_SEG ## seg
 296
 297 #define NBIO_BASE(seg) \
 298                 NBIO_BASE_INNER(seg)
 299
 300 #define NBIO_SR(reg_name)\
 301                 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
 302                 mm ## reg_name
 303
 304 /* DCN */
 305 #undef BASE_INNER
 306 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
 307
 308 #define BASE(seg) BASE_INNER(seg)
 309
 310 #define SR(reg_name)\
 311                 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
 312
 313 #define SF(reg_name, field_name, post_fix)\
 314                 .field_name = reg_name ## __ ## field_name ## post_fix
 315
 316 #define SRI(reg_name, block, id)\
 317                 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name
 318
 319 #define SRI2(reg_name, block, id)\
 320                 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
 321
 322 #define SRII(reg_name, block, id)\
 323                 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 324                 mm ## block ## id ## _ ## reg_name
 325
 326 #define DCCG_SRII(reg_name, block, id)\
 327                 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 328                 mm ## block ## id ## _ ## reg_name
 329
 330 #define VUPDATE_SRII(reg_name, block, id)\
 331                 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
 332                 mm ## reg_name ## _ ## block ## id
 333
 334 #define SRII_DWB(reg_name, temp_name, block, id)\
 335                 .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
 336                 mm ## block ## id ## _ ## temp_name
 337
 338 #define SRII_MPC_RMU(reg_name, block, id)\
 339                 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 340                 mm ## block ## id ## _ ## reg_name
 341
 342 static const struct dcn_hubbub_registers hubbub_reg = {
 343                 HUBBUB_REG_LIST_DCN30(0)
 344 };
 345
 346 static const struct dcn_hubbub_shift hubbub_shift = {
 347                 HUBBUB_MASK_SH_LIST_DCN30(__SHIFT)
 348 };
 349
 350 static const struct dcn_hubbub_mask hubbub_mask = {
 351                 HUBBUB_MASK_SH_LIST_DCN30(_MASK)
 352 };
 353
 354 #define vmid_regs(id)\
 355                 [id] = { DCN20_VMID_REG_LIST(id) }
 356
 357 static const struct dcn_vmid_registers vmid_regs[] = {
 358                 vmid_regs(0),
 359                 vmid_regs(1),
 360                 vmid_regs(2),
 361                 vmid_regs(3),
 362                 vmid_regs(4),
 363                 vmid_regs(5),
 364                 vmid_regs(6),
 365                 vmid_regs(7),
 366                 vmid_regs(8),
 367                 vmid_regs(9),
 368                 vmid_regs(10),
 369                 vmid_regs(11),
 370                 vmid_regs(12),
 371                 vmid_regs(13),
 372                 vmid_regs(14),
 373                 vmid_regs(15)
 374 };
 375
 376 static const struct dcn20_vmid_shift vmid_shifts = {
 377                 DCN20_VMID_MASK_SH_LIST(__SHIFT)
 378 };
 379
 380 static const struct dcn20_vmid_mask vmid_masks = {
 381                 DCN20_VMID_MASK_SH_LIST(_MASK)
 382 };
 383
 384 static struct hubbub *dcn302_hubbub_create(struct dc_context *ctx)
 385 {
 386         int i;
 387
 388         struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), GFP_KERNEL);
 389
 390         if (!hubbub3)
 391                 return NULL;
 392
 393         hubbub3_construct(hubbub3, ctx, &hubbub_reg, &hubbub_shift, &hubbub_mask);
 394
 395         for (i = 0; i < res_cap_dcn302.num_vmid; i++) {
 396                 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
 397
 398                 vmid->ctx = ctx;
 399
 400                 vmid->regs = &vmid_regs[i];
 401                 vmid->shifts = &vmid_shifts;
 402                 vmid->masks = &vmid_masks;
 403         }
 404
 405         return &hubbub3->base;
 406 }
 407
 408 #define vpg_regs(id)\
 409                 [id] = { VPG_DCN3_REG_LIST(id) }
 410
 411 static const struct dcn30_vpg_registers vpg_regs[] = {
 412                 vpg_regs(0),
 413                 vpg_regs(1),
 414                 vpg_regs(2),
 415                 vpg_regs(3),
 416                 vpg_regs(4),
 417                 vpg_regs(5)
 418 };
 419
 420 static const struct dcn30_vpg_shift vpg_shift = {
 421                 DCN3_VPG_MASK_SH_LIST(__SHIFT)
 422 };
 423
 424 static const struct dcn30_vpg_mask vpg_mask = {
 425                 DCN3_VPG_MASK_SH_LIST(_MASK)
 426 };
 427
 428 static struct vpg *dcn302_vpg_create(struct dc_context *ctx, uint32_t inst)
 429 {
 430         struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL);
 431
 432         if (!vpg3)
 433                 return NULL;
 434
 435         vpg3_construct(vpg3, ctx, inst, &vpg_regs[inst], &vpg_shift, &vpg_mask);
 436
 437         return &vpg3->base;
 438 }
 439
 440 #define afmt_regs(id)\
 441                 [id] = { AFMT_DCN3_REG_LIST(id) }
 442
 443 static const struct dcn30_afmt_registers afmt_regs[] = {
 444                 afmt_regs(0),
 445                 afmt_regs(1),
 446                 afmt_regs(2),
 447                 afmt_regs(3),
 448                 afmt_regs(4),
 449                 afmt_regs(5)
 450 };
 451
 452 static const struct dcn30_afmt_shift afmt_shift = {
 453                 DCN3_AFMT_MASK_SH_LIST(__SHIFT)
 454 };
 455
 456 static const struct dcn30_afmt_mask afmt_mask = {
 457                 DCN3_AFMT_MASK_SH_LIST(_MASK)
 458 };
 459
 460 static struct afmt *dcn302_afmt_create(struct dc_context *ctx, uint32_t inst)
 461 {
 462         struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
 463
 464         if (!afmt3)
 465                 return NULL;
 466
 467         afmt3_construct(afmt3, ctx, inst, &afmt_regs[inst], &afmt_shift, &afmt_mask);
 468
 469         return &afmt3->base;
 470 }
 471
 472 #define audio_regs(id)\
 473                 [id] = { AUD_COMMON_REG_LIST(id) }
 474
 475 static const struct dce_audio_registers audio_regs[] = {
 476                 audio_regs(0),
 477                 audio_regs(1),
 478                 audio_regs(2),
 479                 audio_regs(3),
 480                 audio_regs(4),
 481                 audio_regs(5),
 482                 audio_regs(6)
 483 };
 484
 485 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
 486                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
 487                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
 488                 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
 489
 490 static const struct dce_audio_shift audio_shift = {
 491                 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
 492 };
 493
 494 static const struct dce_audio_mask audio_mask = {
 495                 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
 496 };
 497
 498 static struct audio *dcn302_create_audio(struct dc_context *ctx, unsigned int inst)
 499 {
 500         return dce_audio_create(ctx, inst, &audio_regs[inst], &audio_shift, &audio_mask);
 501 }
 502
 503 #define stream_enc_regs(id)\
 504                 [id] = { SE_DCN3_REG_LIST(id) }
 505
 506 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
 507                 stream_enc_regs(0),
 508                 stream_enc_regs(1),
 509                 stream_enc_regs(2),
 510                 stream_enc_regs(3),
 511                 stream_enc_regs(4)
 512 };
 513
 514 static const struct dcn10_stream_encoder_shift se_shift = {
 515                 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 516 };
 517
 518 static const struct dcn10_stream_encoder_mask se_mask = {
 519                 SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
 520 };
 521
 522 static struct stream_encoder *dcn302_stream_encoder_create(enum engine_id eng_id, struct dc_context *ctx)
 523 {
 524         struct dcn10_stream_encoder *enc1;
 525         struct vpg *vpg;
 526         struct afmt *afmt;
 527         int vpg_inst;
 528         int afmt_inst;
 529
 530         /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
 531         if (eng_id <= ENGINE_ID_DIGE) {
 532                 vpg_inst = eng_id;
 533                 afmt_inst = eng_id;
 534         } else
 535                 return NULL;
 536
 537         enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
 538         vpg = dcn302_vpg_create(ctx, vpg_inst);
 539         afmt = dcn302_afmt_create(ctx, afmt_inst);
 540
 541         if (!enc1 || !vpg || !afmt)
 542                 return NULL;
 543
 544         dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, vpg, afmt, &stream_enc_regs[eng_id],
 545                         &se_shift, &se_mask);
 546
 547         return &enc1->base;
 548 }
 549
 550 #define clk_src_regs(index, pllid)\
 551                 [index] = { CS_COMMON_REG_LIST_DCN3_02(index, pllid) }
 552
 553 static const struct dce110_clk_src_regs clk_src_regs[] = {
 554                 clk_src_regs(0, A),
 555                 clk_src_regs(1, B),
 556                 clk_src_regs(2, C),
 557                 clk_src_regs(3, D),
 558                 clk_src_regs(4, E)
 559 };
 560
 561 static const struct dce110_clk_src_shift cs_shift = {
 562                 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
 563 };
 564
 565 static const struct dce110_clk_src_mask cs_mask = {
 566                 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
 567 };
 568
 569 static struct clock_source *dcn302_clock_source_create(struct dc_context *ctx, struct dc_bios *bios,
 570                 enum clock_source_id id, const struct dce110_clk_src_regs *regs, bool dp_clk_src)
 571 {
 572         struct dce110_clk_src *clk_src = kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
 573
 574         if (!clk_src)
 575                 return NULL;
 576
 577         if (dcn3_clk_src_construct(clk_src, ctx, bios, id, regs, &cs_shift, &cs_mask)) {
 578                 clk_src->base.dp_clk_src = dp_clk_src;
 579                 return &clk_src->base;
 580         }
 581
 582         BREAK_TO_DEBUGGER();
 583         return NULL;
 584 }
 585
 586 static const struct dce_hwseq_registers hwseq_reg = {
 587                 HWSEQ_DCN302_REG_LIST()
 588 };
 589
 590 static const struct dce_hwseq_shift hwseq_shift = {
 591                 HWSEQ_DCN302_MASK_SH_LIST(__SHIFT)
 592 };
 593
 594 static const struct dce_hwseq_mask hwseq_mask = {
 595                 HWSEQ_DCN302_MASK_SH_LIST(_MASK)
 596 };
 597
 598 static struct dce_hwseq *dcn302_hwseq_create(struct dc_context *ctx)
 599 {
 600         struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
 601
 602         if (hws) {
 603                 hws->ctx = ctx;
 604                 hws->regs = &hwseq_reg;
 605                 hws->shifts = &hwseq_shift;
 606                 hws->masks = &hwseq_mask;
 607         }
 608         return hws;
 609 }
 610
 611 #define hubp_regs(id)\
 612                 [id] = { HUBP_REG_LIST_DCN30(id) }
 613
 614 static const struct dcn_hubp2_registers hubp_regs[] = {
 615                 hubp_regs(0),
 616                 hubp_regs(1),
 617                 hubp_regs(2),
 618                 hubp_regs(3),
 619                 hubp_regs(4)
 620 };
 621
 622 static const struct dcn_hubp2_shift hubp_shift = {
 623                 HUBP_MASK_SH_LIST_DCN30(__SHIFT)
 624 };
 625
 626 static const struct dcn_hubp2_mask hubp_mask = {
 627                 HUBP_MASK_SH_LIST_DCN30(_MASK)
 628 };
 629
 630 static struct hubp *dcn302_hubp_create(struct dc_context *ctx, uint32_t inst)
 631 {
 632         struct dcn20_hubp *hubp2 = kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
 633
 634         if (!hubp2)
 635                 return NULL;
 636
 637         if (hubp3_construct(hubp2, ctx, inst, &hubp_regs[inst], &hubp_shift, &hubp_mask))
 638                 return &hubp2->base;
 639
 640         BREAK_TO_DEBUGGER();
 641         kfree(hubp2);
 642         return NULL;
 643 }
 644
 645 #define dpp_regs(id)\
 646                 [id] = { DPP_REG_LIST_DCN30(id) }
 647
 648 static const struct dcn3_dpp_registers dpp_regs[] = {
 649                 dpp_regs(0),
 650                 dpp_regs(1),
 651                 dpp_regs(2),
 652                 dpp_regs(3),
 653                 dpp_regs(4)
 654 };
 655
 656 static const struct dcn3_dpp_shift tf_shift = {
 657                 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
 658 };
 659
 660 static const struct dcn3_dpp_mask tf_mask = {
 661                 DPP_REG_LIST_SH_MASK_DCN30(_MASK)
 662 };
 663
 664 static struct dpp *dcn302_dpp_create(struct dc_context *ctx, uint32_t inst)
 665 {
 666         struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
 667
 668         if (!dpp)
 669                 return NULL;
 670
 671         if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask))
 672                 return &dpp->base;
 673
 674         BREAK_TO_DEBUGGER();
 675         kfree(dpp);
 676         return NULL;
 677 }
 678
 679 #define opp_regs(id)\
 680                 [id] = { OPP_REG_LIST_DCN30(id) }
 681
 682 static const struct dcn20_opp_registers opp_regs[] = {
 683                 opp_regs(0),
 684                 opp_regs(1),
 685                 opp_regs(2),
 686                 opp_regs(3),
 687                 opp_regs(4)
 688 };
 689
 690 static const struct dcn20_opp_shift opp_shift = {
 691                 OPP_MASK_SH_LIST_DCN20(__SHIFT)
 692 };
 693
 694 static const struct dcn20_opp_mask opp_mask = {
 695                 OPP_MASK_SH_LIST_DCN20(_MASK)
 696 };
 697
 698 static struct output_pixel_processor *dcn302_opp_create(struct dc_context *ctx, uint32_t inst)
 699 {
 700         struct dcn20_opp *opp = kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
 701
 702         if (!opp) {
 703                 BREAK_TO_DEBUGGER();
 704                 return NULL;
 705         }
 706
 707         dcn20_opp_construct(opp, ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
 708         return &opp->base;
 709 }
 710
 711 #define optc_regs(id)\
 712                 [id] = { OPTC_COMMON_REG_LIST_DCN3_0(id) }
 713
 714 static const struct dcn_optc_registers optc_regs[] = {
 715                 optc_regs(0),
 716                 optc_regs(1),
 717                 optc_regs(2),
 718                 optc_regs(3),
 719                 optc_regs(4)
 720 };
 721
 722 static const struct dcn_optc_shift optc_shift = {
 723                 OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 724 };
 725
 726 static const struct dcn_optc_mask optc_mask = {
 727                 OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK)
 728 };
 729
 730 static struct timing_generator *dcn302_timing_generator_create(struct dc_context *ctx, uint32_t instance)
 731 {
 732         struct optc *tgn10 = kzalloc(sizeof(struct optc), GFP_KERNEL);
 733
 734         if (!tgn10)
 735                 return NULL;
 736
 737         tgn10->base.inst = instance;
 738         tgn10->base.ctx = ctx;
 739
 740         tgn10->tg_regs = &optc_regs[instance];
 741         tgn10->tg_shift = &optc_shift;
 742         tgn10->tg_mask = &optc_mask;
 743
 744         dcn30_timing_generator_init(tgn10);
 745
 746         return &tgn10->base;
 747 }
 748
 749 static const struct dcn30_mpc_registers mpc_regs = {
 750                 MPC_REG_LIST_DCN3_0(0),
 751                 MPC_REG_LIST_DCN3_0(1),
 752                 MPC_REG_LIST_DCN3_0(2),
 753                 MPC_REG_LIST_DCN3_0(3),
 754                 MPC_REG_LIST_DCN3_0(4),
 755                 MPC_OUT_MUX_REG_LIST_DCN3_0(0),
 756                 MPC_OUT_MUX_REG_LIST_DCN3_0(1),
 757                 MPC_OUT_MUX_REG_LIST_DCN3_0(2),
 758                 MPC_OUT_MUX_REG_LIST_DCN3_0(3),
 759                 MPC_OUT_MUX_REG_LIST_DCN3_0(4),
 760                 MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
 761                 MPC_RMU_REG_LIST_DCN3AG(0),
 762                 MPC_RMU_REG_LIST_DCN3AG(1),
 763                 MPC_RMU_REG_LIST_DCN3AG(2),
 764                 MPC_DWB_MUX_REG_LIST_DCN3_0(0),
 765 };
 766
 767 static const struct dcn30_mpc_shift mpc_shift = {
 768                 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 769 };
 770
 771 static const struct dcn30_mpc_mask mpc_mask = {
 772                 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
 773 };
 774
 775 static struct mpc *dcn302_mpc_create(struct dc_context *ctx, int num_mpcc, int num_rmu)
 776 {
 777         struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), GFP_KERNEL);
 778
 779         if (!mpc30)
 780                 return NULL;
 781
 782         dcn30_mpc_construct(mpc30, ctx, &mpc_regs, &mpc_shift, &mpc_mask, num_mpcc, num_rmu);
 783
 784         return &mpc30->base;
 785 }
 786
 787 #define dsc_regsDCN20(id)\
 788 [id] = { DSC_REG_LIST_DCN20(id) }
 789
 790 static const struct dcn20_dsc_registers dsc_regs[] = {
 791                 dsc_regsDCN20(0),
 792                 dsc_regsDCN20(1),
 793                 dsc_regsDCN20(2),
 794                 dsc_regsDCN20(3),
 795                 dsc_regsDCN20(4)
 796 };
 797
 798 static const struct dcn20_dsc_shift dsc_shift = {
 799                 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
 800 };
 801
 802 static const struct dcn20_dsc_mask dsc_mask = {
 803                 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
 804 };
 805
 806 static struct display_stream_compressor *dcn302_dsc_create(struct dc_context *ctx, uint32_t inst)
 807 {
 808         struct dcn20_dsc *dsc = kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
 809
 810         if (!dsc) {
 811                 BREAK_TO_DEBUGGER();
 812                 return NULL;
 813         }
 814
 815         dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
 816         return &dsc->base;
 817 }
 818
 819 #define dwbc_regs_dcn3(id)\
 820 [id] = { DWBC_COMMON_REG_LIST_DCN30(id) }
 821
 822 static const struct dcn30_dwbc_registers dwbc30_regs[] = {
 823                 dwbc_regs_dcn3(0)
 824 };
 825
 826 static const struct dcn30_dwbc_shift dwbc30_shift = {
 827                 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 828 };
 829
 830 static const struct dcn30_dwbc_mask dwbc30_mask = {
 831                 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
 832 };
 833
 834 static bool dcn302_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
 835 {
 836         int i;
 837         uint32_t pipe_count = pool->res_cap->num_dwb;
 838
 839         for (i = 0; i < pipe_count; i++) {
 840                 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), GFP_KERNEL);
 841
 842                 if (!dwbc30) {
 843                         dm_error("DC: failed to create dwbc30!\n");
 844                         return false;
 845                 }
 846
 847                 dcn30_dwbc_construct(dwbc30, ctx, &dwbc30_regs[i], &dwbc30_shift, &dwbc30_mask, i);
 848
 849                 pool->dwbc[i] = &dwbc30->base;
 850         }
 851         return true;
 852 }
 853
 854 #define mcif_wb_regs_dcn3(id)\
 855 [id] = { MCIF_WB_COMMON_REG_LIST_DCN30(id) }
 856
 857 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
 858                 mcif_wb_regs_dcn3(0)
 859 };
 860
 861 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
 862                 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 863 };
 864
 865 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
 866                 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
 867 };
 868
 869 static bool dcn302_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
 870 {
 871         int i;
 872         uint32_t pipe_count = pool->res_cap->num_dwb;
 873
 874         for (i = 0; i < pipe_count; i++) {
 875                 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), GFP_KERNEL);
 876
 877                 if (!mcif_wb30) {
 878                         dm_error("DC: failed to create mcif_wb30!\n");
 879                         return false;
 880                 }
 881
 882                 dcn30_mmhubbub_construct(mcif_wb30, ctx, &mcif_wb30_regs[i], &mcif_wb30_shift, &mcif_wb30_mask, i);
 883
 884                 pool->mcif_wb[i] = &mcif_wb30->base;
 885         }
 886         return true;
 887 }
 888
 889 #define aux_engine_regs(id)\
 890 [id] = {\
 891                 AUX_COMMON_REG_LIST0(id), \
 892                 .AUXN_IMPCAL = 0, \
 893                 .AUXP_IMPCAL = 0, \
 894                 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
 895 }
 896
 897 static const struct dce110_aux_registers aux_engine_regs[] = {
 898                 aux_engine_regs(0),
 899                 aux_engine_regs(1),
 900                 aux_engine_regs(2),
 901                 aux_engine_regs(3),
 902                 aux_engine_regs(4)
 903 };
 904
 905 static const struct dce110_aux_registers_shift aux_shift = {
 906                 DCN_AUX_MASK_SH_LIST(__SHIFT)
 907 };
 908
 909 static const struct dce110_aux_registers_mask aux_mask = {
 910                 DCN_AUX_MASK_SH_LIST(_MASK)
 911 };
 912
 913 static struct dce_aux *dcn302_aux_engine_create(struct dc_context *ctx, uint32_t inst)
 914 {
 915         struct aux_engine_dce110 *aux_engine = kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
 916
 917         if (!aux_engine)
 918                 return NULL;
 919
 920         dce110_aux_engine_construct(aux_engine, ctx, inst, SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
 921                         &aux_engine_regs[inst], &aux_mask, &aux_shift, ctx->dc->caps.extended_aux_timeout_support);
 922
 923         return &aux_engine->base;
 924 }
 925
 926 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
 927
 928 static const struct dce_i2c_registers i2c_hw_regs[] = {
 929                 i2c_inst_regs(1),
 930                 i2c_inst_regs(2),
 931                 i2c_inst_regs(3),
 932                 i2c_inst_regs(4),
 933                 i2c_inst_regs(5)
 934 };
 935
 936 static const struct dce_i2c_shift i2c_shifts = {
 937                 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
 938 };
 939
 940 static const struct dce_i2c_mask i2c_masks = {
 941                 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
 942 };
 943
 944 static struct dce_i2c_hw *dcn302_i2c_hw_create(struct dc_context *ctx, uint32_t inst)
 945 {
 946         struct dce_i2c_hw *dce_i2c_hw = kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
 947
 948         if (!dce_i2c_hw)
 949                 return NULL;
 950
 951         dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
 952
 953         return dce_i2c_hw;
 954 }
 955
 956 static const struct encoder_feature_support link_enc_feature = {
 957                 .max_hdmi_deep_color = COLOR_DEPTH_121212,
 958                 .max_hdmi_pixel_clock = 600000,
 959                 .hdmi_ycbcr420_supported = true,
 960                 .dp_ycbcr420_supported = true,
 961                 .fec_supported = true,
 962                 .flags.bits.IS_HBR2_CAPABLE = true,
 963                 .flags.bits.IS_HBR3_CAPABLE = true,
 964                 .flags.bits.IS_TPS3_CAPABLE = true,
 965                 .flags.bits.IS_TPS4_CAPABLE = true
 966 };
 967
 968 #define link_regs(id, phyid)\
 969                 [id] = {\
 970                                 LE_DCN3_REG_LIST(id), \
 971                                 UNIPHY_DCN2_REG_LIST(phyid), \
 972                                 DPCS_DCN2_REG_LIST(id), \
 973                                 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
 974                 }
 975
 976 static const struct dcn10_link_enc_registers link_enc_regs[] = {
 977                 link_regs(0, A),
 978                 link_regs(1, B),
 979                 link_regs(2, C),
 980                 link_regs(3, D),
 981                 link_regs(4, E)
 982 };
 983
 984 static const struct dcn10_link_enc_shift le_shift = {
 985                 LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT),
 986                 DPCS_DCN2_MASK_SH_LIST(__SHIFT)
 987 };
 988
 989 static const struct dcn10_link_enc_mask le_mask = {
 990                 LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK),
 991                 DPCS_DCN2_MASK_SH_LIST(_MASK)
 992 };
 993
 994 #define aux_regs(id)\
 995                 [id] = { DCN2_AUX_REG_LIST(id) }
 996
 997 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
 998                 aux_regs(0),
 999                 aux_regs(1),
1000                 aux_regs(2),
1001                 aux_regs(3),
1002                 aux_regs(4)
1003 };
1004
1005 #define hpd_regs(id)\
1006                 [id] = { HPD_REG_LIST(id) }
1007
1008 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
1009                 hpd_regs(0),
1010                 hpd_regs(1),
1011                 hpd_regs(2),
1012                 hpd_regs(3),
1013                 hpd_regs(4)
1014 };
1015
1016 static struct link_encoder *dcn302_link_encoder_create(const struct encoder_init_data *enc_init_data)
1017 {
1018         struct dcn20_link_encoder *enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1019
1020         if (!enc20)
1021                 return NULL;
1022
1023         dcn30_link_encoder_construct(enc20, enc_init_data, &link_enc_feature,
1024                         &link_enc_regs[enc_init_data->transmitter], &link_enc_aux_regs[enc_init_data->channel - 1],
1025                         &link_enc_hpd_regs[enc_init_data->hpd_source], &le_shift, &le_mask);
1026
1027         return &enc20->enc10.base;
1028 }
1029
1030 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
1031                 { DCN_PANEL_CNTL_REG_LIST() }
1032 };
1033
1034 static const struct dce_panel_cntl_shift panel_cntl_shift = {
1035                 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
1036 };
1037
1038 static const struct dce_panel_cntl_mask panel_cntl_mask = {
1039                 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
1040 };
1041
1042 static struct panel_cntl *dcn302_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1043 {
1044         struct dce_panel_cntl *panel_cntl = kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
1045
1046         if (!panel_cntl)
1047                 return NULL;
1048
1049         dce_panel_cntl_construct(panel_cntl, init_data, &panel_cntl_regs[init_data->inst],
1050                         &panel_cntl_shift, &panel_cntl_mask);
1051
1052         return &panel_cntl->base;
1053 }
1054
1055 static void read_dce_straps(struct dc_context *ctx, struct resource_straps *straps)
1056 {
1057         generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
1058                         FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1059 }
1060
1061 static const struct resource_create_funcs res_create_funcs = {
1062                 .read_dce_straps = read_dce_straps,
1063                 .create_audio = dcn302_create_audio,
1064                 .create_stream_encoder = dcn302_stream_encoder_create,
1065                 .create_hwseq = dcn302_hwseq_create,
1066 };
1067
1068 static const struct resource_create_funcs res_create_maximus_funcs = {
1069                 .read_dce_straps = NULL,
1070                 .create_audio = NULL,
1071                 .create_stream_encoder = NULL,
1072                 .create_hwseq = dcn302_hwseq_create,
1073 };
1074
1075 static bool is_soc_bounding_box_valid(struct dc *dc)
1076 {
1077         uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;
1078
1079         if (ASICREV_IS_DIMGREY_CAVEFISH_P(hw_internal_rev))
1080                 return true;
1081
1082         return false;
1083 }
1084
1085 static bool init_soc_bounding_box(struct dc *dc,  struct resource_pool *pool)
1086 {
1087         struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_02_soc;
1088         struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_02_ip;
1089
1090         DC_LOGGER_INIT(dc->ctx->logger);
1091
1092         if (!is_soc_bounding_box_valid(dc)) {
1093                 DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__);
1094                 return false;
1095         }
1096
1097         loaded_ip->max_num_otg = pool->pipe_count;
1098         loaded_ip->max_num_dpp = pool->pipe_count;
1099         loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
1100         dcn20_patch_bounding_box(dc, loaded_bb);
1101         return true;
1102 }
1103
1104 static void dcn302_resource_destruct(struct resource_pool *pool)
1105 {
1106         unsigned int i;
1107
1108         for (i = 0; i < pool->stream_enc_count; i++) {
1109                 if (pool->stream_enc[i] != NULL) {
1110                         if (pool->stream_enc[i]->vpg != NULL) {
1111                                 kfree(DCN30_VPG_FROM_VPG(pool->stream_enc[i]->vpg));
1112                                 pool->stream_enc[i]->vpg = NULL;
1113                         }
1114                         if (pool->stream_enc[i]->afmt != NULL) {
1115                                 kfree(DCN30_AFMT_FROM_AFMT(pool->stream_enc[i]->afmt));
1116                                 pool->stream_enc[i]->afmt = NULL;
1117                         }
1118                         kfree(DCN10STRENC_FROM_STRENC(pool->stream_enc[i]));
1119                         pool->stream_enc[i] = NULL;
1120                 }
1121         }
1122
1123         for (i = 0; i < pool->res_cap->num_dsc; i++) {
1124                 if (pool->dscs[i] != NULL)
1125                         dcn20_dsc_destroy(&pool->dscs[i]);
1126         }
1127
1128         if (pool->mpc != NULL) {
1129                 kfree(TO_DCN20_MPC(pool->mpc));
1130                 pool->mpc = NULL;
1131         }
1132
1133         if (pool->hubbub != NULL) {
1134                 kfree(pool->hubbub);
1135                 pool->hubbub = NULL;
1136         }
1137
1138         for (i = 0; i < pool->pipe_count; i++) {
1139                 if (pool->dpps[i] != NULL) {
1140                         kfree(TO_DCN20_DPP(pool->dpps[i]));
1141                         pool->dpps[i] = NULL;
1142                 }
1143
1144                 if (pool->hubps[i] != NULL) {
1145                         kfree(TO_DCN20_HUBP(pool->hubps[i]));
1146                         pool->hubps[i] = NULL;
1147                 }
1148
1149                 if (pool->irqs != NULL)
1150                         dal_irq_service_destroy(&pool->irqs);
1151         }
1152
1153         for (i = 0; i < pool->res_cap->num_ddc; i++) {
1154                 if (pool->engines[i] != NULL)
1155                         dce110_engine_destroy(&pool->engines[i]);
1156                 if (pool->hw_i2cs[i] != NULL) {
1157                         kfree(pool->hw_i2cs[i]);
1158                         pool->hw_i2cs[i] = NULL;
1159                 }
1160                 if (pool->sw_i2cs[i] != NULL) {
1161                         kfree(pool->sw_i2cs[i]);
1162                         pool->sw_i2cs[i] = NULL;
1163                 }
1164         }
1165
1166         for (i = 0; i < pool->res_cap->num_opp; i++) {
1167                 if (pool->opps[i] != NULL)
1168                         pool->opps[i]->funcs->opp_destroy(&pool->opps[i]);
1169         }
1170
1171         for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
1172                 if (pool->timing_generators[i] != NULL) {
1173                         kfree(DCN10TG_FROM_TG(pool->timing_generators[i]));
1174                         pool->timing_generators[i] = NULL;
1175                 }
1176         }
1177
1178         for (i = 0; i < pool->res_cap->num_dwb; i++) {
1179                 if (pool->dwbc[i] != NULL) {
1180                         kfree(TO_DCN30_DWBC(pool->dwbc[i]));
1181                         pool->dwbc[i] = NULL;
1182                 }
1183                 if (pool->mcif_wb[i] != NULL) {
1184                         kfree(TO_DCN30_MMHUBBUB(pool->mcif_wb[i]));
1185                         pool->mcif_wb[i] = NULL;
1186                 }
1187         }
1188
1189         for (i = 0; i < pool->audio_count; i++) {
1190                 if (pool->audios[i])
1191                         dce_aud_destroy(&pool->audios[i]);
1192         }
1193
1194         for (i = 0; i < pool->clk_src_count; i++) {
1195                 if (pool->clock_sources[i] != NULL)
1196                         dcn20_clock_source_destroy(&pool->clock_sources[i]);
1197         }
1198
1199         if (pool->dp_clock_source != NULL)
1200                 dcn20_clock_source_destroy(&pool->dp_clock_source);
1201
1202         for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
1203                 if (pool->mpc_lut[i] != NULL) {
1204                         dc_3dlut_func_release(pool->mpc_lut[i]);
1205                         pool->mpc_lut[i] = NULL;
1206                 }
1207                 if (pool->mpc_shaper[i] != NULL) {
1208                         dc_transfer_func_release(pool->mpc_shaper[i]);
1209                         pool->mpc_shaper[i] = NULL;
1210                 }
1211         }
1212
1213         for (i = 0; i < pool->pipe_count; i++) {
1214                 if (pool->multiple_abms[i] != NULL)
1215                         dce_abm_destroy(&pool->multiple_abms[i]);
1216         }
1217
1218         if (pool->psr != NULL)
1219                 dmub_psr_destroy(&pool->psr);
1220
1221         if (pool->dccg != NULL)
1222                 dcn_dccg_destroy(&pool->dccg);
1223 }
1224
1225 static void dcn302_destroy_resource_pool(struct resource_pool **pool)
1226 {
1227         dcn302_resource_destruct(*pool);
1228         kfree(*pool);
1229         *pool = NULL;
1230 }
1231
1232 static struct resource_funcs dcn302_res_pool_funcs = {
1233                 .destroy = dcn302_destroy_resource_pool,
1234                 .link_enc_create = dcn302_link_encoder_create,
1235                 .panel_cntl_create = dcn302_panel_cntl_create,
1236                 .validate_bandwidth = dcn30_validate_bandwidth,
1237                 .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg,
1238                 .populate_dml_pipes = dcn30_populate_dml_pipes_from_context,
1239                 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
1240                 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1241                 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1242                 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1243                 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1244                 .set_mcif_arb_params = dcn30_set_mcif_arb_params,
1245                 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1246                 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1247                 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1248                 .update_bw_bounding_box = dcn30_update_bw_bounding_box,
1249                 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1250 };
1251
1252 static struct dc_cap_funcs cap_funcs = {
1253                 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1254 };
1255
1256 static const struct bios_registers bios_regs = {
1257                 NBIO_SR(BIOS_SCRATCH_3),
1258                 NBIO_SR(BIOS_SCRATCH_6)
1259 };
1260
1261 static const struct dccg_registers dccg_regs = {
1262                 DCCG_REG_LIST_DCN3_02()
1263 };
1264
1265 static const struct dccg_shift dccg_shift = {
1266                 DCCG_MASK_SH_LIST_DCN3_02(__SHIFT)
1267 };
1268
1269 static const struct dccg_mask dccg_mask = {
1270                 DCCG_MASK_SH_LIST_DCN3_02(_MASK)
1271 };
1272
1273 #define abm_regs(id)\
1274                 [id] = { ABM_DCN301_REG_LIST(id) }
1275
1276 static const struct dce_abm_registers abm_regs[] = {
1277                 abm_regs(0),
1278                 abm_regs(1),
1279                 abm_regs(2),
1280                 abm_regs(3),
1281                 abm_regs(4)
1282 };
1283
1284 static const struct dce_abm_shift abm_shift = {
1285                 ABM_MASK_SH_LIST_DCN30(__SHIFT)
1286 };
1287
1288 static const struct dce_abm_mask abm_mask = {
1289                 ABM_MASK_SH_LIST_DCN30(_MASK)
1290 };
1291
1292 static bool dcn302_resource_construct(
1293                 uint8_t num_virtual_links,
1294                 struct dc *dc,
1295                 struct resource_pool *pool)
1296 {
1297         int i;
1298         struct dc_context *ctx = dc->ctx;
1299         struct irq_service_init_data init_data;
1300
1301         ctx->dc_bios->regs = &bios_regs;
1302
1303         pool->res_cap = &res_cap_dcn302;
1304
1305         pool->funcs = &dcn302_res_pool_funcs;
1306
1307         /*************************************************
1308          *  Resource + asic cap harcoding                *
1309          *************************************************/
1310         pool->underlay_pipe_index = NO_UNDERLAY_PIPE;
1311         pool->pipe_count = pool->res_cap->num_timing_generator;
1312         pool->mpcc_count = pool->res_cap->num_timing_generator;
1313         dc->caps.max_downscale_ratio = 600;
1314         dc->caps.i2c_speed_in_khz = 100;
1315         dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by derfault*/
1316         dc->caps.max_cursor_size = 256;
1317         dc->caps.min_horizontal_blanking_period = 80;
1318         dc->caps.dmdata_alloc_size = 2048;
1319
1320         dc->caps.max_slave_planes = 1;
1321         dc->caps.post_blend_color_processing = true;
1322         dc->caps.force_dp_tps4_for_cp2520 = true;
1323         dc->caps.extended_aux_timeout_support = true;
1324         dc->caps.dmcub_support = true;
1325
1326         /* Color pipeline capabilities */
1327         dc->caps.color.dpp.dcn_arch = 1;
1328         dc->caps.color.dpp.input_lut_shared = 0;
1329         dc->caps.color.dpp.icsc = 1;
1330         dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1331         dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1332         dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1333         dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1334         dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1335         dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1336         dc->caps.color.dpp.post_csc = 1;
1337         dc->caps.color.dpp.gamma_corr = 1;
1338         dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1339
1340         dc->caps.color.dpp.hw_3d_lut = 1;
1341         dc->caps.color.dpp.ogam_ram = 1;
1342         // no OGAM ROM on DCN3
1343         dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1344         dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1345         dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1346         dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1347         dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1348         dc->caps.color.dpp.ocsc = 0;
1349
1350         dc->caps.color.mpc.gamut_remap = 1;
1351         dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut; //3
1352         dc->caps.color.mpc.ogam_ram = 1;
1353         dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1354         dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1355         dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1356         dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1357         dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1358         dc->caps.color.mpc.ocsc = 1;
1359
1360         if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1361                 dc->debug = debug_defaults_drv;
1362         else
1363                 dc->debug = debug_defaults_diags;
1364
1365         // Init the vm_helper
1366         if (dc->vm_helper)
1367                 vm_helper_init(dc->vm_helper, 16);
1368
1369         /*************************************************
1370          *  Create resources                             *
1371          *************************************************/
1372
1373         /* Clock Sources for Pixel Clock*/
1374         pool->clock_sources[DCN302_CLK_SRC_PLL0] =
1375                         dcn302_clock_source_create(ctx, ctx->dc_bios,
1376                                         CLOCK_SOURCE_COMBO_PHY_PLL0,
1377                                         &clk_src_regs[0], false);
1378         pool->clock_sources[DCN302_CLK_SRC_PLL1] =
1379                         dcn302_clock_source_create(ctx, ctx->dc_bios,
1380                                         CLOCK_SOURCE_COMBO_PHY_PLL1,
1381                                         &clk_src_regs[1], false);
1382         pool->clock_sources[DCN302_CLK_SRC_PLL2] =
1383                         dcn302_clock_source_create(ctx, ctx->dc_bios,
1384                                         CLOCK_SOURCE_COMBO_PHY_PLL2,
1385                                         &clk_src_regs[2], false);
1386         pool->clock_sources[DCN302_CLK_SRC_PLL3] =
1387                         dcn302_clock_source_create(ctx, ctx->dc_bios,
1388                                         CLOCK_SOURCE_COMBO_PHY_PLL3,
1389                                         &clk_src_regs[3], false);
1390         pool->clock_sources[DCN302_CLK_SRC_PLL4] =
1391                         dcn302_clock_source_create(ctx, ctx->dc_bios,
1392                                         CLOCK_SOURCE_COMBO_PHY_PLL4,
1393                                         &clk_src_regs[4], false);
1394
1395         pool->clk_src_count = DCN302_CLK_SRC_TOTAL;
1396
1397         /* todo: not reuse phy_pll registers */
1398         pool->dp_clock_source =
1399                         dcn302_clock_source_create(ctx, ctx->dc_bios,
1400                                         CLOCK_SOURCE_ID_DP_DTO,
1401                                         &clk_src_regs[0], true);
1402
1403         for (i = 0; i < pool->clk_src_count; i++) {
1404                 if (pool->clock_sources[i] == NULL) {
1405                         dm_error("DC: failed to create clock sources!\n");
1406                         BREAK_TO_DEBUGGER();
1407                         goto create_fail;
1408                 }
1409         }
1410
1411         /* DCCG */
1412         pool->dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1413         if (pool->dccg == NULL) {
1414                 dm_error("DC: failed to create dccg!\n");
1415                 BREAK_TO_DEBUGGER();
1416                 goto create_fail;
1417         }
1418
1419         /* PP Lib and SMU interfaces */
1420         init_soc_bounding_box(dc, pool);
1421
1422         /* DML */
1423         dml_init_instance(&dc->dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30);
1424
1425         /* IRQ */
1426         init_data.ctx = dc->ctx;
1427         pool->irqs = dal_irq_service_dcn302_create(&init_data);
1428         if (!pool->irqs)
1429                 goto create_fail;
1430
1431         /* HUBBUB */
1432         pool->hubbub = dcn302_hubbub_create(ctx);
1433         if (pool->hubbub == NULL) {
1434                 BREAK_TO_DEBUGGER();
1435                 dm_error("DC: failed to create hubbub!\n");
1436                 goto create_fail;
1437         }
1438
1439         /* HUBPs, DPPs, OPPs and TGs */
1440         for (i = 0; i < pool->pipe_count; i++) {
1441                 pool->hubps[i] = dcn302_hubp_create(ctx, i);
1442                 if (pool->hubps[i] == NULL) {
1443                         BREAK_TO_DEBUGGER();
1444                         dm_error("DC: failed to create hubps!\n");
1445                         goto create_fail;
1446                 }
1447
1448                 pool->dpps[i] = dcn302_dpp_create(ctx, i);
1449                 if (pool->dpps[i] == NULL) {
1450                         BREAK_TO_DEBUGGER();
1451                         dm_error("DC: failed to create dpps!\n");
1452                         goto create_fail;
1453                 }
1454         }
1455
1456         for (i = 0; i < pool->res_cap->num_opp; i++) {
1457                 pool->opps[i] = dcn302_opp_create(ctx, i);
1458                 if (pool->opps[i] == NULL) {
1459                         BREAK_TO_DEBUGGER();
1460                         dm_error("DC: failed to create output pixel processor!\n");
1461                         goto create_fail;
1462                 }
1463         }
1464
1465         for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
1466                 pool->timing_generators[i] = dcn302_timing_generator_create(ctx, i);
1467                 if (pool->timing_generators[i] == NULL) {
1468                         BREAK_TO_DEBUGGER();
1469                         dm_error("DC: failed to create tg!\n");
1470                         goto create_fail;
1471                 }
1472         }
1473         pool->timing_generator_count = i;
1474
1475         /* PSR */
1476         pool->psr = dmub_psr_create(ctx);
1477         if (pool->psr == NULL) {
1478                 dm_error("DC: failed to create psr!\n");
1479                 BREAK_TO_DEBUGGER();
1480                 goto create_fail;
1481         }
1482
1483         /* ABMs */
1484         for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
1485                 pool->multiple_abms[i] = dmub_abm_create(ctx, &abm_regs[i], &abm_shift, &abm_mask);
1486                 if (pool->multiple_abms[i] == NULL) {
1487                         dm_error("DC: failed to create abm for pipe %d!\n", i);
1488                         BREAK_TO_DEBUGGER();
1489                         goto create_fail;
1490                 }
1491         }
1492
1493         /* MPC and DSC */
1494         pool->mpc = dcn302_mpc_create(ctx, pool->mpcc_count, pool->res_cap->num_mpc_3dlut);
1495         if (pool->mpc == NULL) {
1496                 BREAK_TO_DEBUGGER();
1497                 dm_error("DC: failed to create mpc!\n");
1498                 goto create_fail;
1499         }
1500
1501         for (i = 0; i < pool->res_cap->num_dsc; i++) {
1502                 pool->dscs[i] = dcn302_dsc_create(ctx, i);
1503                 if (pool->dscs[i] == NULL) {
1504                         BREAK_TO_DEBUGGER();
1505                         dm_error("DC: failed to create display stream compressor %d!\n", i);
1506                         goto create_fail;
1507                 }
1508         }
1509
1510         /* DWB and MMHUBBUB */
1511         if (!dcn302_dwbc_create(ctx, pool)) {
1512                 BREAK_TO_DEBUGGER();
1513                 dm_error("DC: failed to create dwbc!\n");
1514                 goto create_fail;
1515         }
1516
1517         if (!dcn302_mmhubbub_create(ctx, pool)) {
1518                 BREAK_TO_DEBUGGER();
1519                 dm_error("DC: failed to create mcif_wb!\n");
1520                 goto create_fail;
1521         }
1522
1523         /* AUX and I2C */
1524         for (i = 0; i < pool->res_cap->num_ddc; i++) {
1525                 pool->engines[i] = dcn302_aux_engine_create(ctx, i);
1526                 if (pool->engines[i] == NULL) {
1527                         BREAK_TO_DEBUGGER();
1528                         dm_error("DC:failed to create aux engine!!\n");
1529                         goto create_fail;
1530                 }
1531                 pool->hw_i2cs[i] = dcn302_i2c_hw_create(ctx, i);
1532                 if (pool->hw_i2cs[i] == NULL) {
1533                         BREAK_TO_DEBUGGER();
1534                         dm_error("DC:failed to create hw i2c!!\n");
1535                         goto create_fail;
1536                 }
1537                 pool->sw_i2cs[i] = NULL;
1538         }
1539
1540         /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
1541         if (!resource_construct(num_virtual_links, dc, pool,
1542                         (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
1543                                         &res_create_funcs : &res_create_maximus_funcs)))
1544                 goto create_fail;
1545
1546         /* HW Sequencer and Plane caps */
1547         dcn302_hw_sequencer_construct(dc);
1548
1549         dc->caps.max_planes =  pool->pipe_count;
1550
1551         for (i = 0; i < dc->caps.max_planes; ++i)
1552                 dc->caps.planes[i] = plane_cap;
1553
1554         dc->cap_funcs = cap_funcs;
1555
1556         return true;
1557
1558 create_fail:
1559
1560         dcn302_resource_destruct(pool);
1561
1562         return false;
1563 }
1564
1565 struct resource_pool *dcn302_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc)
1566 {
1567         struct resource_pool *pool = kzalloc(sizeof(struct resource_pool), GFP_KERNEL);
1568
1569         if (!pool)
1570                 return NULL;
1571
1572         if (dcn302_resource_construct(init_data->num_virtual_links, dc, pool))
1573                 return pool;
1574
1575         BREAK_TO_DEBUGGER();
1576         kfree(pool);
1577         return NULL;
1578 }