drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c

   1 /*
   2  * Copyright 2020 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26
  27 #include "dm_services.h"
  28 #include "dc.h"
  29
  30 #include "dcn301_init.h"
  31
  32 #include "resource.h"
  33 #include "include/irq_service_interface.h"
  34 #include "dcn30/dcn30_resource.h"
  35 #include "dcn301_resource.h"
  36
  37 #include "dcn20/dcn20_resource.h"
  38
  39 #include "dcn10/dcn10_ipp.h"
  40 #include "dcn301/dcn301_hubbub.h"
  41 #include "dcn30/dcn30_mpc.h"
  42 #include "dcn30/dcn30_hubp.h"
  43 #include "irq/dcn30/irq_service_dcn30.h"
  44 #include "dcn30/dcn30_dpp.h"
  45 #include "dcn30/dcn30_optc.h"
  46 #include "dcn20/dcn20_hwseq.h"
  47 #include "dcn30/dcn30_hwseq.h"
  48 #include "dce110/dce110_hw_sequencer.h"
  49 #include "dcn30/dcn30_opp.h"
  50 #include "dcn20/dcn20_dsc.h"
  51 #include "dcn30/dcn30_vpg.h"
  52 #include "dcn30/dcn30_afmt.h"
  53 #include "dce/dce_clock_source.h"
  54 #include "dce/dce_audio.h"
  55 #include "dce/dce_hwseq.h"
  56 #include "clk_mgr.h"
  57 #include "virtual/virtual_stream_encoder.h"
  58 #include "dce110/dce110_resource.h"
  59 #include "dml/display_mode_vba.h"
  60 #include "dcn301/dcn301_dccg.h"
  61 #include "dcn10/dcn10_resource.h"
  62 #include "dcn30/dcn30_dio_stream_encoder.h"
  63 #include "dcn301/dcn301_dio_link_encoder.h"
  64 #include "dcn301_panel_cntl.h"
  65
  66 #include "vangogh_ip_offset.h"
  67
  68 #include "dcn30/dcn30_dwb.h"
  69 #include "dcn30/dcn30_mmhubbub.h"
  70
  71 #include "dcn/dcn_3_0_1_offset.h"
  72 #include "dcn/dcn_3_0_1_sh_mask.h"
  73
  74 #include "nbio/nbio_7_2_0_offset.h"
  75
  76 #include "reg_helper.h"
  77 #include "dce/dmub_abm.h"
  78 #include "dce/dce_aux.h"
  79 #include "dce/dce_i2c.h"
  80
  81 #include "dml/dcn30/display_mode_vba_30.h"
  82 #include "vm_helper.h"
  83 #include "dcn20/dcn20_vmid.h"
  84 #include "amdgpu_socbb.h"
  85
  86 #define TO_DCN301_RES_POOL(pool)\
  87         container_of(pool, struct dcn301_resource_pool, base)
  88
  89 #define DC_LOGGER_INIT(logger)
  90
  91 struct _vcs_dpi_ip_params_st dcn3_01_ip = {
  92         .odm_capable = 1,
  93         .gpuvm_enable = 1,
  94         .hostvm_enable = 1,
  95         .gpuvm_max_page_table_levels = 1,
  96         .hostvm_max_page_table_levels = 2,
  97         .hostvm_cached_page_table_levels = 0,
  98         .pte_group_size_bytes = 2048,
  99         .num_dsc = 3,
 100         .rob_buffer_size_kbytes = 184,
 101         .det_buffer_size_kbytes = 184,
 102         .dpte_buffer_size_in_pte_reqs_luma = 64,
 103         .dpte_buffer_size_in_pte_reqs_chroma = 32,
 104         .pde_proc_buffer_size_64k_reqs = 48,
 105         .dpp_output_buffer_pixels = 2560,
 106         .opp_output_buffer_lines = 1,
 107         .pixel_chunk_size_kbytes = 8,
 108         .meta_chunk_size_kbytes = 2,
 109         .writeback_chunk_size_kbytes = 8,
 110         .line_buffer_size_bits = 789504,
 111         .is_line_buffer_bpp_fixed = 0,  // ?
 112         .line_buffer_fixed_bpp = 48,     // ?
 113         .dcc_supported = true,
 114         .writeback_interface_buffer_size_kbytes = 90,
 115         .writeback_line_buffer_buffer_size = 656640,
 116         .max_line_buffer_lines = 12,
 117         .writeback_luma_buffer_size_kbytes = 12,  // writeback_line_buffer_buffer_size = 656640
 118         .writeback_chroma_buffer_size_kbytes = 8,
 119         .writeback_chroma_line_buffer_width_pixels = 4,
 120         .writeback_max_hscl_ratio = 1,
 121         .writeback_max_vscl_ratio = 1,
 122         .writeback_min_hscl_ratio = 1,
 123         .writeback_min_vscl_ratio = 1,
 124         .writeback_max_hscl_taps = 1,
 125         .writeback_max_vscl_taps = 1,
 126         .writeback_line_buffer_luma_buffer_size = 0,
 127         .writeback_line_buffer_chroma_buffer_size = 14643,
 128         .cursor_buffer_size = 8,
 129         .cursor_chunk_size = 2,
 130         .max_num_otg = 4,
 131         .max_num_dpp = 4,
 132         .max_num_wb = 1,
 133         .max_dchub_pscl_bw_pix_per_clk = 4,
 134         .max_pscl_lb_bw_pix_per_clk = 2,
 135         .max_lb_vscl_bw_pix_per_clk = 4,
 136         .max_vscl_hscl_bw_pix_per_clk = 4,
 137         .max_hscl_ratio = 6,
 138         .max_vscl_ratio = 6,
 139         .hscl_mults = 4,
 140         .vscl_mults = 4,
 141         .max_hscl_taps = 8,
 142         .max_vscl_taps = 8,
 143         .dispclk_ramp_margin_percent = 1,
 144         .underscan_factor = 1.11,
 145         .min_vblank_lines = 32,
 146         .dppclk_delay_subtotal = 46,
 147         .dynamic_metadata_vm_enabled = true,
 148         .dppclk_delay_scl_lb_only = 16,
 149         .dppclk_delay_scl = 50,
 150         .dppclk_delay_cnvc_formatter = 27,
 151         .dppclk_delay_cnvc_cursor = 6,
 152         .dispclk_delay_subtotal = 119,
 153         .dcfclk_cstate_latency = 5.2, // SRExitTime
 154         .max_inter_dcn_tile_repeaters = 8,
 155         .max_num_hdmi_frl_outputs = 0,
 156         .odm_combine_4to1_supported = true,
 157
 158         .xfc_supported = false,
 159         .xfc_fill_bw_overhead_percent = 10.0,
 160         .xfc_fill_constant_bytes = 0,
 161         .gfx7_compat_tiling_supported = 0,
 162         .number_of_cursors = 1,
 163 };
 164
 165 struct _vcs_dpi_soc_bounding_box_st dcn3_01_soc = {
 166         .clock_limits = {
 167                         /*TODO: fill out defaults once wm plociy is settled*/
 168                         {
 169                                 .state = 0,
 170                                 .dcfclk_mhz = 810.0,
 171                                 .fabricclk_mhz = 1200.0,
 172                                 .dispclk_mhz = 1015.0,
 173                                 .dppclk_mhz = 1015.0,
 174                                 .phyclk_mhz = 810.0,
 175                                 .socclk_mhz = 1000.0,
 176                                 .dscclk_mhz = 338.0,
 177                                 .dram_speed_mts = 4266.0,
 178                         },
 179                         {
 180                                 .state = 1,
 181                                 .dcfclk_mhz = 810.0,
 182                                 .fabricclk_mhz = 1200.0,
 183                                 .dispclk_mhz = 1015.0,
 184                                 .dppclk_mhz = 1015.0,
 185                                 .phyclk_mhz = 810.0,
 186                                 .socclk_mhz = 1000.0,
 187                                 .dscclk_mhz = 338.0,
 188                                 .dram_speed_mts = 4266.0,
 189                         }
 190                 },
 191
 192         .sr_exit_time_us = 9.0,
 193         .sr_enter_plus_exit_time_us = 11.0,
 194         .urgent_latency_us = 4.0,
 195         .urgent_latency_pixel_data_only_us = 4.0,
 196         .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
 197         .urgent_latency_vm_data_only_us = 4.0,
 198         .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
 199         .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
 200         .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
 201         .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0,
 202         .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 75.0,
 203         .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
 204         .max_avg_sdp_bw_use_normal_percent = 60.0,
 205         .max_avg_dram_bw_use_normal_percent = 60.0,
 206         .writeback_latency_us = 12.0,
 207         .max_request_size_bytes = 256,
 208         .dram_channel_width_bytes = 4,
 209         .fabric_datapath_to_dcn_data_return_bytes = 32,
 210         .dcn_downspread_percent = 0.5,
 211         .downspread_percent = 0.38,
 212         .dram_page_open_time_ns = 50.0,
 213         .dram_rw_turnaround_time_ns = 17.5,
 214         .dram_return_buffer_per_channel_bytes = 8192,
 215         .round_trip_ping_latency_dcfclk_cycles = 191,
 216         .urgent_out_of_order_return_per_channel_bytes = 4096,
 217         .channel_interleave_bytes = 256,
 218         .num_banks = 8,
 219         .num_chans = 4,
 220         .gpuvm_min_page_size_bytes = 4096,
 221         .hostvm_min_page_size_bytes = 4096,
 222         .dram_clock_change_latency_us = 23.84,
 223         .writeback_dram_clock_change_latency_us = 23.0,
 224         .return_bus_width_bytes = 64,
 225         .dispclk_dppclk_vco_speed_mhz = 3550,
 226         .xfc_bus_transport_time_us = 20,      // ?
 227         .xfc_xbuf_latency_tolerance_us = 4,  // ?
 228         .use_urgent_burst_bw = 1,            // ?
 229         .num_states = 2,
 230         .do_urgent_latency_adjustment = false,
 231         .urgent_latency_adjustment_fabric_clock_component_us = 0,
 232         .urgent_latency_adjustment_fabric_clock_reference_mhz = 0,
 233 };
 234
 235 enum dcn301_clk_src_array_id {
 236         DCN301_CLK_SRC_PLL0,
 237         DCN301_CLK_SRC_PLL1,
 238         DCN301_CLK_SRC_PLL2,
 239         DCN301_CLK_SRC_PLL3,
 240         DCN301_CLK_SRC_TOTAL
 241 };
 242
 243 /* begin *********************
 244  * macros to expend register list macro defined in HW object header file
 245  */
 246
 247 /* DCN */
 248 /* TODO awful hack. fixup dcn20_dwb.h */
 249 #undef BASE_INNER
 250 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
 251
 252 #define BASE(seg) BASE_INNER(seg)
 253
 254 #define SR(reg_name)\
 255                 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
 256                                         mm ## reg_name
 257
 258 #define SRI(reg_name, block, id)\
 259         .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 260                                         mm ## block ## id ## _ ## reg_name
 261
 262 #define SRI2(reg_name, block, id)\
 263         .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
 264                                         mm ## reg_name
 265
 266 #define SRIR(var_name, reg_name, block, id)\
 267         .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 268                                         mm ## block ## id ## _ ## reg_name
 269
 270 #define SRII(reg_name, block, id)\
 271         .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 272                                         mm ## block ## id ## _ ## reg_name
 273
 274 #define SRII2(reg_name_pre, reg_name_post, id)\
 275         .reg_name_pre ## _ ##  reg_name_post[id] = BASE(mm ## reg_name_pre \
 276                         ## id ## _ ## reg_name_post ## _BASE_IDX) + \
 277                         mm ## reg_name_pre ## id ## _ ## reg_name_post
 278
 279 #define SRII_MPC_RMU(reg_name, block, id)\
 280         .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 281                                         mm ## block ## id ## _ ## reg_name
 282
 283 #define SRII_DWB(reg_name, temp_name, block, id)\
 284         .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
 285                                         mm ## block ## id ## _ ## temp_name
 286
 287 #define DCCG_SRII(reg_name, block, id)\
 288         .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 289                                         mm ## block ## id ## _ ## reg_name
 290
 291 #define VUPDATE_SRII(reg_name, block, id)\
 292         .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
 293                                         mm ## reg_name ## _ ## block ## id
 294
 295 /* NBIO */
 296 #define NBIO_BASE_INNER(seg) \
 297         NBIO_BASE__INST0_SEG ## seg
 298
 299 #define NBIO_BASE(seg) \
 300         NBIO_BASE_INNER(seg)
 301
 302 #define NBIO_SR(reg_name)\
 303                 .reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
 304                                         regBIF_BX0_ ## reg_name
 305
 306 /* MMHUB */
 307 #define MMHUB_BASE_INNER(seg) \
 308         MMHUB_BASE__INST0_SEG ## seg
 309
 310 #define MMHUB_BASE(seg) \
 311         MMHUB_BASE_INNER(seg)
 312
 313 #define MMHUB_SR(reg_name)\
 314                 .reg_name = MMHUB_BASE(regMM ## reg_name ## _BASE_IDX) + \
 315                                         regMM ## reg_name
 316
 317 /* CLOCK */
 318 #define CLK_BASE_INNER(seg) \
 319         CLK_BASE__INST0_SEG ## seg
 320
 321 #define CLK_BASE(seg) \
 322         CLK_BASE_INNER(seg)
 323
 324 #define CLK_SRI(reg_name, block, inst)\
 325         .reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
 326                                         mm ## block ## _ ## inst ## _ ## reg_name
 327
 328 static const struct bios_registers bios_regs = {
 329                 NBIO_SR(BIOS_SCRATCH_3),
 330                 NBIO_SR(BIOS_SCRATCH_6)
 331 };
 332
 333 #define clk_src_regs(index, pllid)\
 334 [index] = {\
 335         CS_COMMON_REG_LIST_DCN3_01(index, pllid),\
 336 }
 337
 338 static const struct dce110_clk_src_regs clk_src_regs[] = {
 339         clk_src_regs(0, A),
 340         clk_src_regs(1, B),
 341         clk_src_regs(2, C),
 342         clk_src_regs(3, D)
 343 };
 344
 345 static const struct dce110_clk_src_shift cs_shift = {
 346                 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
 347 };
 348
 349 static const struct dce110_clk_src_mask cs_mask = {
 350                 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
 351 };
 352
 353 #define abm_regs(id)\
 354 [id] = {\
 355                 ABM_DCN301_REG_LIST(id)\
 356 }
 357
 358 static const struct dce_abm_registers abm_regs[] = {
 359                 abm_regs(0),
 360                 abm_regs(1),
 361                 abm_regs(2),
 362                 abm_regs(3),
 363 };
 364
 365 static const struct dce_abm_shift abm_shift = {
 366                 ABM_MASK_SH_LIST_DCN301(__SHIFT)
 367 };
 368
 369 static const struct dce_abm_mask abm_mask = {
 370                 ABM_MASK_SH_LIST_DCN301(_MASK)
 371 };
 372
 373 #define audio_regs(id)\
 374 [id] = {\
 375                 AUD_COMMON_REG_LIST(id)\
 376 }
 377
 378 static const struct dce_audio_registers audio_regs[] = {
 379         audio_regs(0),
 380         audio_regs(1),
 381         audio_regs(2),
 382         audio_regs(3),
 383         audio_regs(4),
 384         audio_regs(5),
 385         audio_regs(6)
 386 };
 387
 388 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
 389                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
 390                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
 391                 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
 392
 393 static const struct dce_audio_shift audio_shift = {
 394                 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
 395 };
 396
 397 static const struct dce_audio_mask audio_mask = {
 398                 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
 399 };
 400
 401 #define vpg_regs(id)\
 402 [id] = {\
 403         VPG_DCN3_REG_LIST(id)\
 404 }
 405
 406 static const struct dcn30_vpg_registers vpg_regs[] = {
 407         vpg_regs(0),
 408         vpg_regs(1),
 409         vpg_regs(2),
 410         vpg_regs(3),
 411 };
 412
 413 static const struct dcn30_vpg_shift vpg_shift = {
 414         DCN3_VPG_MASK_SH_LIST(__SHIFT)
 415 };
 416
 417 static const struct dcn30_vpg_mask vpg_mask = {
 418         DCN3_VPG_MASK_SH_LIST(_MASK)
 419 };
 420
 421 #define afmt_regs(id)\
 422 [id] = {\
 423         AFMT_DCN3_REG_LIST(id)\
 424 }
 425
 426 static const struct dcn30_afmt_registers afmt_regs[] = {
 427         afmt_regs(0),
 428         afmt_regs(1),
 429         afmt_regs(2),
 430         afmt_regs(3),
 431 };
 432
 433 static const struct dcn30_afmt_shift afmt_shift = {
 434         DCN3_AFMT_MASK_SH_LIST(__SHIFT)
 435 };
 436
 437 static const struct dcn30_afmt_mask afmt_mask = {
 438         DCN3_AFMT_MASK_SH_LIST(_MASK)
 439 };
 440
 441 #define stream_enc_regs(id)\
 442 [id] = {\
 443         SE_DCN3_REG_LIST(id)\
 444 }
 445
 446 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
 447         stream_enc_regs(0),
 448         stream_enc_regs(1),
 449         stream_enc_regs(2),
 450         stream_enc_regs(3),
 451 };
 452
 453 static const struct dcn10_stream_encoder_shift se_shift = {
 454                 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 455 };
 456
 457 static const struct dcn10_stream_encoder_mask se_mask = {
 458                 SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
 459 };
 460
 461
 462 #define aux_regs(id)\
 463 [id] = {\
 464         DCN2_AUX_REG_LIST(id)\
 465 }
 466
 467 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
 468                 aux_regs(0),
 469                 aux_regs(1),
 470                 aux_regs(2),
 471                 aux_regs(3),
 472 };
 473
 474 #define hpd_regs(id)\
 475 [id] = {\
 476         HPD_REG_LIST(id)\
 477 }
 478
 479 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
 480                 hpd_regs(0),
 481                 hpd_regs(1),
 482                 hpd_regs(2),
 483                 hpd_regs(3),
 484 };
 485
 486 #define link_regs(id, phyid)\
 487 [id] = {\
 488         LE_DCN301_REG_LIST(id), \
 489         UNIPHY_DCN2_REG_LIST(phyid), \
 490 }
 491
 492 static const struct dce110_aux_registers_shift aux_shift = {
 493         DCN_AUX_MASK_SH_LIST(__SHIFT)
 494 };
 495
 496 static const struct dce110_aux_registers_mask aux_mask = {
 497         DCN_AUX_MASK_SH_LIST(_MASK)
 498 };
 499
 500 static const struct dcn10_link_enc_registers link_enc_regs[] = {
 501         link_regs(0, A),
 502         link_regs(1, B),
 503         link_regs(2, C),
 504         link_regs(3, D),
 505 };
 506
 507 static const struct dcn10_link_enc_shift le_shift = {
 508         LINK_ENCODER_MASK_SH_LIST_DCN301(__SHIFT)
 509 };
 510
 511 static const struct dcn10_link_enc_mask le_mask = {
 512         LINK_ENCODER_MASK_SH_LIST_DCN301(_MASK)
 513 };
 514
 515 #define panel_cntl_regs(id)\
 516 [id] = {\
 517         DCN301_PANEL_CNTL_REG_LIST(id),\
 518 }
 519
 520 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
 521         panel_cntl_regs(0),
 522         panel_cntl_regs(1),
 523 };
 524
 525 static const struct dcn301_panel_cntl_shift panel_cntl_shift = {
 526         DCN301_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
 527 };
 528
 529 static const struct dcn301_panel_cntl_mask panel_cntl_mask = {
 530         DCN301_PANEL_CNTL_MASK_SH_LIST(_MASK)
 531 };
 532
 533 #define dpp_regs(id)\
 534 [id] = {\
 535         DPP_REG_LIST_DCN30(id),\
 536 }
 537
 538 static const struct dcn3_dpp_registers dpp_regs[] = {
 539         dpp_regs(0),
 540         dpp_regs(1),
 541         dpp_regs(2),
 542         dpp_regs(3),
 543 };
 544
 545 static const struct dcn3_dpp_shift tf_shift = {
 546                 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
 547 };
 548
 549 static const struct dcn3_dpp_mask tf_mask = {
 550                 DPP_REG_LIST_SH_MASK_DCN30(_MASK)
 551 };
 552
 553 #define opp_regs(id)\
 554 [id] = {\
 555         OPP_REG_LIST_DCN30(id),\
 556 }
 557
 558 static const struct dcn20_opp_registers opp_regs[] = {
 559         opp_regs(0),
 560         opp_regs(1),
 561         opp_regs(2),
 562         opp_regs(3),
 563 };
 564
 565 static const struct dcn20_opp_shift opp_shift = {
 566         OPP_MASK_SH_LIST_DCN20(__SHIFT)
 567 };
 568
 569 static const struct dcn20_opp_mask opp_mask = {
 570         OPP_MASK_SH_LIST_DCN20(_MASK)
 571 };
 572
 573 #define aux_engine_regs(id)\
 574 [id] = {\
 575         AUX_COMMON_REG_LIST0(id), \
 576         .AUXN_IMPCAL = 0, \
 577         .AUXP_IMPCAL = 0, \
 578         .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
 579 }
 580
 581 static const struct dce110_aux_registers aux_engine_regs[] = {
 582                 aux_engine_regs(0),
 583                 aux_engine_regs(1),
 584                 aux_engine_regs(2),
 585                 aux_engine_regs(3),
 586 };
 587
 588 #define dwbc_regs_dcn3(id)\
 589 [id] = {\
 590         DWBC_COMMON_REG_LIST_DCN30(id),\
 591 }
 592
 593 static const struct dcn30_dwbc_registers dwbc30_regs[] = {
 594         dwbc_regs_dcn3(0),
 595 };
 596
 597 static const struct dcn30_dwbc_shift dwbc30_shift = {
 598         DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 599 };
 600
 601 static const struct dcn30_dwbc_mask dwbc30_mask = {
 602         DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
 603 };
 604
 605 #define mcif_wb_regs_dcn3(id)\
 606 [id] = {\
 607         MCIF_WB_COMMON_REG_LIST_DCN30(id),\
 608 }
 609
 610 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
 611         mcif_wb_regs_dcn3(0)
 612 };
 613
 614 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
 615         MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 616 };
 617
 618 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
 619         MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
 620 };
 621
 622 #define dsc_regsDCN20(id)\
 623 [id] = {\
 624         DSC_REG_LIST_DCN20(id)\
 625 }
 626
 627 static const struct dcn20_dsc_registers dsc_regs[] = {
 628         dsc_regsDCN20(0),
 629         dsc_regsDCN20(1),
 630         dsc_regsDCN20(2),
 631 };
 632
 633 static const struct dcn20_dsc_shift dsc_shift = {
 634         DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
 635 };
 636
 637 static const struct dcn20_dsc_mask dsc_mask = {
 638         DSC_REG_LIST_SH_MASK_DCN20(_MASK)
 639 };
 640
 641 static const struct dcn30_mpc_registers mpc_regs = {
 642                 MPC_REG_LIST_DCN3_0(0),
 643                 MPC_REG_LIST_DCN3_0(1),
 644                 MPC_REG_LIST_DCN3_0(2),
 645                 MPC_REG_LIST_DCN3_0(3),
 646                 MPC_OUT_MUX_REG_LIST_DCN3_0(0),
 647                 MPC_OUT_MUX_REG_LIST_DCN3_0(1),
 648                 MPC_OUT_MUX_REG_LIST_DCN3_0(2),
 649                 MPC_OUT_MUX_REG_LIST_DCN3_0(3),
 650                 MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
 651                 MPC_RMU_REG_LIST_DCN3AG(0),
 652                 MPC_RMU_REG_LIST_DCN3AG(1),
 653                 MPC_DWB_MUX_REG_LIST_DCN3_0(0),
 654 };
 655
 656 static const struct dcn30_mpc_shift mpc_shift = {
 657         MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 658 };
 659
 660 static const struct dcn30_mpc_mask mpc_mask = {
 661         MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
 662 };
 663
 664 #define optc_regs(id)\
 665 [id] = {OPTC_COMMON_REG_LIST_DCN3_0(id)}
 666
 667
 668 static const struct dcn_optc_registers optc_regs[] = {
 669         optc_regs(0),
 670         optc_regs(1),
 671         optc_regs(2),
 672         optc_regs(3),
 673 };
 674
 675 static const struct dcn_optc_shift optc_shift = {
 676         OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 677 };
 678
 679 static const struct dcn_optc_mask optc_mask = {
 680         OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK)
 681 };
 682
 683 #define hubp_regs(id)\
 684 [id] = {\
 685         HUBP_REG_LIST_DCN30(id)\
 686 }
 687
 688 static const struct dcn_hubp2_registers hubp_regs[] = {
 689                 hubp_regs(0),
 690                 hubp_regs(1),
 691                 hubp_regs(2),
 692                 hubp_regs(3),
 693 };
 694
 695 static const struct dcn_hubp2_shift hubp_shift = {
 696                 HUBP_MASK_SH_LIST_DCN30(__SHIFT)
 697 };
 698
 699 static const struct dcn_hubp2_mask hubp_mask = {
 700                 HUBP_MASK_SH_LIST_DCN30(_MASK)
 701 };
 702
 703 static const struct dcn_hubbub_registers hubbub_reg = {
 704                 HUBBUB_REG_LIST_DCN301(0)
 705 };
 706
 707 static const struct dcn_hubbub_shift hubbub_shift = {
 708                 HUBBUB_MASK_SH_LIST_DCN301(__SHIFT)
 709 };
 710
 711 static const struct dcn_hubbub_mask hubbub_mask = {
 712                 HUBBUB_MASK_SH_LIST_DCN301(_MASK)
 713 };
 714
 715 static const struct dccg_registers dccg_regs = {
 716                 DCCG_REG_LIST_DCN301()
 717 };
 718
 719 static const struct dccg_shift dccg_shift = {
 720                 DCCG_MASK_SH_LIST_DCN301(__SHIFT)
 721 };
 722
 723 static const struct dccg_mask dccg_mask = {
 724                 DCCG_MASK_SH_LIST_DCN301(_MASK)
 725 };
 726
 727 static const struct dce_hwseq_registers hwseq_reg = {
 728                 HWSEQ_DCN301_REG_LIST()
 729 };
 730
 731 static const struct dce_hwseq_shift hwseq_shift = {
 732                 HWSEQ_DCN301_MASK_SH_LIST(__SHIFT)
 733 };
 734
 735 static const struct dce_hwseq_mask hwseq_mask = {
 736                 HWSEQ_DCN301_MASK_SH_LIST(_MASK)
 737 };
 738 #define vmid_regs(id)\
 739 [id] = {\
 740                 DCN20_VMID_REG_LIST(id)\
 741 }
 742
 743 static const struct dcn_vmid_registers vmid_regs[] = {
 744         vmid_regs(0),
 745         vmid_regs(1),
 746         vmid_regs(2),
 747         vmid_regs(3),
 748         vmid_regs(4),
 749         vmid_regs(5),
 750         vmid_regs(6),
 751         vmid_regs(7),
 752         vmid_regs(8),
 753         vmid_regs(9),
 754         vmid_regs(10),
 755         vmid_regs(11),
 756         vmid_regs(12),
 757         vmid_regs(13),
 758         vmid_regs(14),
 759         vmid_regs(15)
 760 };
 761
 762 static const struct dcn20_vmid_shift vmid_shifts = {
 763                 DCN20_VMID_MASK_SH_LIST(__SHIFT)
 764 };
 765
 766 static const struct dcn20_vmid_mask vmid_masks = {
 767                 DCN20_VMID_MASK_SH_LIST(_MASK)
 768 };
 769
 770 static const struct resource_caps res_cap_dcn301 = {
 771         .num_timing_generator = 4,
 772         .num_opp = 4,
 773         .num_video_plane = 4,
 774         .num_audio = 4,
 775         .num_stream_encoder = 4,
 776         .num_pll = 4,
 777         .num_dwb = 1,
 778         .num_ddc = 4,
 779         .num_vmid = 16,
 780         .num_mpc_3dlut = 2,
 781         .num_dsc = 3,
 782 };
 783
 784 static const struct dc_plane_cap plane_cap = {
 785         .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
 786         .blends_with_above = true,
 787         .blends_with_below = true,
 788         .per_pixel_alpha = true,
 789
 790         .pixel_format_support = {
 791                         .argb8888 = true,
 792                         .nv12 = true,
 793                         .fp16 = true,
 794                         .p010 = false,
 795                         .ayuv = false,
 796         },
 797
 798         .max_upscale_factor = {
 799                         .argb8888 = 16000,
 800                         .nv12 = 16000,
 801                         .fp16 = 16000
 802         },
 803
 804         .max_downscale_factor = {
 805                         .argb8888 = 600,
 806                         .nv12 = 600,
 807                         .fp16 = 600
 808         },
 809         64,
 810         64
 811 };
 812
 813 static const struct dc_debug_options debug_defaults_drv = {
 814         .disable_dmcu = true,
 815         .force_abm_enable = false,
 816         .timing_trace = false,
 817         .clock_trace = true,
 818         .disable_dpp_power_gate = true,
 819         .disable_hubp_power_gate = true,
 820         .disable_clock_gate = true,
 821         .disable_pplib_clock_request = true,
 822         .disable_pplib_wm_range = true,
 823         .disable_stutter = true,
 824         .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
 825         .force_single_disp_pipe_split = false,
 826         .disable_dcc = DCC_ENABLE,
 827         .vsr_support = true,
 828         .performance_trace = false,
 829         .max_downscale_src_width = 7680,/*upto 8K*/
 830         .scl_reset_length10 = true,
 831         .sanity_checks = false,
 832         .underflow_assert_delay_us = 0xFFFFFFFF,
 833         .dwb_fi_phase = -1, // -1 = disable
 834         .dmub_command_table = true,
 835 };
 836
 837 static const struct dc_debug_options debug_defaults_diags = {
 838         .disable_dmcu = true,
 839         .force_abm_enable = false,
 840         .timing_trace = true,
 841         .clock_trace = true,
 842         .disable_dpp_power_gate = true,
 843         .disable_hubp_power_gate = true,
 844         .disable_clock_gate = true,
 845         .disable_pplib_clock_request = true,
 846         .disable_pplib_wm_range = true,
 847         .disable_stutter = true,
 848         .scl_reset_length10 = true,
 849         .dwb_fi_phase = -1, // -1 = disable
 850         .dmub_command_table = true,
 851 };
 852
 853 void dcn301_dpp_destroy(struct dpp **dpp)
 854 {
 855         kfree(TO_DCN20_DPP(*dpp));
 856         *dpp = NULL;
 857 }
 858
 859 struct dpp *dcn301_dpp_create(
 860         struct dc_context *ctx,
 861         uint32_t inst)
 862 {
 863         struct dcn3_dpp *dpp =
 864                 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
 865
 866         if (!dpp)
 867                 return NULL;
 868
 869         if (dpp3_construct(dpp, ctx, inst,
 870                         &dpp_regs[inst], &tf_shift, &tf_mask))
 871                 return &dpp->base;
 872
 873         BREAK_TO_DEBUGGER();
 874         kfree(dpp);
 875         return NULL;
 876 }
 877 struct output_pixel_processor *dcn301_opp_create(
 878         struct dc_context *ctx, uint32_t inst)
 879 {
 880         struct dcn20_opp *opp =
 881                 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
 882
 883         if (!opp) {
 884                 BREAK_TO_DEBUGGER();
 885                 return NULL;
 886         }
 887
 888         dcn20_opp_construct(opp, ctx, inst,
 889                         &opp_regs[inst], &opp_shift, &opp_mask);
 890         return &opp->base;
 891 }
 892
 893 struct dce_aux *dcn301_aux_engine_create(
 894         struct dc_context *ctx,
 895         uint32_t inst)
 896 {
 897         struct aux_engine_dce110 *aux_engine =
 898                 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
 899
 900         if (!aux_engine)
 901                 return NULL;
 902
 903         dce110_aux_engine_construct(aux_engine, ctx, inst,
 904                                     SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
 905                                     &aux_engine_regs[inst],
 906                                         &aux_mask,
 907                                         &aux_shift,
 908                                         ctx->dc->caps.extended_aux_timeout_support);
 909
 910         return &aux_engine->base;
 911 }
 912 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
 913
 914 static const struct dce_i2c_registers i2c_hw_regs[] = {
 915                 i2c_inst_regs(1),
 916                 i2c_inst_regs(2),
 917                 i2c_inst_regs(3),
 918                 i2c_inst_regs(4),
 919 };
 920
 921 static const struct dce_i2c_shift i2c_shifts = {
 922                 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
 923 };
 924
 925 static const struct dce_i2c_mask i2c_masks = {
 926                 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
 927 };
 928
 929 struct dce_i2c_hw *dcn301_i2c_hw_create(
 930         struct dc_context *ctx,
 931         uint32_t inst)
 932 {
 933         struct dce_i2c_hw *dce_i2c_hw =
 934                 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
 935
 936         if (!dce_i2c_hw)
 937                 return NULL;
 938
 939         dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
 940                                     &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
 941
 942         return dce_i2c_hw;
 943 }
 944 static struct mpc *dcn301_mpc_create(
 945                 struct dc_context *ctx,
 946                 int num_mpcc,
 947                 int num_rmu)
 948 {
 949         struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
 950                                           GFP_KERNEL);
 951
 952         if (!mpc30)
 953                 return NULL;
 954
 955         dcn30_mpc_construct(mpc30, ctx,
 956                         &mpc_regs,
 957                         &mpc_shift,
 958                         &mpc_mask,
 959                         num_mpcc,
 960                         num_rmu);
 961
 962         return &mpc30->base;
 963 }
 964
 965 struct hubbub *dcn301_hubbub_create(struct dc_context *ctx)
 966 {
 967         int i;
 968
 969         struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
 970                                           GFP_KERNEL);
 971
 972         if (!hubbub3)
 973                 return NULL;
 974
 975         hubbub301_construct(hubbub3, ctx,
 976                         &hubbub_reg,
 977                         &hubbub_shift,
 978                         &hubbub_mask);
 979
 980
 981         for (i = 0; i < res_cap_dcn301.num_vmid; i++) {
 982                 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
 983
 984                 vmid->ctx = ctx;
 985
 986                 vmid->regs = &vmid_regs[i];
 987                 vmid->shifts = &vmid_shifts;
 988                 vmid->masks = &vmid_masks;
 989         }
 990
 991          hubbub3->num_vmid = res_cap_dcn301.num_vmid;
 992
 993         return &hubbub3->base;
 994 }
 995
 996 struct timing_generator *dcn301_timing_generator_create(
 997                 struct dc_context *ctx,
 998                 uint32_t instance)
 999 {
1000         struct optc *tgn10 =
1001                 kzalloc(sizeof(struct optc), GFP_KERNEL);
1002
1003         if (!tgn10)
1004                 return NULL;
1005
1006         tgn10->base.inst = instance;
1007         tgn10->base.ctx = ctx;
1008
1009         tgn10->tg_regs = &optc_regs[instance];
1010         tgn10->tg_shift = &optc_shift;
1011         tgn10->tg_mask = &optc_mask;
1012
1013         dcn30_timing_generator_init(tgn10);
1014
1015         return &tgn10->base;
1016 }
1017
1018 static const struct encoder_feature_support link_enc_feature = {
1019                 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1020                 .max_hdmi_pixel_clock = 600000,
1021                 .hdmi_ycbcr420_supported = true,
1022                 .dp_ycbcr420_supported = true,
1023                 .fec_supported = true,
1024                 .flags.bits.IS_HBR2_CAPABLE = true,
1025                 .flags.bits.IS_HBR3_CAPABLE = true,
1026                 .flags.bits.IS_TPS3_CAPABLE = true,
1027                 .flags.bits.IS_TPS4_CAPABLE = true
1028 };
1029
1030 struct link_encoder *dcn301_link_encoder_create(
1031         const struct encoder_init_data *enc_init_data)
1032 {
1033         struct dcn20_link_encoder *enc20 =
1034                 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1035
1036         if (!enc20)
1037                 return NULL;
1038
1039         dcn301_link_encoder_construct(enc20,
1040                         enc_init_data,
1041                         &link_enc_feature,
1042                         &link_enc_regs[enc_init_data->transmitter],
1043                         &link_enc_aux_regs[enc_init_data->channel - 1],
1044                         &link_enc_hpd_regs[enc_init_data->hpd_source],
1045                         &le_shift,
1046                         &le_mask);
1047
1048         return &enc20->enc10.base;
1049 }
1050
1051 struct panel_cntl *dcn301_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1052 {
1053         struct dcn301_panel_cntl *panel_cntl =
1054                 kzalloc(sizeof(struct dcn301_panel_cntl), GFP_KERNEL);
1055
1056         if (!panel_cntl)
1057                 return NULL;
1058
1059         dcn301_panel_cntl_construct(panel_cntl,
1060                         init_data,
1061                         &panel_cntl_regs[init_data->inst],
1062                         &panel_cntl_shift,
1063                         &panel_cntl_mask);
1064
1065         return &panel_cntl->base;
1066 }
1067
1068
1069 #define CTX ctx
1070
1071 #define REG(reg_name) \
1072         (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
1073
1074 static uint32_t read_pipe_fuses(struct dc_context *ctx)
1075 {
1076         uint32_t value = REG_READ(CC_DC_PIPE_DIS);
1077         /* RV1 support max 4 pipes */
1078         value = value & 0xf;
1079         return value;
1080 }
1081
1082
1083 static void read_dce_straps(
1084         struct dc_context *ctx,
1085         struct resource_straps *straps)
1086 {
1087         generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
1088                 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1089
1090 }
1091
1092 static struct audio *dcn301_create_audio(
1093                 struct dc_context *ctx, unsigned int inst)
1094 {
1095         return dce_audio_create(ctx, inst,
1096                         &audio_regs[inst], &audio_shift, &audio_mask);
1097 }
1098
1099 static struct vpg *dcn301_vpg_create(
1100         struct dc_context *ctx,
1101         uint32_t inst)
1102 {
1103         struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL);
1104
1105         if (!vpg3)
1106                 return NULL;
1107
1108         vpg3_construct(vpg3, ctx, inst,
1109                         &vpg_regs[inst],
1110                         &vpg_shift,
1111                         &vpg_mask);
1112
1113         return &vpg3->base;
1114 }
1115
1116 static struct afmt *dcn301_afmt_create(
1117         struct dc_context *ctx,
1118         uint32_t inst)
1119 {
1120         struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
1121
1122         if (!afmt3)
1123                 return NULL;
1124
1125         afmt3_construct(afmt3, ctx, inst,
1126                         &afmt_regs[inst],
1127                         &afmt_shift,
1128                         &afmt_mask);
1129
1130         return &afmt3->base;
1131 }
1132
1133 struct stream_encoder *dcn301_stream_encoder_create(
1134         enum engine_id eng_id,
1135         struct dc_context *ctx)
1136 {
1137         struct dcn10_stream_encoder *enc1;
1138         struct vpg *vpg;
1139         struct afmt *afmt;
1140         int vpg_inst;
1141         int afmt_inst;
1142
1143         /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1144         if (eng_id <= ENGINE_ID_DIGF) {
1145                 vpg_inst = eng_id;
1146                 afmt_inst = eng_id;
1147         } else
1148                 return NULL;
1149
1150         enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1151         vpg = dcn301_vpg_create(ctx, vpg_inst);
1152         afmt = dcn301_afmt_create(ctx, afmt_inst);
1153
1154         if (!enc1 || !vpg || !afmt)
1155                 return NULL;
1156
1157         dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1158                                         eng_id, vpg, afmt,
1159                                         &stream_enc_regs[eng_id],
1160                                         &se_shift, &se_mask);
1161
1162         return &enc1->base;
1163 }
1164
1165 struct dce_hwseq *dcn301_hwseq_create(
1166         struct dc_context *ctx)
1167 {
1168         struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1169
1170         if (hws) {
1171                 hws->ctx = ctx;
1172                 hws->regs = &hwseq_reg;
1173                 hws->shifts = &hwseq_shift;
1174                 hws->masks = &hwseq_mask;
1175         }
1176         return hws;
1177 }
1178 static const struct resource_create_funcs res_create_funcs = {
1179         .read_dce_straps = read_dce_straps,
1180         .create_audio = dcn301_create_audio,
1181         .create_stream_encoder = dcn301_stream_encoder_create,
1182         .create_hwseq = dcn301_hwseq_create,
1183 };
1184
1185 static const struct resource_create_funcs res_create_maximus_funcs = {
1186         .read_dce_straps = NULL,
1187         .create_audio = NULL,
1188         .create_stream_encoder = NULL,
1189         .create_hwseq = dcn301_hwseq_create,
1190 };
1191
1192 static void dcn301_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
1193
1194 static void dcn301_destruct(struct dcn301_resource_pool *pool)
1195 {
1196         unsigned int i;
1197
1198         for (i = 0; i < pool->base.stream_enc_count; i++) {
1199                 if (pool->base.stream_enc[i] != NULL) {
1200                         if (pool->base.stream_enc[i]->vpg != NULL) {
1201                                 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1202                                 pool->base.stream_enc[i]->vpg = NULL;
1203                         }
1204                         if (pool->base.stream_enc[i]->afmt != NULL) {
1205                                 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1206                                 pool->base.stream_enc[i]->afmt = NULL;
1207                         }
1208                         kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1209                         pool->base.stream_enc[i] = NULL;
1210                 }
1211         }
1212
1213         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1214                 if (pool->base.dscs[i] != NULL)
1215                         dcn20_dsc_destroy(&pool->base.dscs[i]);
1216         }
1217
1218         if (pool->base.mpc != NULL) {
1219                 kfree(TO_DCN20_MPC(pool->base.mpc));
1220                 pool->base.mpc = NULL;
1221         }
1222         if (pool->base.hubbub != NULL) {
1223                 kfree(pool->base.hubbub);
1224                 pool->base.hubbub = NULL;
1225         }
1226         for (i = 0; i < pool->base.pipe_count; i++) {
1227                 if (pool->base.dpps[i] != NULL)
1228                         dcn301_dpp_destroy(&pool->base.dpps[i]);
1229
1230                 if (pool->base.ipps[i] != NULL)
1231                         pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1232
1233                 if (pool->base.hubps[i] != NULL) {
1234                         kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1235                         pool->base.hubps[i] = NULL;
1236                 }
1237
1238                 if (pool->base.irqs != NULL) {
1239                         dal_irq_service_destroy(&pool->base.irqs);
1240                 }
1241         }
1242
1243         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1244                 if (pool->base.engines[i] != NULL)
1245                         dce110_engine_destroy(&pool->base.engines[i]);
1246                 if (pool->base.hw_i2cs[i] != NULL) {
1247                         kfree(pool->base.hw_i2cs[i]);
1248                         pool->base.hw_i2cs[i] = NULL;
1249                 }
1250                 if (pool->base.sw_i2cs[i] != NULL) {
1251                         kfree(pool->base.sw_i2cs[i]);
1252                         pool->base.sw_i2cs[i] = NULL;
1253                 }
1254         }
1255
1256         for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1257                 if (pool->base.opps[i] != NULL)
1258                         pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1259         }
1260
1261         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1262                 if (pool->base.timing_generators[i] != NULL)    {
1263                         kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1264                         pool->base.timing_generators[i] = NULL;
1265                 }
1266         }
1267
1268         for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1269                 if (pool->base.dwbc[i] != NULL) {
1270                         kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1271                         pool->base.dwbc[i] = NULL;
1272                 }
1273                 if (pool->base.mcif_wb[i] != NULL) {
1274                         kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1275                         pool->base.mcif_wb[i] = NULL;
1276                 }
1277         }
1278
1279         for (i = 0; i < pool->base.audio_count; i++) {
1280                 if (pool->base.audios[i])
1281                         dce_aud_destroy(&pool->base.audios[i]);
1282         }
1283
1284         for (i = 0; i < pool->base.clk_src_count; i++) {
1285                 if (pool->base.clock_sources[i] != NULL) {
1286                         dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1287                         pool->base.clock_sources[i] = NULL;
1288                 }
1289         }
1290
1291         for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1292                 if (pool->base.mpc_lut[i] != NULL) {
1293                         dc_3dlut_func_release(pool->base.mpc_lut[i]);
1294                         pool->base.mpc_lut[i] = NULL;
1295                 }
1296                 if (pool->base.mpc_shaper[i] != NULL) {
1297                         dc_transfer_func_release(pool->base.mpc_shaper[i]);
1298                         pool->base.mpc_shaper[i] = NULL;
1299                 }
1300         }
1301
1302         if (pool->base.dp_clock_source != NULL) {
1303                 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1304                 pool->base.dp_clock_source = NULL;
1305         }
1306
1307         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1308                 if (pool->base.multiple_abms[i] != NULL)
1309                         dce_abm_destroy(&pool->base.multiple_abms[i]);
1310         }
1311
1312         if (pool->base.dccg != NULL)
1313                 dcn_dccg_destroy(&pool->base.dccg);
1314
1315         if (pool->base.pp_smu != NULL)
1316                 dcn301_pp_smu_destroy(&pool->base.pp_smu);
1317 }
1318
1319 struct hubp *dcn301_hubp_create(
1320         struct dc_context *ctx,
1321         uint32_t inst)
1322 {
1323         struct dcn20_hubp *hubp2 =
1324                 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1325
1326         if (!hubp2)
1327                 return NULL;
1328
1329         if (hubp3_construct(hubp2, ctx, inst,
1330                         &hubp_regs[inst], &hubp_shift, &hubp_mask))
1331                 return &hubp2->base;
1332
1333         BREAK_TO_DEBUGGER();
1334         kfree(hubp2);
1335         return NULL;
1336 }
1337
1338 bool dcn301_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1339 {
1340         int i;
1341         uint32_t pipe_count = pool->res_cap->num_dwb;
1342
1343         for (i = 0; i < pipe_count; i++) {
1344                 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1345                                                     GFP_KERNEL);
1346
1347                 if (!dwbc30) {
1348                         dm_error("DC: failed to create dwbc30!\n");
1349                         return false;
1350                 }
1351
1352                 dcn30_dwbc_construct(dwbc30, ctx,
1353                                 &dwbc30_regs[i],
1354                                 &dwbc30_shift,
1355                                 &dwbc30_mask,
1356                                 i);
1357
1358                 pool->dwbc[i] = &dwbc30->base;
1359         }
1360         return true;
1361 }
1362
1363 bool dcn301_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1364 {
1365         int i;
1366         uint32_t pipe_count = pool->res_cap->num_dwb;
1367
1368         for (i = 0; i < pipe_count; i++) {
1369                 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1370                                                     GFP_KERNEL);
1371
1372                 if (!mcif_wb30) {
1373                         dm_error("DC: failed to create mcif_wb30!\n");
1374                         return false;
1375                 }
1376
1377                 dcn30_mmhubbub_construct(mcif_wb30, ctx,
1378                                 &mcif_wb30_regs[i],
1379                                 &mcif_wb30_shift,
1380                                 &mcif_wb30_mask,
1381                                 i);
1382
1383                 pool->mcif_wb[i] = &mcif_wb30->base;
1384         }
1385         return true;
1386 }
1387
1388 static struct display_stream_compressor *dcn301_dsc_create(
1389         struct dc_context *ctx, uint32_t inst)
1390 {
1391         struct dcn20_dsc *dsc =
1392                 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1393
1394         if (!dsc) {
1395                 BREAK_TO_DEBUGGER();
1396                 return NULL;
1397         }
1398
1399         dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1400         return &dsc->base;
1401 }
1402
1403
1404 static void dcn301_destroy_resource_pool(struct resource_pool **pool)
1405 {
1406         struct dcn301_resource_pool *dcn301_pool = TO_DCN301_RES_POOL(*pool);
1407
1408         dcn301_destruct(dcn301_pool);
1409         kfree(dcn301_pool);
1410         *pool = NULL;
1411 }
1412
1413 static struct clock_source *dcn301_clock_source_create(
1414                 struct dc_context *ctx,
1415                 struct dc_bios *bios,
1416                 enum clock_source_id id,
1417                 const struct dce110_clk_src_regs *regs,
1418                 bool dp_clk_src)
1419 {
1420         struct dce110_clk_src *clk_src =
1421                 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1422
1423         if (!clk_src)
1424                 return NULL;
1425
1426         if (dcn301_clk_src_construct(clk_src, ctx, bios, id,
1427                         regs, &cs_shift, &cs_mask)) {
1428                 clk_src->base.dp_clk_src = dp_clk_src;
1429                 return &clk_src->base;
1430         }
1431
1432         BREAK_TO_DEBUGGER();
1433         return NULL;
1434 }
1435
1436 static struct dc_cap_funcs cap_funcs = {
1437         .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1438 };
1439
1440 #define fixed16_to_double(x) (((double) x) / ((double) (1 << 16)))
1441 #define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x))
1442
1443 static bool is_soc_bounding_box_valid(struct dc *dc)
1444 {
1445         uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;
1446
1447         if (ASICREV_IS_VANGOGH(hw_internal_rev))
1448                 return true;
1449
1450         return false;
1451 }
1452
1453 static bool init_soc_bounding_box(struct dc *dc,
1454                                   struct dcn301_resource_pool *pool)
1455 {
1456         const struct gpu_info_soc_bounding_box_v1_0 *bb = dc->soc_bounding_box;
1457         struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_01_soc;
1458         struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_01_ip;
1459
1460         DC_LOGGER_INIT(dc->ctx->logger);
1461
1462         if (!bb && !is_soc_bounding_box_valid(dc)) {
1463                 DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__);
1464                 return false;
1465         }
1466
1467         if (bb && !is_soc_bounding_box_valid(dc)) {
1468                 int i;
1469
1470                 dcn3_01_soc.sr_exit_time_us =
1471                                 fixed16_to_double_to_cpu(bb->sr_exit_time_us);
1472                 dcn3_01_soc.sr_enter_plus_exit_time_us =
1473                                 fixed16_to_double_to_cpu(bb->sr_enter_plus_exit_time_us);
1474                 dcn3_01_soc.urgent_latency_us =
1475                                 fixed16_to_double_to_cpu(bb->urgent_latency_us);
1476                 dcn3_01_soc.urgent_latency_pixel_data_only_us =
1477                                 fixed16_to_double_to_cpu(bb->urgent_latency_pixel_data_only_us);
1478                 dcn3_01_soc.urgent_latency_pixel_mixed_with_vm_data_us =
1479                                 fixed16_to_double_to_cpu(bb->urgent_latency_pixel_mixed_with_vm_data_us);
1480                 dcn3_01_soc.urgent_latency_vm_data_only_us =
1481                                 fixed16_to_double_to_cpu(bb->urgent_latency_vm_data_only_us);
1482                 dcn3_01_soc.urgent_out_of_order_return_per_channel_pixel_only_bytes =
1483                                 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_only_bytes);
1484                 dcn3_01_soc.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes =
1485                                 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes);
1486                 dcn3_01_soc.urgent_out_of_order_return_per_channel_vm_only_bytes =
1487                                 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_vm_only_bytes);
1488                 dcn3_01_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only =
1489                                 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_only);
1490                 dcn3_01_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm =
1491                                 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm);
1492                 dcn3_01_soc.pct_ideal_dram_sdp_bw_after_urgent_vm_only =
1493                                 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_vm_only);
1494                 dcn3_01_soc.max_avg_sdp_bw_use_normal_percent =
1495                                 fixed16_to_double_to_cpu(bb->max_avg_sdp_bw_use_normal_percent);
1496                 dcn3_01_soc.max_avg_dram_bw_use_normal_percent =
1497                                 fixed16_to_double_to_cpu(bb->max_avg_dram_bw_use_normal_percent);
1498                 dcn3_01_soc.writeback_latency_us =
1499                                 fixed16_to_double_to_cpu(bb->writeback_latency_us);
1500                 dcn3_01_soc.ideal_dram_bw_after_urgent_percent =
1501                                 fixed16_to_double_to_cpu(bb->ideal_dram_bw_after_urgent_percent);
1502                 dcn3_01_soc.max_request_size_bytes =
1503                                 le32_to_cpu(bb->max_request_size_bytes);
1504                 dcn3_01_soc.dram_channel_width_bytes =
1505                                 le32_to_cpu(bb->dram_channel_width_bytes);
1506                 dcn3_01_soc.fabric_datapath_to_dcn_data_return_bytes =
1507                                 le32_to_cpu(bb->fabric_datapath_to_dcn_data_return_bytes);
1508                 dcn3_01_soc.dcn_downspread_percent =
1509                                 fixed16_to_double_to_cpu(bb->dcn_downspread_percent);
1510                 dcn3_01_soc.downspread_percent =
1511                                 fixed16_to_double_to_cpu(bb->downspread_percent);
1512                 dcn3_01_soc.dram_page_open_time_ns =
1513                                 fixed16_to_double_to_cpu(bb->dram_page_open_time_ns);
1514                 dcn3_01_soc.dram_rw_turnaround_time_ns =
1515                                 fixed16_to_double_to_cpu(bb->dram_rw_turnaround_time_ns);
1516                 dcn3_01_soc.dram_return_buffer_per_channel_bytes =
1517                                 le32_to_cpu(bb->dram_return_buffer_per_channel_bytes);
1518                 dcn3_01_soc.round_trip_ping_latency_dcfclk_cycles =
1519                                 le32_to_cpu(bb->round_trip_ping_latency_dcfclk_cycles);
1520                 dcn3_01_soc.urgent_out_of_order_return_per_channel_bytes =
1521                                 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_bytes);
1522                 dcn3_01_soc.channel_interleave_bytes =
1523                                 le32_to_cpu(bb->channel_interleave_bytes);
1524                 dcn3_01_soc.num_banks =
1525                                 le32_to_cpu(bb->num_banks);
1526                 dcn3_01_soc.num_chans =
1527                                 le32_to_cpu(bb->num_chans);
1528                 dcn3_01_soc.gpuvm_min_page_size_bytes =
1529                                 le32_to_cpu(bb->vmm_page_size_bytes);
1530                 dcn3_01_soc.dram_clock_change_latency_us =
1531                                 fixed16_to_double_to_cpu(bb->dram_clock_change_latency_us);
1532                 dcn3_01_soc.writeback_dram_clock_change_latency_us =
1533                                 fixed16_to_double_to_cpu(bb->writeback_dram_clock_change_latency_us);
1534                 dcn3_01_soc.return_bus_width_bytes =
1535                                 le32_to_cpu(bb->return_bus_width_bytes);
1536                 dcn3_01_soc.dispclk_dppclk_vco_speed_mhz =
1537                                 le32_to_cpu(bb->dispclk_dppclk_vco_speed_mhz);
1538                 dcn3_01_soc.xfc_bus_transport_time_us =
1539                                 le32_to_cpu(bb->xfc_bus_transport_time_us);
1540                 dcn3_01_soc.xfc_xbuf_latency_tolerance_us =
1541                                 le32_to_cpu(bb->xfc_xbuf_latency_tolerance_us);
1542                 dcn3_01_soc.use_urgent_burst_bw =
1543                                 le32_to_cpu(bb->use_urgent_burst_bw);
1544                 dcn3_01_soc.num_states =
1545                                 le32_to_cpu(bb->num_states);
1546
1547                 for (i = 0; i < dcn3_01_soc.num_states; i++) {
1548                         dcn3_01_soc.clock_limits[i].state =
1549                                         le32_to_cpu(bb->clock_limits[i].state);
1550                         dcn3_01_soc.clock_limits[i].dcfclk_mhz =
1551                                         fixed16_to_double_to_cpu(bb->clock_limits[i].dcfclk_mhz);
1552                         dcn3_01_soc.clock_limits[i].fabricclk_mhz =
1553                                         fixed16_to_double_to_cpu(bb->clock_limits[i].fabricclk_mhz);
1554                         dcn3_01_soc.clock_limits[i].dispclk_mhz =
1555                                         fixed16_to_double_to_cpu(bb->clock_limits[i].dispclk_mhz);
1556                         dcn3_01_soc.clock_limits[i].dppclk_mhz =
1557                                         fixed16_to_double_to_cpu(bb->clock_limits[i].dppclk_mhz);
1558                         dcn3_01_soc.clock_limits[i].phyclk_mhz =
1559                                         fixed16_to_double_to_cpu(bb->clock_limits[i].phyclk_mhz);
1560                         dcn3_01_soc.clock_limits[i].socclk_mhz =
1561                                         fixed16_to_double_to_cpu(bb->clock_limits[i].socclk_mhz);
1562                         dcn3_01_soc.clock_limits[i].dscclk_mhz =
1563                                         fixed16_to_double_to_cpu(bb->clock_limits[i].dscclk_mhz);
1564                         dcn3_01_soc.clock_limits[i].dram_speed_mts =
1565                                         fixed16_to_double_to_cpu(bb->clock_limits[i].dram_speed_mts);
1566                 }
1567         }
1568
1569         if (pool->base.pp_smu) {
1570                 struct pp_smu_nv_clock_table max_clocks = {0};
1571                 unsigned int uclk_states[8] = {0};
1572                 unsigned int num_states = 0;
1573                 enum pp_smu_status status;
1574                 bool clock_limits_available = false;
1575                 bool uclk_states_available = false;
1576
1577                 if (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) {
1578                         status = (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states)
1579                                 (&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states);
1580
1581                         uclk_states_available = (status == PP_SMU_RESULT_OK);
1582                 }
1583
1584                 if (pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) {
1585                         status = (*pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks)
1586                                         (&pool->base.pp_smu->nv_funcs.pp_smu, &max_clocks);
1587                         /* SMU cannot set DCF clock to anything equal to or higher than SOC clock
1588                          */
1589                         if (max_clocks.dcfClockInKhz >= max_clocks.socClockInKhz)
1590                                 max_clocks.dcfClockInKhz = max_clocks.socClockInKhz - 1000;
1591                         clock_limits_available = (status == PP_SMU_RESULT_OK);
1592                 }
1593
1594                 if (clock_limits_available && uclk_states_available && num_states)
1595                         dcn20_update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states);
1596                 else if (clock_limits_available)
1597                         dcn20_cap_soc_clocks(loaded_bb, max_clocks);
1598         }
1599
1600         loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;
1601         loaded_ip->max_num_dpp = pool->base.pipe_count;
1602         dcn20_patch_bounding_box(dc, loaded_bb);
1603
1604         return true;
1605 }
1606
1607 static void set_wm_ranges(
1608                 struct pp_smu_funcs *pp_smu,
1609                 struct _vcs_dpi_soc_bounding_box_st *loaded_bb)
1610 {
1611         struct pp_smu_wm_range_sets ranges = {0};
1612         int i;
1613
1614         ranges.num_reader_wm_sets = 0;
1615
1616         if (loaded_bb->num_states == 1) {
1617                 ranges.reader_wm_sets[0].wm_inst = 0;
1618                 ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
1619                 ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
1620                 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
1621                 ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
1622
1623                 ranges.num_reader_wm_sets = 1;
1624         } else if (loaded_bb->num_states > 1) {
1625                 for (i = 0; i < 4 && i < loaded_bb->num_states; i++) {
1626                         ranges.reader_wm_sets[i].wm_inst = i;
1627                         ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
1628                         ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
1629                         ranges.reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0;
1630                         ranges.reader_wm_sets[i].max_fill_clk_mhz = loaded_bb->clock_limits[i].dram_speed_mts / 16;
1631
1632                         ranges.num_reader_wm_sets = i + 1;
1633                 }
1634
1635                 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
1636                 ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
1637         }
1638
1639         ranges.num_writer_wm_sets = 1;
1640
1641         ranges.writer_wm_sets[0].wm_inst = 0;
1642         ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
1643         ranges.writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
1644         ranges.writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
1645         ranges.writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
1646
1647         /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
1648         pp_smu->nv_funcs.set_wm_ranges(&pp_smu->nv_funcs.pp_smu, &ranges);
1649 }
1650
1651 static struct pp_smu_funcs *dcn301_pp_smu_create(struct dc_context *ctx)
1652 {
1653         struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
1654
1655         if (!pp_smu)
1656                 return pp_smu;
1657
1658         if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment) && !IS_DIAG_DC(ctx->dce_environment)) {
1659                 dm_pp_get_funcs(ctx, pp_smu);
1660
1661                 /* TODO: update once we have n21 smu*/
1662                 if (pp_smu->ctx.ver != PP_SMU_VER_NV)
1663                         pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs));
1664         }
1665
1666         return pp_smu;
1667 }
1668
1669 static void dcn301_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
1670 {
1671         if (pp_smu && *pp_smu) {
1672                 kfree(*pp_smu);
1673                 *pp_smu = NULL;
1674         }
1675 }
1676
1677 static void dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1678 {
1679         dcn3_01_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
1680         dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
1681 }
1682
1683 static struct resource_funcs dcn301_res_pool_funcs = {
1684         .destroy = dcn301_destroy_resource_pool,
1685         .link_enc_create = dcn301_link_encoder_create,
1686         .panel_cntl_create = dcn301_panel_cntl_create,
1687         .validate_bandwidth = dcn30_validate_bandwidth,
1688         .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg,
1689         .populate_dml_pipes = dcn30_populate_dml_pipes_from_context,
1690         .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
1691         .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1692         .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1693         .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1694         .set_mcif_arb_params = dcn30_set_mcif_arb_params,
1695         .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1696         .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1697         .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1698         .update_bw_bounding_box = dcn301_update_bw_bounding_box
1699 };
1700
1701 static bool dcn301_resource_construct(
1702         uint8_t num_virtual_links,
1703         struct dc *dc,
1704         struct dcn301_resource_pool *pool)
1705 {
1706         int i, j;
1707         struct dc_context *ctx = dc->ctx;
1708         struct irq_service_init_data init_data;
1709         uint32_t pipe_fuses = read_pipe_fuses(ctx);
1710         uint32_t num_pipes = 0;
1711
1712         DC_LOGGER_INIT(dc->ctx->logger);
1713
1714         ctx->dc_bios->regs = &bios_regs;
1715
1716         pool->base.res_cap = &res_cap_dcn301;
1717
1718         pool->base.funcs = &dcn301_res_pool_funcs;
1719
1720         /*************************************************
1721          *  Resource + asic cap harcoding                *
1722          *************************************************/
1723         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1724         pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1725         pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
1726         dc->caps.max_downscale_ratio = 600;
1727         dc->caps.i2c_speed_in_khz = 100;
1728         dc->caps.max_cursor_size = 256;
1729         dc->caps.dmdata_alloc_size = 2048;
1730         dc->caps.max_slave_planes = 1;
1731         dc->caps.is_apu = true;
1732         dc->caps.post_blend_color_processing = true;
1733         dc->caps.force_dp_tps4_for_cp2520 = true;
1734         dc->caps.extended_aux_timeout_support = true;
1735 #ifdef CONFIG_DRM_AMD_DC_DMUB
1736         dc->caps.dmcub_support = true;
1737 #endif
1738
1739         /* Color pipeline capabilities */
1740         dc->caps.color.dpp.dcn_arch = 1;
1741         dc->caps.color.dpp.input_lut_shared = 0;
1742         dc->caps.color.dpp.icsc = 1;
1743         dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1744         dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1745         dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1746         dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1747         dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1748         dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1749         dc->caps.color.dpp.post_csc = 1;
1750         dc->caps.color.dpp.gamma_corr = 1;
1751
1752         dc->caps.color.dpp.hw_3d_lut = 1;
1753         dc->caps.color.dpp.ogam_ram = 1;
1754         // no OGAM ROM on DCN301
1755         dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1756         dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1757         dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1758         dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1759         dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1760         dc->caps.color.dpp.ocsc = 0;
1761
1762         dc->caps.color.mpc.gamut_remap = 1;
1763         dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
1764         dc->caps.color.mpc.ogam_ram = 1;
1765         dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1766         dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1767         dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1768         dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1769         dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1770         dc->caps.color.mpc.ocsc = 1;
1771
1772         if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1773                 dc->debug = debug_defaults_drv;
1774         else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
1775                 dc->debug = debug_defaults_diags;
1776         } else
1777                 dc->debug = debug_defaults_diags;
1778         // Init the vm_helper
1779         if (dc->vm_helper)
1780                 vm_helper_init(dc->vm_helper, 16);
1781
1782         /*************************************************
1783          *  Create resources                             *
1784          *************************************************/
1785
1786         /* Clock Sources for Pixel Clock*/
1787         pool->base.clock_sources[DCN301_CLK_SRC_PLL0] =
1788                         dcn301_clock_source_create(ctx, ctx->dc_bios,
1789                                 CLOCK_SOURCE_COMBO_PHY_PLL0,
1790                                 &clk_src_regs[0], false);
1791         pool->base.clock_sources[DCN301_CLK_SRC_PLL1] =
1792                         dcn301_clock_source_create(ctx, ctx->dc_bios,
1793                                 CLOCK_SOURCE_COMBO_PHY_PLL1,
1794                                 &clk_src_regs[1], false);
1795         pool->base.clock_sources[DCN301_CLK_SRC_PLL2] =
1796                         dcn301_clock_source_create(ctx, ctx->dc_bios,
1797                                 CLOCK_SOURCE_COMBO_PHY_PLL2,
1798                                 &clk_src_regs[2], false);
1799         pool->base.clock_sources[DCN301_CLK_SRC_PLL3] =
1800                         dcn301_clock_source_create(ctx, ctx->dc_bios,
1801                                 CLOCK_SOURCE_COMBO_PHY_PLL3,
1802                                 &clk_src_regs[3], false);
1803
1804         pool->base.clk_src_count = DCN301_CLK_SRC_TOTAL;
1805
1806         /* todo: not reuse phy_pll registers */
1807         pool->base.dp_clock_source =
1808                         dcn301_clock_source_create(ctx, ctx->dc_bios,
1809                                 CLOCK_SOURCE_ID_DP_DTO,
1810                                 &clk_src_regs[0], true);
1811
1812         for (i = 0; i < pool->base.clk_src_count; i++) {
1813                 if (pool->base.clock_sources[i] == NULL) {
1814                         dm_error("DC: failed to create clock sources!\n");
1815                         BREAK_TO_DEBUGGER();
1816                         goto create_fail;
1817                 }
1818         }
1819
1820         /* DCCG */
1821         pool->base.dccg = dccg301_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1822         if (pool->base.dccg == NULL) {
1823                 dm_error("DC: failed to create dccg!\n");
1824                 BREAK_TO_DEBUGGER();
1825                 goto create_fail;
1826         }
1827
1828         /* PP Lib and SMU interfaces */
1829         pool->base.pp_smu = dcn301_pp_smu_create(ctx);
1830         init_soc_bounding_box(dc, pool);
1831         if (!dc->debug.disable_pplib_wm_range && pool->base.pp_smu->nv_funcs.set_wm_ranges)
1832                 set_wm_ranges(pool->base.pp_smu, &dcn3_01_soc);
1833
1834         num_pipes = dcn3_01_ip.max_num_dpp;
1835
1836         for (i = 0; i < dcn3_01_ip.max_num_dpp; i++)
1837                 if (pipe_fuses & 1 << i)
1838                         num_pipes--;
1839         dcn3_01_ip.max_num_dpp = num_pipes;
1840         dcn3_01_ip.max_num_otg = num_pipes;
1841
1842
1843         dml_init_instance(&dc->dml, &dcn3_01_soc, &dcn3_01_ip, DML_PROJECT_DCN30);
1844
1845         /* IRQ */
1846         init_data.ctx = dc->ctx;
1847         pool->base.irqs = dal_irq_service_dcn30_create(&init_data);
1848         if (!pool->base.irqs)
1849                 goto create_fail;
1850
1851         /* HUBBUB */
1852         pool->base.hubbub = dcn301_hubbub_create(ctx);
1853         if (pool->base.hubbub == NULL) {
1854                 BREAK_TO_DEBUGGER();
1855                 dm_error("DC: failed to create hubbub!\n");
1856                 goto create_fail;
1857         }
1858
1859         j = 0;
1860         /* HUBPs, DPPs, OPPs and TGs */
1861         for (i = 0; i < pool->base.pipe_count; i++) {
1862
1863                 /* if pipe is disabled, skip instance of HW pipe,
1864                  * i.e, skip ASIC register instance
1865                  */
1866                 if ((pipe_fuses & (1 << i)) != 0) {
1867                         DC_LOG_DEBUG("%s: fusing pipe %d\n", __func__, i);
1868                         continue;
1869                 }
1870
1871                 pool->base.hubps[j] = dcn301_hubp_create(ctx, i);
1872                 if (pool->base.hubps[j] == NULL) {
1873                         BREAK_TO_DEBUGGER();
1874                         dm_error(
1875                                 "DC: failed to create hubps!\n");
1876                         goto create_fail;
1877                 }
1878
1879                 pool->base.dpps[j] = dcn301_dpp_create(ctx, i);
1880                 if (pool->base.dpps[j] == NULL) {
1881                         BREAK_TO_DEBUGGER();
1882                         dm_error(
1883                                 "DC: failed to create dpps!\n");
1884                         goto create_fail;
1885                 }
1886
1887                 pool->base.opps[j] = dcn301_opp_create(ctx, i);
1888                 if (pool->base.opps[j] == NULL) {
1889                         BREAK_TO_DEBUGGER();
1890                         dm_error(
1891                                 "DC: failed to create output pixel processor!\n");
1892                         goto create_fail;
1893                 }
1894
1895                 pool->base.timing_generators[j] = dcn301_timing_generator_create(ctx, i);
1896                 if (pool->base.timing_generators[j] == NULL) {
1897                         BREAK_TO_DEBUGGER();
1898                         dm_error("DC: failed to create tg!\n");
1899                         goto create_fail;
1900                 }
1901                 j++;
1902         }
1903         pool->base.timing_generator_count = j;
1904         pool->base.pipe_count = j;
1905         pool->base.mpcc_count = j;
1906
1907         /* ABM (or ABMs for NV2x) */
1908         /* TODO: */
1909         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1910                 pool->base.multiple_abms[i] = dmub_abm_create(ctx,
1911                                 &abm_regs[i],
1912                                 &abm_shift,
1913                                 &abm_mask);
1914                 if (pool->base.multiple_abms[i] == NULL) {
1915                         dm_error("DC: failed to create abm for pipe %d!\n", i);
1916                         BREAK_TO_DEBUGGER();
1917                         goto create_fail;
1918                 }
1919         }
1920
1921         /* MPC and DSC */
1922         pool->base.mpc = dcn301_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
1923         if (pool->base.mpc == NULL) {
1924                 BREAK_TO_DEBUGGER();
1925                 dm_error("DC: failed to create mpc!\n");
1926                 goto create_fail;
1927         }
1928
1929         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1930                 pool->base.dscs[i] = dcn301_dsc_create(ctx, i);
1931                 if (pool->base.dscs[i] == NULL) {
1932                         BREAK_TO_DEBUGGER();
1933                         dm_error("DC: failed to create display stream compressor %d!\n", i);
1934                         goto create_fail;
1935                 }
1936         }
1937
1938         /* DWB and MMHUBBUB */
1939         if (!dcn301_dwbc_create(ctx, &pool->base)) {
1940                 BREAK_TO_DEBUGGER();
1941                 dm_error("DC: failed to create dwbc!\n");
1942                 goto create_fail;
1943         }
1944
1945         if (!dcn301_mmhubbub_create(ctx, &pool->base)) {
1946                 BREAK_TO_DEBUGGER();
1947                 dm_error("DC: failed to create mcif_wb!\n");
1948                 goto create_fail;
1949         }
1950
1951         /* AUX and I2C */
1952         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1953                 pool->base.engines[i] = dcn301_aux_engine_create(ctx, i);
1954                 if (pool->base.engines[i] == NULL) {
1955                         BREAK_TO_DEBUGGER();
1956                         dm_error(
1957                                 "DC:failed to create aux engine!!\n");
1958                         goto create_fail;
1959                 }
1960                 pool->base.hw_i2cs[i] = dcn301_i2c_hw_create(ctx, i);
1961                 if (pool->base.hw_i2cs[i] == NULL) {
1962                         BREAK_TO_DEBUGGER();
1963                         dm_error(
1964                                 "DC:failed to create hw i2c!!\n");
1965                         goto create_fail;
1966                 }
1967                 pool->base.sw_i2cs[i] = NULL;
1968         }
1969
1970         /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
1971         if (!resource_construct(num_virtual_links, dc, &pool->base,
1972                         (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
1973                         &res_create_funcs : &res_create_maximus_funcs)))
1974                         goto create_fail;
1975
1976         /* HW Sequencer and Plane caps */
1977         dcn301_hw_sequencer_construct(dc);
1978
1979         dc->caps.max_planes =  pool->base.pipe_count;
1980
1981         for (i = 0; i < dc->caps.max_planes; ++i)
1982                 dc->caps.planes[i] = plane_cap;
1983
1984         dc->cap_funcs = cap_funcs;
1985
1986         return true;
1987
1988 create_fail:
1989
1990         dcn301_destruct(pool);
1991
1992         return false;
1993 }
1994
1995 struct resource_pool *dcn301_create_resource_pool(
1996                 const struct dc_init_data *init_data,
1997                 struct dc *dc)
1998 {
1999         struct dcn301_resource_pool *pool =
2000                 kzalloc(sizeof(struct dcn301_resource_pool), GFP_KERNEL);
2001
2002         if (!pool)
2003                 return NULL;
2004
2005         if (dcn301_resource_construct(init_data->num_virtual_links, dc, pool))
2006                 return &pool->base;
2007
2008         BREAK_TO_DEBUGGER();
2009         kfree(pool);
2010         return NULL;
2011 }