drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c

   1 /*
   2  * Copyright 2020 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26
  27 #include "dm_services.h"
  28 #include "dc.h"
  29
  30 #include "dcn30_init.h"
  31
  32 #include "resource.h"
  33 #include "include/irq_service_interface.h"
  34 #include "dcn20/dcn20_resource.h"
  35
  36 #include "dcn30_resource.h"
  37
  38 #include "dcn10/dcn10_ipp.h"
  39 #include "dcn30/dcn30_hubbub.h"
  40 #include "dcn30/dcn30_mpc.h"
  41 #include "dcn30/dcn30_hubp.h"
  42 #include "irq/dcn30/irq_service_dcn30.h"
  43 #include "dcn30/dcn30_dpp.h"
  44 #include "dcn30/dcn30_optc.h"
  45 #include "dcn20/dcn20_hwseq.h"
  46 #include "dcn30/dcn30_hwseq.h"
  47 #include "dce110/dce110_hw_sequencer.h"
  48 #include "dcn30/dcn30_opp.h"
  49 #include "dcn20/dcn20_dsc.h"
  50 #include "dcn30/dcn30_vpg.h"
  51 #include "dcn30/dcn30_afmt.h"
  52 #include "dcn30/dcn30_dio_stream_encoder.h"
  53 #include "dcn30/dcn30_dio_link_encoder.h"
  54 #include "dce/dce_clock_source.h"
  55 #include "dce/dce_audio.h"
  56 #include "dce/dce_hwseq.h"
  57 #include "clk_mgr.h"
  58 #include "virtual/virtual_stream_encoder.h"
  59 #include "dce110/dce110_resource.h"
  60 #include "dml/display_mode_vba.h"
  61 #include "dcn30/dcn30_dccg.h"
  62 #include "dcn10/dcn10_resource.h"
  63 #include "dc_link_ddc.h"
  64 #include "dce/dce_panel_cntl.h"
  65
  66 #include "dcn30/dcn30_dwb.h"
  67 #include "dcn30/dcn30_mmhubbub.h"
  68
  69 #include "sienna_cichlid_ip_offset.h"
  70 #include "dcn/dcn_3_0_0_offset.h"
  71 #include "dcn/dcn_3_0_0_sh_mask.h"
  72
  73 #include "nbio/nbio_7_4_offset.h"
  74
  75 #include "dcn/dpcs_3_0_0_offset.h"
  76 #include "dcn/dpcs_3_0_0_sh_mask.h"
  77
  78 #include "mmhub/mmhub_2_0_0_offset.h"
  79 #include "mmhub/mmhub_2_0_0_sh_mask.h"
  80
  81 #include "reg_helper.h"
  82 #include "dce/dmub_abm.h"
  83 #include "dce/dmub_psr.h"
  84 #include "dce/dce_aux.h"
  85 #include "dce/dce_i2c.h"
  86
  87 #include "dml/dcn30/display_mode_vba_30.h"
  88 #include "vm_helper.h"
  89 #include "dcn20/dcn20_vmid.h"
  90 #include "amdgpu_socbb.h"
  91
  92 #define DC_LOGGER_INIT(logger)
  93
  94 struct _vcs_dpi_ip_params_st dcn3_0_ip = {
  95         .use_min_dcfclk = 0,
  96         .clamp_min_dcfclk = 0,
  97         .odm_capable = 1,
  98         .gpuvm_enable = 0,
  99         .hostvm_enable = 0,
 100         .gpuvm_max_page_table_levels = 4,
 101         .hostvm_max_page_table_levels = 4,
 102         .hostvm_cached_page_table_levels = 0,
 103         .pte_group_size_bytes = 2048,
 104         .num_dsc = 6,
 105         .rob_buffer_size_kbytes = 184,
 106         .det_buffer_size_kbytes = 184,
 107         .dpte_buffer_size_in_pte_reqs_luma = 84,
 108         .pde_proc_buffer_size_64k_reqs = 48,
 109         .dpp_output_buffer_pixels = 2560,
 110         .opp_output_buffer_lines = 1,
 111         .pixel_chunk_size_kbytes = 8,
 112         .pte_enable = 1,
 113         .max_page_table_levels = 2,
 114         .pte_chunk_size_kbytes = 2,  // ?
 115         .meta_chunk_size_kbytes = 2,
 116         .writeback_chunk_size_kbytes = 8,
 117         .line_buffer_size_bits = 789504,
 118         .is_line_buffer_bpp_fixed = 0,  // ?
 119         .line_buffer_fixed_bpp = 0,     // ?
 120         .dcc_supported = true,
 121         .writeback_interface_buffer_size_kbytes = 90,
 122         .writeback_line_buffer_buffer_size = 0,
 123         .max_line_buffer_lines = 12,
 124         .writeback_luma_buffer_size_kbytes = 12,  // writeback_line_buffer_buffer_size = 656640
 125         .writeback_chroma_buffer_size_kbytes = 8,
 126         .writeback_chroma_line_buffer_width_pixels = 4,
 127         .writeback_max_hscl_ratio = 1,
 128         .writeback_max_vscl_ratio = 1,
 129         .writeback_min_hscl_ratio = 1,
 130         .writeback_min_vscl_ratio = 1,
 131         .writeback_max_hscl_taps = 1,
 132         .writeback_max_vscl_taps = 1,
 133         .writeback_line_buffer_luma_buffer_size = 0,
 134         .writeback_line_buffer_chroma_buffer_size = 14643,
 135         .cursor_buffer_size = 8,
 136         .cursor_chunk_size = 2,
 137         .max_num_otg = 6,
 138         .max_num_dpp = 6,
 139         .max_num_wb = 1,
 140         .max_dchub_pscl_bw_pix_per_clk = 4,
 141         .max_pscl_lb_bw_pix_per_clk = 2,
 142         .max_lb_vscl_bw_pix_per_clk = 4,
 143         .max_vscl_hscl_bw_pix_per_clk = 4,
 144         .max_hscl_ratio = 6,
 145         .max_vscl_ratio = 6,
 146         .hscl_mults = 4,
 147         .vscl_mults = 4,
 148         .max_hscl_taps = 8,
 149         .max_vscl_taps = 8,
 150         .dispclk_ramp_margin_percent = 1,
 151         .underscan_factor = 1.11,
 152         .min_vblank_lines = 32,
 153         .dppclk_delay_subtotal = 46,
 154         .dynamic_metadata_vm_enabled = true,
 155         .dppclk_delay_scl_lb_only = 16,
 156         .dppclk_delay_scl = 50,
 157         .dppclk_delay_cnvc_formatter = 27,
 158         .dppclk_delay_cnvc_cursor = 6,
 159         .dispclk_delay_subtotal = 119,
 160         .dcfclk_cstate_latency = 5.2, // SRExitTime
 161         .max_inter_dcn_tile_repeaters = 8,
 162         .odm_combine_4to1_supported = true,
 163
 164         .xfc_supported = false,
 165         .xfc_fill_bw_overhead_percent = 10.0,
 166         .xfc_fill_constant_bytes = 0,
 167         .gfx7_compat_tiling_supported = 0,
 168         .number_of_cursors = 1,
 169 };
 170
 171 struct _vcs_dpi_soc_bounding_box_st dcn3_0_soc = {
 172         .clock_limits = {
 173                         {
 174                                 .state = 0,
 175                                 .dispclk_mhz = 562.0,
 176                                 .dppclk_mhz = 300.0,
 177                                 .phyclk_mhz = 300.0,
 178                                 .phyclk_d18_mhz = 667.0,
 179                                 .dscclk_mhz = 405.6,
 180                         },
 181                 },
 182         .min_dcfclk = 500.0, /* TODO: set this to actual min DCFCLK */
 183         .num_states = 1,
 184         .sr_exit_time_us = 15.5,
 185         .sr_enter_plus_exit_time_us = 20,
 186         .urgent_latency_us = 4.0,
 187         .urgent_latency_pixel_data_only_us = 4.0,
 188         .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
 189         .urgent_latency_vm_data_only_us = 4.0,
 190         .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
 191         .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
 192         .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
 193         .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0,
 194         .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0,
 195         .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
 196         .max_avg_sdp_bw_use_normal_percent = 60.0,
 197         .max_avg_dram_bw_use_normal_percent = 40.0,
 198         .writeback_latency_us = 12.0,
 199         .max_request_size_bytes = 256,
 200         .fabric_datapath_to_dcn_data_return_bytes = 64,
 201         .dcn_downspread_percent = 0.5,
 202         .downspread_percent = 0.38,
 203         .dram_page_open_time_ns = 50.0,
 204         .dram_rw_turnaround_time_ns = 17.5,
 205         .dram_return_buffer_per_channel_bytes = 8192,
 206         .round_trip_ping_latency_dcfclk_cycles = 191,
 207         .urgent_out_of_order_return_per_channel_bytes = 4096,
 208         .channel_interleave_bytes = 256,
 209         .num_banks = 8,
 210         .gpuvm_min_page_size_bytes = 4096,
 211         .hostvm_min_page_size_bytes = 4096,
 212         .dram_clock_change_latency_us = 404,
 213         .dummy_pstate_latency_us = 5,
 214         .writeback_dram_clock_change_latency_us = 23.0,
 215         .return_bus_width_bytes = 64,
 216         .dispclk_dppclk_vco_speed_mhz = 3650,
 217         .xfc_bus_transport_time_us = 20,      // ?
 218         .xfc_xbuf_latency_tolerance_us = 4,  // ?
 219         .use_urgent_burst_bw = 1,            // ?
 220         .do_urgent_latency_adjustment = true,
 221         .urgent_latency_adjustment_fabric_clock_component_us = 1.0,
 222         .urgent_latency_adjustment_fabric_clock_reference_mhz = 1000,
 223 };
 224
 225 enum dcn30_clk_src_array_id {
 226         DCN30_CLK_SRC_PLL0,
 227         DCN30_CLK_SRC_PLL1,
 228         DCN30_CLK_SRC_PLL2,
 229         DCN30_CLK_SRC_PLL3,
 230         DCN30_CLK_SRC_PLL4,
 231         DCN30_CLK_SRC_PLL5,
 232         DCN30_CLK_SRC_TOTAL
 233 };
 234
 235 /* begin *********************
 236  * macros to expend register list macro defined in HW object header file
 237  */
 238
 239 /* DCN */
 240 /* TODO awful hack. fixup dcn20_dwb.h */
 241 #undef BASE_INNER
 242 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
 243
 244 #define BASE(seg) BASE_INNER(seg)
 245
 246 #define SR(reg_name)\
 247                 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
 248                                         mm ## reg_name
 249
 250 #define SRI(reg_name, block, id)\
 251         .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 252                                         mm ## block ## id ## _ ## reg_name
 253
 254 #define SRI2(reg_name, block, id)\
 255         .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
 256                                         mm ## reg_name
 257
 258 #define SRIR(var_name, reg_name, block, id)\
 259         .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 260                                         mm ## block ## id ## _ ## reg_name
 261
 262 #define SRII(reg_name, block, id)\
 263         .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 264                                         mm ## block ## id ## _ ## reg_name
 265
 266 #define SRII_MPC_RMU(reg_name, block, id)\
 267         .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 268                                         mm ## block ## id ## _ ## reg_name
 269
 270 #define SRII_DWB(reg_name, temp_name, block, id)\
 271         .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
 272                                         mm ## block ## id ## _ ## temp_name
 273
 274 #define DCCG_SRII(reg_name, block, id)\
 275         .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 276                                         mm ## block ## id ## _ ## reg_name
 277
 278 #define VUPDATE_SRII(reg_name, block, id)\
 279         .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
 280                                         mm ## reg_name ## _ ## block ## id
 281
 282 /* NBIO */
 283 #define NBIO_BASE_INNER(seg) \
 284         NBIO_BASE__INST0_SEG ## seg
 285
 286 #define NBIO_BASE(seg) \
 287         NBIO_BASE_INNER(seg)
 288
 289 #define NBIO_SR(reg_name)\
 290                 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
 291                                         mm ## reg_name
 292
 293 /* MMHUB */
 294 #define MMHUB_BASE_INNER(seg) \
 295         MMHUB_BASE__INST0_SEG ## seg
 296
 297 #define MMHUB_BASE(seg) \
 298         MMHUB_BASE_INNER(seg)
 299
 300 #define MMHUB_SR(reg_name)\
 301                 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
 302                                         mmMM ## reg_name
 303
 304 /* CLOCK */
 305 #define CLK_BASE_INNER(seg) \
 306         CLK_BASE__INST0_SEG ## seg
 307
 308 #define CLK_BASE(seg) \
 309         CLK_BASE_INNER(seg)
 310
 311 #define CLK_SRI(reg_name, block, inst)\
 312         .reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
 313                                         mm ## block ## _ ## inst ## _ ## reg_name
 314
 315
 316 static const struct bios_registers bios_regs = {
 317                 NBIO_SR(BIOS_SCRATCH_3),
 318                 NBIO_SR(BIOS_SCRATCH_6)
 319 };
 320
 321 #define clk_src_regs(index, pllid)\
 322 [index] = {\
 323         CS_COMMON_REG_LIST_DCN2_0(index, pllid),\
 324 }
 325
 326 static const struct dce110_clk_src_regs clk_src_regs[] = {
 327         clk_src_regs(0, A),
 328         clk_src_regs(1, B),
 329         clk_src_regs(2, C),
 330         clk_src_regs(3, D),
 331         clk_src_regs(4, E),
 332         clk_src_regs(5, F)
 333 };
 334
 335 static const struct dce110_clk_src_shift cs_shift = {
 336                 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
 337 };
 338
 339 static const struct dce110_clk_src_mask cs_mask = {
 340                 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
 341 };
 342
 343 #define abm_regs(id)\
 344 [id] = {\
 345                 ABM_DCN30_REG_LIST(id)\
 346 }
 347
 348 static const struct dce_abm_registers abm_regs[] = {
 349                 abm_regs(0),
 350                 abm_regs(1),
 351                 abm_regs(2),
 352                 abm_regs(3),
 353                 abm_regs(4),
 354                 abm_regs(5),
 355 };
 356
 357 static const struct dce_abm_shift abm_shift = {
 358                 ABM_MASK_SH_LIST_DCN30(__SHIFT)
 359 };
 360
 361 static const struct dce_abm_mask abm_mask = {
 362                 ABM_MASK_SH_LIST_DCN30(_MASK)
 363 };
 364
 365
 366
 367 #define audio_regs(id)\
 368 [id] = {\
 369                 AUD_COMMON_REG_LIST(id)\
 370 }
 371
 372 static const struct dce_audio_registers audio_regs[] = {
 373         audio_regs(0),
 374         audio_regs(1),
 375         audio_regs(2),
 376         audio_regs(3),
 377         audio_regs(4),
 378         audio_regs(5),
 379         audio_regs(6)
 380 };
 381
 382 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
 383                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
 384                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
 385                 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
 386
 387 static const struct dce_audio_shift audio_shift = {
 388                 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
 389 };
 390
 391 static const struct dce_audio_mask audio_mask = {
 392                 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
 393 };
 394
 395 #define vpg_regs(id)\
 396 [id] = {\
 397         VPG_DCN3_REG_LIST(id)\
 398 }
 399
 400 static const struct dcn30_vpg_registers vpg_regs[] = {
 401         vpg_regs(0),
 402         vpg_regs(1),
 403         vpg_regs(2),
 404         vpg_regs(3),
 405         vpg_regs(4),
 406         vpg_regs(5),
 407         vpg_regs(6),
 408 };
 409
 410 static const struct dcn30_vpg_shift vpg_shift = {
 411         DCN3_VPG_MASK_SH_LIST(__SHIFT)
 412 };
 413
 414 static const struct dcn30_vpg_mask vpg_mask = {
 415         DCN3_VPG_MASK_SH_LIST(_MASK)
 416 };
 417
 418 #define afmt_regs(id)\
 419 [id] = {\
 420         AFMT_DCN3_REG_LIST(id)\
 421 }
 422
 423 static const struct dcn30_afmt_registers afmt_regs[] = {
 424         afmt_regs(0),
 425         afmt_regs(1),
 426         afmt_regs(2),
 427         afmt_regs(3),
 428         afmt_regs(4),
 429         afmt_regs(5),
 430         afmt_regs(6),
 431 };
 432
 433 static const struct dcn30_afmt_shift afmt_shift = {
 434         DCN3_AFMT_MASK_SH_LIST(__SHIFT)
 435 };
 436
 437 static const struct dcn30_afmt_mask afmt_mask = {
 438         DCN3_AFMT_MASK_SH_LIST(_MASK)
 439 };
 440
 441 #define stream_enc_regs(id)\
 442 [id] = {\
 443         SE_DCN3_REG_LIST(id)\
 444 }
 445
 446 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
 447         stream_enc_regs(0),
 448         stream_enc_regs(1),
 449         stream_enc_regs(2),
 450         stream_enc_regs(3),
 451         stream_enc_regs(4),
 452         stream_enc_regs(5)
 453 };
 454
 455 static const struct dcn10_stream_encoder_shift se_shift = {
 456                 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 457 };
 458
 459 static const struct dcn10_stream_encoder_mask se_mask = {
 460                 SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
 461 };
 462
 463
 464 #define aux_regs(id)\
 465 [id] = {\
 466         DCN2_AUX_REG_LIST(id)\
 467 }
 468
 469 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
 470                 aux_regs(0),
 471                 aux_regs(1),
 472                 aux_regs(2),
 473                 aux_regs(3),
 474                 aux_regs(4),
 475                 aux_regs(5)
 476 };
 477
 478 #define hpd_regs(id)\
 479 [id] = {\
 480         HPD_REG_LIST(id)\
 481 }
 482
 483 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
 484                 hpd_regs(0),
 485                 hpd_regs(1),
 486                 hpd_regs(2),
 487                 hpd_regs(3),
 488                 hpd_regs(4),
 489                 hpd_regs(5)
 490 };
 491
 492 #define link_regs(id, phyid)\
 493 [id] = {\
 494         LE_DCN3_REG_LIST(id), \
 495         UNIPHY_DCN2_REG_LIST(phyid), \
 496         DPCS_DCN2_REG_LIST(id), \
 497         SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
 498 }
 499
 500 static const struct dce110_aux_registers_shift aux_shift = {
 501         DCN_AUX_MASK_SH_LIST(__SHIFT)
 502 };
 503
 504 static const struct dce110_aux_registers_mask aux_mask = {
 505         DCN_AUX_MASK_SH_LIST(_MASK)
 506 };
 507
 508 static const struct dcn10_link_enc_registers link_enc_regs[] = {
 509         link_regs(0, A),
 510         link_regs(1, B),
 511         link_regs(2, C),
 512         link_regs(3, D),
 513         link_regs(4, E),
 514         link_regs(5, F)
 515 };
 516
 517 static const struct dcn10_link_enc_shift le_shift = {
 518         LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT),\
 519         DPCS_DCN2_MASK_SH_LIST(__SHIFT)
 520 };
 521
 522 static const struct dcn10_link_enc_mask le_mask = {
 523         LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK),\
 524         DPCS_DCN2_MASK_SH_LIST(_MASK)
 525 };
 526
 527
 528 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
 529         { DCN_PANEL_CNTL_REG_LIST() }
 530 };
 531
 532 static const struct dce_panel_cntl_shift panel_cntl_shift = {
 533         DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
 534 };
 535
 536 static const struct dce_panel_cntl_mask panel_cntl_mask = {
 537         DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
 538 };
 539
 540 #define dpp_regs(id)\
 541 [id] = {\
 542         DPP_REG_LIST_DCN30(id),\
 543 }
 544
 545 static const struct dcn3_dpp_registers dpp_regs[] = {
 546         dpp_regs(0),
 547         dpp_regs(1),
 548         dpp_regs(2),
 549         dpp_regs(3),
 550         dpp_regs(4),
 551         dpp_regs(5),
 552 };
 553
 554 static const struct dcn3_dpp_shift tf_shift = {
 555                 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
 556 };
 557
 558 static const struct dcn3_dpp_mask tf_mask = {
 559                 DPP_REG_LIST_SH_MASK_DCN30(_MASK)
 560 };
 561
 562 #define opp_regs(id)\
 563 [id] = {\
 564         OPP_REG_LIST_DCN30(id),\
 565 }
 566
 567 static const struct dcn20_opp_registers opp_regs[] = {
 568         opp_regs(0),
 569         opp_regs(1),
 570         opp_regs(2),
 571         opp_regs(3),
 572         opp_regs(4),
 573         opp_regs(5)
 574 };
 575
 576 static const struct dcn20_opp_shift opp_shift = {
 577         OPP_MASK_SH_LIST_DCN20(__SHIFT)
 578 };
 579
 580 static const struct dcn20_opp_mask opp_mask = {
 581         OPP_MASK_SH_LIST_DCN20(_MASK)
 582 };
 583
 584 #define aux_engine_regs(id)\
 585 [id] = {\
 586         AUX_COMMON_REG_LIST0(id), \
 587         .AUXN_IMPCAL = 0, \
 588         .AUXP_IMPCAL = 0, \
 589         .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
 590 }
 591
 592 static const struct dce110_aux_registers aux_engine_regs[] = {
 593                 aux_engine_regs(0),
 594                 aux_engine_regs(1),
 595                 aux_engine_regs(2),
 596                 aux_engine_regs(3),
 597                 aux_engine_regs(4),
 598                 aux_engine_regs(5)
 599 };
 600
 601 #define dwbc_regs_dcn3(id)\
 602 [id] = {\
 603         DWBC_COMMON_REG_LIST_DCN30(id),\
 604 }
 605
 606 static const struct dcn30_dwbc_registers dwbc30_regs[] = {
 607         dwbc_regs_dcn3(0),
 608 };
 609
 610 static const struct dcn30_dwbc_shift dwbc30_shift = {
 611         DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 612 };
 613
 614 static const struct dcn30_dwbc_mask dwbc30_mask = {
 615         DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
 616 };
 617
 618 #define mcif_wb_regs_dcn3(id)\
 619 [id] = {\
 620         MCIF_WB_COMMON_REG_LIST_DCN30(id),\
 621 }
 622
 623 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
 624         mcif_wb_regs_dcn3(0)
 625 };
 626
 627 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
 628         MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 629 };
 630
 631 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
 632         MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
 633 };
 634
 635 #define dsc_regsDCN20(id)\
 636 [id] = {\
 637         DSC_REG_LIST_DCN20(id)\
 638 }
 639
 640 static const struct dcn20_dsc_registers dsc_regs[] = {
 641         dsc_regsDCN20(0),
 642         dsc_regsDCN20(1),
 643         dsc_regsDCN20(2),
 644         dsc_regsDCN20(3),
 645         dsc_regsDCN20(4),
 646         dsc_regsDCN20(5)
 647 };
 648
 649 static const struct dcn20_dsc_shift dsc_shift = {
 650         DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
 651 };
 652
 653 static const struct dcn20_dsc_mask dsc_mask = {
 654         DSC_REG_LIST_SH_MASK_DCN20(_MASK)
 655 };
 656
 657 static const struct dcn30_mpc_registers mpc_regs = {
 658                 MPC_REG_LIST_DCN3_0(0),
 659                 MPC_REG_LIST_DCN3_0(1),
 660                 MPC_REG_LIST_DCN3_0(2),
 661                 MPC_REG_LIST_DCN3_0(3),
 662                 MPC_REG_LIST_DCN3_0(4),
 663                 MPC_REG_LIST_DCN3_0(5),
 664                 MPC_OUT_MUX_REG_LIST_DCN3_0(0),
 665                 MPC_OUT_MUX_REG_LIST_DCN3_0(1),
 666                 MPC_OUT_MUX_REG_LIST_DCN3_0(2),
 667                 MPC_OUT_MUX_REG_LIST_DCN3_0(3),
 668                 MPC_OUT_MUX_REG_LIST_DCN3_0(4),
 669                 MPC_OUT_MUX_REG_LIST_DCN3_0(5),
 670                 MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
 671                 MPC_RMU_REG_LIST_DCN3AG(0),
 672                 MPC_RMU_REG_LIST_DCN3AG(1),
 673                 MPC_RMU_REG_LIST_DCN3AG(2),
 674                 MPC_DWB_MUX_REG_LIST_DCN3_0(0),
 675 };
 676
 677 static const struct dcn30_mpc_shift mpc_shift = {
 678         MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 679 };
 680
 681 static const struct dcn30_mpc_mask mpc_mask = {
 682         MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
 683 };
 684
 685 #define optc_regs(id)\
 686 [id] = {OPTC_COMMON_REG_LIST_DCN3_0(id)}
 687
 688
 689 static const struct dcn_optc_registers optc_regs[] = {
 690         optc_regs(0),
 691         optc_regs(1),
 692         optc_regs(2),
 693         optc_regs(3),
 694         optc_regs(4),
 695         optc_regs(5)
 696 };
 697
 698 static const struct dcn_optc_shift optc_shift = {
 699         OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 700 };
 701
 702 static const struct dcn_optc_mask optc_mask = {
 703         OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK)
 704 };
 705
 706 #define hubp_regs(id)\
 707 [id] = {\
 708         HUBP_REG_LIST_DCN30(id)\
 709 }
 710
 711 static const struct dcn_hubp2_registers hubp_regs[] = {
 712                 hubp_regs(0),
 713                 hubp_regs(1),
 714                 hubp_regs(2),
 715                 hubp_regs(3),
 716                 hubp_regs(4),
 717                 hubp_regs(5)
 718 };
 719
 720 static const struct dcn_hubp2_shift hubp_shift = {
 721                 HUBP_MASK_SH_LIST_DCN30(__SHIFT)
 722 };
 723
 724 static const struct dcn_hubp2_mask hubp_mask = {
 725                 HUBP_MASK_SH_LIST_DCN30(_MASK)
 726 };
 727
 728 static const struct dcn_hubbub_registers hubbub_reg = {
 729                 HUBBUB_REG_LIST_DCN30(0)
 730 };
 731
 732 static const struct dcn_hubbub_shift hubbub_shift = {
 733                 HUBBUB_MASK_SH_LIST_DCN30(__SHIFT)
 734 };
 735
 736 static const struct dcn_hubbub_mask hubbub_mask = {
 737                 HUBBUB_MASK_SH_LIST_DCN30(_MASK)
 738 };
 739
 740 static const struct dccg_registers dccg_regs = {
 741                 DCCG_REG_LIST_DCN30()
 742 };
 743
 744 static const struct dccg_shift dccg_shift = {
 745                 DCCG_MASK_SH_LIST_DCN3(__SHIFT)
 746 };
 747
 748 static const struct dccg_mask dccg_mask = {
 749                 DCCG_MASK_SH_LIST_DCN3(_MASK)
 750 };
 751
 752 static const struct dce_hwseq_registers hwseq_reg = {
 753                 HWSEQ_DCN30_REG_LIST()
 754 };
 755
 756 static const struct dce_hwseq_shift hwseq_shift = {
 757                 HWSEQ_DCN30_MASK_SH_LIST(__SHIFT)
 758 };
 759
 760 static const struct dce_hwseq_mask hwseq_mask = {
 761                 HWSEQ_DCN30_MASK_SH_LIST(_MASK)
 762 };
 763 #define vmid_regs(id)\
 764 [id] = {\
 765                 DCN20_VMID_REG_LIST(id)\
 766 }
 767
 768 static const struct dcn_vmid_registers vmid_regs[] = {
 769         vmid_regs(0),
 770         vmid_regs(1),
 771         vmid_regs(2),
 772         vmid_regs(3),
 773         vmid_regs(4),
 774         vmid_regs(5),
 775         vmid_regs(6),
 776         vmid_regs(7),
 777         vmid_regs(8),
 778         vmid_regs(9),
 779         vmid_regs(10),
 780         vmid_regs(11),
 781         vmid_regs(12),
 782         vmid_regs(13),
 783         vmid_regs(14),
 784         vmid_regs(15)
 785 };
 786
 787 static const struct dcn20_vmid_shift vmid_shifts = {
 788                 DCN20_VMID_MASK_SH_LIST(__SHIFT)
 789 };
 790
 791 static const struct dcn20_vmid_mask vmid_masks = {
 792                 DCN20_VMID_MASK_SH_LIST(_MASK)
 793 };
 794
 795 static const struct resource_caps res_cap_dcn3 = {
 796         .num_timing_generator = 6,
 797         .num_opp = 6,
 798         .num_video_plane = 6,
 799         .num_audio = 6,
 800         .num_stream_encoder = 6,
 801         .num_pll = 6,
 802         .num_dwb = 1,
 803         .num_ddc = 6,
 804         .num_vmid = 16,
 805         .num_mpc_3dlut = 3,
 806         .num_dsc = 6,
 807 };
 808
 809 static const struct dc_plane_cap plane_cap = {
 810         .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
 811         .blends_with_above = true,
 812         .blends_with_below = true,
 813         .per_pixel_alpha = true,
 814
 815         .pixel_format_support = {
 816                         .argb8888 = true,
 817                         .nv12 = true,
 818                         .fp16 = true,
 819                         .p010 = false,
 820                         .ayuv = false,
 821         },
 822
 823         .max_upscale_factor = {
 824                         .argb8888 = 16000,
 825                         .nv12 = 16000,
 826                         .fp16 = 16000
 827         },
 828
 829         /* 6:1 downscaling ratio: 1000/6 = 166.666 */
 830         .max_downscale_factor = {
 831                         .argb8888 = 167,
 832                         .nv12 = 167,
 833                         .fp16 = 167
 834         }
 835 };
 836
 837 static const struct dc_debug_options debug_defaults_drv = {
 838         .disable_dmcu = true, //No DMCU on DCN30
 839         .force_abm_enable = false,
 840         .timing_trace = false,
 841         .clock_trace = true,
 842         .disable_pplib_clock_request = true,
 843         .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
 844         .force_single_disp_pipe_split = false,
 845         .disable_dcc = DCC_ENABLE,
 846         .vsr_support = true,
 847         .performance_trace = false,
 848         .max_downscale_src_width = 7680,/*upto 8K*/
 849         .disable_pplib_wm_range = false,
 850         .scl_reset_length10 = true,
 851         .sanity_checks = false,
 852         .underflow_assert_delay_us = 0xFFFFFFFF,
 853         .dwb_fi_phase = -1, // -1 = disable,
 854         .dmub_command_table = true,
 855         .disable_psr = false,
 856         .use_max_lb = true
 857 };
 858
 859 static const struct dc_debug_options debug_defaults_diags = {
 860         .disable_dmcu = true, //No dmcu on DCN30
 861         .force_abm_enable = false,
 862         .timing_trace = true,
 863         .clock_trace = true,
 864         .disable_dpp_power_gate = true,
 865         .disable_hubp_power_gate = true,
 866         .disable_clock_gate = true,
 867         .disable_pplib_clock_request = true,
 868         .disable_pplib_wm_range = true,
 869         .disable_stutter = false,
 870         .scl_reset_length10 = true,
 871         .dwb_fi_phase = -1, // -1 = disable
 872         .dmub_command_table = true,
 873         .disable_psr = true,
 874         .enable_tri_buf = true,
 875         .use_max_lb = true
 876 };
 877
 878 void dcn30_dpp_destroy(struct dpp **dpp)
 879 {
 880         kfree(TO_DCN20_DPP(*dpp));
 881         *dpp = NULL;
 882 }
 883
 884 static struct dpp *dcn30_dpp_create(
 885         struct dc_context *ctx,
 886         uint32_t inst)
 887 {
 888         struct dcn3_dpp *dpp =
 889                 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
 890
 891         if (!dpp)
 892                 return NULL;
 893
 894         if (dpp3_construct(dpp, ctx, inst,
 895                         &dpp_regs[inst], &tf_shift, &tf_mask))
 896                 return &dpp->base;
 897
 898         BREAK_TO_DEBUGGER();
 899         kfree(dpp);
 900         return NULL;
 901 }
 902
 903 static struct output_pixel_processor *dcn30_opp_create(
 904         struct dc_context *ctx, uint32_t inst)
 905 {
 906         struct dcn20_opp *opp =
 907                 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
 908
 909         if (!opp) {
 910                 BREAK_TO_DEBUGGER();
 911                 return NULL;
 912         }
 913
 914         dcn20_opp_construct(opp, ctx, inst,
 915                         &opp_regs[inst], &opp_shift, &opp_mask);
 916         return &opp->base;
 917 }
 918
 919 static struct dce_aux *dcn30_aux_engine_create(
 920         struct dc_context *ctx,
 921         uint32_t inst)
 922 {
 923         struct aux_engine_dce110 *aux_engine =
 924                 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
 925
 926         if (!aux_engine)
 927                 return NULL;
 928
 929         dce110_aux_engine_construct(aux_engine, ctx, inst,
 930                                     SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
 931                                     &aux_engine_regs[inst],
 932                                         &aux_mask,
 933                                         &aux_shift,
 934                                         ctx->dc->caps.extended_aux_timeout_support);
 935
 936         return &aux_engine->base;
 937 }
 938
 939 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
 940
 941 static const struct dce_i2c_registers i2c_hw_regs[] = {
 942                 i2c_inst_regs(1),
 943                 i2c_inst_regs(2),
 944                 i2c_inst_regs(3),
 945                 i2c_inst_regs(4),
 946                 i2c_inst_regs(5),
 947                 i2c_inst_regs(6),
 948 };
 949
 950 static const struct dce_i2c_shift i2c_shifts = {
 951                 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 952 };
 953
 954 static const struct dce_i2c_mask i2c_masks = {
 955                 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
 956 };
 957
 958 static struct dce_i2c_hw *dcn30_i2c_hw_create(
 959         struct dc_context *ctx,
 960         uint32_t inst)
 961 {
 962         struct dce_i2c_hw *dce_i2c_hw =
 963                 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
 964
 965         if (!dce_i2c_hw)
 966                 return NULL;
 967
 968         dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
 969                                     &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
 970
 971         return dce_i2c_hw;
 972 }
 973
 974 static struct mpc *dcn30_mpc_create(
 975                 struct dc_context *ctx,
 976                 int num_mpcc,
 977                 int num_rmu)
 978 {
 979         struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
 980                                           GFP_KERNEL);
 981
 982         if (!mpc30)
 983                 return NULL;
 984
 985         dcn30_mpc_construct(mpc30, ctx,
 986                         &mpc_regs,
 987                         &mpc_shift,
 988                         &mpc_mask,
 989                         num_mpcc,
 990                         num_rmu);
 991
 992         return &mpc30->base;
 993 }
 994
 995 struct hubbub *dcn30_hubbub_create(struct dc_context *ctx)
 996 {
 997         int i;
 998
 999         struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
1000                                           GFP_KERNEL);
1001
1002         if (!hubbub3)
1003                 return NULL;
1004
1005         hubbub3_construct(hubbub3, ctx,
1006                         &hubbub_reg,
1007                         &hubbub_shift,
1008                         &hubbub_mask);
1009
1010
1011         for (i = 0; i < res_cap_dcn3.num_vmid; i++) {
1012                 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
1013
1014                 vmid->ctx = ctx;
1015
1016                 vmid->regs = &vmid_regs[i];
1017                 vmid->shifts = &vmid_shifts;
1018                 vmid->masks = &vmid_masks;
1019         }
1020
1021         return &hubbub3->base;
1022 }
1023
1024 static struct timing_generator *dcn30_timing_generator_create(
1025                 struct dc_context *ctx,
1026                 uint32_t instance)
1027 {
1028         struct optc *tgn10 =
1029                 kzalloc(sizeof(struct optc), GFP_KERNEL);
1030
1031         if (!tgn10)
1032                 return NULL;
1033
1034         tgn10->base.inst = instance;
1035         tgn10->base.ctx = ctx;
1036
1037         tgn10->tg_regs = &optc_regs[instance];
1038         tgn10->tg_shift = &optc_shift;
1039         tgn10->tg_mask = &optc_mask;
1040
1041         dcn30_timing_generator_init(tgn10);
1042
1043         return &tgn10->base;
1044 }
1045
1046 static const struct encoder_feature_support link_enc_feature = {
1047                 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1048                 .max_hdmi_pixel_clock = 600000,
1049                 .hdmi_ycbcr420_supported = true,
1050                 .dp_ycbcr420_supported = true,
1051                 .fec_supported = true,
1052                 .flags.bits.IS_HBR2_CAPABLE = true,
1053                 .flags.bits.IS_HBR3_CAPABLE = true,
1054                 .flags.bits.IS_TPS3_CAPABLE = true,
1055                 .flags.bits.IS_TPS4_CAPABLE = true
1056 };
1057
1058 static struct link_encoder *dcn30_link_encoder_create(
1059         const struct encoder_init_data *enc_init_data)
1060 {
1061         struct dcn20_link_encoder *enc20 =
1062                 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1063
1064         if (!enc20)
1065                 return NULL;
1066
1067         dcn30_link_encoder_construct(enc20,
1068                         enc_init_data,
1069                         &link_enc_feature,
1070                         &link_enc_regs[enc_init_data->transmitter],
1071                         &link_enc_aux_regs[enc_init_data->channel - 1],
1072                         &link_enc_hpd_regs[enc_init_data->hpd_source],
1073                         &le_shift,
1074                         &le_mask);
1075
1076         return &enc20->enc10.base;
1077 }
1078
1079 static struct panel_cntl *dcn30_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1080 {
1081         struct dce_panel_cntl *panel_cntl =
1082                 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
1083
1084         if (!panel_cntl)
1085                 return NULL;
1086
1087         dce_panel_cntl_construct(panel_cntl,
1088                         init_data,
1089                         &panel_cntl_regs[init_data->inst],
1090                         &panel_cntl_shift,
1091                         &panel_cntl_mask);
1092
1093         return &panel_cntl->base;
1094 }
1095
1096 static void read_dce_straps(
1097         struct dc_context *ctx,
1098         struct resource_straps *straps)
1099 {
1100         generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
1101                 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1102
1103 }
1104
1105 static struct audio *dcn30_create_audio(
1106                 struct dc_context *ctx, unsigned int inst)
1107 {
1108         return dce_audio_create(ctx, inst,
1109                         &audio_regs[inst], &audio_shift, &audio_mask);
1110 }
1111
1112 static struct vpg *dcn30_vpg_create(
1113         struct dc_context *ctx,
1114         uint32_t inst)
1115 {
1116         struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL);
1117
1118         if (!vpg3)
1119                 return NULL;
1120
1121         vpg3_construct(vpg3, ctx, inst,
1122                         &vpg_regs[inst],
1123                         &vpg_shift,
1124                         &vpg_mask);
1125
1126         return &vpg3->base;
1127 }
1128
1129 static struct afmt *dcn30_afmt_create(
1130         struct dc_context *ctx,
1131         uint32_t inst)
1132 {
1133         struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
1134
1135         if (!afmt3)
1136                 return NULL;
1137
1138         afmt3_construct(afmt3, ctx, inst,
1139                         &afmt_regs[inst],
1140                         &afmt_shift,
1141                         &afmt_mask);
1142
1143         return &afmt3->base;
1144 }
1145
1146 struct stream_encoder *dcn30_stream_encoder_create(
1147         enum engine_id eng_id,
1148         struct dc_context *ctx)
1149 {
1150         struct dcn10_stream_encoder *enc1;
1151         struct vpg *vpg;
1152         struct afmt *afmt;
1153         int vpg_inst;
1154         int afmt_inst;
1155
1156         /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1157         if (eng_id <= ENGINE_ID_DIGF) {
1158                 vpg_inst = eng_id;
1159                 afmt_inst = eng_id;
1160         } else
1161                 return NULL;
1162
1163         enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1164         vpg = dcn30_vpg_create(ctx, vpg_inst);
1165         afmt = dcn30_afmt_create(ctx, afmt_inst);
1166
1167         if (!enc1 || !vpg || !afmt) {
1168                 kfree(enc1);
1169                 kfree(vpg);
1170                 kfree(afmt);
1171                 return NULL;
1172         }
1173
1174         dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1175                                         eng_id, vpg, afmt,
1176                                         &stream_enc_regs[eng_id],
1177                                         &se_shift, &se_mask);
1178
1179         return &enc1->base;
1180 }
1181
1182 struct dce_hwseq *dcn30_hwseq_create(
1183         struct dc_context *ctx)
1184 {
1185         struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1186
1187         if (hws) {
1188                 hws->ctx = ctx;
1189                 hws->regs = &hwseq_reg;
1190                 hws->shifts = &hwseq_shift;
1191                 hws->masks = &hwseq_mask;
1192         }
1193         return hws;
1194 }
1195 static const struct resource_create_funcs res_create_funcs = {
1196         .read_dce_straps = read_dce_straps,
1197         .create_audio = dcn30_create_audio,
1198         .create_stream_encoder = dcn30_stream_encoder_create,
1199         .create_hwseq = dcn30_hwseq_create,
1200 };
1201
1202 static const struct resource_create_funcs res_create_maximus_funcs = {
1203         .read_dce_straps = NULL,
1204         .create_audio = NULL,
1205         .create_stream_encoder = NULL,
1206         .create_hwseq = dcn30_hwseq_create,
1207 };
1208
1209 static void dcn30_resource_destruct(struct dcn30_resource_pool *pool)
1210 {
1211         unsigned int i;
1212
1213         for (i = 0; i < pool->base.stream_enc_count; i++) {
1214                 if (pool->base.stream_enc[i] != NULL) {
1215                         if (pool->base.stream_enc[i]->vpg != NULL) {
1216                                 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1217                                 pool->base.stream_enc[i]->vpg = NULL;
1218                         }
1219                         if (pool->base.stream_enc[i]->afmt != NULL) {
1220                                 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1221                                 pool->base.stream_enc[i]->afmt = NULL;
1222                         }
1223                         kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1224                         pool->base.stream_enc[i] = NULL;
1225                 }
1226         }
1227
1228         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1229                 if (pool->base.dscs[i] != NULL)
1230                         dcn20_dsc_destroy(&pool->base.dscs[i]);
1231         }
1232
1233         if (pool->base.mpc != NULL) {
1234                 kfree(TO_DCN20_MPC(pool->base.mpc));
1235                 pool->base.mpc = NULL;
1236         }
1237         if (pool->base.hubbub != NULL) {
1238                 kfree(pool->base.hubbub);
1239                 pool->base.hubbub = NULL;
1240         }
1241         for (i = 0; i < pool->base.pipe_count; i++) {
1242                 if (pool->base.dpps[i] != NULL)
1243                         dcn30_dpp_destroy(&pool->base.dpps[i]);
1244
1245                 if (pool->base.ipps[i] != NULL)
1246                         pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1247
1248                 if (pool->base.hubps[i] != NULL) {
1249                         kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1250                         pool->base.hubps[i] = NULL;
1251                 }
1252
1253                 if (pool->base.irqs != NULL) {
1254                         dal_irq_service_destroy(&pool->base.irqs);
1255                 }
1256         }
1257
1258         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1259                 if (pool->base.engines[i] != NULL)
1260                         dce110_engine_destroy(&pool->base.engines[i]);
1261                 if (pool->base.hw_i2cs[i] != NULL) {
1262                         kfree(pool->base.hw_i2cs[i]);
1263                         pool->base.hw_i2cs[i] = NULL;
1264                 }
1265                 if (pool->base.sw_i2cs[i] != NULL) {
1266                         kfree(pool->base.sw_i2cs[i]);
1267                         pool->base.sw_i2cs[i] = NULL;
1268                 }
1269         }
1270
1271         for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1272                 if (pool->base.opps[i] != NULL)
1273                         pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1274         }
1275
1276         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1277                 if (pool->base.timing_generators[i] != NULL)    {
1278                         kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1279                         pool->base.timing_generators[i] = NULL;
1280                 }
1281         }
1282
1283         for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1284                 if (pool->base.dwbc[i] != NULL) {
1285                         kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1286                         pool->base.dwbc[i] = NULL;
1287                 }
1288                 if (pool->base.mcif_wb[i] != NULL) {
1289                         kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1290                         pool->base.mcif_wb[i] = NULL;
1291                 }
1292         }
1293
1294         for (i = 0; i < pool->base.audio_count; i++) {
1295                 if (pool->base.audios[i])
1296                         dce_aud_destroy(&pool->base.audios[i]);
1297         }
1298
1299         for (i = 0; i < pool->base.clk_src_count; i++) {
1300                 if (pool->base.clock_sources[i] != NULL) {
1301                         dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1302                         pool->base.clock_sources[i] = NULL;
1303                 }
1304         }
1305
1306         for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1307                 if (pool->base.mpc_lut[i] != NULL) {
1308                         dc_3dlut_func_release(pool->base.mpc_lut[i]);
1309                         pool->base.mpc_lut[i] = NULL;
1310                 }
1311                 if (pool->base.mpc_shaper[i] != NULL) {
1312                         dc_transfer_func_release(pool->base.mpc_shaper[i]);
1313                         pool->base.mpc_shaper[i] = NULL;
1314                 }
1315         }
1316
1317         if (pool->base.dp_clock_source != NULL) {
1318                 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1319                 pool->base.dp_clock_source = NULL;
1320         }
1321
1322         for (i = 0; i < pool->base.pipe_count; i++) {
1323                 if (pool->base.multiple_abms[i] != NULL)
1324                         dce_abm_destroy(&pool->base.multiple_abms[i]);
1325         }
1326
1327         if (pool->base.psr != NULL)
1328                 dmub_psr_destroy(&pool->base.psr);
1329
1330         if (pool->base.dccg != NULL)
1331                 dcn_dccg_destroy(&pool->base.dccg);
1332
1333         if (pool->base.oem_device != NULL)
1334                 dal_ddc_service_destroy(&pool->base.oem_device);
1335 }
1336
1337 static struct hubp *dcn30_hubp_create(
1338         struct dc_context *ctx,
1339         uint32_t inst)
1340 {
1341         struct dcn20_hubp *hubp2 =
1342                 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1343
1344         if (!hubp2)
1345                 return NULL;
1346
1347         if (hubp3_construct(hubp2, ctx, inst,
1348                         &hubp_regs[inst], &hubp_shift, &hubp_mask))
1349                 return &hubp2->base;
1350
1351         BREAK_TO_DEBUGGER();
1352         kfree(hubp2);
1353         return NULL;
1354 }
1355
1356 static bool dcn30_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1357 {
1358         int i;
1359         uint32_t pipe_count = pool->res_cap->num_dwb;
1360
1361         for (i = 0; i < pipe_count; i++) {
1362                 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1363                                                     GFP_KERNEL);
1364
1365                 if (!dwbc30) {
1366                         dm_error("DC: failed to create dwbc30!\n");
1367                         return false;
1368                 }
1369
1370                 dcn30_dwbc_construct(dwbc30, ctx,
1371                                 &dwbc30_regs[i],
1372                                 &dwbc30_shift,
1373                                 &dwbc30_mask,
1374                                 i);
1375
1376                 pool->dwbc[i] = &dwbc30->base;
1377         }
1378         return true;
1379 }
1380
1381 static bool dcn30_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1382 {
1383         int i;
1384         uint32_t pipe_count = pool->res_cap->num_dwb;
1385
1386         for (i = 0; i < pipe_count; i++) {
1387                 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1388                                                     GFP_KERNEL);
1389
1390                 if (!mcif_wb30) {
1391                         dm_error("DC: failed to create mcif_wb30!\n");
1392                         return false;
1393                 }
1394
1395                 dcn30_mmhubbub_construct(mcif_wb30, ctx,
1396                                 &mcif_wb30_regs[i],
1397                                 &mcif_wb30_shift,
1398                                 &mcif_wb30_mask,
1399                                 i);
1400
1401                 pool->mcif_wb[i] = &mcif_wb30->base;
1402         }
1403         return true;
1404 }
1405
1406 static struct display_stream_compressor *dcn30_dsc_create(
1407         struct dc_context *ctx, uint32_t inst)
1408 {
1409         struct dcn20_dsc *dsc =
1410                 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1411
1412         if (!dsc) {
1413                 BREAK_TO_DEBUGGER();
1414                 return NULL;
1415         }
1416
1417         dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1418         return &dsc->base;
1419 }
1420
1421 enum dc_status dcn30_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1422 {
1423
1424         return dcn20_add_stream_to_ctx(dc, new_ctx, dc_stream);
1425 }
1426
1427 static void dcn30_destroy_resource_pool(struct resource_pool **pool)
1428 {
1429         struct dcn30_resource_pool *dcn30_pool = TO_DCN30_RES_POOL(*pool);
1430
1431         dcn30_resource_destruct(dcn30_pool);
1432         kfree(dcn30_pool);
1433         *pool = NULL;
1434 }
1435
1436 static struct clock_source *dcn30_clock_source_create(
1437                 struct dc_context *ctx,
1438                 struct dc_bios *bios,
1439                 enum clock_source_id id,
1440                 const struct dce110_clk_src_regs *regs,
1441                 bool dp_clk_src)
1442 {
1443         struct dce110_clk_src *clk_src =
1444                 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1445
1446         if (!clk_src)
1447                 return NULL;
1448
1449         if (dcn3_clk_src_construct(clk_src, ctx, bios, id,
1450                         regs, &cs_shift, &cs_mask)) {
1451                 clk_src->base.dp_clk_src = dp_clk_src;
1452                 return &clk_src->base;
1453         }
1454
1455         BREAK_TO_DEBUGGER();
1456         return NULL;
1457 }
1458
1459 int dcn30_populate_dml_pipes_from_context(
1460         struct dc *dc, struct dc_state *context,
1461         display_e2e_pipe_params_st *pipes,
1462         bool fast_validate)
1463 {
1464         int i, pipe_cnt;
1465         struct resource_context *res_ctx = &context->res_ctx;
1466
1467         dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
1468
1469         for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1470                 if (!res_ctx->pipe_ctx[i].stream)
1471                         continue;
1472
1473                 pipes[pipe_cnt++].pipe.scale_ratio_depth.lb_depth =
1474                         dm_lb_16;
1475         }
1476
1477         return pipe_cnt;
1478 }
1479
1480 void dcn30_populate_dml_writeback_from_context(
1481         struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
1482 {
1483         int pipe_cnt, i, j;
1484         double max_calc_writeback_dispclk;
1485         double writeback_dispclk;
1486         struct writeback_st dout_wb;
1487
1488         for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1489                 struct dc_stream_state *stream = res_ctx->pipe_ctx[i].stream;
1490
1491                 if (!stream)
1492                         continue;
1493                 max_calc_writeback_dispclk = 0;
1494
1495                 /* Set writeback information */
1496                 pipes[pipe_cnt].dout.wb_enable = 0;
1497                 pipes[pipe_cnt].dout.num_active_wb = 0;
1498                 for (j = 0; j < stream->num_wb_info; j++) {
1499                         struct dc_writeback_info *wb_info = &stream->writeback_info[j];
1500
1501                         if (wb_info->wb_enabled && wb_info->writeback_source_plane &&
1502                                         (wb_info->writeback_source_plane == res_ctx->pipe_ctx[i].plane_state)) {
1503                                 pipes[pipe_cnt].dout.wb_enable = 1;
1504                                 pipes[pipe_cnt].dout.num_active_wb++;
1505                                 dout_wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_en ?
1506                                         wb_info->dwb_params.cnv_params.crop_height :
1507                                         wb_info->dwb_params.cnv_params.src_height;
1508                                 dout_wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_en ?
1509                                         wb_info->dwb_params.cnv_params.crop_width :
1510                                         wb_info->dwb_params.cnv_params.src_width;
1511                                 dout_wb.wb_dst_width = wb_info->dwb_params.dest_width;
1512                                 dout_wb.wb_dst_height = wb_info->dwb_params.dest_height;
1513
1514                                 /* For IP that doesn't support WB scaling, set h/v taps to 1 to avoid DML validation failure */
1515                                 if (dc->dml.ip.writeback_max_hscl_taps > 1) {
1516                                         dout_wb.wb_htaps_luma = wb_info->dwb_params.scaler_taps.h_taps;
1517                                         dout_wb.wb_vtaps_luma = wb_info->dwb_params.scaler_taps.v_taps;
1518                                 } else {
1519                                         dout_wb.wb_htaps_luma = 1;
1520                                         dout_wb.wb_vtaps_luma = 1;
1521                                 }
1522                                 dout_wb.wb_htaps_chroma = 0;
1523                                 dout_wb.wb_vtaps_chroma = 0;
1524                                 dout_wb.wb_hratio = wb_info->dwb_params.cnv_params.crop_en ?
1525                                         (double)wb_info->dwb_params.cnv_params.crop_width /
1526                                                 (double)wb_info->dwb_params.dest_width :
1527                                         (double)wb_info->dwb_params.cnv_params.src_width /
1528                                                 (double)wb_info->dwb_params.dest_width;
1529                                 dout_wb.wb_vratio = wb_info->dwb_params.cnv_params.crop_en ?
1530                                         (double)wb_info->dwb_params.cnv_params.crop_height /
1531                                                 (double)wb_info->dwb_params.dest_height :
1532                                         (double)wb_info->dwb_params.cnv_params.src_height /
1533                                                 (double)wb_info->dwb_params.dest_height;
1534                                 if (wb_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_ARGB ||
1535                                         wb_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_RGBA)
1536                                         dout_wb.wb_pixel_format = dm_444_64;
1537                                 else
1538                                         dout_wb.wb_pixel_format = dm_444_32;
1539
1540                                 /* Workaround for cases where multiple writebacks are connected to same plane
1541                                  * In which case, need to compute worst case and set the associated writeback parameters
1542                                  * This workaround is necessary due to DML computation assuming only 1 set of writeback
1543                                  * parameters per pipe
1544                                  */
1545                                 writeback_dispclk = dml30_CalculateWriteBackDISPCLK(
1546                                                 dout_wb.wb_pixel_format,
1547                                                 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz,
1548                                                 dout_wb.wb_hratio,
1549                                                 dout_wb.wb_vratio,
1550                                                 dout_wb.wb_htaps_luma,
1551                                                 dout_wb.wb_vtaps_luma,
1552                                                 dout_wb.wb_src_width,
1553                                                 dout_wb.wb_dst_width,
1554                                                 pipes[pipe_cnt].pipe.dest.htotal,
1555                                                 dc->current_state->bw_ctx.dml.ip.writeback_line_buffer_buffer_size);
1556
1557                                 if (writeback_dispclk > max_calc_writeback_dispclk) {
1558                                         max_calc_writeback_dispclk = writeback_dispclk;
1559                                         pipes[pipe_cnt].dout.wb = dout_wb;
1560                                 }
1561                         }
1562                 }
1563
1564                 pipe_cnt++;
1565         }
1566
1567 }
1568
1569 unsigned int dcn30_calc_max_scaled_time(
1570                 unsigned int time_per_pixel,
1571                 enum mmhubbub_wbif_mode mode,
1572                 unsigned int urgent_watermark)
1573 {
1574         unsigned int time_per_byte = 0;
1575         unsigned int total_free_entry = 0xb40;
1576         unsigned int buf_lh_capability;
1577         unsigned int max_scaled_time;
1578
1579         if (mode == PACKED_444) /* packed mode 32 bpp */
1580                 time_per_byte = time_per_pixel/4;
1581         else if (mode == PACKED_444_FP16) /* packed mode 64 bpp */
1582                 time_per_byte = time_per_pixel/8;
1583
1584         if (time_per_byte == 0)
1585                 time_per_byte = 1;
1586
1587         buf_lh_capability = (total_free_entry*time_per_byte*32) >> 6; /* time_per_byte is in u6.6*/
1588         max_scaled_time   = buf_lh_capability - urgent_watermark;
1589         return max_scaled_time;
1590 }
1591
1592 void dcn30_set_mcif_arb_params(
1593                 struct dc *dc,
1594                 struct dc_state *context,
1595                 display_e2e_pipe_params_st *pipes,
1596                 int pipe_cnt)
1597 {
1598         enum mmhubbub_wbif_mode wbif_mode;
1599         struct display_mode_lib *dml = &context->bw_ctx.dml;
1600         struct mcif_arb_params *wb_arb_params;
1601         int i, j, k, dwb_pipe;
1602
1603         /* Writeback MCIF_WB arbitration parameters */
1604         dwb_pipe = 0;
1605         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1606
1607                 if (!context->res_ctx.pipe_ctx[i].stream)
1608                         continue;
1609
1610                 for (j = 0; j < MAX_DWB_PIPES; j++) {
1611                         struct dc_writeback_info *writeback_info = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j];
1612
1613                         if (writeback_info->wb_enabled == false)
1614                                 continue;
1615
1616                         //wb_arb_params = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j].mcif_arb_params;
1617                         wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe];
1618
1619                         if (writeback_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_ARGB ||
1620                                 writeback_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_RGBA)
1621                                 wbif_mode = PACKED_444_FP16;
1622                         else
1623                                 wbif_mode = PACKED_444;
1624
1625                         for (k = 0; k < sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]); k++) {
1626                                 wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(dml, pipes, pipe_cnt) * 1000;
1627                                 wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(dml, pipes, pipe_cnt) * 1000;
1628                         }
1629                         wb_arb_params->time_per_pixel = (1000000 << 6) / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk; /* time_per_pixel should be in u6.6 format */
1630                         wb_arb_params->slice_lines = 32;
1631                         wb_arb_params->arbitration_slice = 2; /* irrelevant since there is no YUV output */
1632                         wb_arb_params->max_scaled_time = dcn30_calc_max_scaled_time(wb_arb_params->time_per_pixel,
1633                                         wbif_mode,
1634                                         wb_arb_params->cli_watermark[0]); /* assume 4 watermark sets have the same value */
1635                         wb_arb_params->dram_speed_change_duration = dml->vba.WritebackAllowDRAMClockChangeEndPosition[j] * pipes[0].clks_cfg.refclk_mhz; /* num_clock_cycles = us * MHz */
1636
1637                         dwb_pipe++;
1638
1639                         if (dwb_pipe >= MAX_DWB_PIPES)
1640                                 return;
1641                 }
1642                 if (dwb_pipe >= MAX_DWB_PIPES)
1643                         return;
1644         }
1645
1646 }
1647
1648 static struct dc_cap_funcs cap_funcs = {
1649         .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1650 };
1651
1652 bool dcn30_acquire_post_bldn_3dlut(
1653                 struct resource_context *res_ctx,
1654                 const struct resource_pool *pool,
1655                 int mpcc_id,
1656                 struct dc_3dlut **lut,
1657                 struct dc_transfer_func **shaper)
1658 {
1659         int i;
1660         bool ret = false;
1661         union dc_3dlut_state *state;
1662
1663         ASSERT(*lut == NULL && *shaper == NULL);
1664         *lut = NULL;
1665         *shaper = NULL;
1666
1667         for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
1668                 if (!res_ctx->is_mpc_3dlut_acquired[i]) {
1669                         *lut = pool->mpc_lut[i];
1670                         *shaper = pool->mpc_shaper[i];
1671                         state = &pool->mpc_lut[i]->state;
1672                         res_ctx->is_mpc_3dlut_acquired[i] = true;
1673                         state->bits.rmu_idx_valid = 1;
1674                         state->bits.rmu_mux_num = i;
1675                         if (state->bits.rmu_mux_num == 0)
1676                                 state->bits.mpc_rmu0_mux = mpcc_id;
1677                         else if (state->bits.rmu_mux_num == 1)
1678                                 state->bits.mpc_rmu1_mux = mpcc_id;
1679                         else if (state->bits.rmu_mux_num == 2)
1680                                 state->bits.mpc_rmu2_mux = mpcc_id;
1681                         ret = true;
1682                         break;
1683                         }
1684                 }
1685         return ret;
1686 }
1687
1688 bool dcn30_release_post_bldn_3dlut(
1689                 struct resource_context *res_ctx,
1690                 const struct resource_pool *pool,
1691                 struct dc_3dlut **lut,
1692                 struct dc_transfer_func **shaper)
1693 {
1694         int i;
1695         bool ret = false;
1696
1697         for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
1698                 if (pool->mpc_lut[i] == *lut && pool->mpc_shaper[i] == *shaper) {
1699                         res_ctx->is_mpc_3dlut_acquired[i] = false;
1700                         pool->mpc_lut[i]->state.raw = 0;
1701                         *lut = NULL;
1702                         *shaper = NULL;
1703                         ret = true;
1704                         break;
1705                 }
1706         }
1707         return ret;
1708 }
1709
1710 static bool is_soc_bounding_box_valid(struct dc *dc)
1711 {
1712         uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;
1713
1714         if (ASICREV_IS_SIENNA_CICHLID_P(hw_internal_rev))
1715                 return true;
1716
1717         return false;
1718 }
1719
1720 static bool init_soc_bounding_box(struct dc *dc,
1721                                   struct dcn30_resource_pool *pool)
1722 {
1723         struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_0_soc;
1724         struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_0_ip;
1725
1726         DC_LOGGER_INIT(dc->ctx->logger);
1727
1728         if (!is_soc_bounding_box_valid(dc)) {
1729                 DC_LOG_ERROR("%s: not valid soc bounding box\n", __func__);
1730                 return false;
1731         }
1732
1733         loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;
1734         loaded_ip->max_num_dpp = pool->base.pipe_count;
1735         loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
1736         dcn20_patch_bounding_box(dc, loaded_bb);
1737
1738         if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {
1739                 struct bp_soc_bb_info bb_info = {0};
1740
1741                 if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {
1742                         if (bb_info.dram_clock_change_latency_100ns > 0)
1743                                 dcn3_0_soc.dram_clock_change_latency_us = bb_info.dram_clock_change_latency_100ns * 10;
1744
1745                         if (bb_info.dram_sr_enter_exit_latency_100ns > 0)
1746                                 dcn3_0_soc.sr_enter_plus_exit_time_us = bb_info.dram_sr_enter_exit_latency_100ns * 10;
1747
1748                         if (bb_info.dram_sr_exit_latency_100ns > 0)
1749                                 dcn3_0_soc.sr_exit_time_us = bb_info.dram_sr_exit_latency_100ns * 10;
1750                 }
1751         }
1752
1753         return true;
1754 }
1755
1756 static bool dcn30_split_stream_for_mpc_or_odm(
1757                 const struct dc *dc,
1758                 struct resource_context *res_ctx,
1759                 struct pipe_ctx *pri_pipe,
1760                 struct pipe_ctx *sec_pipe,
1761                 bool odm)
1762 {
1763         int pipe_idx = sec_pipe->pipe_idx;
1764         const struct resource_pool *pool = dc->res_pool;
1765
1766         *sec_pipe = *pri_pipe;
1767
1768         sec_pipe->pipe_idx = pipe_idx;
1769         sec_pipe->plane_res.mi = pool->mis[pipe_idx];
1770         sec_pipe->plane_res.hubp = pool->hubps[pipe_idx];
1771         sec_pipe->plane_res.ipp = pool->ipps[pipe_idx];
1772         sec_pipe->plane_res.xfm = pool->transforms[pipe_idx];
1773         sec_pipe->plane_res.dpp = pool->dpps[pipe_idx];
1774         sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst;
1775         sec_pipe->stream_res.dsc = NULL;
1776         if (odm) {
1777                 if (pri_pipe->next_odm_pipe) {
1778                         ASSERT(pri_pipe->next_odm_pipe != sec_pipe);
1779                         sec_pipe->next_odm_pipe = pri_pipe->next_odm_pipe;
1780                         sec_pipe->next_odm_pipe->prev_odm_pipe = sec_pipe;
1781                 }
1782                 if (pri_pipe->top_pipe && pri_pipe->top_pipe->next_odm_pipe) {
1783                         pri_pipe->top_pipe->next_odm_pipe->bottom_pipe = sec_pipe;
1784                         sec_pipe->top_pipe = pri_pipe->top_pipe->next_odm_pipe;
1785                 }
1786                 if (pri_pipe->bottom_pipe && pri_pipe->bottom_pipe->next_odm_pipe) {
1787                         pri_pipe->bottom_pipe->next_odm_pipe->top_pipe = sec_pipe;
1788                         sec_pipe->bottom_pipe = pri_pipe->bottom_pipe->next_odm_pipe;
1789                 }
1790                 pri_pipe->next_odm_pipe = sec_pipe;
1791                 sec_pipe->prev_odm_pipe = pri_pipe;
1792
1793                 if (!sec_pipe->top_pipe)
1794                         sec_pipe->stream_res.opp = pool->opps[pipe_idx];
1795                 else
1796                         sec_pipe->stream_res.opp = sec_pipe->top_pipe->stream_res.opp;
1797                 if (sec_pipe->stream->timing.flags.DSC == 1) {
1798                         dcn20_acquire_dsc(dc, res_ctx, &sec_pipe->stream_res.dsc, pipe_idx);
1799                         ASSERT(sec_pipe->stream_res.dsc);
1800                         if (sec_pipe->stream_res.dsc == NULL)
1801                                 return false;
1802                 }
1803         } else {
1804                 if (pri_pipe->bottom_pipe) {
1805                         ASSERT(pri_pipe->bottom_pipe != sec_pipe);
1806                         sec_pipe->bottom_pipe = pri_pipe->bottom_pipe;
1807                         sec_pipe->bottom_pipe->top_pipe = sec_pipe;
1808                 }
1809                 pri_pipe->bottom_pipe = sec_pipe;
1810                 sec_pipe->top_pipe = pri_pipe;
1811
1812                 ASSERT(pri_pipe->plane_state);
1813         }
1814
1815         return true;
1816 }
1817
1818 static struct pipe_ctx *dcn30_find_split_pipe(
1819                 struct dc *dc,
1820                 struct dc_state *context,
1821                 int old_index)
1822 {
1823         struct pipe_ctx *pipe = NULL;
1824         int i;
1825
1826         if (old_index >= 0 && context->res_ctx.pipe_ctx[old_index].stream == NULL) {
1827                 pipe = &context->res_ctx.pipe_ctx[old_index];
1828                 pipe->pipe_idx = old_index;
1829         }
1830
1831         if (!pipe)
1832                 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
1833                         if (dc->current_state->res_ctx.pipe_ctx[i].top_pipe == NULL
1834                                         && dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) {
1835                                 if (context->res_ctx.pipe_ctx[i].stream == NULL) {
1836                                         pipe = &context->res_ctx.pipe_ctx[i];
1837                                         pipe->pipe_idx = i;
1838                                         break;
1839                                 }
1840                         }
1841                 }
1842
1843         /*
1844          * May need to fix pipes getting tossed from 1 opp to another on flip
1845          * Add for debugging transient underflow during topology updates:
1846          * ASSERT(pipe);
1847          */
1848         if (!pipe)
1849                 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
1850                         if (context->res_ctx.pipe_ctx[i].stream == NULL) {
1851                                 pipe = &context->res_ctx.pipe_ctx[i];
1852                                 pipe->pipe_idx = i;
1853                                 break;
1854                         }
1855                 }
1856
1857         return pipe;
1858 }
1859
1860 noinline bool dcn30_internal_validate_bw(
1861                 struct dc *dc,
1862                 struct dc_state *context,
1863                 display_e2e_pipe_params_st *pipes,
1864                 int *pipe_cnt_out,
1865                 int *vlevel_out,
1866                 bool fast_validate)
1867 {
1868         bool out = false;
1869         bool repopulate_pipes = false;
1870         int split[MAX_PIPES] = { 0 };
1871         bool merge[MAX_PIPES] = { false };
1872         bool newly_split[MAX_PIPES] = { false };
1873         int pipe_cnt, i, pipe_idx, vlevel;
1874         struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
1875
1876         ASSERT(pipes);
1877         if (!pipes)
1878                 return false;
1879
1880         dc->res_pool->funcs->update_soc_for_wm_a(dc, context);
1881         pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
1882
1883         DC_FP_START();
1884         if (!pipe_cnt) {
1885                 out = true;
1886                 goto validate_out;
1887         }
1888
1889         dml_log_pipe_params(&context->bw_ctx.dml, pipes, pipe_cnt);
1890
1891         if (!fast_validate) {
1892                 /*
1893                  * DML favors voltage over p-state, but we're more interested in
1894                  * supporting p-state over voltage. We can't support p-state in
1895                  * prefetch mode > 0 so try capping the prefetch mode to start.
1896                  */
1897                 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
1898                         dm_allow_self_refresh_and_mclk_switch;
1899                 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
1900                 /* This may adjust vlevel and maxMpcComb */
1901                 if (vlevel < context->bw_ctx.dml.soc.num_states)
1902                         vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
1903         }
1904         if (fast_validate || vlevel == context->bw_ctx.dml.soc.num_states ||
1905                         vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported) {
1906                 /*
1907                  * If mode is unsupported or there's still no p-state support then
1908                  * fall back to favoring voltage.
1909                  *
1910                  * We don't actually support prefetch mode 2, so require that we
1911                  * at least support prefetch mode 1.
1912                  */
1913                 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
1914                         dm_allow_self_refresh;
1915
1916                 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
1917                 if (vlevel < context->bw_ctx.dml.soc.num_states) {
1918                         memset(split, 0, sizeof(split));
1919                         memset(merge, 0, sizeof(merge));
1920                         vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
1921                 }
1922         }
1923
1924         dml_log_mode_support_params(&context->bw_ctx.dml);
1925
1926         if (vlevel == context->bw_ctx.dml.soc.num_states)
1927                 goto validate_fail;
1928
1929         if (!dc->config.enable_windowed_mpo_odm) {
1930                 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1931                         struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1932                         struct pipe_ctx *mpo_pipe = pipe->bottom_pipe;
1933
1934                         if (!pipe->stream)
1935                                 continue;
1936
1937                         /* We only support full screen mpo with ODM */
1938                         if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled
1939                                         && pipe->plane_state && mpo_pipe
1940                                         && memcmp(&mpo_pipe->plane_res.scl_data.recout,
1941                                                         &pipe->plane_res.scl_data.recout,
1942                                                         sizeof(struct rect)) != 0) {
1943                                 ASSERT(mpo_pipe->plane_state != pipe->plane_state);
1944                                 goto validate_fail;
1945                         }
1946                         pipe_idx++;
1947                 }
1948         }
1949
1950         /* merge pipes if necessary */
1951         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1952                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1953
1954                 /*skip pipes that don't need merging*/
1955                 if (!merge[i])
1956                         continue;
1957
1958                 /* if ODM merge we ignore mpc tree, mpo pipes will have their own flags */
1959                 if (pipe->prev_odm_pipe) {
1960                         /*split off odm pipe*/
1961                         pipe->prev_odm_pipe->next_odm_pipe = pipe->next_odm_pipe;
1962                         if (pipe->next_odm_pipe)
1963                                 pipe->next_odm_pipe->prev_odm_pipe = pipe->prev_odm_pipe;
1964
1965                         pipe->bottom_pipe = NULL;
1966                         pipe->next_odm_pipe = NULL;
1967                         pipe->plane_state = NULL;
1968                         pipe->stream = NULL;
1969                         pipe->top_pipe = NULL;
1970                         pipe->prev_odm_pipe = NULL;
1971                         if (pipe->stream_res.dsc)
1972                                 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc);
1973                         memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
1974                         memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
1975                         repopulate_pipes = true;
1976                 } else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {
1977                         struct pipe_ctx *top_pipe = pipe->top_pipe;
1978                         struct pipe_ctx *bottom_pipe = pipe->bottom_pipe;
1979
1980                         top_pipe->bottom_pipe = bottom_pipe;
1981                         if (bottom_pipe)
1982                                 bottom_pipe->top_pipe = top_pipe;
1983
1984                         pipe->top_pipe = NULL;
1985                         pipe->bottom_pipe = NULL;
1986                         pipe->plane_state = NULL;
1987                         pipe->stream = NULL;
1988                         memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
1989                         memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
1990                         repopulate_pipes = true;
1991                 } else
1992                         ASSERT(0); /* Should never try to merge master pipe */
1993
1994         }
1995
1996         for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
1997                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1998                 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1999                 struct pipe_ctx *hsplit_pipe = NULL;
2000                 bool odm;
2001                 int old_index = -1;
2002
2003                 if (!pipe->stream || newly_split[i])
2004                         continue;
2005
2006                 pipe_idx++;
2007                 odm = vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled;
2008
2009                 if (!pipe->plane_state && !odm)
2010                         continue;
2011
2012                 if (split[i]) {
2013                         if (odm) {
2014                                 if (split[i] == 4 && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe)
2015                                         old_index = old_pipe->next_odm_pipe->next_odm_pipe->pipe_idx;
2016                                 else if (old_pipe->next_odm_pipe)
2017                                         old_index = old_pipe->next_odm_pipe->pipe_idx;
2018                         } else {
2019                                 if (split[i] == 4 && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe &&
2020                                                 old_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
2021                                         old_index = old_pipe->bottom_pipe->bottom_pipe->pipe_idx;
2022                                 else if (old_pipe->bottom_pipe &&
2023                                                 old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
2024                                         old_index = old_pipe->bottom_pipe->pipe_idx;
2025                         }
2026                         hsplit_pipe = dcn30_find_split_pipe(dc, context, old_index);
2027                         ASSERT(hsplit_pipe);
2028                         if (!hsplit_pipe)
2029                                 goto validate_fail;
2030
2031                         if (!dcn30_split_stream_for_mpc_or_odm(
2032                                         dc, &context->res_ctx,
2033                                         pipe, hsplit_pipe, odm))
2034                                 goto validate_fail;
2035
2036                         newly_split[hsplit_pipe->pipe_idx] = true;
2037                         repopulate_pipes = true;
2038                 }
2039                 if (split[i] == 4) {
2040                         struct pipe_ctx *pipe_4to1;
2041
2042                         if (odm && old_pipe->next_odm_pipe)
2043                                 old_index = old_pipe->next_odm_pipe->pipe_idx;
2044                         else if (!odm && old_pipe->bottom_pipe &&
2045                                                 old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
2046                                 old_index = old_pipe->bottom_pipe->pipe_idx;
2047                         else
2048                                 old_index = -1;
2049                         pipe_4to1 = dcn30_find_split_pipe(dc, context, old_index);
2050                         ASSERT(pipe_4to1);
2051                         if (!pipe_4to1)
2052                                 goto validate_fail;
2053                         if (!dcn30_split_stream_for_mpc_or_odm(
2054                                         dc, &context->res_ctx,
2055                                         pipe, pipe_4to1, odm))
2056                                 goto validate_fail;
2057                         newly_split[pipe_4to1->pipe_idx] = true;
2058
2059                         if (odm && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe
2060                                         && old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe)
2061                                 old_index = old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe->pipe_idx;
2062                         else if (!odm && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe &&
2063                                         old_pipe->bottom_pipe->bottom_pipe->bottom_pipe &&
2064                                         old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
2065                                 old_index = old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->pipe_idx;
2066                         else
2067                                 old_index = -1;
2068                         pipe_4to1 = dcn30_find_split_pipe(dc, context, old_index);
2069                         ASSERT(pipe_4to1);
2070                         if (!pipe_4to1)
2071                                 goto validate_fail;
2072                         if (!dcn30_split_stream_for_mpc_or_odm(
2073                                         dc, &context->res_ctx,
2074                                         hsplit_pipe, pipe_4to1, odm))
2075                                 goto validate_fail;
2076                         newly_split[pipe_4to1->pipe_idx] = true;
2077                 }
2078                 if (odm)
2079                         dcn20_build_mapped_resource(dc, context, pipe->stream);
2080         }
2081
2082         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2083                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2084
2085                 if (pipe->plane_state) {
2086                         if (!resource_build_scaling_params(pipe))
2087                                 goto validate_fail;
2088                 }
2089         }
2090
2091         /* Actual dsc count per stream dsc validation*/
2092         if (!dcn20_validate_dsc(dc, context)) {
2093                 vba->ValidationStatus[vba->soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE;
2094                 goto validate_fail;
2095         }
2096
2097         if (repopulate_pipes)
2098                 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
2099         *vlevel_out = vlevel;
2100         *pipe_cnt_out = pipe_cnt;
2101
2102         out = true;
2103         goto validate_out;
2104
2105 validate_fail:
2106         out = false;
2107
2108 validate_out:
2109         DC_FP_END();
2110         return out;
2111 }
2112
2113 /*
2114  * This must be noinline to ensure anything that deals with FP registers
2115  * is contained within this call; previously our compiling with hard-float
2116  * would result in fp instructions being emitted outside of the boundaries
2117  * of the DC_FP_START/END macros, which makes sense as the compiler has no
2118  * idea about what is wrapped and what is not
2119  *
2120  * This is largely just a workaround to avoid breakage introduced with 5.6,
2121  * ideally all fp-using code should be moved into its own file, only that
2122  * should be compiled with hard-float, and all code exported from there
2123  * should be strictly wrapped with DC_FP_START/END
2124  */
2125 static noinline void dcn30_calculate_wm_and_dlg_fp(
2126                 struct dc *dc, struct dc_state *context,
2127                 display_e2e_pipe_params_st *pipes,
2128                 int pipe_cnt,
2129                 int vlevel)
2130 {
2131         int i, pipe_idx;
2132         double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
2133         bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] !=
2134                         dm_dram_clock_change_unsupported;
2135
2136         if (context->bw_ctx.dml.soc.min_dcfclk > dcfclk)
2137                 dcfclk = context->bw_ctx.dml.soc.min_dcfclk;
2138
2139         pipes[0].clks_cfg.voltage = vlevel;
2140         pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
2141         pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
2142
2143         /* Set B:
2144          * DCFCLK: 1GHz or min required above 1GHz
2145          * FCLK/UCLK: Max
2146          */
2147         if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) {
2148                 if (vlevel == 0) {
2149                         pipes[0].clks_cfg.voltage = 1;
2150                         pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dcfclk_mhz;
2151                 }
2152                 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us;
2153                 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us;
2154                 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us;
2155         }
2156         context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2157         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2158         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2159         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2160         context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2161         context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2162         context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2163         context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2164
2165         pipes[0].clks_cfg.voltage = vlevel;
2166         pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
2167
2168         /* Set D:
2169          * DCFCLK: Min Required
2170          * FCLK(proportional to UCLK): 1GHz or Max
2171          * MALL stutter, sr_enter_exit = 4, sr_exit = 2us
2172          */
2173         /*
2174         if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].valid) {
2175                 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us;
2176                 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us;
2177                 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us;
2178         }
2179         context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2180         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2181         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2182         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2183         context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2184         context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2185         context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2186         context->bw_ctx.bw.dcn.watermarks.d.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2187         */
2188
2189         /* Set C:
2190          * DCFCLK: Min Required
2191          * FCLK(proportional to UCLK): 1GHz or Max
2192          * pstate latency overridden to 5us
2193          */
2194         if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) {
2195                 unsigned int min_dram_speed_mts = context->bw_ctx.dml.vba.DRAMSpeed;
2196                 unsigned int min_dram_speed_mts_margin = 160;
2197
2198                 if (context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == dm_dram_clock_change_unsupported)
2199                         min_dram_speed_mts = dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz * 16;
2200
2201                 /* find largest table entry that is lower than dram speed, but lower than DPM0 still uses DPM0 */
2202                 for (i = 3; i > 0; i--)
2203                         if (min_dram_speed_mts + min_dram_speed_mts_margin > dc->clk_mgr->bw_params->dummy_pstate_table[i].dram_speed_mts)
2204                                 break;
2205
2206                 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->dummy_pstate_table[i].dummy_pstate_latency_us;
2207                 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us;
2208                 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us;
2209         }
2210         context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2211         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2212         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2213         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2214         context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2215         context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2216         context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2217         context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2218
2219         if (!pstate_en) {
2220                 /* The only difference between A and C is p-state latency, if p-state is not supported we want to
2221                  * calculate DLG based on dummy p-state latency, and max out the set A p-state watermark
2222                  */
2223                 context->bw_ctx.bw.dcn.watermarks.a = context->bw_ctx.bw.dcn.watermarks.c;
2224                 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 0;
2225         } else {
2226                 /* Set A:
2227                  * DCFCLK: Min Required
2228                  * FCLK(proportional to UCLK): 1GHz or Max
2229                  *
2230                  * Set A calculated last so that following calculations are based on Set A
2231                  */
2232                 dc->res_pool->funcs->update_soc_for_wm_a(dc, context);
2233                 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2234                 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2235                 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2236                 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2237                 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2238                 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2239                 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2240                 context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2241         }
2242
2243         context->perf_params.stutter_period_us = context->bw_ctx.dml.vba.StutterPeriod;
2244
2245         /* Make set D = set A until set D is enabled */
2246         context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a;
2247
2248         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2249                 if (!context->res_ctx.pipe_ctx[i].stream)
2250                         continue;
2251
2252                 pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt);
2253                 pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
2254
2255                 if (dc->config.forced_clocks) {
2256                         pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
2257                         pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
2258                 }
2259                 if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000)
2260                         pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
2261                 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
2262                         pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
2263
2264                 pipe_idx++;
2265         }
2266
2267         dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
2268
2269         if (!pstate_en)
2270                 /* Restore full p-state latency */
2271                 context->bw_ctx.dml.soc.dram_clock_change_latency_us =
2272                                 dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
2273 }
2274
2275 void dcn30_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)
2276 {
2277         if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid) {
2278                 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
2279                 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us;
2280                 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us;
2281         }
2282 }
2283
2284 void dcn30_calculate_wm_and_dlg(
2285                 struct dc *dc, struct dc_state *context,
2286                 display_e2e_pipe_params_st *pipes,
2287                 int pipe_cnt,
2288                 int vlevel)
2289 {
2290         DC_FP_START();
2291         dcn30_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel);
2292         DC_FP_END();
2293 }
2294
2295 bool dcn30_validate_bandwidth(struct dc *dc,
2296                 struct dc_state *context,
2297                 bool fast_validate)
2298 {
2299         bool out = false;
2300
2301         BW_VAL_TRACE_SETUP();
2302
2303         int vlevel = 0;
2304         int pipe_cnt = 0;
2305         display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
2306         DC_LOGGER_INIT(dc->ctx->logger);
2307
2308         BW_VAL_TRACE_COUNT();
2309
2310         out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate);
2311
2312         if (pipe_cnt == 0)
2313                 goto validate_out;
2314
2315         if (!out)
2316                 goto validate_fail;
2317
2318         BW_VAL_TRACE_END_VOLTAGE_LEVEL();
2319
2320         if (fast_validate) {
2321                 BW_VAL_TRACE_SKIP(fast);
2322                 goto validate_out;
2323         }
2324
2325         DC_FP_START();
2326         dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);
2327         DC_FP_END();
2328
2329         BW_VAL_TRACE_END_WATERMARKS();
2330
2331         goto validate_out;
2332
2333 validate_fail:
2334         DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
2335                 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
2336
2337         BW_VAL_TRACE_SKIP(fail);
2338         out = false;
2339
2340 validate_out:
2341         kfree(pipes);
2342
2343         BW_VAL_TRACE_FINISH();
2344
2345         return out;
2346 }
2347
2348 /*
2349  * This must be noinline to ensure anything that deals with FP registers
2350  * is contained within this call; previously our compiling with hard-float
2351  * would result in fp instructions being emitted outside of the boundaries
2352  * of the DC_FP_START/END macros, which makes sense as the compiler has no
2353  * idea about what is wrapped and what is not
2354  *
2355  * This is largely just a workaround to avoid breakage introduced with 5.6,
2356  * ideally all fp-using code should be moved into its own file, only that
2357  * should be compiled with hard-float, and all code exported from there
2358  * should be strictly wrapped with DC_FP_START/END
2359  */
2360 static noinline void dcn30_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts,
2361                 unsigned int *optimal_dcfclk,
2362                 unsigned int *optimal_fclk)
2363 {
2364        double bw_from_dram, bw_from_dram1, bw_from_dram2;
2365
2366        bw_from_dram1 = uclk_mts * dcn3_0_soc.num_chans *
2367                 dcn3_0_soc.dram_channel_width_bytes * (dcn3_0_soc.max_avg_dram_bw_use_normal_percent / 100);
2368        bw_from_dram2 = uclk_mts * dcn3_0_soc.num_chans *
2369                 dcn3_0_soc.dram_channel_width_bytes * (dcn3_0_soc.max_avg_sdp_bw_use_normal_percent / 100);
2370
2371        bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2;
2372
2373        if (optimal_fclk)
2374                *optimal_fclk = bw_from_dram /
2375                (dcn3_0_soc.fabric_datapath_to_dcn_data_return_bytes * (dcn3_0_soc.max_avg_sdp_bw_use_normal_percent / 100));
2376
2377        if (optimal_dcfclk)
2378                *optimal_dcfclk =  bw_from_dram /
2379                (dcn3_0_soc.return_bus_width_bytes * (dcn3_0_soc.max_avg_sdp_bw_use_normal_percent / 100));
2380 }
2381
2382 void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
2383 {
2384         unsigned int i, j;
2385         unsigned int num_states = 0;
2386
2387         unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0};
2388         unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0};
2389         unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0};
2390         unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0};
2391
2392         unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200};
2393         unsigned int num_dcfclk_sta_targets = 4;
2394         unsigned int num_uclk_states;
2395
2396         if (dc->ctx->dc_bios->vram_info.num_chans)
2397                 dcn3_0_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans;
2398
2399         if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes)
2400                 dcn3_0_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes;
2401
2402         dcn3_0_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
2403         dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
2404
2405         if (bw_params->clk_table.entries[0].memclk_mhz) {
2406                 int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0;
2407
2408                 for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
2409                         if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)
2410                                 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
2411                         if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz)
2412                                 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
2413                         if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz)
2414                                 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
2415                         if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz)
2416                                 max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
2417                 }
2418
2419                 if (!max_dcfclk_mhz)
2420                         max_dcfclk_mhz = dcn3_0_soc.clock_limits[0].dcfclk_mhz;
2421                 if (!max_dispclk_mhz)
2422                         max_dispclk_mhz = dcn3_0_soc.clock_limits[0].dispclk_mhz;
2423                 if (!max_dppclk_mhz)
2424                         max_dppclk_mhz = dcn3_0_soc.clock_limits[0].dppclk_mhz;
2425                 if (!max_phyclk_mhz)
2426                         max_phyclk_mhz = dcn3_0_soc.clock_limits[0].phyclk_mhz;
2427
2428                 if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
2429                         // If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array
2430                         dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz;
2431                         num_dcfclk_sta_targets++;
2432                 } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
2433                         // If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates
2434                         for (i = 0; i < num_dcfclk_sta_targets; i++) {
2435                                 if (dcfclk_sta_targets[i] > max_dcfclk_mhz) {
2436                                         dcfclk_sta_targets[i] = max_dcfclk_mhz;
2437                                         break;
2438                                 }
2439                         }
2440                         // Update size of array since we "removed" duplicates
2441                         num_dcfclk_sta_targets = i + 1;
2442                 }
2443
2444                 num_uclk_states = bw_params->clk_table.num_entries;
2445
2446                 // Calculate optimal dcfclk for each uclk
2447                 for (i = 0; i < num_uclk_states; i++) {
2448                         DC_FP_START();
2449                         dcn30_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16,
2450                                         &optimal_dcfclk_for_uclk[i], NULL);
2451                         DC_FP_END();
2452                         if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) {
2453                                 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz;
2454                         }
2455                 }
2456
2457                 // Calculate optimal uclk for each dcfclk sta target
2458                 for (i = 0; i < num_dcfclk_sta_targets; i++) {
2459                         for (j = 0; j < num_uclk_states; j++) {
2460                                 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
2461                                         optimal_uclk_for_dcfclk_sta_targets[i] =
2462                                                         bw_params->clk_table.entries[j].memclk_mhz * 16;
2463                                         break;
2464                                 }
2465                         }
2466                 }
2467
2468                 i = 0;
2469                 j = 0;
2470                 // create the final dcfclk and uclk table
2471                 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {
2472                         if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {
2473                                 dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
2474                                 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
2475                         } else {
2476                                 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
2477                                         dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
2478                                         dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
2479                                 } else {
2480                                         j = num_uclk_states;
2481                                 }
2482                         }
2483                 }
2484
2485                 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) {
2486                         dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
2487                         dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
2488                 }
2489
2490                 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES &&
2491                                 optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
2492                         dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
2493                         dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
2494                 }
2495
2496                 dcn3_0_soc.num_states = num_states;
2497                 for (i = 0; i < dcn3_0_soc.num_states; i++) {
2498                         dcn3_0_soc.clock_limits[i].state = i;
2499                         dcn3_0_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i];
2500                         dcn3_0_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i];
2501                         dcn3_0_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i];
2502
2503                         /* Fill all states with max values of all other clocks */
2504                         dcn3_0_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz;
2505                         dcn3_0_soc.clock_limits[i].dppclk_mhz  = max_dppclk_mhz;
2506                         dcn3_0_soc.clock_limits[i].phyclk_mhz  = max_phyclk_mhz;
2507                         dcn3_0_soc.clock_limits[i].dtbclk_mhz = dcn3_0_soc.clock_limits[0].dtbclk_mhz;
2508                         /* These clocks cannot come from bw_params, always fill from dcn3_0_soc[1] */
2509                         /* FCLK, PHYCLK_D18, SOCCLK, DSCCLK */
2510                         dcn3_0_soc.clock_limits[i].phyclk_d18_mhz = dcn3_0_soc.clock_limits[0].phyclk_d18_mhz;
2511                         dcn3_0_soc.clock_limits[i].socclk_mhz = dcn3_0_soc.clock_limits[0].socclk_mhz;
2512                         dcn3_0_soc.clock_limits[i].dscclk_mhz = dcn3_0_soc.clock_limits[0].dscclk_mhz;
2513                 }
2514                 /* re-init DML with updated bb */
2515                 dml_init_instance(&dc->dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30);
2516                 if (dc->current_state)
2517                         dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30);
2518         }
2519 }
2520
2521 static const struct resource_funcs dcn30_res_pool_funcs = {
2522         .destroy = dcn30_destroy_resource_pool,
2523         .link_enc_create = dcn30_link_encoder_create,
2524         .panel_cntl_create = dcn30_panel_cntl_create,
2525         .validate_bandwidth = dcn30_validate_bandwidth,
2526         .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg,
2527         .update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
2528         .populate_dml_pipes = dcn30_populate_dml_pipes_from_context,
2529         .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
2530         .add_stream_to_ctx = dcn30_add_stream_to_ctx,
2531         .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
2532         .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
2533         .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
2534         .set_mcif_arb_params = dcn30_set_mcif_arb_params,
2535         .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
2536         .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
2537         .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
2538         .update_bw_bounding_box = dcn30_update_bw_bounding_box,
2539         .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
2540 };
2541
2542 #define CTX ctx
2543
2544 #define REG(reg_name) \
2545         (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
2546
2547 static uint32_t read_pipe_fuses(struct dc_context *ctx)
2548 {
2549         uint32_t value = REG_READ(CC_DC_PIPE_DIS);
2550         /* Support for max 6 pipes */
2551         value = value & 0x3f;
2552         return value;
2553 }
2554
2555 static bool dcn30_resource_construct(
2556         uint8_t num_virtual_links,
2557         struct dc *dc,
2558         struct dcn30_resource_pool *pool)
2559 {
2560         int i;
2561         struct dc_context *ctx = dc->ctx;
2562         struct irq_service_init_data init_data;
2563         struct ddc_service_init_data ddc_init_data = {0};
2564         uint32_t pipe_fuses = read_pipe_fuses(ctx);
2565         uint32_t num_pipes = 0;
2566
2567         if (!(pipe_fuses == 0 || pipe_fuses == 0x3e)) {
2568                 BREAK_TO_DEBUGGER();
2569                 dm_error("DC: Unexpected fuse recipe for navi2x !\n");
2570                 /* fault to single pipe */
2571                 pipe_fuses = 0x3e;
2572         }
2573
2574         DC_FP_START();
2575
2576         ctx->dc_bios->regs = &bios_regs;
2577
2578         pool->base.res_cap = &res_cap_dcn3;
2579
2580         pool->base.funcs = &dcn30_res_pool_funcs;
2581
2582         /*************************************************
2583          *  Resource + asic cap harcoding                *
2584          *************************************************/
2585         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
2586         pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
2587         pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
2588         dc->caps.max_downscale_ratio = 600;
2589         dc->caps.i2c_speed_in_khz = 100;
2590         dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/
2591         dc->caps.max_cursor_size = 256;
2592         dc->caps.min_horizontal_blanking_period = 80;
2593         dc->caps.dmdata_alloc_size = 2048;
2594         dc->caps.mall_size_per_mem_channel = 8;
2595         /* total size = mall per channel * num channels * 1024 * 1024 */
2596         dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576;
2597         dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
2598
2599         dc->caps.max_slave_planes = 1;
2600         dc->caps.max_slave_yuv_planes = 1;
2601         dc->caps.max_slave_rgb_planes = 1;
2602         dc->caps.post_blend_color_processing = true;
2603         dc->caps.force_dp_tps4_for_cp2520 = true;
2604         dc->caps.extended_aux_timeout_support = true;
2605         dc->caps.dmcub_support = true;
2606
2607         /* Color pipeline capabilities */
2608         dc->caps.color.dpp.dcn_arch = 1;
2609         dc->caps.color.dpp.input_lut_shared = 0;
2610         dc->caps.color.dpp.icsc = 1;
2611         dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
2612         dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
2613         dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
2614         dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
2615         dc->caps.color.dpp.dgam_rom_caps.pq = 1;
2616         dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
2617         dc->caps.color.dpp.post_csc = 1;
2618         dc->caps.color.dpp.gamma_corr = 1;
2619         dc->caps.color.dpp.dgam_rom_for_yuv = 0;
2620
2621         dc->caps.color.dpp.hw_3d_lut = 1;
2622         dc->caps.color.dpp.ogam_ram = 1;
2623         // no OGAM ROM on DCN3
2624         dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
2625         dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
2626         dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
2627         dc->caps.color.dpp.ogam_rom_caps.pq = 0;
2628         dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
2629         dc->caps.color.dpp.ocsc = 0;
2630
2631         dc->caps.color.mpc.gamut_remap = 1;
2632         dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //3
2633         dc->caps.color.mpc.ogam_ram = 1;
2634         dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
2635         dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
2636         dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
2637         dc->caps.color.mpc.ogam_rom_caps.pq = 0;
2638         dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
2639         dc->caps.color.mpc.ocsc = 1;
2640
2641         /* read VBIOS LTTPR caps */
2642         {
2643                 if (ctx->dc_bios->funcs->get_lttpr_caps) {
2644                         enum bp_result bp_query_result;
2645                         uint8_t is_vbios_lttpr_enable = 0;
2646
2647                         bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
2648                         dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
2649                 }
2650
2651                 if (ctx->dc_bios->funcs->get_lttpr_interop) {
2652                         enum bp_result bp_query_result;
2653                         uint8_t is_vbios_interop_enabled = 0;
2654
2655                         bp_query_result = ctx->dc_bios->funcs->get_lttpr_interop(ctx->dc_bios,
2656                                         &is_vbios_interop_enabled);
2657                         dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled;
2658                 }
2659         }
2660
2661         if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
2662                 dc->debug = debug_defaults_drv;
2663         else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
2664                 dc->debug = debug_defaults_diags;
2665         } else
2666                 dc->debug = debug_defaults_diags;
2667         // Init the vm_helper
2668         if (dc->vm_helper)
2669                 vm_helper_init(dc->vm_helper, 16);
2670
2671         /*************************************************
2672          *  Create resources                             *
2673          *************************************************/
2674
2675         /* Clock Sources for Pixel Clock*/
2676         pool->base.clock_sources[DCN30_CLK_SRC_PLL0] =
2677                         dcn30_clock_source_create(ctx, ctx->dc_bios,
2678                                 CLOCK_SOURCE_COMBO_PHY_PLL0,
2679                                 &clk_src_regs[0], false);
2680         pool->base.clock_sources[DCN30_CLK_SRC_PLL1] =
2681                         dcn30_clock_source_create(ctx, ctx->dc_bios,
2682                                 CLOCK_SOURCE_COMBO_PHY_PLL1,
2683                                 &clk_src_regs[1], false);
2684         pool->base.clock_sources[DCN30_CLK_SRC_PLL2] =
2685                         dcn30_clock_source_create(ctx, ctx->dc_bios,
2686                                 CLOCK_SOURCE_COMBO_PHY_PLL2,
2687                                 &clk_src_regs[2], false);
2688         pool->base.clock_sources[DCN30_CLK_SRC_PLL3] =
2689                         dcn30_clock_source_create(ctx, ctx->dc_bios,
2690                                 CLOCK_SOURCE_COMBO_PHY_PLL3,
2691                                 &clk_src_regs[3], false);
2692         pool->base.clock_sources[DCN30_CLK_SRC_PLL4] =
2693                         dcn30_clock_source_create(ctx, ctx->dc_bios,
2694                                 CLOCK_SOURCE_COMBO_PHY_PLL4,
2695                                 &clk_src_regs[4], false);
2696         pool->base.clock_sources[DCN30_CLK_SRC_PLL5] =
2697                         dcn30_clock_source_create(ctx, ctx->dc_bios,
2698                                 CLOCK_SOURCE_COMBO_PHY_PLL5,
2699                                 &clk_src_regs[5], false);
2700
2701         pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL;
2702
2703         /* todo: not reuse phy_pll registers */
2704         pool->base.dp_clock_source =
2705                         dcn30_clock_source_create(ctx, ctx->dc_bios,
2706                                 CLOCK_SOURCE_ID_DP_DTO,
2707                                 &clk_src_regs[0], true);
2708
2709         for (i = 0; i < pool->base.clk_src_count; i++) {
2710                 if (pool->base.clock_sources[i] == NULL) {
2711                         dm_error("DC: failed to create clock sources!\n");
2712                         BREAK_TO_DEBUGGER();
2713                         goto create_fail;
2714                 }
2715         }
2716
2717         /* DCCG */
2718         pool->base.dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2719         if (pool->base.dccg == NULL) {
2720                 dm_error("DC: failed to create dccg!\n");
2721                 BREAK_TO_DEBUGGER();
2722                 goto create_fail;
2723         }
2724
2725         /* PP Lib and SMU interfaces */
2726         init_soc_bounding_box(dc, pool);
2727
2728         num_pipes = dcn3_0_ip.max_num_dpp;
2729
2730         for (i = 0; i < dcn3_0_ip.max_num_dpp; i++)
2731                 if (pipe_fuses & 1 << i)
2732                         num_pipes--;
2733
2734         dcn3_0_ip.max_num_dpp = num_pipes;
2735         dcn3_0_ip.max_num_otg = num_pipes;
2736
2737         dml_init_instance(&dc->dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30);
2738
2739         /* IRQ */
2740         init_data.ctx = dc->ctx;
2741         pool->base.irqs = dal_irq_service_dcn30_create(&init_data);
2742         if (!pool->base.irqs)
2743                 goto create_fail;
2744
2745         /* HUBBUB */
2746         pool->base.hubbub = dcn30_hubbub_create(ctx);
2747         if (pool->base.hubbub == NULL) {
2748                 BREAK_TO_DEBUGGER();
2749                 dm_error("DC: failed to create hubbub!\n");
2750                 goto create_fail;
2751         }
2752
2753         /* HUBPs, DPPs, OPPs and TGs */
2754         for (i = 0; i < pool->base.pipe_count; i++) {
2755                 pool->base.hubps[i] = dcn30_hubp_create(ctx, i);
2756                 if (pool->base.hubps[i] == NULL) {
2757                         BREAK_TO_DEBUGGER();
2758                         dm_error(
2759                                 "DC: failed to create hubps!\n");
2760                         goto create_fail;
2761                 }
2762
2763                 pool->base.dpps[i] = dcn30_dpp_create(ctx, i);
2764                 if (pool->base.dpps[i] == NULL) {
2765                         BREAK_TO_DEBUGGER();
2766                         dm_error(
2767                                 "DC: failed to create dpps!\n");
2768                         goto create_fail;
2769                 }
2770         }
2771
2772         for (i = 0; i < pool->base.res_cap->num_opp; i++) {
2773                 pool->base.opps[i] = dcn30_opp_create(ctx, i);
2774                 if (pool->base.opps[i] == NULL) {
2775                         BREAK_TO_DEBUGGER();
2776                         dm_error(
2777                                 "DC: failed to create output pixel processor!\n");
2778                         goto create_fail;
2779                 }
2780         }
2781
2782         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2783                 pool->base.timing_generators[i] = dcn30_timing_generator_create(
2784                                 ctx, i);
2785                 if (pool->base.timing_generators[i] == NULL) {
2786                         BREAK_TO_DEBUGGER();
2787                         dm_error("DC: failed to create tg!\n");
2788                         goto create_fail;
2789                 }
2790         }
2791         pool->base.timing_generator_count = i;
2792         /* PSR */
2793         pool->base.psr = dmub_psr_create(ctx);
2794
2795         if (pool->base.psr == NULL) {
2796                 dm_error("DC: failed to create PSR obj!\n");
2797                 BREAK_TO_DEBUGGER();
2798                 goto create_fail;
2799         }
2800
2801         /* ABM */
2802         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2803                 pool->base.multiple_abms[i] = dmub_abm_create(ctx,
2804                                 &abm_regs[i],
2805                                 &abm_shift,
2806                                 &abm_mask);
2807                 if (pool->base.multiple_abms[i] == NULL) {
2808                         dm_error("DC: failed to create abm for pipe %d!\n", i);
2809                         BREAK_TO_DEBUGGER();
2810                         goto create_fail;
2811                 }
2812         }
2813         /* MPC and DSC */
2814         pool->base.mpc = dcn30_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
2815         if (pool->base.mpc == NULL) {
2816                 BREAK_TO_DEBUGGER();
2817                 dm_error("DC: failed to create mpc!\n");
2818                 goto create_fail;
2819         }
2820
2821         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2822                 pool->base.dscs[i] = dcn30_dsc_create(ctx, i);
2823                 if (pool->base.dscs[i] == NULL) {
2824                         BREAK_TO_DEBUGGER();
2825                         dm_error("DC: failed to create display stream compressor %d!\n", i);
2826                         goto create_fail;
2827                 }
2828         }
2829
2830         /* DWB and MMHUBBUB */
2831         if (!dcn30_dwbc_create(ctx, &pool->base)) {
2832                 BREAK_TO_DEBUGGER();
2833                 dm_error("DC: failed to create dwbc!\n");
2834                 goto create_fail;
2835         }
2836
2837         if (!dcn30_mmhubbub_create(ctx, &pool->base)) {
2838                 BREAK_TO_DEBUGGER();
2839                 dm_error("DC: failed to create mcif_wb!\n");
2840                 goto create_fail;
2841         }
2842
2843         /* AUX and I2C */
2844         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2845                 pool->base.engines[i] = dcn30_aux_engine_create(ctx, i);
2846                 if (pool->base.engines[i] == NULL) {
2847                         BREAK_TO_DEBUGGER();
2848                         dm_error(
2849                                 "DC:failed to create aux engine!!\n");
2850                         goto create_fail;
2851                 }
2852                 pool->base.hw_i2cs[i] = dcn30_i2c_hw_create(ctx, i);
2853                 if (pool->base.hw_i2cs[i] == NULL) {
2854                         BREAK_TO_DEBUGGER();
2855                         dm_error(
2856                                 "DC:failed to create hw i2c!!\n");
2857                         goto create_fail;
2858                 }
2859                 pool->base.sw_i2cs[i] = NULL;
2860         }
2861
2862         /* Audio, Stream Encoders including DIG and virtual, MPC 3D LUTs */
2863         if (!resource_construct(num_virtual_links, dc, &pool->base,
2864                         (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
2865                         &res_create_funcs : &res_create_maximus_funcs)))
2866                 goto create_fail;
2867
2868         /* HW Sequencer and Plane caps */
2869         dcn30_hw_sequencer_construct(dc);
2870
2871         dc->caps.max_planes =  pool->base.pipe_count;
2872
2873         for (i = 0; i < dc->caps.max_planes; ++i)
2874                 dc->caps.planes[i] = plane_cap;
2875
2876         dc->cap_funcs = cap_funcs;
2877
2878         if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
2879                 ddc_init_data.ctx = dc->ctx;
2880                 ddc_init_data.link = NULL;
2881                 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
2882                 ddc_init_data.id.enum_id = 0;
2883                 ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
2884                 pool->base.oem_device = dal_ddc_service_create(&ddc_init_data);
2885         } else {
2886                 pool->base.oem_device = NULL;
2887         }
2888
2889         DC_FP_END();
2890
2891         return true;
2892
2893 create_fail:
2894
2895         DC_FP_END();
2896         dcn30_resource_destruct(pool);
2897
2898         return false;
2899 }
2900
2901 struct resource_pool *dcn30_create_resource_pool(
2902                 const struct dc_init_data *init_data,
2903                 struct dc *dc)
2904 {
2905         struct dcn30_resource_pool *pool =
2906                 kzalloc(sizeof(struct dcn30_resource_pool), GFP_KERNEL);
2907
2908         if (!pool)
2909                 return NULL;
2910
2911         if (dcn30_resource_construct(init_data->num_virtual_links, dc, pool))
2912                 return &pool->base;
2913
2914         BREAK_TO_DEBUGGER();
2915         kfree(pool);
2916         return NULL;
2917 }