2 * Copyright 2020 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
27 #include "dm_services.h"
30 #include "dcn30_init.h"
33 #include "include/irq_service_interface.h"
34 #include "dcn20/dcn20_resource.h"
36 #include "dcn30_resource.h"
38 #include "dcn10/dcn10_ipp.h"
39 #include "dcn30/dcn30_hubbub.h"
40 #include "dcn30/dcn30_mpc.h"
41 #include "dcn30/dcn30_hubp.h"
42 #include "irq/dcn30/irq_service_dcn30.h"
43 #include "dcn30/dcn30_dpp.h"
44 #include "dcn30/dcn30_optc.h"
45 #include "dcn20/dcn20_hwseq.h"
46 #include "dcn30/dcn30_hwseq.h"
47 #include "dce110/dce110_hw_sequencer.h"
48 #include "dcn30/dcn30_opp.h"
49 #include "dcn20/dcn20_dsc.h"
50 #include "dcn30/dcn30_vpg.h"
51 #include "dcn30/dcn30_afmt.h"
52 #include "dcn30/dcn30_dio_stream_encoder.h"
53 #include "dcn30/dcn30_dio_link_encoder.h"
54 #include "dce/dce_clock_source.h"
55 #include "dce/dce_audio.h"
56 #include "dce/dce_hwseq.h"
58 #include "virtual/virtual_stream_encoder.h"
59 #include "dce110/dce110_resource.h"
60 #include "dml/display_mode_vba.h"
61 #include "dcn30/dcn30_dccg.h"
62 #include "dcn10/dcn10_resource.h"
63 #include "dc_link_ddc.h"
64 #include "dce/dce_panel_cntl.h"
66 #include "dcn30/dcn30_dwb.h"
67 #include "dcn30/dcn30_mmhubbub.h"
69 #include "sienna_cichlid_ip_offset.h"
70 #include "dcn/dcn_3_0_0_offset.h"
71 #include "dcn/dcn_3_0_0_sh_mask.h"
73 #include "nbio/nbio_7_4_offset.h"
75 #include "dcn/dpcs_3_0_0_offset.h"
76 #include "dcn/dpcs_3_0_0_sh_mask.h"
78 #include "mmhub/mmhub_2_0_0_offset.h"
79 #include "mmhub/mmhub_2_0_0_sh_mask.h"
81 #include "reg_helper.h"
82 #include "dce/dmub_abm.h"
83 #include "dce/dmub_psr.h"
84 #include "dce/dce_aux.h"
85 #include "dce/dce_i2c.h"
87 #include "dml/dcn30/display_mode_vba_30.h"
88 #include "vm_helper.h"
89 #include "dcn20/dcn20_vmid.h"
90 #include "amdgpu_socbb.h"
92 #define DC_LOGGER_INIT(logger)
94 struct _vcs_dpi_ip_params_st dcn3_0_ip = {
96 .clamp_min_dcfclk = 0,
100 .gpuvm_max_page_table_levels = 4,
101 .hostvm_max_page_table_levels = 4,
102 .hostvm_cached_page_table_levels = 0,
103 .pte_group_size_bytes = 2048,
105 .rob_buffer_size_kbytes = 184,
106 .det_buffer_size_kbytes = 184,
107 .dpte_buffer_size_in_pte_reqs_luma = 84,
108 .pde_proc_buffer_size_64k_reqs = 48,
109 .dpp_output_buffer_pixels = 2560,
110 .opp_output_buffer_lines = 1,
111 .pixel_chunk_size_kbytes = 8,
113 .max_page_table_levels = 2,
114 .pte_chunk_size_kbytes = 2, // ?
115 .meta_chunk_size_kbytes = 2,
116 .writeback_chunk_size_kbytes = 8,
117 .line_buffer_size_bits = 789504,
118 .is_line_buffer_bpp_fixed = 0, // ?
119 .line_buffer_fixed_bpp = 0, // ?
120 .dcc_supported = true,
121 .writeback_interface_buffer_size_kbytes = 90,
122 .writeback_line_buffer_buffer_size = 0,
123 .max_line_buffer_lines = 12,
124 .writeback_luma_buffer_size_kbytes = 12, // writeback_line_buffer_buffer_size = 656640
125 .writeback_chroma_buffer_size_kbytes = 8,
126 .writeback_chroma_line_buffer_width_pixels = 4,
127 .writeback_max_hscl_ratio = 1,
128 .writeback_max_vscl_ratio = 1,
129 .writeback_min_hscl_ratio = 1,
130 .writeback_min_vscl_ratio = 1,
131 .writeback_max_hscl_taps = 1,
132 .writeback_max_vscl_taps = 1,
133 .writeback_line_buffer_luma_buffer_size = 0,
134 .writeback_line_buffer_chroma_buffer_size = 14643,
135 .cursor_buffer_size = 8,
136 .cursor_chunk_size = 2,
140 .max_dchub_pscl_bw_pix_per_clk = 4,
141 .max_pscl_lb_bw_pix_per_clk = 2,
142 .max_lb_vscl_bw_pix_per_clk = 4,
143 .max_vscl_hscl_bw_pix_per_clk = 4,
150 .dispclk_ramp_margin_percent = 1,
151 .underscan_factor = 1.11,
152 .min_vblank_lines = 32,
153 .dppclk_delay_subtotal = 46,
154 .dynamic_metadata_vm_enabled = true,
155 .dppclk_delay_scl_lb_only = 16,
156 .dppclk_delay_scl = 50,
157 .dppclk_delay_cnvc_formatter = 27,
158 .dppclk_delay_cnvc_cursor = 6,
159 .dispclk_delay_subtotal = 119,
160 .dcfclk_cstate_latency = 5.2, // SRExitTime
161 .max_inter_dcn_tile_repeaters = 8,
162 .odm_combine_4to1_supported = true,
164 .xfc_supported = false,
165 .xfc_fill_bw_overhead_percent = 10.0,
166 .xfc_fill_constant_bytes = 0,
167 .gfx7_compat_tiling_supported = 0,
168 .number_of_cursors = 1,
171 struct _vcs_dpi_soc_bounding_box_st dcn3_0_soc = {
175 .dispclk_mhz = 562.0,
178 .phyclk_d18_mhz = 667.0,
182 .min_dcfclk = 500.0, /* TODO: set this to actual min DCFCLK */
184 .sr_exit_time_us = 12,
185 .sr_enter_plus_exit_time_us = 20,
186 .urgent_latency_us = 4.0,
187 .urgent_latency_pixel_data_only_us = 4.0,
188 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
189 .urgent_latency_vm_data_only_us = 4.0,
190 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
191 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
192 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
193 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0,
194 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0,
195 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
196 .max_avg_sdp_bw_use_normal_percent = 60.0,
197 .max_avg_dram_bw_use_normal_percent = 40.0,
198 .writeback_latency_us = 12.0,
199 .max_request_size_bytes = 256,
200 .fabric_datapath_to_dcn_data_return_bytes = 64,
201 .dcn_downspread_percent = 0.5,
202 .downspread_percent = 0.38,
203 .dram_page_open_time_ns = 50.0,
204 .dram_rw_turnaround_time_ns = 17.5,
205 .dram_return_buffer_per_channel_bytes = 8192,
206 .round_trip_ping_latency_dcfclk_cycles = 191,
207 .urgent_out_of_order_return_per_channel_bytes = 4096,
208 .channel_interleave_bytes = 256,
210 .gpuvm_min_page_size_bytes = 4096,
211 .hostvm_min_page_size_bytes = 4096,
212 .dram_clock_change_latency_us = 404,
213 .dummy_pstate_latency_us = 5,
214 .writeback_dram_clock_change_latency_us = 23.0,
215 .return_bus_width_bytes = 64,
216 .dispclk_dppclk_vco_speed_mhz = 3650,
217 .xfc_bus_transport_time_us = 20, // ?
218 .xfc_xbuf_latency_tolerance_us = 4, // ?
219 .use_urgent_burst_bw = 1, // ?
220 .do_urgent_latency_adjustment = true,
221 .urgent_latency_adjustment_fabric_clock_component_us = 1.0,
222 .urgent_latency_adjustment_fabric_clock_reference_mhz = 1000,
225 enum dcn30_clk_src_array_id {
235 /* begin *********************
236 * macros to expend register list macro defined in HW object header file
240 /* TODO awful hack. fixup dcn20_dwb.h */
242 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
244 #define BASE(seg) BASE_INNER(seg)
246 #define SR(reg_name)\
247 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
250 #define SRI(reg_name, block, id)\
251 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
252 mm ## block ## id ## _ ## reg_name
254 #define SRI2(reg_name, block, id)\
255 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
258 #define SRIR(var_name, reg_name, block, id)\
259 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
260 mm ## block ## id ## _ ## reg_name
262 #define SRII(reg_name, block, id)\
263 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
264 mm ## block ## id ## _ ## reg_name
266 #define SRII_MPC_RMU(reg_name, block, id)\
267 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
268 mm ## block ## id ## _ ## reg_name
270 #define SRII_DWB(reg_name, temp_name, block, id)\
271 .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
272 mm ## block ## id ## _ ## temp_name
274 #define DCCG_SRII(reg_name, block, id)\
275 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
276 mm ## block ## id ## _ ## reg_name
278 #define VUPDATE_SRII(reg_name, block, id)\
279 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
280 mm ## reg_name ## _ ## block ## id
283 #define NBIO_BASE_INNER(seg) \
284 NBIO_BASE__INST0_SEG ## seg
286 #define NBIO_BASE(seg) \
289 #define NBIO_SR(reg_name)\
290 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
294 #define MMHUB_BASE_INNER(seg) \
295 MMHUB_BASE__INST0_SEG ## seg
297 #define MMHUB_BASE(seg) \
298 MMHUB_BASE_INNER(seg)
300 #define MMHUB_SR(reg_name)\
301 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
305 #define CLK_BASE_INNER(seg) \
306 CLK_BASE__INST0_SEG ## seg
308 #define CLK_BASE(seg) \
311 #define CLK_SRI(reg_name, block, inst)\
312 .reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
313 mm ## block ## _ ## inst ## _ ## reg_name
316 static const struct bios_registers bios_regs = {
317 NBIO_SR(BIOS_SCRATCH_3),
318 NBIO_SR(BIOS_SCRATCH_6)
321 #define clk_src_regs(index, pllid)\
323 CS_COMMON_REG_LIST_DCN2_0(index, pllid),\
326 static const struct dce110_clk_src_regs clk_src_regs[] = {
335 static const struct dce110_clk_src_shift cs_shift = {
336 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
339 static const struct dce110_clk_src_mask cs_mask = {
340 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
343 #define abm_regs(id)\
345 ABM_DCN30_REG_LIST(id)\
348 static const struct dce_abm_registers abm_regs[] = {
357 static const struct dce_abm_shift abm_shift = {
358 ABM_MASK_SH_LIST_DCN301(__SHIFT)
361 static const struct dce_abm_mask abm_mask = {
362 ABM_MASK_SH_LIST_DCN301(_MASK)
367 #define audio_regs(id)\
369 AUD_COMMON_REG_LIST(id)\
372 static const struct dce_audio_registers audio_regs[] = {
382 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
383 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
384 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
385 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
387 static const struct dce_audio_shift audio_shift = {
388 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
391 static const struct dce_audio_mask audio_mask = {
392 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
395 #define vpg_regs(id)\
397 VPG_DCN3_REG_LIST(id)\
400 static const struct dcn30_vpg_registers vpg_regs[] = {
410 static const struct dcn30_vpg_shift vpg_shift = {
411 DCN3_VPG_MASK_SH_LIST(__SHIFT)
414 static const struct dcn30_vpg_mask vpg_mask = {
415 DCN3_VPG_MASK_SH_LIST(_MASK)
418 #define afmt_regs(id)\
420 AFMT_DCN3_REG_LIST(id)\
423 static const struct dcn30_afmt_registers afmt_regs[] = {
433 static const struct dcn30_afmt_shift afmt_shift = {
434 DCN3_AFMT_MASK_SH_LIST(__SHIFT)
437 static const struct dcn30_afmt_mask afmt_mask = {
438 DCN3_AFMT_MASK_SH_LIST(_MASK)
441 #define stream_enc_regs(id)\
443 SE_DCN3_REG_LIST(id)\
446 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
455 static const struct dcn10_stream_encoder_shift se_shift = {
456 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
459 static const struct dcn10_stream_encoder_mask se_mask = {
460 SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
464 #define aux_regs(id)\
466 DCN2_AUX_REG_LIST(id)\
469 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
478 #define hpd_regs(id)\
483 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
492 #define link_regs(id, phyid)\
494 LE_DCN3_REG_LIST(id), \
495 UNIPHY_DCN2_REG_LIST(phyid), \
496 DPCS_DCN2_REG_LIST(id), \
497 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
500 static const struct dce110_aux_registers_shift aux_shift = {
501 DCN_AUX_MASK_SH_LIST(__SHIFT)
504 static const struct dce110_aux_registers_mask aux_mask = {
505 DCN_AUX_MASK_SH_LIST(_MASK)
508 static const struct dcn10_link_enc_registers link_enc_regs[] = {
517 static const struct dcn10_link_enc_shift le_shift = {
518 LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT),\
519 DPCS_DCN2_MASK_SH_LIST(__SHIFT)
522 static const struct dcn10_link_enc_mask le_mask = {
523 LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK),\
524 DPCS_DCN2_MASK_SH_LIST(_MASK)
528 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
529 { DCN_PANEL_CNTL_REG_LIST() }
532 static const struct dce_panel_cntl_shift panel_cntl_shift = {
533 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
536 static const struct dce_panel_cntl_mask panel_cntl_mask = {
537 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
540 #define dpp_regs(id)\
542 DPP_REG_LIST_DCN30(id),\
545 static const struct dcn3_dpp_registers dpp_regs[] = {
554 static const struct dcn3_dpp_shift tf_shift = {
555 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
558 static const struct dcn3_dpp_mask tf_mask = {
559 DPP_REG_LIST_SH_MASK_DCN30(_MASK)
562 #define opp_regs(id)\
564 OPP_REG_LIST_DCN30(id),\
567 static const struct dcn20_opp_registers opp_regs[] = {
576 static const struct dcn20_opp_shift opp_shift = {
577 OPP_MASK_SH_LIST_DCN20(__SHIFT)
580 static const struct dcn20_opp_mask opp_mask = {
581 OPP_MASK_SH_LIST_DCN20(_MASK)
584 #define aux_engine_regs(id)\
586 AUX_COMMON_REG_LIST0(id), \
589 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
592 static const struct dce110_aux_registers aux_engine_regs[] = {
601 #define dwbc_regs_dcn3(id)\
603 DWBC_COMMON_REG_LIST_DCN30(id),\
606 static const struct dcn30_dwbc_registers dwbc30_regs[] = {
610 static const struct dcn30_dwbc_shift dwbc30_shift = {
611 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
614 static const struct dcn30_dwbc_mask dwbc30_mask = {
615 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
618 #define mcif_wb_regs_dcn3(id)\
620 MCIF_WB_COMMON_REG_LIST_DCN30(id),\
623 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
627 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
628 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
631 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
632 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
635 #define dsc_regsDCN20(id)\
637 DSC_REG_LIST_DCN20(id)\
640 static const struct dcn20_dsc_registers dsc_regs[] = {
649 static const struct dcn20_dsc_shift dsc_shift = {
650 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
653 static const struct dcn20_dsc_mask dsc_mask = {
654 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
657 static const struct dcn30_mpc_registers mpc_regs = {
658 MPC_REG_LIST_DCN3_0(0),
659 MPC_REG_LIST_DCN3_0(1),
660 MPC_REG_LIST_DCN3_0(2),
661 MPC_REG_LIST_DCN3_0(3),
662 MPC_REG_LIST_DCN3_0(4),
663 MPC_REG_LIST_DCN3_0(5),
664 MPC_OUT_MUX_REG_LIST_DCN3_0(0),
665 MPC_OUT_MUX_REG_LIST_DCN3_0(1),
666 MPC_OUT_MUX_REG_LIST_DCN3_0(2),
667 MPC_OUT_MUX_REG_LIST_DCN3_0(3),
668 MPC_OUT_MUX_REG_LIST_DCN3_0(4),
669 MPC_OUT_MUX_REG_LIST_DCN3_0(5),
670 MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
671 MPC_RMU_REG_LIST_DCN3AG(0),
672 MPC_RMU_REG_LIST_DCN3AG(1),
673 MPC_RMU_REG_LIST_DCN3AG(2),
674 MPC_DWB_MUX_REG_LIST_DCN3_0(0),
677 static const struct dcn30_mpc_shift mpc_shift = {
678 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
681 static const struct dcn30_mpc_mask mpc_mask = {
682 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
685 #define optc_regs(id)\
686 [id] = {OPTC_COMMON_REG_LIST_DCN3_0(id)}
689 static const struct dcn_optc_registers optc_regs[] = {
698 static const struct dcn_optc_shift optc_shift = {
699 OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
702 static const struct dcn_optc_mask optc_mask = {
703 OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK)
706 #define hubp_regs(id)\
708 HUBP_REG_LIST_DCN30(id)\
711 static const struct dcn_hubp2_registers hubp_regs[] = {
720 static const struct dcn_hubp2_shift hubp_shift = {
721 HUBP_MASK_SH_LIST_DCN30(__SHIFT)
724 static const struct dcn_hubp2_mask hubp_mask = {
725 HUBP_MASK_SH_LIST_DCN30(_MASK)
728 static const struct dcn_hubbub_registers hubbub_reg = {
729 HUBBUB_REG_LIST_DCN30(0)
732 static const struct dcn_hubbub_shift hubbub_shift = {
733 HUBBUB_MASK_SH_LIST_DCN30(__SHIFT)
736 static const struct dcn_hubbub_mask hubbub_mask = {
737 HUBBUB_MASK_SH_LIST_DCN30(_MASK)
740 static const struct dccg_registers dccg_regs = {
741 DCCG_REG_LIST_DCN30()
744 static const struct dccg_shift dccg_shift = {
745 DCCG_MASK_SH_LIST_DCN3(__SHIFT)
748 static const struct dccg_mask dccg_mask = {
749 DCCG_MASK_SH_LIST_DCN3(_MASK)
752 static const struct dce_hwseq_registers hwseq_reg = {
753 HWSEQ_DCN30_REG_LIST()
756 static const struct dce_hwseq_shift hwseq_shift = {
757 HWSEQ_DCN30_MASK_SH_LIST(__SHIFT)
760 static const struct dce_hwseq_mask hwseq_mask = {
761 HWSEQ_DCN30_MASK_SH_LIST(_MASK)
763 #define vmid_regs(id)\
765 DCN20_VMID_REG_LIST(id)\
768 static const struct dcn_vmid_registers vmid_regs[] = {
787 static const struct dcn20_vmid_shift vmid_shifts = {
788 DCN20_VMID_MASK_SH_LIST(__SHIFT)
791 static const struct dcn20_vmid_mask vmid_masks = {
792 DCN20_VMID_MASK_SH_LIST(_MASK)
795 static const struct resource_caps res_cap_dcn3 = {
796 .num_timing_generator = 6,
798 .num_video_plane = 6,
800 .num_stream_encoder = 6,
809 static const struct dc_plane_cap plane_cap = {
810 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
811 .blends_with_above = true,
812 .blends_with_below = true,
813 .per_pixel_alpha = true,
815 .pixel_format_support = {
823 .max_upscale_factor = {
829 .max_downscale_factor = {
836 static const struct dc_debug_options debug_defaults_drv = {
837 .disable_dmcu = true, //No DMCU on DCN30
838 .force_abm_enable = false,
839 .timing_trace = false,
841 .disable_pplib_clock_request = true,
842 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
843 .force_single_disp_pipe_split = false,
844 .disable_dcc = DCC_ENABLE,
846 .performance_trace = false,
847 .max_downscale_src_width = 7680,/*upto 8K*/
848 .disable_pplib_wm_range = false,
849 .scl_reset_length10 = true,
850 .sanity_checks = false,
851 .underflow_assert_delay_us = 0xFFFFFFFF,
852 .dwb_fi_phase = -1, // -1 = disable,
853 .dmub_command_table = true,
854 .disable_psr = false,
857 static const struct dc_debug_options debug_defaults_diags = {
858 .disable_dmcu = true, //No dmcu on DCN30
859 .force_abm_enable = false,
860 .timing_trace = true,
862 .disable_dpp_power_gate = true,
863 .disable_hubp_power_gate = true,
864 .disable_clock_gate = true,
865 .disable_pplib_clock_request = true,
866 .disable_pplib_wm_range = true,
867 .disable_stutter = false,
868 .scl_reset_length10 = true,
869 .dwb_fi_phase = -1, // -1 = disable
870 .dmub_command_table = true,
872 .enable_tri_buf = true,
875 void dcn30_dpp_destroy(struct dpp **dpp)
877 kfree(TO_DCN20_DPP(*dpp));
881 static struct dpp *dcn30_dpp_create(
882 struct dc_context *ctx,
885 struct dcn3_dpp *dpp =
886 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
891 if (dpp3_construct(dpp, ctx, inst,
892 &dpp_regs[inst], &tf_shift, &tf_mask))
900 static struct output_pixel_processor *dcn30_opp_create(
901 struct dc_context *ctx, uint32_t inst)
903 struct dcn20_opp *opp =
904 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
911 dcn20_opp_construct(opp, ctx, inst,
912 &opp_regs[inst], &opp_shift, &opp_mask);
916 static struct dce_aux *dcn30_aux_engine_create(
917 struct dc_context *ctx,
920 struct aux_engine_dce110 *aux_engine =
921 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
926 dce110_aux_engine_construct(aux_engine, ctx, inst,
927 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
928 &aux_engine_regs[inst],
931 ctx->dc->caps.extended_aux_timeout_support);
933 return &aux_engine->base;
936 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
938 static const struct dce_i2c_registers i2c_hw_regs[] = {
947 static const struct dce_i2c_shift i2c_shifts = {
948 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
951 static const struct dce_i2c_mask i2c_masks = {
952 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
955 static struct dce_i2c_hw *dcn30_i2c_hw_create(
956 struct dc_context *ctx,
959 struct dce_i2c_hw *dce_i2c_hw =
960 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
965 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
966 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
971 static struct mpc *dcn30_mpc_create(
972 struct dc_context *ctx,
976 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
982 dcn30_mpc_construct(mpc30, ctx,
992 struct hubbub *dcn30_hubbub_create(struct dc_context *ctx)
996 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
1002 hubbub3_construct(hubbub3, ctx,
1008 for (i = 0; i < res_cap_dcn3.num_vmid; i++) {
1009 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
1013 vmid->regs = &vmid_regs[i];
1014 vmid->shifts = &vmid_shifts;
1015 vmid->masks = &vmid_masks;
1018 return &hubbub3->base;
1021 static struct timing_generator *dcn30_timing_generator_create(
1022 struct dc_context *ctx,
1025 struct optc *tgn10 =
1026 kzalloc(sizeof(struct optc), GFP_KERNEL);
1031 tgn10->base.inst = instance;
1032 tgn10->base.ctx = ctx;
1034 tgn10->tg_regs = &optc_regs[instance];
1035 tgn10->tg_shift = &optc_shift;
1036 tgn10->tg_mask = &optc_mask;
1038 dcn30_timing_generator_init(tgn10);
1040 return &tgn10->base;
1043 static const struct encoder_feature_support link_enc_feature = {
1044 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1045 .max_hdmi_pixel_clock = 600000,
1046 .hdmi_ycbcr420_supported = true,
1047 .dp_ycbcr420_supported = true,
1048 .fec_supported = true,
1049 .flags.bits.IS_HBR2_CAPABLE = true,
1050 .flags.bits.IS_HBR3_CAPABLE = true,
1051 .flags.bits.IS_TPS3_CAPABLE = true,
1052 .flags.bits.IS_TPS4_CAPABLE = true
1055 static struct link_encoder *dcn30_link_encoder_create(
1056 const struct encoder_init_data *enc_init_data)
1058 struct dcn20_link_encoder *enc20 =
1059 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1064 dcn30_link_encoder_construct(enc20,
1067 &link_enc_regs[enc_init_data->transmitter],
1068 &link_enc_aux_regs[enc_init_data->channel - 1],
1069 &link_enc_hpd_regs[enc_init_data->hpd_source],
1073 return &enc20->enc10.base;
1076 static struct panel_cntl *dcn30_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1078 struct dce_panel_cntl *panel_cntl =
1079 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
1084 dce_panel_cntl_construct(panel_cntl,
1086 &panel_cntl_regs[init_data->inst],
1090 return &panel_cntl->base;
1093 static void read_dce_straps(
1094 struct dc_context *ctx,
1095 struct resource_straps *straps)
1097 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
1098 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1102 static struct audio *dcn30_create_audio(
1103 struct dc_context *ctx, unsigned int inst)
1105 return dce_audio_create(ctx, inst,
1106 &audio_regs[inst], &audio_shift, &audio_mask);
1109 static struct vpg *dcn30_vpg_create(
1110 struct dc_context *ctx,
1113 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL);
1118 vpg3_construct(vpg3, ctx, inst,
1126 static struct afmt *dcn30_afmt_create(
1127 struct dc_context *ctx,
1130 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
1135 afmt3_construct(afmt3, ctx, inst,
1140 return &afmt3->base;
1143 struct stream_encoder *dcn30_stream_encoder_create(
1144 enum engine_id eng_id,
1145 struct dc_context *ctx)
1147 struct dcn10_stream_encoder *enc1;
1153 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1154 if (eng_id <= ENGINE_ID_DIGF) {
1160 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1161 vpg = dcn30_vpg_create(ctx, vpg_inst);
1162 afmt = dcn30_afmt_create(ctx, afmt_inst);
1164 if (!enc1 || !vpg || !afmt)
1167 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1169 &stream_enc_regs[eng_id],
1170 &se_shift, &se_mask);
1175 struct dce_hwseq *dcn30_hwseq_create(
1176 struct dc_context *ctx)
1178 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1182 hws->regs = &hwseq_reg;
1183 hws->shifts = &hwseq_shift;
1184 hws->masks = &hwseq_mask;
1188 static const struct resource_create_funcs res_create_funcs = {
1189 .read_dce_straps = read_dce_straps,
1190 .create_audio = dcn30_create_audio,
1191 .create_stream_encoder = dcn30_stream_encoder_create,
1192 .create_hwseq = dcn30_hwseq_create,
1195 static const struct resource_create_funcs res_create_maximus_funcs = {
1196 .read_dce_straps = NULL,
1197 .create_audio = NULL,
1198 .create_stream_encoder = NULL,
1199 .create_hwseq = dcn30_hwseq_create,
1202 static void dcn30_resource_destruct(struct dcn30_resource_pool *pool)
1206 for (i = 0; i < pool->base.stream_enc_count; i++) {
1207 if (pool->base.stream_enc[i] != NULL) {
1208 if (pool->base.stream_enc[i]->vpg != NULL) {
1209 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1210 pool->base.stream_enc[i]->vpg = NULL;
1212 if (pool->base.stream_enc[i]->afmt != NULL) {
1213 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1214 pool->base.stream_enc[i]->afmt = NULL;
1216 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1217 pool->base.stream_enc[i] = NULL;
1221 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1222 if (pool->base.dscs[i] != NULL)
1223 dcn20_dsc_destroy(&pool->base.dscs[i]);
1226 if (pool->base.mpc != NULL) {
1227 kfree(TO_DCN20_MPC(pool->base.mpc));
1228 pool->base.mpc = NULL;
1230 if (pool->base.hubbub != NULL) {
1231 kfree(pool->base.hubbub);
1232 pool->base.hubbub = NULL;
1234 for (i = 0; i < pool->base.pipe_count; i++) {
1235 if (pool->base.dpps[i] != NULL)
1236 dcn30_dpp_destroy(&pool->base.dpps[i]);
1238 if (pool->base.ipps[i] != NULL)
1239 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1241 if (pool->base.hubps[i] != NULL) {
1242 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1243 pool->base.hubps[i] = NULL;
1246 if (pool->base.irqs != NULL) {
1247 dal_irq_service_destroy(&pool->base.irqs);
1251 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1252 if (pool->base.engines[i] != NULL)
1253 dce110_engine_destroy(&pool->base.engines[i]);
1254 if (pool->base.hw_i2cs[i] != NULL) {
1255 kfree(pool->base.hw_i2cs[i]);
1256 pool->base.hw_i2cs[i] = NULL;
1258 if (pool->base.sw_i2cs[i] != NULL) {
1259 kfree(pool->base.sw_i2cs[i]);
1260 pool->base.sw_i2cs[i] = NULL;
1264 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1265 if (pool->base.opps[i] != NULL)
1266 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1269 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1270 if (pool->base.timing_generators[i] != NULL) {
1271 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1272 pool->base.timing_generators[i] = NULL;
1276 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1277 if (pool->base.dwbc[i] != NULL) {
1278 kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1279 pool->base.dwbc[i] = NULL;
1281 if (pool->base.mcif_wb[i] != NULL) {
1282 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1283 pool->base.mcif_wb[i] = NULL;
1287 for (i = 0; i < pool->base.audio_count; i++) {
1288 if (pool->base.audios[i])
1289 dce_aud_destroy(&pool->base.audios[i]);
1292 for (i = 0; i < pool->base.clk_src_count; i++) {
1293 if (pool->base.clock_sources[i] != NULL) {
1294 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1295 pool->base.clock_sources[i] = NULL;
1299 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1300 if (pool->base.mpc_lut[i] != NULL) {
1301 dc_3dlut_func_release(pool->base.mpc_lut[i]);
1302 pool->base.mpc_lut[i] = NULL;
1304 if (pool->base.mpc_shaper[i] != NULL) {
1305 dc_transfer_func_release(pool->base.mpc_shaper[i]);
1306 pool->base.mpc_shaper[i] = NULL;
1310 if (pool->base.dp_clock_source != NULL) {
1311 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1312 pool->base.dp_clock_source = NULL;
1315 for (i = 0; i < pool->base.pipe_count; i++) {
1316 if (pool->base.multiple_abms[i] != NULL)
1317 dce_abm_destroy(&pool->base.multiple_abms[i]);
1320 if (pool->base.psr != NULL)
1321 dmub_psr_destroy(&pool->base.psr);
1323 if (pool->base.dccg != NULL)
1324 dcn_dccg_destroy(&pool->base.dccg);
1326 if (pool->base.oem_device != NULL)
1327 dal_ddc_service_destroy(&pool->base.oem_device);
1330 static struct hubp *dcn30_hubp_create(
1331 struct dc_context *ctx,
1334 struct dcn20_hubp *hubp2 =
1335 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1340 if (hubp3_construct(hubp2, ctx, inst,
1341 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1342 return &hubp2->base;
1344 BREAK_TO_DEBUGGER();
1349 static bool dcn30_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1352 uint32_t pipe_count = pool->res_cap->num_dwb;
1354 for (i = 0; i < pipe_count; i++) {
1355 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1359 dm_error("DC: failed to create dwbc30!\n");
1363 dcn30_dwbc_construct(dwbc30, ctx,
1369 pool->dwbc[i] = &dwbc30->base;
1374 static bool dcn30_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1377 uint32_t pipe_count = pool->res_cap->num_dwb;
1379 for (i = 0; i < pipe_count; i++) {
1380 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1384 dm_error("DC: failed to create mcif_wb30!\n");
1388 dcn30_mmhubbub_construct(mcif_wb30, ctx,
1394 pool->mcif_wb[i] = &mcif_wb30->base;
1399 static struct display_stream_compressor *dcn30_dsc_create(
1400 struct dc_context *ctx, uint32_t inst)
1402 struct dcn20_dsc *dsc =
1403 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1406 BREAK_TO_DEBUGGER();
1410 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1414 enum dc_status dcn30_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1417 return dcn20_add_stream_to_ctx(dc, new_ctx, dc_stream);
1420 static void dcn30_destroy_resource_pool(struct resource_pool **pool)
1422 struct dcn30_resource_pool *dcn30_pool = TO_DCN30_RES_POOL(*pool);
1424 dcn30_resource_destruct(dcn30_pool);
1429 static struct clock_source *dcn30_clock_source_create(
1430 struct dc_context *ctx,
1431 struct dc_bios *bios,
1432 enum clock_source_id id,
1433 const struct dce110_clk_src_regs *regs,
1436 struct dce110_clk_src *clk_src =
1437 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1442 if (dcn3_clk_src_construct(clk_src, ctx, bios, id,
1443 regs, &cs_shift, &cs_mask)) {
1444 clk_src->base.dp_clk_src = dp_clk_src;
1445 return &clk_src->base;
1448 BREAK_TO_DEBUGGER();
1452 int dcn30_populate_dml_pipes_from_context(
1453 struct dc *dc, struct dc_state *context,
1454 display_e2e_pipe_params_st *pipes)
1457 struct resource_context *res_ctx = &context->res_ctx;
1459 dcn20_populate_dml_pipes_from_context(dc, context, pipes);
1461 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1462 if (!res_ctx->pipe_ctx[i].stream)
1465 pipes[pipe_cnt++].pipe.scale_ratio_depth.lb_depth =
1472 void dcn30_populate_dml_writeback_from_context(
1473 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
1476 double max_calc_writeback_dispclk;
1477 double writeback_dispclk;
1478 struct writeback_st dout_wb;
1480 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1481 struct dc_stream_state *stream = res_ctx->pipe_ctx[i].stream;
1485 max_calc_writeback_dispclk = 0;
1487 /* Set writeback information */
1488 pipes[pipe_cnt].dout.wb_enable = 0;
1489 pipes[pipe_cnt].dout.num_active_wb = 0;
1490 for (j = 0; j < stream->num_wb_info; j++) {
1491 struct dc_writeback_info *wb_info = &stream->writeback_info[j];
1493 if (wb_info->wb_enabled && wb_info->writeback_source_plane &&
1494 (wb_info->writeback_source_plane == res_ctx->pipe_ctx[i].plane_state)) {
1495 pipes[pipe_cnt].dout.wb_enable = 1;
1496 pipes[pipe_cnt].dout.num_active_wb++;
1497 dout_wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_en ?
1498 wb_info->dwb_params.cnv_params.crop_height :
1499 wb_info->dwb_params.cnv_params.src_height;
1500 dout_wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_en ?
1501 wb_info->dwb_params.cnv_params.crop_width :
1502 wb_info->dwb_params.cnv_params.src_width;
1503 dout_wb.wb_dst_width = wb_info->dwb_params.dest_width;
1504 dout_wb.wb_dst_height = wb_info->dwb_params.dest_height;
1506 /* For IP that doesn't support WB scaling, set h/v taps to 1 to avoid DML validation failure */
1507 if (dc->dml.ip.writeback_max_hscl_taps > 1) {
1508 dout_wb.wb_htaps_luma = wb_info->dwb_params.scaler_taps.h_taps;
1509 dout_wb.wb_vtaps_luma = wb_info->dwb_params.scaler_taps.v_taps;
1511 dout_wb.wb_htaps_luma = 1;
1512 dout_wb.wb_vtaps_luma = 1;
1514 dout_wb.wb_htaps_chroma = 0;
1515 dout_wb.wb_vtaps_chroma = 0;
1516 dout_wb.wb_hratio = wb_info->dwb_params.cnv_params.crop_en ?
1517 (double)wb_info->dwb_params.cnv_params.crop_width /
1518 (double)wb_info->dwb_params.dest_width :
1519 (double)wb_info->dwb_params.cnv_params.src_width /
1520 (double)wb_info->dwb_params.dest_width;
1521 dout_wb.wb_vratio = wb_info->dwb_params.cnv_params.crop_en ?
1522 (double)wb_info->dwb_params.cnv_params.crop_height /
1523 (double)wb_info->dwb_params.dest_height :
1524 (double)wb_info->dwb_params.cnv_params.src_height /
1525 (double)wb_info->dwb_params.dest_height;
1526 if (wb_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_ARGB ||
1527 wb_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_RGBA)
1528 dout_wb.wb_pixel_format = dm_444_64;
1530 dout_wb.wb_pixel_format = dm_444_32;
1532 /* Workaround for cases where multiple writebacks are connected to same plane
1533 * In which case, need to compute worst case and set the associated writeback parameters
1534 * This workaround is necessary due to DML computation assuming only 1 set of writeback
1535 * parameters per pipe
1537 writeback_dispclk = dml30_CalculateWriteBackDISPCLK(
1538 dout_wb.wb_pixel_format,
1539 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz,
1542 dout_wb.wb_htaps_luma,
1543 dout_wb.wb_vtaps_luma,
1544 dout_wb.wb_src_width,
1545 dout_wb.wb_dst_width,
1546 pipes[pipe_cnt].pipe.dest.htotal,
1547 dc->current_state->bw_ctx.dml.ip.writeback_line_buffer_buffer_size);
1549 if (writeback_dispclk > max_calc_writeback_dispclk) {
1550 max_calc_writeback_dispclk = writeback_dispclk;
1551 pipes[pipe_cnt].dout.wb = dout_wb;
1561 unsigned int dcn30_calc_max_scaled_time(
1562 unsigned int time_per_pixel,
1563 enum mmhubbub_wbif_mode mode,
1564 unsigned int urgent_watermark)
1566 unsigned int time_per_byte = 0;
1567 unsigned int total_free_entry = 0xb40;
1568 unsigned int buf_lh_capability;
1569 unsigned int max_scaled_time;
1571 if (mode == PACKED_444) /* packed mode 32 bpp */
1572 time_per_byte = time_per_pixel/4;
1573 else if (mode == PACKED_444_FP16) /* packed mode 64 bpp */
1574 time_per_byte = time_per_pixel/8;
1576 if (time_per_byte == 0)
1579 buf_lh_capability = (total_free_entry*time_per_byte*32) >> 6; /* time_per_byte is in u6.6*/
1580 max_scaled_time = buf_lh_capability - urgent_watermark;
1581 return max_scaled_time;
1584 void dcn30_set_mcif_arb_params(
1586 struct dc_state *context,
1587 display_e2e_pipe_params_st *pipes,
1590 enum mmhubbub_wbif_mode wbif_mode;
1591 struct display_mode_lib *dml = &context->bw_ctx.dml;
1592 struct mcif_arb_params *wb_arb_params;
1593 int i, j, k, dwb_pipe;
1595 /* Writeback MCIF_WB arbitration parameters */
1597 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1599 if (!context->res_ctx.pipe_ctx[i].stream)
1602 for (j = 0; j < MAX_DWB_PIPES; j++) {
1603 struct dc_writeback_info *writeback_info = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j];
1605 if (writeback_info->wb_enabled == false)
1608 //wb_arb_params = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j].mcif_arb_params;
1609 wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe];
1611 if (writeback_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_ARGB ||
1612 writeback_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_RGBA)
1613 wbif_mode = PACKED_444_FP16;
1615 wbif_mode = PACKED_444;
1617 for (k = 0; k < sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]); k++) {
1618 wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(dml, pipes, pipe_cnt) * 1000;
1619 wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(dml, pipes, pipe_cnt) * 1000;
1621 wb_arb_params->time_per_pixel = (1000000 << 6) / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk; /* time_per_pixel should be in u6.6 format */
1622 wb_arb_params->slice_lines = 32;
1623 wb_arb_params->arbitration_slice = 2; /* irrelevant since there is no YUV output */
1624 wb_arb_params->max_scaled_time = dcn30_calc_max_scaled_time(wb_arb_params->time_per_pixel,
1626 wb_arb_params->cli_watermark[0]); /* assume 4 watermark sets have the same value */
1627 wb_arb_params->dram_speed_change_duration = dml->vba.WritebackAllowDRAMClockChangeEndPosition[j] * pipes[0].clks_cfg.refclk_mhz; /* num_clock_cycles = us * MHz */
1631 if (dwb_pipe >= MAX_DWB_PIPES)
1634 if (dwb_pipe >= MAX_DWB_PIPES)
1640 static struct dc_cap_funcs cap_funcs = {
1641 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1644 bool dcn30_acquire_post_bldn_3dlut(
1645 struct resource_context *res_ctx,
1646 const struct resource_pool *pool,
1648 struct dc_3dlut **lut,
1649 struct dc_transfer_func **shaper)
1653 union dc_3dlut_state *state;
1655 ASSERT(*lut == NULL && *shaper == NULL);
1659 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
1660 if (!res_ctx->is_mpc_3dlut_acquired[i]) {
1661 *lut = pool->mpc_lut[i];
1662 *shaper = pool->mpc_shaper[i];
1663 state = &pool->mpc_lut[i]->state;
1664 res_ctx->is_mpc_3dlut_acquired[i] = true;
1665 state->bits.rmu_idx_valid = 1;
1666 state->bits.rmu_mux_num = i;
1667 if (state->bits.rmu_mux_num == 0)
1668 state->bits.mpc_rmu0_mux = mpcc_id;
1669 else if (state->bits.rmu_mux_num == 1)
1670 state->bits.mpc_rmu1_mux = mpcc_id;
1671 else if (state->bits.rmu_mux_num == 2)
1672 state->bits.mpc_rmu2_mux = mpcc_id;
1680 bool dcn30_release_post_bldn_3dlut(
1681 struct resource_context *res_ctx,
1682 const struct resource_pool *pool,
1683 struct dc_3dlut **lut,
1684 struct dc_transfer_func **shaper)
1689 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
1690 if (pool->mpc_lut[i] == *lut && pool->mpc_shaper[i] == *shaper) {
1691 res_ctx->is_mpc_3dlut_acquired[i] = false;
1692 pool->mpc_lut[i]->state.raw = 0;
1702 #define fixed16_to_double(x) (((double) x) / ((double) (1 << 16)))
1703 #define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x))
1705 static bool is_soc_bounding_box_valid(struct dc *dc)
1707 uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;
1709 if (ASICREV_IS_SIENNA_CICHLID_P(hw_internal_rev))
1715 static bool init_soc_bounding_box(struct dc *dc,
1716 struct dcn30_resource_pool *pool)
1718 const struct gpu_info_soc_bounding_box_v1_0 *bb = dc->soc_bounding_box;
1719 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_0_soc;
1720 struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_0_ip;
1722 DC_LOGGER_INIT(dc->ctx->logger);
1724 if (!bb && !is_soc_bounding_box_valid(dc)) {
1725 DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__);
1729 if (bb && !is_soc_bounding_box_valid(dc)) {
1732 dcn3_0_soc.sr_exit_time_us =
1733 fixed16_to_double_to_cpu(bb->sr_exit_time_us);
1734 dcn3_0_soc.sr_enter_plus_exit_time_us =
1735 fixed16_to_double_to_cpu(bb->sr_enter_plus_exit_time_us);
1736 dcn3_0_soc.urgent_latency_us =
1737 fixed16_to_double_to_cpu(bb->urgent_latency_us);
1738 dcn3_0_soc.urgent_latency_pixel_data_only_us =
1739 fixed16_to_double_to_cpu(bb->urgent_latency_pixel_data_only_us);
1740 dcn3_0_soc.urgent_latency_pixel_mixed_with_vm_data_us =
1741 fixed16_to_double_to_cpu(bb->urgent_latency_pixel_mixed_with_vm_data_us);
1742 dcn3_0_soc.urgent_latency_vm_data_only_us =
1743 fixed16_to_double_to_cpu(bb->urgent_latency_vm_data_only_us);
1744 dcn3_0_soc.urgent_out_of_order_return_per_channel_pixel_only_bytes =
1745 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_only_bytes);
1746 dcn3_0_soc.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes =
1747 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes);
1748 dcn3_0_soc.urgent_out_of_order_return_per_channel_vm_only_bytes =
1749 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_vm_only_bytes);
1750 dcn3_0_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only =
1751 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_only);
1752 dcn3_0_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm =
1753 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm);
1754 dcn3_0_soc.pct_ideal_dram_sdp_bw_after_urgent_vm_only =
1755 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_vm_only);
1756 dcn3_0_soc.max_avg_sdp_bw_use_normal_percent =
1757 fixed16_to_double_to_cpu(bb->max_avg_sdp_bw_use_normal_percent);
1758 dcn3_0_soc.max_avg_dram_bw_use_normal_percent =
1759 fixed16_to_double_to_cpu(bb->max_avg_dram_bw_use_normal_percent);
1760 dcn3_0_soc.writeback_latency_us =
1761 fixed16_to_double_to_cpu(bb->writeback_latency_us);
1762 dcn3_0_soc.ideal_dram_bw_after_urgent_percent =
1763 fixed16_to_double_to_cpu(bb->ideal_dram_bw_after_urgent_percent);
1764 dcn3_0_soc.max_request_size_bytes =
1765 le32_to_cpu(bb->max_request_size_bytes);
1766 dcn3_0_soc.dram_channel_width_bytes =
1767 le32_to_cpu(bb->dram_channel_width_bytes);
1768 dcn3_0_soc.fabric_datapath_to_dcn_data_return_bytes =
1769 le32_to_cpu(bb->fabric_datapath_to_dcn_data_return_bytes);
1770 dcn3_0_soc.dcn_downspread_percent =
1771 fixed16_to_double_to_cpu(bb->dcn_downspread_percent);
1772 dcn3_0_soc.downspread_percent =
1773 fixed16_to_double_to_cpu(bb->downspread_percent);
1774 dcn3_0_soc.dram_page_open_time_ns =
1775 fixed16_to_double_to_cpu(bb->dram_page_open_time_ns);
1776 dcn3_0_soc.dram_rw_turnaround_time_ns =
1777 fixed16_to_double_to_cpu(bb->dram_rw_turnaround_time_ns);
1778 dcn3_0_soc.dram_return_buffer_per_channel_bytes =
1779 le32_to_cpu(bb->dram_return_buffer_per_channel_bytes);
1780 dcn3_0_soc.round_trip_ping_latency_dcfclk_cycles =
1781 le32_to_cpu(bb->round_trip_ping_latency_dcfclk_cycles);
1782 dcn3_0_soc.urgent_out_of_order_return_per_channel_bytes =
1783 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_bytes);
1784 dcn3_0_soc.channel_interleave_bytes =
1785 le32_to_cpu(bb->channel_interleave_bytes);
1786 dcn3_0_soc.num_banks =
1787 le32_to_cpu(bb->num_banks);
1788 dcn3_0_soc.num_chans =
1789 le32_to_cpu(bb->num_chans);
1790 dcn3_0_soc.gpuvm_min_page_size_bytes =
1791 le32_to_cpu(bb->vmm_page_size_bytes);
1792 dcn3_0_soc.dram_clock_change_latency_us =
1793 fixed16_to_double_to_cpu(bb->dram_clock_change_latency_us);
1794 dcn3_0_soc.writeback_dram_clock_change_latency_us =
1795 fixed16_to_double_to_cpu(bb->writeback_dram_clock_change_latency_us);
1796 dcn3_0_soc.return_bus_width_bytes =
1797 le32_to_cpu(bb->return_bus_width_bytes);
1798 dcn3_0_soc.dispclk_dppclk_vco_speed_mhz =
1799 le32_to_cpu(bb->dispclk_dppclk_vco_speed_mhz);
1800 dcn3_0_soc.xfc_bus_transport_time_us =
1801 le32_to_cpu(bb->xfc_bus_transport_time_us);
1802 dcn3_0_soc.xfc_xbuf_latency_tolerance_us =
1803 le32_to_cpu(bb->xfc_xbuf_latency_tolerance_us);
1804 dcn3_0_soc.use_urgent_burst_bw =
1805 le32_to_cpu(bb->use_urgent_burst_bw);
1806 dcn3_0_soc.num_states =
1807 le32_to_cpu(bb->num_states);
1809 for (i = 0; i < dcn3_0_soc.num_states; i++) {
1810 dcn3_0_soc.clock_limits[i].state =
1811 le32_to_cpu(bb->clock_limits[i].state);
1812 dcn3_0_soc.clock_limits[i].dcfclk_mhz =
1813 fixed16_to_double_to_cpu(bb->clock_limits[i].dcfclk_mhz);
1814 dcn3_0_soc.clock_limits[i].fabricclk_mhz =
1815 fixed16_to_double_to_cpu(bb->clock_limits[i].fabricclk_mhz);
1816 dcn3_0_soc.clock_limits[i].dispclk_mhz =
1817 fixed16_to_double_to_cpu(bb->clock_limits[i].dispclk_mhz);
1818 dcn3_0_soc.clock_limits[i].dppclk_mhz =
1819 fixed16_to_double_to_cpu(bb->clock_limits[i].dppclk_mhz);
1820 dcn3_0_soc.clock_limits[i].phyclk_mhz =
1821 fixed16_to_double_to_cpu(bb->clock_limits[i].phyclk_mhz);
1822 dcn3_0_soc.clock_limits[i].socclk_mhz =
1823 fixed16_to_double_to_cpu(bb->clock_limits[i].socclk_mhz);
1824 dcn3_0_soc.clock_limits[i].dscclk_mhz =
1825 fixed16_to_double_to_cpu(bb->clock_limits[i].dscclk_mhz);
1826 dcn3_0_soc.clock_limits[i].dram_speed_mts =
1827 fixed16_to_double_to_cpu(bb->clock_limits[i].dram_speed_mts);
1831 loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;
1832 loaded_ip->max_num_dpp = pool->base.pipe_count;
1833 loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
1834 dcn20_patch_bounding_box(dc, loaded_bb);
1836 if (!bb && dc->ctx->dc_bios->funcs->get_soc_bb_info) {
1837 struct bp_soc_bb_info bb_info = {0};
1839 if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {
1840 if (bb_info.dram_clock_change_latency_100ns > 0)
1841 dcn3_0_soc.dram_clock_change_latency_us = bb_info.dram_clock_change_latency_100ns * 10;
1843 if (bb_info.dram_sr_enter_exit_latency_100ns > 0)
1844 dcn3_0_soc.sr_enter_plus_exit_time_us = bb_info.dram_sr_enter_exit_latency_100ns * 10;
1846 if (bb_info.dram_sr_exit_latency_100ns > 0)
1847 dcn3_0_soc.sr_exit_time_us = bb_info.dram_sr_exit_latency_100ns * 10;
1854 static bool dcn30_split_stream_for_mpc_or_odm(
1855 const struct dc *dc,
1856 struct resource_context *res_ctx,
1857 struct pipe_ctx *pri_pipe,
1858 struct pipe_ctx *sec_pipe,
1861 int pipe_idx = sec_pipe->pipe_idx;
1862 const struct resource_pool *pool = dc->res_pool;
1864 *sec_pipe = *pri_pipe;
1866 sec_pipe->pipe_idx = pipe_idx;
1867 sec_pipe->plane_res.mi = pool->mis[pipe_idx];
1868 sec_pipe->plane_res.hubp = pool->hubps[pipe_idx];
1869 sec_pipe->plane_res.ipp = pool->ipps[pipe_idx];
1870 sec_pipe->plane_res.xfm = pool->transforms[pipe_idx];
1871 sec_pipe->plane_res.dpp = pool->dpps[pipe_idx];
1872 sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst;
1873 sec_pipe->stream_res.dsc = NULL;
1875 if (pri_pipe->next_odm_pipe) {
1876 ASSERT(pri_pipe->next_odm_pipe != sec_pipe);
1877 sec_pipe->next_odm_pipe = pri_pipe->next_odm_pipe;
1878 sec_pipe->next_odm_pipe->prev_odm_pipe = sec_pipe;
1880 if (pri_pipe->top_pipe && pri_pipe->top_pipe->next_odm_pipe) {
1881 pri_pipe->top_pipe->next_odm_pipe->bottom_pipe = sec_pipe;
1882 sec_pipe->top_pipe = pri_pipe->top_pipe->next_odm_pipe;
1884 if (pri_pipe->bottom_pipe && pri_pipe->bottom_pipe->next_odm_pipe) {
1885 pri_pipe->bottom_pipe->next_odm_pipe->top_pipe = sec_pipe;
1886 sec_pipe->bottom_pipe = pri_pipe->bottom_pipe->next_odm_pipe;
1888 pri_pipe->next_odm_pipe = sec_pipe;
1889 sec_pipe->prev_odm_pipe = pri_pipe;
1890 ASSERT(sec_pipe->top_pipe == NULL);
1892 if (!sec_pipe->top_pipe)
1893 sec_pipe->stream_res.opp = pool->opps[pipe_idx];
1895 sec_pipe->stream_res.opp = sec_pipe->top_pipe->stream_res.opp;
1896 if (sec_pipe->stream->timing.flags.DSC == 1) {
1897 dcn20_acquire_dsc(dc, res_ctx, &sec_pipe->stream_res.dsc, pipe_idx);
1898 ASSERT(sec_pipe->stream_res.dsc);
1899 if (sec_pipe->stream_res.dsc == NULL)
1903 if (pri_pipe->bottom_pipe) {
1904 ASSERT(pri_pipe->bottom_pipe != sec_pipe);
1905 sec_pipe->bottom_pipe = pri_pipe->bottom_pipe;
1906 sec_pipe->bottom_pipe->top_pipe = sec_pipe;
1908 pri_pipe->bottom_pipe = sec_pipe;
1909 sec_pipe->top_pipe = pri_pipe;
1911 ASSERT(pri_pipe->plane_state);
1917 static struct pipe_ctx *dcn30_find_split_pipe(
1919 struct dc_state *context,
1922 struct pipe_ctx *pipe = NULL;
1925 if (old_index >= 0 && context->res_ctx.pipe_ctx[old_index].stream == NULL) {
1926 pipe = &context->res_ctx.pipe_ctx[old_index];
1927 pipe->pipe_idx = old_index;
1931 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
1932 if (dc->current_state->res_ctx.pipe_ctx[i].top_pipe == NULL
1933 && dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) {
1934 if (context->res_ctx.pipe_ctx[i].stream == NULL) {
1935 pipe = &context->res_ctx.pipe_ctx[i];
1943 * May need to fix pipes getting tossed from 1 opp to another on flip
1944 * Add for debugging transient underflow during topology updates:
1948 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
1949 if (context->res_ctx.pipe_ctx[i].stream == NULL) {
1950 pipe = &context->res_ctx.pipe_ctx[i];
1959 static bool dcn30_internal_validate_bw(
1961 struct dc_state *context,
1962 display_e2e_pipe_params_st *pipes,
1968 bool repopulate_pipes = false;
1969 int split[MAX_PIPES] = { 0 };
1970 bool merge[MAX_PIPES] = { false };
1971 bool newly_split[MAX_PIPES] = { false };
1972 int pipe_cnt, i, pipe_idx, vlevel;
1973 struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
1979 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes);
1986 dml_log_pipe_params(&context->bw_ctx.dml, pipes, pipe_cnt);
1988 if (!fast_validate) {
1990 * DML favors voltage over p-state, but we're more interested in
1991 * supporting p-state over voltage. We can't support p-state in
1992 * prefetch mode > 0 so try capping the prefetch mode to start.
1994 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
1995 dm_allow_self_refresh_and_mclk_switch;
1996 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
1997 /* This may adjust vlevel and maxMpcComb */
1998 if (vlevel < context->bw_ctx.dml.soc.num_states)
1999 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
2001 if (fast_validate || vlevel == context->bw_ctx.dml.soc.num_states ||
2002 vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported) {
2004 * If mode is unsupported or there's still no p-state support then
2005 * fall back to favoring voltage.
2007 * We don't actually support prefetch mode 2, so require that we
2008 * at least support prefetch mode 1.
2010 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
2011 dm_allow_self_refresh;
2013 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
2014 if (vlevel < context->bw_ctx.dml.soc.num_states) {
2015 memset(split, 0, sizeof(split));
2016 memset(merge, 0, sizeof(merge));
2017 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
2021 dml_log_mode_support_params(&context->bw_ctx.dml);
2023 /* TODO: Need to check calculated vlevel why that fails validation of below resolutions */
2024 if (context->res_ctx.pipe_ctx[0].stream != NULL) {
2025 if (context->res_ctx.pipe_ctx[0].stream->timing.h_addressable == 640 && context->res_ctx.pipe_ctx[0].stream->timing.v_addressable == 480)
2027 if (context->res_ctx.pipe_ctx[0].stream->timing.h_addressable == 1280 && context->res_ctx.pipe_ctx[0].stream->timing.v_addressable == 800)
2029 if (context->res_ctx.pipe_ctx[0].stream->timing.h_addressable == 1280 && context->res_ctx.pipe_ctx[0].stream->timing.v_addressable == 768)
2031 if (context->res_ctx.pipe_ctx[0].stream->timing.h_addressable == 1280 && context->res_ctx.pipe_ctx[0].stream->timing.v_addressable == 1024)
2033 if (context->res_ctx.pipe_ctx[0].stream->timing.h_addressable == 2048 && context->res_ctx.pipe_ctx[0].stream->timing.v_addressable == 1536)
2037 if (vlevel == context->bw_ctx.dml.soc.num_states)
2040 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2041 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2042 struct pipe_ctx *mpo_pipe = pipe->bottom_pipe;
2047 /* We only support full screen mpo with ODM */
2048 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled
2049 && pipe->plane_state && mpo_pipe
2050 && memcmp(&mpo_pipe->plane_res.scl_data.recout,
2051 &pipe->plane_res.scl_data.recout,
2052 sizeof(struct rect)) != 0) {
2053 ASSERT(mpo_pipe->plane_state != pipe->plane_state);
2059 /* merge pipes if necessary */
2060 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2061 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2063 /*skip pipes that don't need merging*/
2067 /* if ODM merge we ignore mpc tree, mpo pipes will have their own flags */
2068 if (pipe->prev_odm_pipe) {
2069 /*split off odm pipe*/
2070 pipe->prev_odm_pipe->next_odm_pipe = pipe->next_odm_pipe;
2071 if (pipe->next_odm_pipe)
2072 pipe->next_odm_pipe->prev_odm_pipe = pipe->prev_odm_pipe;
2074 pipe->bottom_pipe = NULL;
2075 pipe->next_odm_pipe = NULL;
2076 pipe->plane_state = NULL;
2077 pipe->stream = NULL;
2078 pipe->top_pipe = NULL;
2079 pipe->prev_odm_pipe = NULL;
2080 if (pipe->stream_res.dsc)
2081 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc);
2082 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
2083 memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
2084 repopulate_pipes = true;
2085 } else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {
2086 struct pipe_ctx *top_pipe = pipe->top_pipe;
2087 struct pipe_ctx *bottom_pipe = pipe->bottom_pipe;
2089 top_pipe->bottom_pipe = bottom_pipe;
2091 bottom_pipe->top_pipe = top_pipe;
2093 pipe->top_pipe = NULL;
2094 pipe->bottom_pipe = NULL;
2095 pipe->plane_state = NULL;
2096 pipe->stream = NULL;
2097 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
2098 memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
2099 repopulate_pipes = true;
2101 ASSERT(0); /* Should never try to merge master pipe */
2105 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
2106 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2107 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
2108 struct pipe_ctx *hsplit_pipe = NULL;
2112 if (!pipe->stream || newly_split[i])
2116 odm = vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled;
2118 if (!pipe->plane_state && !odm)
2123 if (split[i] == 4 && old_pipe->next_odm_pipe->next_odm_pipe)
2124 old_index = old_pipe->next_odm_pipe->next_odm_pipe->pipe_idx;
2125 else if (old_pipe->next_odm_pipe)
2126 old_index = old_pipe->next_odm_pipe->pipe_idx;
2128 if (split[i] == 4 && old_pipe->bottom_pipe->bottom_pipe &&
2129 old_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
2130 old_index = old_pipe->bottom_pipe->bottom_pipe->pipe_idx;
2131 else if (old_pipe->bottom_pipe &&
2132 old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
2133 old_index = old_pipe->bottom_pipe->pipe_idx;
2135 hsplit_pipe = dcn30_find_split_pipe(dc, context, old_index);
2136 ASSERT(hsplit_pipe);
2140 if (!dcn30_split_stream_for_mpc_or_odm(
2141 dc, &context->res_ctx,
2142 pipe, hsplit_pipe, odm))
2145 newly_split[hsplit_pipe->pipe_idx] = true;
2146 repopulate_pipes = true;
2148 if (split[i] == 4) {
2149 struct pipe_ctx *pipe_4to1;
2151 if (odm && old_pipe->next_odm_pipe)
2152 old_index = old_pipe->next_odm_pipe->pipe_idx;
2153 else if (!odm && old_pipe->bottom_pipe &&
2154 old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
2155 old_index = old_pipe->bottom_pipe->pipe_idx;
2158 pipe_4to1 = dcn30_find_split_pipe(dc, context, old_index);
2162 if (!dcn30_split_stream_for_mpc_or_odm(
2163 dc, &context->res_ctx,
2164 pipe, pipe_4to1, odm))
2166 newly_split[pipe_4to1->pipe_idx] = true;
2168 if (odm && old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe)
2169 old_index = old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe->pipe_idx;
2170 else if (!odm && old_pipe->bottom_pipe->bottom_pipe->bottom_pipe &&
2171 old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
2172 old_index = old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->pipe_idx;
2175 pipe_4to1 = dcn30_find_split_pipe(dc, context, old_index);
2179 if (!dcn30_split_stream_for_mpc_or_odm(
2180 dc, &context->res_ctx,
2181 hsplit_pipe, pipe_4to1, odm))
2183 newly_split[pipe_4to1->pipe_idx] = true;
2186 dcn20_build_mapped_resource(dc, context, pipe->stream);
2189 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2190 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2192 if (pipe->plane_state) {
2193 if (!resource_build_scaling_params(pipe))
2198 /* Actual dsc count per stream dsc validation*/
2199 if (!dcn20_validate_dsc(dc, context)) {
2200 vba->ValidationStatus[vba->soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE;
2204 if (repopulate_pipes)
2205 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes);
2206 *vlevel_out = vlevel;
2207 *pipe_cnt_out = pipe_cnt;
2219 void dcn30_calculate_wm_and_dlg(
2220 struct dc *dc, struct dc_state *context,
2221 display_e2e_pipe_params_st *pipes,
2226 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
2227 bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] !=
2228 dm_dram_clock_change_unsupported;
2230 if (context->bw_ctx.dml.soc.min_dcfclk > dcfclk)
2231 dcfclk = context->bw_ctx.dml.soc.min_dcfclk;
2233 pipes[0].clks_cfg.voltage = vlevel;
2234 pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
2235 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
2238 * DCFCLK: 1GHz or min required above 1GHz
2241 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) {
2243 pipes[0].clks_cfg.voltage = 1;
2244 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dcfclk_mhz;
2246 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us;
2247 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us;
2248 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us;
2250 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2251 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2252 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2253 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2254 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2255 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2256 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2257 context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2259 pipes[0].clks_cfg.voltage = vlevel;
2260 pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
2263 * DCFCLK: Min Required
2264 * FCLK(proportional to UCLK): 1GHz or Max
2265 * MALL stutter, sr_enter_exit = 4, sr_exit = 2us
2268 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].valid) {
2269 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us;
2270 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us;
2271 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us;
2273 context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2274 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2275 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2276 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2277 context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2278 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2279 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2280 context->bw_ctx.bw.dcn.watermarks.d.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2284 * DCFCLK: Min Required
2285 * FCLK(proportional to UCLK): 1GHz or Max
2286 * pstate latency overridden to 5us
2288 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) {
2289 unsigned int min_dram_speed_mts = context->bw_ctx.dml.vba.DRAMSpeed;
2290 unsigned int min_dram_speed_mts_margin = 160;
2292 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->dummy_pstate_table[0].dummy_pstate_latency_us;
2294 if (context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == dm_dram_clock_change_unsupported)
2295 min_dram_speed_mts = dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz * 16;
2297 for (i = 3; i > 0; i--) {
2298 if ((min_dram_speed_mts + min_dram_speed_mts_margin > dc->clk_mgr->bw_params->dummy_pstate_table[i].dram_speed_mts) &&
2299 (min_dram_speed_mts - min_dram_speed_mts_margin < dc->clk_mgr->bw_params->dummy_pstate_table[i].dram_speed_mts))
2300 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->dummy_pstate_table[i].dummy_pstate_latency_us;
2303 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us;
2304 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us;
2306 context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2307 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2308 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2309 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2310 context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2311 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2312 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2313 context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2316 /* The only difference between A and C is p-state latency, if p-state is not supported we want to
2317 * calculate DLG based on dummy p-state latency, and max out the set A p-state watermark
2319 context->bw_ctx.bw.dcn.watermarks.a = context->bw_ctx.bw.dcn.watermarks.c;
2320 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 0;
2323 * DCFCLK: Min Required
2324 * FCLK(proportional to UCLK): 1GHz or Max
2326 * Set A calculated last so that following calculations are based on Set A
2328 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid) {
2329 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
2330 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us;
2331 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us;
2333 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2334 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2335 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2336 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2337 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2338 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2339 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2340 context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2343 context->perf_params.stutter_period_us = context->bw_ctx.dml.vba.StutterPeriod;
2345 /* Make set D = set A until set D is enabled */
2346 context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a;
2348 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2349 if (!context->res_ctx.pipe_ctx[i].stream)
2352 pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt);
2353 pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
2355 if (dc->config.forced_clocks) {
2356 pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
2357 pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
2359 if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000)
2360 pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
2361 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
2362 pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
2367 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
2370 /* Restore full p-state latency */
2371 context->bw_ctx.dml.soc.dram_clock_change_latency_us =
2372 dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
2375 bool dcn30_validate_bandwidth(struct dc *dc,
2376 struct dc_state *context,
2381 BW_VAL_TRACE_SETUP();
2385 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
2386 DC_LOGGER_INIT(dc->ctx->logger);
2388 BW_VAL_TRACE_COUNT();
2390 out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate);
2398 BW_VAL_TRACE_END_VOLTAGE_LEVEL();
2400 if (fast_validate) {
2401 BW_VAL_TRACE_SKIP(fast);
2405 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);
2407 BW_VAL_TRACE_END_WATERMARKS();
2412 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
2413 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
2415 BW_VAL_TRACE_SKIP(fail);
2421 BW_VAL_TRACE_FINISH();
2426 static void get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts,
2427 unsigned int *optimal_dcfclk,
2428 unsigned int *optimal_fclk)
2430 double bw_from_dram, bw_from_dram1, bw_from_dram2;
2432 bw_from_dram1 = uclk_mts * dcn3_0_soc.num_chans *
2433 dcn3_0_soc.dram_channel_width_bytes * (dcn3_0_soc.max_avg_dram_bw_use_normal_percent / 100);
2434 bw_from_dram2 = uclk_mts * dcn3_0_soc.num_chans *
2435 dcn3_0_soc.dram_channel_width_bytes * (dcn3_0_soc.max_avg_sdp_bw_use_normal_percent / 100);
2437 bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2;
2440 *optimal_fclk = bw_from_dram /
2441 (dcn3_0_soc.fabric_datapath_to_dcn_data_return_bytes * (dcn3_0_soc.max_avg_sdp_bw_use_normal_percent / 100));
2444 *optimal_dcfclk = bw_from_dram /
2445 (dcn3_0_soc.return_bus_width_bytes * (dcn3_0_soc.max_avg_sdp_bw_use_normal_percent / 100));
2448 void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
2451 unsigned int num_states = 0;
2453 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0};
2454 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0};
2455 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0};
2456 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0};
2458 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200};
2459 unsigned int num_dcfclk_sta_targets = 4;
2460 unsigned int num_uclk_states;
2462 if (dc->ctx->dc_bios->vram_info.num_chans)
2463 dcn3_0_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans;
2465 if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes)
2466 dcn3_0_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes;
2468 dcn3_0_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
2469 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
2471 if (bw_params->clk_table.entries[0].memclk_mhz) {
2473 if (bw_params->clk_table.entries[1].dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
2474 // If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array
2475 dcfclk_sta_targets[num_dcfclk_sta_targets] = bw_params->clk_table.entries[1].dcfclk_mhz;
2476 num_dcfclk_sta_targets++;
2477 } else if (bw_params->clk_table.entries[1].dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
2478 // If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates
2479 for (i = 0; i < num_dcfclk_sta_targets; i++) {
2480 if (dcfclk_sta_targets[i] > bw_params->clk_table.entries[1].dcfclk_mhz) {
2481 dcfclk_sta_targets[i] = bw_params->clk_table.entries[1].dcfclk_mhz;
2485 // Update size of array since we "removed" duplicates
2486 num_dcfclk_sta_targets = i + 1;
2489 num_uclk_states = bw_params->clk_table.num_entries;
2491 // Calculate optimal dcfclk for each uclk
2492 for (i = 0; i < num_uclk_states; i++) {
2493 get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16,
2494 &optimal_dcfclk_for_uclk[i], NULL);
2495 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) {
2496 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz;
2500 // Calculate optimal uclk for each dcfclk sta target
2501 for (i = 0; i < num_dcfclk_sta_targets; i++) {
2502 for (j = 0; j < num_uclk_states; j++) {
2503 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
2504 optimal_uclk_for_dcfclk_sta_targets[i] =
2505 bw_params->clk_table.entries[j].memclk_mhz * 16;
2513 // create the final dcfclk and uclk table
2514 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {
2515 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {
2516 dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
2517 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
2519 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= bw_params->clk_table.entries[1].dcfclk_mhz) {
2520 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
2521 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
2523 j = num_uclk_states;
2528 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) {
2529 dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
2530 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
2533 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES &&
2534 optimal_dcfclk_for_uclk[j] <= bw_params->clk_table.entries[1].dcfclk_mhz) {
2535 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
2536 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
2539 for (i = 0; i < dcn3_0_soc.num_states; i++) {
2540 dcn3_0_soc.clock_limits[i].state = i;
2541 dcn3_0_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i];
2542 dcn3_0_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i];
2543 dcn3_0_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i];
2545 /* Fill all states with max values of all other clocks */
2546 dcn3_0_soc.clock_limits[i].dispclk_mhz = bw_params->clk_table.entries[1].dispclk_mhz;
2547 dcn3_0_soc.clock_limits[i].dppclk_mhz = bw_params->clk_table.entries[1].dppclk_mhz;
2548 dcn3_0_soc.clock_limits[i].phyclk_mhz = bw_params->clk_table.entries[1].phyclk_mhz;
2549 dcn3_0_soc.clock_limits[i].dtbclk_mhz = dcn3_0_soc.clock_limits[0].dtbclk_mhz;
2550 /* These clocks cannot come from bw_params, always fill from dcn3_0_soc[1] */
2551 /* FCLK, PHYCLK_D18, SOCCLK, DSCCLK */
2552 dcn3_0_soc.clock_limits[i].phyclk_d18_mhz = dcn3_0_soc.clock_limits[0].phyclk_d18_mhz;
2553 dcn3_0_soc.clock_limits[i].socclk_mhz = dcn3_0_soc.clock_limits[0].socclk_mhz;
2554 dcn3_0_soc.clock_limits[i].dscclk_mhz = dcn3_0_soc.clock_limits[0].dscclk_mhz;
2556 /* re-init DML with updated bb */
2557 dml_init_instance(&dc->dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30);
2558 if (dc->current_state)
2559 dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30);
2562 /* re-init DML with updated bb */
2563 dml_init_instance(&dc->dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30);
2564 if (dc->current_state)
2565 dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30);
2568 static const struct resource_funcs dcn30_res_pool_funcs = {
2569 .destroy = dcn30_destroy_resource_pool,
2570 .link_enc_create = dcn30_link_encoder_create,
2571 .panel_cntl_create = dcn30_panel_cntl_create,
2572 .validate_bandwidth = dcn30_validate_bandwidth,
2573 .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg,
2574 .populate_dml_pipes = dcn30_populate_dml_pipes_from_context,
2575 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
2576 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
2577 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
2578 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
2579 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
2580 .set_mcif_arb_params = dcn30_set_mcif_arb_params,
2581 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
2582 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
2583 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
2584 .update_bw_bounding_box = dcn30_update_bw_bounding_box,
2585 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
2588 static bool dcn30_resource_construct(
2589 uint8_t num_virtual_links,
2591 struct dcn30_resource_pool *pool)
2594 struct dc_context *ctx = dc->ctx;
2595 struct irq_service_init_data init_data;
2596 struct ddc_service_init_data ddc_init_data;
2598 ctx->dc_bios->regs = &bios_regs;
2600 pool->base.res_cap = &res_cap_dcn3;
2602 pool->base.funcs = &dcn30_res_pool_funcs;
2604 /*************************************************
2605 * Resource + asic cap harcoding *
2606 *************************************************/
2607 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
2608 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
2609 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
2610 dc->caps.max_downscale_ratio = 600;
2611 dc->caps.i2c_speed_in_khz = 100;
2612 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/
2613 dc->caps.max_cursor_size = 256;
2614 dc->caps.min_horizontal_blanking_period = 80;
2615 dc->caps.dmdata_alloc_size = 2048;
2617 dc->caps.max_slave_planes = 1;
2618 dc->caps.post_blend_color_processing = true;
2619 dc->caps.force_dp_tps4_for_cp2520 = true;
2620 dc->caps.extended_aux_timeout_support = true;
2621 dc->caps.dmcub_support = true;
2623 /* Color pipeline capabilities */
2624 dc->caps.color.dpp.dcn_arch = 1;
2625 dc->caps.color.dpp.input_lut_shared = 0;
2626 dc->caps.color.dpp.icsc = 1;
2627 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
2628 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
2629 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
2630 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
2631 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
2632 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
2633 dc->caps.color.dpp.post_csc = 1;
2634 dc->caps.color.dpp.gamma_corr = 1;
2636 dc->caps.color.dpp.hw_3d_lut = 1;
2637 dc->caps.color.dpp.ogam_ram = 1;
2638 // no OGAM ROM on DCN3
2639 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
2640 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
2641 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
2642 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
2643 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
2644 dc->caps.color.dpp.ocsc = 0;
2646 dc->caps.color.mpc.gamut_remap = 1;
2647 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //3
2648 dc->caps.color.mpc.ogam_ram = 1;
2649 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
2650 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
2651 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
2652 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
2653 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
2654 dc->caps.color.mpc.ocsc = 1;
2656 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
2657 dc->debug = debug_defaults_drv;
2658 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
2659 dc->debug = debug_defaults_diags;
2661 dc->debug = debug_defaults_diags;
2662 // Init the vm_helper
2664 vm_helper_init(dc->vm_helper, 16);
2666 /*************************************************
2667 * Create resources *
2668 *************************************************/
2670 /* Clock Sources for Pixel Clock*/
2671 pool->base.clock_sources[DCN30_CLK_SRC_PLL0] =
2672 dcn30_clock_source_create(ctx, ctx->dc_bios,
2673 CLOCK_SOURCE_COMBO_PHY_PLL0,
2674 &clk_src_regs[0], false);
2675 pool->base.clock_sources[DCN30_CLK_SRC_PLL1] =
2676 dcn30_clock_source_create(ctx, ctx->dc_bios,
2677 CLOCK_SOURCE_COMBO_PHY_PLL1,
2678 &clk_src_regs[1], false);
2679 pool->base.clock_sources[DCN30_CLK_SRC_PLL2] =
2680 dcn30_clock_source_create(ctx, ctx->dc_bios,
2681 CLOCK_SOURCE_COMBO_PHY_PLL2,
2682 &clk_src_regs[2], false);
2683 pool->base.clock_sources[DCN30_CLK_SRC_PLL3] =
2684 dcn30_clock_source_create(ctx, ctx->dc_bios,
2685 CLOCK_SOURCE_COMBO_PHY_PLL3,
2686 &clk_src_regs[3], false);
2687 pool->base.clock_sources[DCN30_CLK_SRC_PLL4] =
2688 dcn30_clock_source_create(ctx, ctx->dc_bios,
2689 CLOCK_SOURCE_COMBO_PHY_PLL4,
2690 &clk_src_regs[4], false);
2691 pool->base.clock_sources[DCN30_CLK_SRC_PLL5] =
2692 dcn30_clock_source_create(ctx, ctx->dc_bios,
2693 CLOCK_SOURCE_COMBO_PHY_PLL5,
2694 &clk_src_regs[5], false);
2696 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL;
2698 /* todo: not reuse phy_pll registers */
2699 pool->base.dp_clock_source =
2700 dcn30_clock_source_create(ctx, ctx->dc_bios,
2701 CLOCK_SOURCE_ID_DP_DTO,
2702 &clk_src_regs[0], true);
2704 for (i = 0; i < pool->base.clk_src_count; i++) {
2705 if (pool->base.clock_sources[i] == NULL) {
2706 dm_error("DC: failed to create clock sources!\n");
2707 BREAK_TO_DEBUGGER();
2713 pool->base.dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2714 if (pool->base.dccg == NULL) {
2715 dm_error("DC: failed to create dccg!\n");
2716 BREAK_TO_DEBUGGER();
2720 /* PP Lib and SMU interfaces */
2721 init_soc_bounding_box(dc, pool);
2723 dml_init_instance(&dc->dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30);
2726 init_data.ctx = dc->ctx;
2727 pool->base.irqs = dal_irq_service_dcn30_create(&init_data);
2728 if (!pool->base.irqs)
2732 pool->base.hubbub = dcn30_hubbub_create(ctx);
2733 if (pool->base.hubbub == NULL) {
2734 BREAK_TO_DEBUGGER();
2735 dm_error("DC: failed to create hubbub!\n");
2739 /* HUBPs, DPPs, OPPs and TGs */
2740 for (i = 0; i < pool->base.pipe_count; i++) {
2741 pool->base.hubps[i] = dcn30_hubp_create(ctx, i);
2742 if (pool->base.hubps[i] == NULL) {
2743 BREAK_TO_DEBUGGER();
2745 "DC: failed to create hubps!\n");
2749 pool->base.dpps[i] = dcn30_dpp_create(ctx, i);
2750 if (pool->base.dpps[i] == NULL) {
2751 BREAK_TO_DEBUGGER();
2753 "DC: failed to create dpps!\n");
2758 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
2759 pool->base.opps[i] = dcn30_opp_create(ctx, i);
2760 if (pool->base.opps[i] == NULL) {
2761 BREAK_TO_DEBUGGER();
2763 "DC: failed to create output pixel processor!\n");
2768 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2769 pool->base.timing_generators[i] = dcn30_timing_generator_create(
2771 if (pool->base.timing_generators[i] == NULL) {
2772 BREAK_TO_DEBUGGER();
2773 dm_error("DC: failed to create tg!\n");
2777 pool->base.timing_generator_count = i;
2779 pool->base.psr = dmub_psr_create(ctx);
2781 if (pool->base.psr == NULL) {
2782 dm_error("DC: failed to create PSR obj!\n");
2783 BREAK_TO_DEBUGGER();
2788 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2789 pool->base.multiple_abms[i] = dmub_abm_create(ctx,
2793 if (pool->base.multiple_abms[i] == NULL) {
2794 dm_error("DC: failed to create abm for pipe %d!\n", i);
2795 BREAK_TO_DEBUGGER();
2800 pool->base.mpc = dcn30_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
2801 if (pool->base.mpc == NULL) {
2802 BREAK_TO_DEBUGGER();
2803 dm_error("DC: failed to create mpc!\n");
2807 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2808 pool->base.dscs[i] = dcn30_dsc_create(ctx, i);
2809 if (pool->base.dscs[i] == NULL) {
2810 BREAK_TO_DEBUGGER();
2811 dm_error("DC: failed to create display stream compressor %d!\n", i);
2816 /* DWB and MMHUBBUB */
2817 if (!dcn30_dwbc_create(ctx, &pool->base)) {
2818 BREAK_TO_DEBUGGER();
2819 dm_error("DC: failed to create dwbc!\n");
2823 if (!dcn30_mmhubbub_create(ctx, &pool->base)) {
2824 BREAK_TO_DEBUGGER();
2825 dm_error("DC: failed to create mcif_wb!\n");
2830 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2831 pool->base.engines[i] = dcn30_aux_engine_create(ctx, i);
2832 if (pool->base.engines[i] == NULL) {
2833 BREAK_TO_DEBUGGER();
2835 "DC:failed to create aux engine!!\n");
2838 pool->base.hw_i2cs[i] = dcn30_i2c_hw_create(ctx, i);
2839 if (pool->base.hw_i2cs[i] == NULL) {
2840 BREAK_TO_DEBUGGER();
2842 "DC:failed to create hw i2c!!\n");
2845 pool->base.sw_i2cs[i] = NULL;
2848 /* Audio, Stream Encoders including DIG and virtual, MPC 3D LUTs */
2849 if (!resource_construct(num_virtual_links, dc, &pool->base,
2850 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
2851 &res_create_funcs : &res_create_maximus_funcs)))
2854 /* HW Sequencer and Plane caps */
2855 dcn30_hw_sequencer_construct(dc);
2857 dc->caps.max_planes = pool->base.pipe_count;
2859 for (i = 0; i < dc->caps.max_planes; ++i)
2860 dc->caps.planes[i] = plane_cap;
2862 dc->cap_funcs = cap_funcs;
2864 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
2865 ddc_init_data.ctx = dc->ctx;
2866 ddc_init_data.link = NULL;
2867 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
2868 ddc_init_data.id.enum_id = 0;
2869 ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
2870 pool->base.oem_device = dal_ddc_service_create(&ddc_init_data);
2872 pool->base.oem_device = NULL;
2879 dcn30_resource_destruct(pool);
2884 struct resource_pool *dcn30_create_resource_pool(
2885 const struct dc_init_data *init_data,
2888 struct dcn30_resource_pool *pool =
2889 kzalloc(sizeof(struct dcn30_resource_pool), GFP_KERNEL);
2894 if (dcn30_resource_construct(init_data->num_virtual_links, dc, pool))
2897 BREAK_TO_DEBUGGER();