drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h

   1 /*
   2 * Copyright 2020 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #ifndef __DC_HWSS_DCN30_H__
  27 #define __DC_HWSS_DCN30_H__
  28
  29 #include "hw_sequencer_private.h"
  30
  31 struct dc;
  32
  33 void dcn30_init_hw(struct dc *dc);
  34 void dcn30_program_all_writeback_pipes_in_tree(
  35                 struct dc *dc,
  36                 const struct dc_stream_state *stream,
  37                 struct dc_state *context);
  38 void dcn30_update_writeback(
  39                 struct dc *dc,
  40                 struct dc_writeback_info *wb_info,
  41                 struct dc_state *context);
  42 void dcn30_enable_writeback(
  43                 struct dc *dc,
  44                 struct dc_writeback_info *wb_info,
  45                 struct dc_state *context);
  46 void dcn30_disable_writeback(
  47                 struct dc *dc,
  48                 unsigned int dwb_pipe_inst);
  49
  50 bool dcn30_mmhubbub_warmup(
  51         struct dc *dc,
  52         unsigned int num_dwb,
  53         struct dc_writeback_info *wb_info);
  54
  55 bool dcn30_set_blend_lut(struct pipe_ctx *pipe_ctx,
  56                 const struct dc_plane_state *plane_state);
  57
  58 bool dcn30_set_input_transfer_func(struct dc *dc,
  59                                 struct pipe_ctx *pipe_ctx,
  60                                 const struct dc_plane_state *plane_state);
  61 bool dcn30_set_output_transfer_func(struct dc *dc,
  62                                 struct pipe_ctx *pipe_ctx,
  63                                 const struct dc_stream_state *stream);
  64 void dcn30_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);
  65 void dcn30_update_info_frame(struct pipe_ctx *pipe_ctx);
  66 void dcn30_program_dmdata_engine(struct pipe_ctx *pipe_ctx);
  67
  68 bool dcn30_does_plane_fit_in_mall(struct dc *dc, struct dc_plane_state *plane,
  69                 struct dc_cursor_attributes *cursor_attr);
  70
  71 bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable);
  72
  73 void dcn30_hardware_release(struct dc *dc);
  74
  75 void dcn30_set_disp_pattern_generator(const struct dc *dc,
  76                 struct pipe_ctx *pipe_ctx,
  77                 enum controller_dp_test_pattern test_pattern,
  78                 enum controller_dp_color_space color_space,
  79                 enum dc_color_depth color_depth,
  80                 const struct tg_color *solid_color,
  81                 int width, int height, int offset);
  82
  83 #endif /* __DC_HWSS_DCN30_H__ */