drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c

   1 /*
   2  * Copyright 2020 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26
  27 #include "dm_services.h"
  28 #include "dm_helpers.h"
  29 #include "core_types.h"
  30 #include "resource.h"
  31 #include "dcn30_hwseq.h"
  32 #include "dccg.h"
  33 #include "dce/dce_hwseq.h"
  34 #include "dcn30_mpc.h"
  35 #include "dcn30_dpp.h"
  36 #include "dcn10/dcn10_cm_common.h"
  37 #include "dcn30_cm_common.h"
  38 #include "clk_mgr.h"
  39 #include "reg_helper.h"
  40 #include "abm.h"
  41 #include "clk_mgr.h"
  42 #include "hubp.h"
  43 #include "dchubbub.h"
  44 #include "timing_generator.h"
  45 #include "opp.h"
  46 #include "ipp.h"
  47 #include "mpc.h"
  48 #include "mcif_wb.h"
  49 #include "dc_dmub_srv.h"
  50
  51
  52
  53
  54 #define DC_LOGGER_INIT(logger)
  55
  56 #define CTX \
  57         hws->ctx
  58 #define REG(reg)\
  59         hws->regs->reg
  60 #define DC_LOGGER \
  61                 dc->ctx->logger
  62
  63
  64 #undef FN
  65 #define FN(reg_name, field_name) \
  66         hws->shifts->field_name, hws->masks->field_name
  67
  68 bool dcn30_set_blend_lut(
  69         struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
  70 {
  71         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
  72         bool result = true;
  73         struct pwl_params *blend_lut = NULL;
  74
  75         if (plane_state->blend_tf) {
  76                 if (plane_state->blend_tf->type == TF_TYPE_HWPWL)
  77                         blend_lut = &plane_state->blend_tf->pwl;
  78                 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) {
  79                         cm3_helper_translate_curve_to_hw_format(
  80                                         plane_state->blend_tf, &dpp_base->regamma_params, false);
  81                         blend_lut = &dpp_base->regamma_params;
  82                 }
  83         }
  84         result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut);
  85
  86         return result;
  87 }
  88
  89 static bool dcn30_set_mpc_shaper_3dlut(
  90         struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream)
  91 {
  92         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
  93         int mpcc_id = pipe_ctx->plane_res.hubp->inst;
  94         struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
  95         bool result = false;
  96         int acquired_rmu = 0;
  97         int mpcc_id_projected = 0;
  98
  99         const struct pwl_params *shaper_lut = NULL;
 100         //get the shaper lut params
 101         if (stream->func_shaper) {
 102                 if (stream->func_shaper->type == TF_TYPE_HWPWL)
 103                         shaper_lut = &stream->func_shaper->pwl;
 104                 else if (stream->func_shaper->type == TF_TYPE_DISTRIBUTED_POINTS) {
 105                         cm_helper_translate_curve_to_hw_format(
 106                                         stream->func_shaper,
 107                                         &dpp_base->shaper_params, true);
 108                         shaper_lut = &dpp_base->shaper_params;
 109                 }
 110         }
 111
 112         if (stream->lut3d_func &&
 113                 stream->lut3d_func->state.bits.initialized == 1 &&
 114                 stream->lut3d_func->state.bits.rmu_idx_valid == 1) {
 115                 if (stream->lut3d_func->state.bits.rmu_mux_num == 0)
 116                         mpcc_id_projected = stream->lut3d_func->state.bits.mpc_rmu0_mux;
 117                 else if (stream->lut3d_func->state.bits.rmu_mux_num == 1)
 118                         mpcc_id_projected = stream->lut3d_func->state.bits.mpc_rmu1_mux;
 119                 else if (stream->lut3d_func->state.bits.rmu_mux_num == 2)
 120                         mpcc_id_projected = stream->lut3d_func->state.bits.mpc_rmu2_mux;
 121                 if (mpcc_id_projected != mpcc_id)
 122                         BREAK_TO_DEBUGGER();
 123                 /*find the reason why logical layer assigned a differant mpcc_id into acquire_post_bldn_3dlut*/
 124                 acquired_rmu = mpc->funcs->acquire_rmu(mpc, mpcc_id,
 125                                 stream->lut3d_func->state.bits.rmu_mux_num);
 126                 if (acquired_rmu != stream->lut3d_func->state.bits.rmu_mux_num)
 127                         BREAK_TO_DEBUGGER();
 128                 result = mpc->funcs->program_3dlut(mpc,
 129                                                                 &stream->lut3d_func->lut_3d,
 130                                                                 stream->lut3d_func->state.bits.rmu_mux_num);
 131                 result = mpc->funcs->program_shaper(mpc, shaper_lut,
 132                                 stream->lut3d_func->state.bits.rmu_mux_num);
 133         } else
 134                 /*loop through the available mux and release the requested mpcc_id*/
 135                 mpc->funcs->release_rmu(mpc, mpcc_id);
 136
 137
 138         return result;
 139 }
 140
 141 bool dcn30_set_input_transfer_func(struct dc *dc,
 142                                 struct pipe_ctx *pipe_ctx,
 143                                 const struct dc_plane_state *plane_state)
 144 {
 145         struct dce_hwseq *hws = dc->hwseq;
 146         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
 147         enum dc_transfer_func_predefined tf;
 148         bool result = true;
 149         struct pwl_params *params = NULL;
 150
 151         if (dpp_base == NULL || plane_state == NULL)
 152                 return false;
 153
 154         tf = TRANSFER_FUNCTION_UNITY;
 155
 156         if (plane_state->in_transfer_func &&
 157                 plane_state->in_transfer_func->type == TF_TYPE_PREDEFINED)
 158                 tf = plane_state->in_transfer_func->tf;
 159
 160         dpp_base->funcs->dpp_set_pre_degam(dpp_base, tf);
 161
 162         if (plane_state->in_transfer_func) {
 163                 if (plane_state->in_transfer_func->type == TF_TYPE_HWPWL)
 164                         params = &plane_state->in_transfer_func->pwl;
 165                 else if (plane_state->in_transfer_func->type == TF_TYPE_DISTRIBUTED_POINTS &&
 166                         cm3_helper_translate_curve_to_hw_format(plane_state->in_transfer_func,
 167                                         &dpp_base->degamma_params, false))
 168                         params = &dpp_base->degamma_params;
 169         }
 170
 171         result = dpp_base->funcs->dpp_program_gamcor_lut(dpp_base, params);
 172
 173         if (pipe_ctx->stream_res.opp && pipe_ctx->stream_res.opp->ctx) {
 174                 if (dpp_base->funcs->dpp_program_blnd_lut)
 175                         hws->funcs.set_blend_lut(pipe_ctx, plane_state);
 176                 if (dpp_base->funcs->dpp_program_shaper_lut &&
 177                                 dpp_base->funcs->dpp_program_3dlut)
 178                         hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state);
 179         }
 180
 181         return result;
 182 }
 183
 184 bool dcn30_set_output_transfer_func(struct dc *dc,
 185                                 struct pipe_ctx *pipe_ctx,
 186                                 const struct dc_stream_state *stream)
 187 {
 188         int mpcc_id = pipe_ctx->plane_res.hubp->inst;
 189         struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
 190         struct pwl_params *params = NULL;
 191         bool ret = false;
 192
 193         /* program OGAM or 3DLUT only for the top pipe*/
 194         if (pipe_ctx->top_pipe == NULL) {
 195                 /*program rmu shaper and 3dlut in MPC*/
 196                 ret = dcn30_set_mpc_shaper_3dlut(pipe_ctx, stream);
 197                 if (ret == false && mpc->funcs->set_output_gamma && stream->out_transfer_func) {
 198                         if (stream->out_transfer_func->type == TF_TYPE_HWPWL)
 199                                 params = &stream->out_transfer_func->pwl;
 200                         else if (pipe_ctx->stream->out_transfer_func->type ==
 201                                         TF_TYPE_DISTRIBUTED_POINTS &&
 202                                         cm3_helper_translate_curve_to_hw_format(
 203                                         stream->out_transfer_func,
 204                                         &mpc->blender_params, false))
 205                                 params = &mpc->blender_params;
 206                          /* there are no ROM LUTs in OUTGAM */
 207                         if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED)
 208                                 BREAK_TO_DEBUGGER();
 209                 }
 210         }
 211
 212         mpc->funcs->set_output_gamma(mpc, mpcc_id, params);
 213         return ret;
 214 }
 215
 216 static void dcn30_set_writeback(
 217                 struct dc *dc,
 218                 struct dc_writeback_info *wb_info,
 219                 struct dc_state *context)
 220 {
 221         struct dwbc *dwb;
 222         struct mcif_wb *mcif_wb;
 223         struct mcif_buf_params *mcif_buf_params;
 224
 225         ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES);
 226         ASSERT(wb_info->wb_enabled);
 227         ASSERT(wb_info->mpcc_inst >= 0);
 228         ASSERT(wb_info->mpcc_inst < 4);
 229         dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
 230         mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];
 231         mcif_buf_params = &wb_info->mcif_buf_params;
 232
 233         /* set DWB MPC mux */
 234         dc->res_pool->mpc->funcs->set_dwb_mux(dc->res_pool->mpc,
 235                         wb_info->dwb_pipe_inst, wb_info->mpcc_inst);
 236         /* set MCIF_WB buffer and arbitration configuration */
 237         mcif_wb->funcs->config_mcif_buf(mcif_wb, mcif_buf_params, wb_info->dwb_params.dest_height);
 238         mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]);
 239 }
 240
 241 void dcn30_update_writeback(
 242                 struct dc *dc,
 243                 struct dc_writeback_info *wb_info,
 244                 struct dc_state *context)
 245 {
 246         struct dwbc *dwb;
 247         dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
 248         DC_LOG_DWB("%s dwb_pipe_inst = %d, mpcc_inst = %d",\
 249                 __func__, wb_info->dwb_pipe_inst,\
 250                 wb_info->mpcc_inst);
 251
 252         dcn30_set_writeback(dc, wb_info, context);
 253
 254         /* update DWB */
 255         dwb->funcs->update(dwb, &wb_info->dwb_params);
 256 }
 257
 258 bool dcn30_mmhubbub_warmup(
 259         struct dc *dc,
 260         unsigned int num_dwb,
 261         struct dc_writeback_info *wb_info)
 262 {
 263         struct dwbc *dwb;
 264         struct mcif_wb *mcif_wb;
 265         struct mcif_warmup_params warmup_params = {0};
 266         unsigned int  i, i_buf;
 267         /*make sure there is no active DWB eanbled */
 268         for (i = 0; i < num_dwb; i++) {
 269                 dwb = dc->res_pool->dwbc[wb_info[i].dwb_pipe_inst];
 270                 if (dwb->dwb_is_efc_transition || dwb->dwb_is_drc) {
 271                         /*can not do warmup while any dwb enabled*/
 272                         return false;
 273                 }
 274         }
 275
 276         if (wb_info->mcif_warmup_params.p_vmid == 0)
 277                 return false;
 278
 279         /*check whether this is new interface: warmup big buffer once*/
 280         if (wb_info->mcif_warmup_params.start_address.quad_part != 0 &&
 281                 wb_info->mcif_warmup_params.region_size != 0) {
 282                 /*mmhubbub is shared, so it does not matter which MCIF*/
 283                 mcif_wb = dc->res_pool->mcif_wb[0];
 284                 /*warmup a big chunk of VM buffer at once*/
 285                 warmup_params.start_address.quad_part = wb_info->mcif_warmup_params.start_address.quad_part;
 286                 warmup_params.address_increment =  wb_info->mcif_warmup_params.region_size;
 287                 warmup_params.region_size = wb_info->mcif_warmup_params.region_size;
 288                 warmup_params.p_vmid = wb_info->mcif_warmup_params.p_vmid;
 289
 290                 if (warmup_params.address_increment == 0)
 291                         warmup_params.address_increment = dc->dml.soc.vmm_page_size_bytes;
 292
 293                 mcif_wb->funcs->warmup_mcif(mcif_wb, &warmup_params);
 294                 return true;
 295         }
 296         /*following is the original: warmup each DWB's mcif buffer*/
 297         for (i = 0; i < num_dwb; i++) {
 298                 dwb = dc->res_pool->dwbc[wb_info[i].dwb_pipe_inst];
 299                 mcif_wb = dc->res_pool->mcif_wb[wb_info[i].dwb_pipe_inst];
 300                 /*warmup is for VM mode only*/
 301                 if (wb_info[i].mcif_buf_params.p_vmid == 0)
 302                         return false;
 303
 304                 /* Warmup MCIF_WB */
 305                 for (i_buf = 0; i_buf < MCIF_BUF_COUNT; i_buf++) {
 306                         warmup_params.start_address.quad_part = wb_info[i].mcif_buf_params.luma_address[i_buf];
 307                         warmup_params.address_increment = dc->dml.soc.vmm_page_size_bytes;
 308                         warmup_params.region_size = wb_info[i].mcif_buf_params.luma_pitch * wb_info[i].dwb_params.dest_height;
 309                         warmup_params.p_vmid = wb_info[i].mcif_buf_params.p_vmid;
 310                         mcif_wb->funcs->warmup_mcif(mcif_wb, &warmup_params);
 311                 }
 312         }
 313         return true;
 314 }
 315
 316 void dcn30_enable_writeback(
 317                 struct dc *dc,
 318                 struct dc_writeback_info *wb_info,
 319                 struct dc_state *context)
 320 {
 321         struct dwbc *dwb;
 322         struct mcif_wb *mcif_wb;
 323         struct timing_generator *optc;
 324
 325         dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
 326         mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];
 327
 328         /* set the OPTC source mux */
 329         optc = dc->res_pool->timing_generators[dwb->otg_inst];
 330         DC_LOG_DWB("%s dwb_pipe_inst = %d, mpcc_inst = %d",\
 331                 __func__, wb_info->dwb_pipe_inst,\
 332                 wb_info->mpcc_inst);
 333         if (IS_DIAG_DC(dc->ctx->dce_environment)) {
 334                 /*till diags switch to warmup interface*/
 335                 dcn30_mmhubbub_warmup(dc, 1, wb_info);
 336         }
 337         /* Update writeback pipe */
 338         dcn30_set_writeback(dc, wb_info, context);
 339
 340         /* Enable MCIF_WB */
 341         mcif_wb->funcs->enable_mcif(mcif_wb);
 342         /* Enable DWB */
 343         dwb->funcs->enable(dwb, &wb_info->dwb_params);
 344 }
 345
 346 void dcn30_disable_writeback(
 347                 struct dc *dc,
 348                 unsigned int dwb_pipe_inst)
 349 {
 350         struct dwbc *dwb;
 351         struct mcif_wb *mcif_wb;
 352
 353         ASSERT(dwb_pipe_inst < MAX_DWB_PIPES);
 354         dwb = dc->res_pool->dwbc[dwb_pipe_inst];
 355         mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst];
 356         DC_LOG_DWB("%s dwb_pipe_inst = %d",\
 357                 __func__, dwb_pipe_inst);
 358
 359         /* disable DWB */
 360         dwb->funcs->disable(dwb);
 361         /* disable MCIF */
 362         mcif_wb->funcs->disable_mcif(mcif_wb);
 363         /* disable MPC DWB mux */
 364         dc->res_pool->mpc->funcs->disable_dwb_mux(dc->res_pool->mpc, dwb_pipe_inst);
 365 }
 366
 367 void dcn30_program_all_writeback_pipes_in_tree(
 368                 struct dc *dc,
 369                 const struct dc_stream_state *stream,
 370                 struct dc_state *context)
 371 {
 372         struct dc_writeback_info wb_info;
 373         struct dwbc *dwb;
 374         struct dc_stream_status *stream_status = NULL;
 375         int i_wb, i_pipe, i_stream;
 376         DC_LOG_DWB("%s", __func__);
 377
 378         ASSERT(stream);
 379         for (i_stream = 0; i_stream < context->stream_count; i_stream++) {
 380                 if (context->streams[i_stream] == stream) {
 381                         stream_status = &context->stream_status[i_stream];
 382                         break;
 383                 }
 384         }
 385         ASSERT(stream_status);
 386
 387         ASSERT(stream->num_wb_info <= dc->res_pool->res_cap->num_dwb);
 388         /* For each writeback pipe */
 389         for (i_wb = 0; i_wb < stream->num_wb_info; i_wb++) {
 390
 391                 /* copy writeback info to local non-const so mpcc_inst can be set */
 392                 wb_info = stream->writeback_info[i_wb];
 393                 if (wb_info.wb_enabled) {
 394
 395                         /* get the MPCC instance for writeback_source_plane */
 396                         wb_info.mpcc_inst = -1;
 397                         for (i_pipe = 0; i_pipe < dc->res_pool->pipe_count; i_pipe++) {
 398                                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i_pipe];
 399
 400                                 if (pipe_ctx->plane_state == wb_info.writeback_source_plane) {
 401                                         wb_info.mpcc_inst = pipe_ctx->plane_res.mpcc_inst;
 402                                         break;
 403                                 }
 404                         }
 405                         ASSERT(wb_info.mpcc_inst != -1);
 406
 407                         ASSERT(wb_info.dwb_pipe_inst < dc->res_pool->res_cap->num_dwb);
 408                         dwb = dc->res_pool->dwbc[wb_info.dwb_pipe_inst];
 409                         if (dwb->funcs->is_enabled(dwb)) {
 410                                 /* writeback pipe already enabled, only need to update */
 411                                 dc->hwss.update_writeback(dc, &wb_info, context);
 412                         } else {
 413                                 /* Enable writeback pipe and connect to MPCC */
 414                                 dc->hwss.enable_writeback(dc, &wb_info, context);
 415                         }
 416                 } else {
 417                         /* Disable writeback pipe and disconnect from MPCC */
 418                         dc->hwss.disable_writeback(dc, wb_info.dwb_pipe_inst);
 419                 }
 420         }
 421 }
 422
 423 void dcn30_init_hw(struct dc *dc)
 424 {
 425         int i, j;
 426         struct abm **abms = dc->res_pool->multiple_abms;
 427         struct dce_hwseq *hws = dc->hwseq;
 428         struct dc_bios *dcb = dc->ctx->dc_bios;
 429         struct resource_pool *res_pool = dc->res_pool;
 430         struct dc_state  *context = dc->current_state;
 431         uint32_t backlight = MAX_BACKLIGHT_LEVEL;
 432
 433         if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
 434                 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
 435
 436         // Initialize the dccg
 437         if (res_pool->dccg->funcs->dccg_init)
 438                 res_pool->dccg->funcs->dccg_init(res_pool->dccg);
 439
 440         //Enable ability to power gate / don't force power on permanently
 441         hws->funcs.enable_power_gating_plane(dc->hwseq, true);
 442
 443         if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
 444                 REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF);
 445                 REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF);
 446
 447                 hws->funcs.dccg_init(hws);
 448
 449                 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2);
 450                 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
 451                 REG_WRITE(REFCLK_CNTL, 0);
 452         } else {
 453                 if (!dcb->funcs->is_accelerated_mode(dcb)) {
 454                         hws->funcs.bios_golden_init(dc);
 455                         hws->funcs.disable_vga(dc->hwseq);
 456                 }
 457
 458                 if (dc->ctx->dc_bios->fw_info_valid) {
 459                         res_pool->ref_clocks.xtalin_clock_inKhz =
 460                                         dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
 461
 462                         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
 463                                 if (res_pool->dccg && res_pool->hubbub) {
 464
 465                                         (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
 466                                                         dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
 467                                                         &res_pool->ref_clocks.dccg_ref_clock_inKhz);
 468
 469                                         (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
 470                                                         res_pool->ref_clocks.dccg_ref_clock_inKhz,
 471                                                         &res_pool->ref_clocks.dchub_ref_clock_inKhz);
 472                                 } else {
 473                                         // Not all ASICs have DCCG sw component
 474                                         res_pool->ref_clocks.dccg_ref_clock_inKhz =
 475                                                         res_pool->ref_clocks.xtalin_clock_inKhz;
 476                                         res_pool->ref_clocks.dchub_ref_clock_inKhz =
 477                                                         res_pool->ref_clocks.xtalin_clock_inKhz;
 478                                 }
 479                         }
 480                 } else
 481                         ASSERT_CRITICAL(false);
 482
 483                 for (i = 0; i < dc->link_count; i++) {
 484                         /* Power up AND update implementation according to the
 485                          * required signal (which may be different from the
 486                          * default signal on connector).
 487                          */
 488                         struct dc_link *link = dc->links[i];
 489
 490                         link->link_enc->funcs->hw_init(link->link_enc);
 491                 }
 492         }
 493
 494         /* Power gate DSCs */
 495         for (i = 0; i < res_pool->res_cap->num_dsc; i++)
 496                 hws->funcs.dsc_pg_control(hws, res_pool->dscs[i]->inst, false);
 497
 498         /* Blank pixel data with OPP DPG */
 499         for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
 500                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
 501
 502                 if (tg->funcs->is_tg_enabled(tg))
 503                         hws->funcs.init_blank(dc, tg);
 504         }
 505
 506         for (i = 0; i < res_pool->timing_generator_count; i++) {
 507                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
 508
 509                 if (tg->funcs->is_tg_enabled(tg))
 510                         tg->funcs->lock(tg);
 511         }
 512
 513         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 514                 struct dpp *dpp = res_pool->dpps[i];
 515
 516                 dpp->funcs->dpp_reset(dpp);
 517         }
 518
 519         /* Reset all MPCC muxes */
 520         res_pool->mpc->funcs->mpc_init(res_pool->mpc);
 521
 522         /* initialize OPP mpc_tree parameter */
 523         for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {
 524                 res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst;
 525                 res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
 526                 for (j = 0; j < MAX_PIPES; j++)
 527                         res_pool->opps[i]->mpcc_disconnect_pending[j] = false;
 528         }
 529
 530         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 531                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
 532                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
 533                 struct hubp *hubp = dc->res_pool->hubps[i];
 534                 struct dpp *dpp = dc->res_pool->dpps[i];
 535
 536                 pipe_ctx->stream_res.tg = tg;
 537                 pipe_ctx->pipe_idx = i;
 538
 539                 pipe_ctx->plane_res.hubp = hubp;
 540                 pipe_ctx->plane_res.dpp = dpp;
 541                 pipe_ctx->plane_res.mpcc_inst = dpp->inst;
 542                 hubp->mpcc_id = dpp->inst;
 543                 hubp->opp_id = OPP_ID_INVALID;
 544                 hubp->power_gated = false;
 545                 pipe_ctx->stream_res.opp = NULL;
 546
 547                 hubp->funcs->hubp_init(hubp);
 548
 549                 //dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
 550                 //dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
 551                 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
 552                 pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
 553                 /*to do*/
 554                 hws->funcs.plane_atomic_disconnect(dc, pipe_ctx);
 555         }
 556
 557         /* initialize DWB pointer to MCIF_WB */
 558         for (i = 0; i < res_pool->res_cap->num_dwb; i++)
 559                 res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i];
 560
 561         for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
 562                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
 563
 564                 if (tg->funcs->is_tg_enabled(tg))
 565                         tg->funcs->unlock(tg);
 566         }
 567
 568         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 569                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
 570
 571                 dc->hwss.disable_plane(dc, pipe_ctx);
 572
 573                 pipe_ctx->stream_res.tg = NULL;
 574                 pipe_ctx->plane_res.hubp = NULL;
 575         }
 576
 577         for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
 578                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
 579
 580                 tg->funcs->tg_init(tg);
 581         }
 582
 583         /* end of FPGA. Below if real ASIC */
 584         if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
 585                 return;
 586
 587
 588         for (i = 0; i < res_pool->audio_count; i++) {
 589                 struct audio *audio = res_pool->audios[i];
 590
 591                 audio->funcs->hw_init(audio);
 592         }
 593
 594         for (i = 0; i < dc->link_count; i++) {
 595                 struct dc_link *link = dc->links[i];
 596
 597                 if (link->panel_cntl)
 598                         backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl);
 599         }
 600
 601         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 602                 if (abms[i] != NULL)
 603                         abms[i]->funcs->abm_init(abms[i], backlight);
 604         }
 605
 606         /* power AFMT HDMI memory TODO: may move to dis/en output save power*/
 607         REG_WRITE(DIO_MEM_PWR_CTRL, 0);
 608
 609         if (!dc->debug.disable_clock_gate) {
 610                 /* enable all DCN clock gating */
 611                 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
 612
 613                 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
 614
 615                 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
 616         }
 617
 618         if (dc->clk_mgr->funcs->notify_wm_ranges)
 619                 dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);
 620
 621         if (dc->clk_mgr->funcs->set_hard_max_memclk)
 622                 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
 623 }
 624
 625 void dcn30_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
 626 {
 627         if (pipe_ctx == NULL)
 628                 return;
 629
 630         if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) && pipe_ctx->stream_res.stream_enc != NULL)
 631                 pipe_ctx->stream_res.stream_enc->funcs->set_avmute(
 632                                 pipe_ctx->stream_res.stream_enc,
 633                                 enable);
 634 }
 635
 636 void dcn30_update_info_frame(struct pipe_ctx *pipe_ctx)
 637 {
 638         bool is_hdmi_tmds;
 639         bool is_dp;
 640
 641         ASSERT(pipe_ctx->stream);
 642
 643         if (pipe_ctx->stream_res.stream_enc == NULL)
 644                 return;  /* this is not root pipe */
 645
 646         is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal);
 647         is_dp = dc_is_dp_signal(pipe_ctx->stream->signal);
 648
 649         if (!is_hdmi_tmds)
 650                 return;
 651
 652         if (is_hdmi_tmds)
 653                 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(
 654                         pipe_ctx->stream_res.stream_enc,
 655                         &pipe_ctx->stream_res.encoder_info_frame);
 656         else
 657                 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(
 658                         pipe_ctx->stream_res.stream_enc,
 659                         &pipe_ctx->stream_res.encoder_info_frame);
 660 }
 661
 662 void dcn30_program_dmdata_engine(struct pipe_ctx *pipe_ctx)
 663 {
 664         struct dc_stream_state    *stream     = pipe_ctx->stream;
 665         struct hubp               *hubp       = pipe_ctx->plane_res.hubp;
 666         bool                       enable     = false;
 667         struct stream_encoder     *stream_enc = pipe_ctx->stream_res.stream_enc;
 668         enum dynamic_metadata_mode mode       = dc_is_dp_signal(stream->signal)
 669                                                         ? dmdata_dp
 670                                                         : dmdata_hdmi;
 671
 672         /* if using dynamic meta, don't set up generic infopackets */
 673         if (pipe_ctx->stream->dmdata_address.quad_part != 0) {
 674                 pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false;
 675                 enable = true;
 676         }
 677
 678         if (!hubp)
 679                 return;
 680
 681         if (!stream_enc || !stream_enc->funcs->set_dynamic_metadata)
 682                 return;
 683
 684         stream_enc->funcs->set_dynamic_metadata(stream_enc, enable,
 685                                                         hubp->inst, mode);
 686 }
 687
 688 bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)
 689 {
 690         unsigned int surface_size;
 691
 692         if (!dc->ctx->dmub_srv)
 693                 return false;
 694
 695         if (enable) {
 696                 if (dc->current_state
 697                                 && dc->current_state->stream_count == 1 // single display only
 698                                 && dc->current_state->stream_status[0].plane_count == 1 // single surface only
 699                                 && dc->current_state->stream_status[0].plane_states[0]->address.page_table_base.quad_part == 0 // no VM
 700                                 // Only 8 and 16 bit formats
 701                                 && dc->current_state->stream_status[0].plane_states[0]->format <= SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F
 702                                 && dc->current_state->stream_status[0].plane_states[0]->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB8888) {
 703
 704                         surface_size = dc->current_state->stream_status[0].plane_states[0]->plane_size.surface_pitch *
 705                                         dc->current_state->stream_status[0].plane_states[0]->plane_size.surface_size.height *
 706                                         (dc->current_state->stream_status[0].plane_states[0]->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ? 8 : 4);
 707
 708                 }
 709
 710                 return false;
 711         }
 712
 713         return true;
 714 }