drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp_cm.c

   1 /*
   2  * Copyright 2020 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27 #include "core_types.h"
  28 #include "reg_helper.h"
  29 #include "dcn30_dpp.h"
  30 #include "basics/conversion.h"
  31 #include "dcn30_cm_common.h"
  32
  33 #define REG(reg)\
  34         dpp->tf_regs->reg
  35
  36 #define CTX \
  37         dpp->base.ctx
  38
  39 #undef FN
  40 #define FN(reg_name, field_name) \
  41         dpp->tf_shift->field_name, dpp->tf_mask->field_name
  42
  43 static void dpp3_enable_cm_block(
  44                 struct dpp *dpp_base)
  45 {
  46         struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
  47
  48         unsigned int cm_bypass_mode = 0;
  49
  50         // debug option: put CM in bypass mode
  51         if (dpp_base->ctx->dc->debug.cm_in_bypass)
  52                 cm_bypass_mode = 1;
  53
  54         REG_UPDATE(CM_CONTROL, CM_BYPASS, cm_bypass_mode);
  55 }
  56
  57 static enum dc_lut_mode dpp30_get_gamcor_current(struct dpp *dpp_base)
  58 {
  59         enum dc_lut_mode mode;
  60         uint32_t state_mode;
  61         uint32_t lut_mode;
  62         struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
  63
  64         REG_GET(CM_GAMCOR_CONTROL,
  65                         CM_GAMCOR_MODE_CURRENT, &state_mode);
  66
  67                 if (state_mode == 0)
  68                         mode = LUT_BYPASS;
  69
  70                 if (state_mode == 2) {//Programmable RAM LUT
  71                         REG_GET(CM_GAMCOR_CONTROL,
  72                                         CM_GAMCOR_SELECT_CURRENT, &lut_mode);
  73
  74                         if (lut_mode == 0)
  75                                 mode = LUT_RAM_A;
  76                         else
  77                                 mode = LUT_RAM_B;
  78                 }
  79
  80                 return mode;
  81 }
  82
  83 static void dpp3_program_gammcor_lut(
  84                 struct dpp *dpp_base,
  85                 const struct pwl_result_data *rgb,
  86                 uint32_t num,
  87                 bool is_ram_a)
  88 {
  89         uint32_t i;
  90         struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
  91         uint32_t last_base_value_red = rgb[num-1].red_reg + rgb[num-1].delta_red_reg;
  92         uint32_t last_base_value_green = rgb[num-1].green_reg + rgb[num-1].delta_green_reg;
  93         uint32_t last_base_value_blue = rgb[num-1].blue_reg + rgb[num-1].delta_blue_reg;
  94
  95         /*fill in the LUT with all base values to be used by pwl module
  96          * HW auto increments the LUT index: back-to-back write
  97          */
  98         if (is_rgb_equal(rgb,  num)) {
  99                 for (i = 0 ; i < num; i++)
 100                         REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, rgb[i].red_reg);
 101
 102                 REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, last_base_value_red);
 103
 104         } else {
 105                 REG_UPDATE(CM_GAMCOR_LUT_CONTROL,
 106                                 CM_GAMCOR_LUT_WRITE_COLOR_MASK, 4);
 107                 for (i = 0 ; i < num; i++)
 108                         REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, rgb[i].red_reg);
 109
 110                 REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, last_base_value_red);
 111
 112                 REG_SET(CM_GAMCOR_LUT_INDEX, 0, CM_GAMCOR_LUT_INDEX, 0);
 113
 114                 REG_UPDATE(CM_GAMCOR_LUT_CONTROL,
 115                                 CM_GAMCOR_LUT_WRITE_COLOR_MASK, 2);
 116                 for (i = 0 ; i < num; i++)
 117                         REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, rgb[i].green_reg);
 118
 119                 REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, last_base_value_green);
 120
 121                 REG_SET(CM_GAMCOR_LUT_INDEX, 0, CM_GAMCOR_LUT_INDEX, 0);
 122
 123                 REG_UPDATE(CM_GAMCOR_LUT_CONTROL,
 124                                 CM_GAMCOR_LUT_WRITE_COLOR_MASK, 1);
 125                 for (i = 0 ; i < num; i++)
 126                         REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, rgb[i].blue_reg);
 127
 128                 REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, last_base_value_blue);
 129         }
 130 }
 131
 132 static void dpp3_power_on_gamcor_lut(
 133                 struct dpp *dpp_base,
 134         bool power_on)
 135 {
 136         uint32_t power_status;
 137         struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
 138
 139         if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) {
 140                 REG_UPDATE(CM_MEM_PWR_CTRL, GAMCOR_MEM_PWR_FORCE, power_on ? 0 : 3);
 141                 if (power_on)
 142                         REG_WAIT(CM_MEM_PWR_STATUS, GAMCOR_MEM_PWR_STATE, 0, 1, 5);
 143         } else
 144                 REG_SET(CM_MEM_PWR_CTRL, 0,
 145                                 GAMCOR_MEM_PWR_DIS, power_on == true ? 0:1);
 146
 147         REG_GET(CM_MEM_PWR_STATUS, GAMCOR_MEM_PWR_STATE, &power_status);
 148         if (power_status != 0)
 149                 BREAK_TO_DEBUGGER();
 150
 151
 152 }
 153
 154 void dpp3_program_cm_dealpha(
 155                 struct dpp *dpp_base,
 156         uint32_t enable, uint32_t additive_blending)
 157 {
 158         struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
 159
 160         REG_SET_2(CM_DEALPHA, 0,
 161                         CM_DEALPHA_EN, enable,
 162                         CM_DEALPHA_ABLND, additive_blending);
 163 }
 164
 165 void dpp3_program_cm_bias(
 166         struct dpp *dpp_base,
 167         struct CM_bias_params *bias_params)
 168 {
 169         struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
 170
 171         REG_SET(CM_BIAS_CR_R, 0, CM_BIAS_CR_R, bias_params->cm_bias_cr_r);
 172         REG_SET_2(CM_BIAS_Y_G_CB_B, 0,
 173                         CM_BIAS_Y_G, bias_params->cm_bias_y_g,
 174                         CM_BIAS_CB_B, bias_params->cm_bias_cb_b);
 175 }
 176
 177 static void dpp3_gamcor_reg_field(
 178                 struct dcn3_dpp *dpp,
 179                 struct dcn3_xfer_func_reg *reg)
 180 {
 181
 182         reg->shifts.field_region_start_base = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B;
 183         reg->masks.field_region_start_base = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B;
 184         reg->shifts.field_offset = dpp->tf_shift->CM_GAMCOR_RAMA_OFFSET_B;
 185         reg->masks.field_offset = dpp->tf_mask->CM_GAMCOR_RAMA_OFFSET_B;
 186
 187         reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET;
 188         reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET;
 189         reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS;
 190         reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS;
 191         reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET;
 192         reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET;
 193         reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS;
 194         reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS;
 195
 196         reg->shifts.field_region_end = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_END_B;
 197         reg->masks.field_region_end = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_END_B;
 198         reg->shifts.field_region_end_slope = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B;
 199         reg->masks.field_region_end_slope = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B;
 200         reg->shifts.field_region_end_base = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B;
 201         reg->masks.field_region_end_base = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B;
 202         reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B;
 203         reg->masks.field_region_linear_slope = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B;
 204         reg->shifts.exp_region_start = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_START_B;
 205         reg->masks.exp_region_start = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_START_B;
 206         reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B;
 207         reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B;
 208 }
 209
 210 static void dpp3_configure_gamcor_lut(
 211                 struct dpp *dpp_base,
 212                 bool is_ram_a)
 213 {
 214         struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
 215
 216         REG_UPDATE(CM_GAMCOR_LUT_CONTROL,
 217                         CM_GAMCOR_LUT_WRITE_COLOR_MASK, 7);
 218         REG_UPDATE(CM_GAMCOR_LUT_CONTROL,
 219                         CM_GAMCOR_LUT_HOST_SEL, is_ram_a == true ? 0:1);
 220         REG_SET(CM_GAMCOR_LUT_INDEX, 0, CM_GAMCOR_LUT_INDEX, 0);
 221 }
 222
 223
 224 bool dpp3_program_gamcor_lut(
 225         struct dpp *dpp_base, const struct pwl_params *params)
 226 {
 227         enum dc_lut_mode current_mode;
 228         enum dc_lut_mode next_mode;
 229         struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
 230         struct dcn3_xfer_func_reg gam_regs;
 231
 232         dpp3_enable_cm_block(dpp_base);
 233
 234         if (params == NULL) { //bypass if we have no pwl data
 235                 REG_SET(CM_GAMCOR_CONTROL, 0, CM_GAMCOR_MODE, 0);
 236                 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm)
 237                         dpp3_power_on_gamcor_lut(dpp_base, false);
 238                 return false;
 239         }
 240         dpp3_power_on_gamcor_lut(dpp_base, true);
 241         REG_SET(CM_GAMCOR_CONTROL, 0, CM_GAMCOR_MODE, 2);
 242
 243         current_mode = dpp30_get_gamcor_current(dpp_base);
 244         if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A)
 245                 next_mode = LUT_RAM_B;
 246         else
 247                 next_mode = LUT_RAM_A;
 248
 249         dpp3_power_on_gamcor_lut(dpp_base, true);
 250         dpp3_configure_gamcor_lut(dpp_base, next_mode == LUT_RAM_A ? true:false);
 251
 252         if (next_mode == LUT_RAM_B) {
 253                 gam_regs.start_cntl_b = REG(CM_GAMCOR_RAMB_START_CNTL_B);
 254                 gam_regs.start_cntl_g = REG(CM_GAMCOR_RAMB_START_CNTL_G);
 255                 gam_regs.start_cntl_r = REG(CM_GAMCOR_RAMB_START_CNTL_R);
 256                 gam_regs.start_slope_cntl_b = REG(CM_GAMCOR_RAMB_START_SLOPE_CNTL_B);
 257                 gam_regs.start_slope_cntl_g = REG(CM_GAMCOR_RAMB_START_SLOPE_CNTL_G);
 258                 gam_regs.start_slope_cntl_r = REG(CM_GAMCOR_RAMB_START_SLOPE_CNTL_R);
 259                 gam_regs.start_end_cntl1_b = REG(CM_GAMCOR_RAMB_END_CNTL1_B);
 260                 gam_regs.start_end_cntl2_b = REG(CM_GAMCOR_RAMB_END_CNTL2_B);
 261                 gam_regs.start_end_cntl1_g = REG(CM_GAMCOR_RAMB_END_CNTL1_G);
 262                 gam_regs.start_end_cntl2_g = REG(CM_GAMCOR_RAMB_END_CNTL2_G);
 263                 gam_regs.start_end_cntl1_r = REG(CM_GAMCOR_RAMB_END_CNTL1_R);
 264                 gam_regs.start_end_cntl2_r = REG(CM_GAMCOR_RAMB_END_CNTL2_R);
 265                 gam_regs.region_start = REG(CM_GAMCOR_RAMB_REGION_0_1);
 266                 gam_regs.region_end = REG(CM_GAMCOR_RAMB_REGION_32_33);
 267                 //New registers in DCN3AG/DCN GAMCOR block
 268                 gam_regs.offset_b =  REG(CM_GAMCOR_RAMB_OFFSET_B);
 269                 gam_regs.offset_g =  REG(CM_GAMCOR_RAMB_OFFSET_G);
 270                 gam_regs.offset_r =  REG(CM_GAMCOR_RAMB_OFFSET_R);
 271                 gam_regs.start_base_cntl_b = REG(CM_GAMCOR_RAMB_START_BASE_CNTL_B);
 272                 gam_regs.start_base_cntl_g = REG(CM_GAMCOR_RAMB_START_BASE_CNTL_G);
 273                 gam_regs.start_base_cntl_r = REG(CM_GAMCOR_RAMB_START_BASE_CNTL_R);
 274         } else {
 275                 gam_regs.start_cntl_b = REG(CM_GAMCOR_RAMA_START_CNTL_B);
 276                 gam_regs.start_cntl_g = REG(CM_GAMCOR_RAMA_START_CNTL_G);
 277                 gam_regs.start_cntl_r = REG(CM_GAMCOR_RAMA_START_CNTL_R);
 278                 gam_regs.start_slope_cntl_b = REG(CM_GAMCOR_RAMA_START_SLOPE_CNTL_B);
 279                 gam_regs.start_slope_cntl_g = REG(CM_GAMCOR_RAMA_START_SLOPE_CNTL_G);
 280                 gam_regs.start_slope_cntl_r = REG(CM_GAMCOR_RAMA_START_SLOPE_CNTL_R);
 281                 gam_regs.start_end_cntl1_b = REG(CM_GAMCOR_RAMA_END_CNTL1_B);
 282                 gam_regs.start_end_cntl2_b = REG(CM_GAMCOR_RAMA_END_CNTL2_B);
 283                 gam_regs.start_end_cntl1_g = REG(CM_GAMCOR_RAMA_END_CNTL1_G);
 284                 gam_regs.start_end_cntl2_g = REG(CM_GAMCOR_RAMA_END_CNTL2_G);
 285                 gam_regs.start_end_cntl1_r = REG(CM_GAMCOR_RAMA_END_CNTL1_R);
 286                 gam_regs.start_end_cntl2_r = REG(CM_GAMCOR_RAMA_END_CNTL2_R);
 287                 gam_regs.region_start = REG(CM_GAMCOR_RAMA_REGION_0_1);
 288                 gam_regs.region_end = REG(CM_GAMCOR_RAMA_REGION_32_33);
 289                 //New registers in DCN3AG/DCN GAMCOR block
 290                 gam_regs.offset_b =  REG(CM_GAMCOR_RAMA_OFFSET_B);
 291                 gam_regs.offset_g =  REG(CM_GAMCOR_RAMA_OFFSET_G);
 292                 gam_regs.offset_r =  REG(CM_GAMCOR_RAMA_OFFSET_R);
 293                 gam_regs.start_base_cntl_b = REG(CM_GAMCOR_RAMA_START_BASE_CNTL_B);
 294                 gam_regs.start_base_cntl_g = REG(CM_GAMCOR_RAMA_START_BASE_CNTL_G);
 295                 gam_regs.start_base_cntl_r = REG(CM_GAMCOR_RAMA_START_BASE_CNTL_R);
 296         }
 297
 298         //get register fields
 299         dpp3_gamcor_reg_field(dpp, &gam_regs);
 300
 301         //program register set for LUTA/LUTB
 302         cm_helper_program_gamcor_xfer_func(dpp_base->ctx, params, &gam_regs);
 303
 304         dpp3_program_gammcor_lut(dpp_base, params->rgb_resulted, params->hw_points_num,
 305                         next_mode == LUT_RAM_A ? true:false);
 306
 307         //select Gamma LUT to use for next frame
 308         REG_UPDATE(CM_GAMCOR_CONTROL, CM_GAMCOR_SELECT, next_mode == LUT_RAM_A ? 0:1);
 309
 310         return true;
 311 }
 312
 313 void dpp3_set_hdr_multiplier(
 314                 struct dpp *dpp_base,
 315                 uint32_t multiplier)
 316 {
 317         struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
 318
 319         REG_UPDATE(CM_HDR_MULT_COEF, CM_HDR_MULT_COEF, multiplier);
 320 }
 321
 322
 323 static void program_gamut_remap(
 324                 struct dcn3_dpp *dpp,
 325                 const uint16_t *regval,
 326                 int select)
 327 {
 328         uint16_t selection = 0;
 329         struct color_matrices_reg gam_regs;
 330
 331         if (regval == NULL || select == GAMUT_REMAP_BYPASS) {
 332                 REG_SET(CM_GAMUT_REMAP_CONTROL, 0,
 333                                 CM_GAMUT_REMAP_MODE, 0);
 334                 return;
 335         }
 336         switch (select) {
 337         case GAMUT_REMAP_COEFF:
 338                 selection = 1;
 339                 break;
 340                 /*this corresponds to GAMUT_REMAP coefficients set B
 341                  *we don't have common coefficient sets in dcn3ag/dcn3
 342                  */
 343         case GAMUT_REMAP_COMA_COEFF:
 344                 selection = 2;
 345                 break;
 346         default:
 347                 break;
 348         }
 349
 350         gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11;
 351         gam_regs.masks.csc_c11  = dpp->tf_mask->CM_GAMUT_REMAP_C11;
 352         gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12;
 353         gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12;
 354
 355
 356         if (select == GAMUT_REMAP_COEFF) {
 357                 gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_C11_C12);
 358                 gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_C33_C34);
 359
 360                 cm_helper_program_color_matrices(
 361                                 dpp->base.ctx,
 362                                 regval,
 363                                 &gam_regs);
 364
 365         } else  if (select == GAMUT_REMAP_COMA_COEFF) {
 366
 367                 gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_B_C11_C12);
 368                 gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_B_C33_C34);
 369
 370                 cm_helper_program_color_matrices(
 371                                 dpp->base.ctx,
 372                                 regval,
 373                                 &gam_regs);
 374
 375         }
 376         //select coefficient set to use
 377         REG_SET(
 378                         CM_GAMUT_REMAP_CONTROL, 0,
 379                         CM_GAMUT_REMAP_MODE, selection);
 380 }
 381
 382 void dpp3_cm_set_gamut_remap(
 383         struct dpp *dpp_base,
 384         const struct dpp_grph_csc_adjustment *adjust)
 385 {
 386         struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
 387         int i = 0;
 388         int gamut_mode;
 389
 390         if (adjust->gamut_adjust_type != GRAPHICS_GAMUT_ADJUST_TYPE_SW)
 391                 /* Bypass if type is bypass or hw */
 392                 program_gamut_remap(dpp, NULL, GAMUT_REMAP_BYPASS);
 393         else {
 394                 struct fixed31_32 arr_matrix[12];
 395                 uint16_t arr_reg_val[12];
 396
 397                 for (i = 0; i < 12; i++)
 398                         arr_matrix[i] = adjust->temperature_matrix[i];
 399
 400                 convert_float_matrix(
 401                         arr_reg_val, arr_matrix, 12);
 402
 403                 //current coefficient set in use
 404                 REG_GET(CM_GAMUT_REMAP_CONTROL, CM_GAMUT_REMAP_MODE_CURRENT, &gamut_mode);
 405
 406                 if (gamut_mode == 0)
 407                         gamut_mode = 1; //use coefficient set A
 408                 else if (gamut_mode == 1)
 409                         gamut_mode = 2;
 410                 else
 411                         gamut_mode = 1;
 412
 413                 //follow dcn2 approach for now - using only coefficient set A
 414                 program_gamut_remap(dpp, arr_reg_val, GAMUT_REMAP_COEFF);
 415         }
 416 }