drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c

   1 /*
   2  * Copyright 2020 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27 #include "core_types.h"
  28 #include "reg_helper.h"
  29 #include "dcn30_dpp.h"
  30 #include "basics/conversion.h"
  31 #include "dcn30_cm_common.h"
  32
  33 #define REG(reg)\
  34         dpp->tf_regs->reg
  35
  36 #define CTX \
  37         dpp->base.ctx
  38
  39 #undef FN
  40 #define FN(reg_name, field_name) \
  41         dpp->tf_shift->field_name, dpp->tf_mask->field_name
  42
  43
  44 void dpp30_read_state(struct dpp *dpp_base,
  45                 struct dcn_dpp_state *s)
  46 {
  47         struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
  48
  49         REG_GET(DPP_CONTROL,
  50                         DPP_CLOCK_ENABLE, &s->is_enabled);
  51
  52         // TODO: Implement for DCN3
  53 }
  54 /*program post scaler scs block in dpp CM*/
  55 void dpp3_program_post_csc(
  56                 struct dpp *dpp_base,
  57                 enum dc_color_space color_space,
  58                 enum dcn10_input_csc_select input_select,
  59                 const struct out_csc_color_matrix *tbl_entry)
  60 {
  61         struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
  62         int i;
  63         int arr_size = sizeof(dpp_input_csc_matrix)/sizeof(struct dpp_input_csc_matrix);
  64         const uint16_t *regval = NULL;
  65         uint32_t cur_select = 0;
  66         enum dcn10_input_csc_select select;
  67         struct color_matrices_reg gam_regs;
  68
  69         if (input_select == INPUT_CSC_SELECT_BYPASS) {
  70                 REG_SET(CM_POST_CSC_CONTROL, 0, CM_POST_CSC_MODE, 0);
  71                 return;
  72         }
  73
  74         if (tbl_entry == NULL) {
  75                 for (i = 0; i < arr_size; i++)
  76                         if (dpp_input_csc_matrix[i].color_space == color_space) {
  77                                 regval = dpp_input_csc_matrix[i].regval;
  78                                 break;
  79                         }
  80
  81                 if (regval == NULL) {
  82                         BREAK_TO_DEBUGGER();
  83                         return;
  84                 }
  85         } else {
  86                 regval = tbl_entry->regval;
  87         }
  88
  89         /* determine which CSC matrix (icsc or coma) we are using
  90          * currently.  select the alternate set to double buffer
  91          * the CSC update so CSC is updated on frame boundary
  92          */
  93         REG_GET(CM_POST_CSC_CONTROL,
  94                         CM_POST_CSC_MODE_CURRENT, &cur_select);
  95
  96         if (cur_select != INPUT_CSC_SELECT_ICSC)
  97                 select = INPUT_CSC_SELECT_ICSC;
  98         else
  99                 select = INPUT_CSC_SELECT_COMA;
 100
 101         gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_POST_CSC_C11;
 102         gam_regs.masks.csc_c11  = dpp->tf_mask->CM_POST_CSC_C11;
 103         gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_POST_CSC_C12;
 104         gam_regs.masks.csc_c12 = dpp->tf_mask->CM_POST_CSC_C12;
 105
 106         if (select == INPUT_CSC_SELECT_ICSC) {
 107
 108                 gam_regs.csc_c11_c12 = REG(CM_POST_CSC_C11_C12);
 109                 gam_regs.csc_c33_c34 = REG(CM_POST_CSC_C33_C34);
 110
 111         } else {
 112
 113                 gam_regs.csc_c11_c12 = REG(CM_POST_CSC_B_C11_C12);
 114                 gam_regs.csc_c33_c34 = REG(CM_POST_CSC_B_C33_C34);
 115
 116         }
 117
 118         cm_helper_program_color_matrices(
 119                         dpp->base.ctx,
 120                         regval,
 121                         &gam_regs);
 122
 123         REG_SET(CM_POST_CSC_CONTROL, 0,
 124                         CM_POST_CSC_MODE, select);
 125 }
 126
 127
 128 /*CNVC degam unit has read only LUTs*/
 129 void dpp3_set_pre_degam(struct dpp *dpp_base, enum dc_transfer_func_predefined tr)
 130 {
 131         struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
 132         int pre_degam_en = 1;
 133         int degamma_lut_selection = 0;
 134
 135         switch (tr) {
 136         case TRANSFER_FUNCTION_LINEAR:
 137         case TRANSFER_FUNCTION_UNITY:
 138                 pre_degam_en = 0; //bypass
 139                 break;
 140         case TRANSFER_FUNCTION_SRGB:
 141                 degamma_lut_selection = 0;
 142                 break;
 143         case TRANSFER_FUNCTION_BT709:
 144                 degamma_lut_selection = 4;
 145                 break;
 146         case TRANSFER_FUNCTION_PQ:
 147                 degamma_lut_selection = 5;
 148                 break;
 149         case TRANSFER_FUNCTION_HLG:
 150                 degamma_lut_selection = 6;
 151                 break;
 152         case TRANSFER_FUNCTION_GAMMA22:
 153                 degamma_lut_selection = 1;
 154                 break;
 155         case TRANSFER_FUNCTION_GAMMA24:
 156                 degamma_lut_selection = 2;
 157                 break;
 158         case TRANSFER_FUNCTION_GAMMA26:
 159                 degamma_lut_selection = 3;
 160                 break;
 161         default:
 162                 pre_degam_en = 0;
 163                 break;
 164         }
 165
 166         REG_SET_2(PRE_DEGAM, 0,
 167                         PRE_DEGAM_MODE, pre_degam_en,
 168                         PRE_DEGAM_SELECT, degamma_lut_selection);
 169 }
 170
 171 static void dpp3_cnv_setup (
 172                 struct dpp *dpp_base,
 173                 enum surface_pixel_format format,
 174                 enum expansion_mode mode,
 175                 struct dc_csc_transform input_csc_color_matrix,
 176                 enum dc_color_space input_color_space,
 177                 struct cnv_alpha_2bit_lut *alpha_2bit_lut)
 178 {
 179         struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
 180         uint32_t pixel_format = 0;
 181         uint32_t alpha_en = 1;
 182         enum dc_color_space color_space = COLOR_SPACE_SRGB;
 183         enum dcn10_input_csc_select select = INPUT_CSC_SELECT_BYPASS;
 184         bool force_disable_cursor = false;
 185         uint32_t is_2bit = 0;
 186         uint32_t alpha_plane_enable = 0;
 187         uint32_t dealpha_en = 0, dealpha_ablnd_en = 0;
 188         uint32_t realpha_en = 0, realpha_ablnd_en = 0;
 189         uint32_t program_prealpha_dealpha = 0;
 190         struct out_csc_color_matrix tbl_entry;
 191         int i;
 192
 193         REG_SET_2(FORMAT_CONTROL, 0,
 194                 CNVC_BYPASS, 0,
 195                 FORMAT_EXPANSION_MODE, mode);
 196
 197         REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0);
 198         REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0);
 199         REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0);
 200         REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0);
 201
 202         REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_R, 0);
 203         REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_G, 1);
 204         REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_B, 2);
 205
 206         switch (format) {
 207         case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
 208                 pixel_format = 1;
 209                 break;
 210         case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
 211                 pixel_format = 3;
 212                 alpha_en = 0;
 213                 break;
 214         case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
 215         case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
 216                 pixel_format = 8;
 217                 break;
 218         case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
 219         case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
 220                 pixel_format = 10;
 221                 is_2bit = 1;
 222                 break;
 223         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
 224                 force_disable_cursor = false;
 225                 pixel_format = 65;
 226                 color_space = COLOR_SPACE_YCBCR709;
 227                 select = INPUT_CSC_SELECT_ICSC;
 228                 break;
 229         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
 230                 force_disable_cursor = true;
 231                 pixel_format = 64;
 232                 color_space = COLOR_SPACE_YCBCR709;
 233                 select = INPUT_CSC_SELECT_ICSC;
 234                 break;
 235         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
 236                 force_disable_cursor = true;
 237                 pixel_format = 67;
 238                 color_space = COLOR_SPACE_YCBCR709;
 239                 select = INPUT_CSC_SELECT_ICSC;
 240                 break;
 241         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
 242                 force_disable_cursor = true;
 243                 pixel_format = 66;
 244                 color_space = COLOR_SPACE_YCBCR709;
 245                 select = INPUT_CSC_SELECT_ICSC;
 246                 break;
 247         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
 248         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
 249                 pixel_format = 26; /* ARGB16161616_UNORM */
 250                 break;
 251         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
 252                 pixel_format = 24;
 253                 break;
 254         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
 255                 pixel_format = 25;
 256                 break;
 257         case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888:
 258                 pixel_format = 12;
 259                 color_space = COLOR_SPACE_YCBCR709;
 260                 select = INPUT_CSC_SELECT_ICSC;
 261                 break;
 262         case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX:
 263                 pixel_format = 112;
 264                 break;
 265         case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX:
 266                 pixel_format = 113;
 267                 break;
 268         case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010:
 269                 pixel_format = 114;
 270                 color_space = COLOR_SPACE_YCBCR709;
 271                 select = INPUT_CSC_SELECT_ICSC;
 272                 is_2bit = 1;
 273                 break;
 274         case SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102:
 275                 pixel_format = 115;
 276                 color_space = COLOR_SPACE_YCBCR709;
 277                 select = INPUT_CSC_SELECT_ICSC;
 278                 is_2bit = 1;
 279                 break;
 280         case SURFACE_PIXEL_FORMAT_GRPH_RGBE:
 281                 pixel_format = 116;
 282                 alpha_plane_enable = 0;
 283                 break;
 284         case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
 285                 pixel_format = 116;
 286                 alpha_plane_enable = 1;
 287                 break;
 288         case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT:
 289                 pixel_format = 118;
 290                 break;
 291         case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT:
 292                 pixel_format = 119;
 293                 break;
 294         default:
 295                 break;
 296         }
 297
 298         if (is_2bit == 1 && alpha_2bit_lut != NULL) {
 299                 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0);
 300                 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1);
 301                 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, alpha_2bit_lut->lut2);
 302                 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT3, alpha_2bit_lut->lut3);
 303         }
 304
 305         REG_SET_2(CNVC_SURFACE_PIXEL_FORMAT, 0,
 306                         CNVC_SURFACE_PIXEL_FORMAT, pixel_format,
 307                         CNVC_ALPHA_PLANE_ENABLE, alpha_plane_enable);
 308         REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en);
 309
 310         if (program_prealpha_dealpha) {
 311                 dealpha_en = 1;
 312                 realpha_en = 1;
 313         }
 314         REG_SET_2(PRE_DEALPHA, 0,
 315                         PRE_DEALPHA_EN, dealpha_en,
 316                         PRE_DEALPHA_ABLND_EN, dealpha_ablnd_en);
 317         REG_SET_2(PRE_REALPHA, 0,
 318                         PRE_REALPHA_EN, realpha_en,
 319                         PRE_REALPHA_ABLND_EN, realpha_ablnd_en);
 320
 321         /* If input adjustment exists, program the ICSC with those values. */
 322         if (input_csc_color_matrix.enable_adjustment == true) {
 323                 for (i = 0; i < 12; i++)
 324                         tbl_entry.regval[i] = input_csc_color_matrix.matrix[i];
 325
 326                 tbl_entry.color_space = input_color_space;
 327
 328                 if (color_space >= COLOR_SPACE_YCBCR601)
 329                         select = INPUT_CSC_SELECT_ICSC;
 330                 else
 331                         select = INPUT_CSC_SELECT_BYPASS;
 332
 333                 dpp3_program_post_csc(dpp_base, color_space, select,
 334                                       &tbl_entry);
 335         } else {
 336                 dpp3_program_post_csc(dpp_base, color_space, select, NULL);
 337         }
 338
 339         if (force_disable_cursor) {
 340                 REG_UPDATE(CURSOR_CONTROL,
 341                                 CURSOR_ENABLE, 0);
 342                 REG_UPDATE(CURSOR0_CONTROL,
 343                                 CUR0_ENABLE, 0);
 344         }
 345 }
 346
 347 #define IDENTITY_RATIO(ratio) (dc_fixpt_u3d19(ratio) == (1 << 19))
 348
 349 void dpp3_set_cursor_attributes(
 350                 struct dpp *dpp_base,
 351                 struct dc_cursor_attributes *cursor_attributes)
 352 {
 353         enum dc_cursor_color_format color_format = cursor_attributes->color_format;
 354         struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
 355         int cur_rom_en = 0;
 356
 357         if (color_format == CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA ||
 358                 color_format == CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA)
 359                 cur_rom_en = 1;
 360
 361         REG_UPDATE_3(CURSOR0_CONTROL,
 362                         CUR0_MODE, color_format,
 363                         CUR0_EXPANSION_MODE, 0,
 364                         CUR0_ROM_EN, cur_rom_en);
 365
 366         if (color_format == CURSOR_MODE_MONO) {
 367                 /* todo: clarify what to program these to */
 368                 REG_UPDATE(CURSOR0_COLOR0,
 369                                 CUR0_COLOR0, 0x00000000);
 370                 REG_UPDATE(CURSOR0_COLOR1,
 371                                 CUR0_COLOR1, 0xFFFFFFFF);
 372         }
 373 }
 374
 375
 376 bool dpp3_get_optimal_number_of_taps(
 377                 struct dpp *dpp,
 378                 struct scaler_data *scl_data,
 379                 const struct scaling_taps *in_taps)
 380 {
 381         int num_part_y, num_part_c;
 382         int max_taps_y, max_taps_c;
 383         int min_taps_y, min_taps_c;
 384         enum lb_memory_config lb_config;
 385
 386         if (scl_data->viewport.width > scl_data->h_active &&
 387                 dpp->ctx->dc->debug.max_downscale_src_width != 0 &&
 388                 scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width)
 389                 return false;
 390
 391         /*
 392          * Set default taps if none are provided
 393          * From programming guide: taps = min{ ceil(2*H_RATIO,1), 8} for downscaling
 394          * taps = 4 for upscaling
 395          */
 396         if (in_taps->h_taps == 0) {
 397                 if (dc_fixpt_ceil(scl_data->ratios.horz) > 1)
 398                         scl_data->taps.h_taps = min(2 * dc_fixpt_ceil(scl_data->ratios.horz), 8);
 399                 else
 400                         scl_data->taps.h_taps = 4;
 401         } else
 402                 scl_data->taps.h_taps = in_taps->h_taps;
 403         if (in_taps->v_taps == 0) {
 404                 if (dc_fixpt_ceil(scl_data->ratios.vert) > 1)
 405                         scl_data->taps.v_taps = min(dc_fixpt_ceil(dc_fixpt_mul_int(scl_data->ratios.vert, 2)), 8);
 406                 else
 407                         scl_data->taps.v_taps = 4;
 408         } else
 409                 scl_data->taps.v_taps = in_taps->v_taps;
 410         if (in_taps->v_taps_c == 0) {
 411                 if (dc_fixpt_ceil(scl_data->ratios.vert_c) > 1)
 412                         scl_data->taps.v_taps_c = min(dc_fixpt_ceil(dc_fixpt_mul_int(scl_data->ratios.vert_c, 2)), 8);
 413                 else
 414                         scl_data->taps.v_taps_c = 4;
 415         } else
 416                 scl_data->taps.v_taps_c = in_taps->v_taps_c;
 417         if (in_taps->h_taps_c == 0) {
 418                 if (dc_fixpt_ceil(scl_data->ratios.horz_c) > 1)
 419                         scl_data->taps.h_taps_c = min(2 * dc_fixpt_ceil(scl_data->ratios.horz_c), 8);
 420                 else
 421                         scl_data->taps.h_taps_c = 4;
 422         } else if ((in_taps->h_taps_c % 2) != 0 && in_taps->h_taps_c != 1)
 423                 /* Only 1 and even h_taps_c are supported by hw */
 424                 scl_data->taps.h_taps_c = in_taps->h_taps_c - 1;
 425         else
 426                 scl_data->taps.h_taps_c = in_taps->h_taps_c;
 427
 428         /*Ensure we can support the requested number of vtaps*/
 429         min_taps_y = dc_fixpt_ceil(scl_data->ratios.vert);
 430         min_taps_c = dc_fixpt_ceil(scl_data->ratios.vert_c);
 431
 432         /* Use LB_MEMORY_CONFIG_3 for 4:2:0 */
 433         if ((scl_data->format == PIXEL_FORMAT_420BPP8) || (scl_data->format == PIXEL_FORMAT_420BPP10))
 434                 lb_config = LB_MEMORY_CONFIG_3;
 435         else
 436                 lb_config = LB_MEMORY_CONFIG_0;
 437
 438         dpp->caps->dscl_calc_lb_num_partitions(
 439                         scl_data, lb_config, &num_part_y, &num_part_c);
 440
 441         /* MAX_V_TAPS = MIN (NUM_LINES - MAX(CEILING(V_RATIO,1)-2, 0), 8) */
 442         if (dc_fixpt_ceil(scl_data->ratios.vert) > 2)
 443                 max_taps_y = num_part_y - (dc_fixpt_ceil(scl_data->ratios.vert) - 2);
 444         else
 445                 max_taps_y = num_part_y;
 446
 447         if (dc_fixpt_ceil(scl_data->ratios.vert_c) > 2)
 448                 max_taps_c = num_part_c - (dc_fixpt_ceil(scl_data->ratios.vert_c) - 2);
 449         else
 450                 max_taps_c = num_part_c;
 451
 452         if (max_taps_y < min_taps_y)
 453                 return false;
 454         else if (max_taps_c < min_taps_c)
 455                 return false;
 456
 457         if (scl_data->taps.v_taps > max_taps_y)
 458                 scl_data->taps.v_taps = max_taps_y;
 459
 460         if (scl_data->taps.v_taps_c > max_taps_c)
 461                 scl_data->taps.v_taps_c = max_taps_c;
 462
 463         if (!dpp->ctx->dc->debug.always_scale) {
 464                 if (IDENTITY_RATIO(scl_data->ratios.horz))
 465                         scl_data->taps.h_taps = 1;
 466                 if (IDENTITY_RATIO(scl_data->ratios.vert))
 467                         scl_data->taps.v_taps = 1;
 468                 if (IDENTITY_RATIO(scl_data->ratios.horz_c))
 469                         scl_data->taps.h_taps_c = 1;
 470                 if (IDENTITY_RATIO(scl_data->ratios.vert_c))
 471                         scl_data->taps.v_taps_c = 1;
 472         }
 473
 474         return true;
 475 }
 476
 477 void dpp3_cnv_set_bias_scale(
 478                 struct dpp *dpp_base,
 479                 struct  dc_bias_and_scale *bias_and_scale)
 480 {
 481         struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
 482
 483         REG_UPDATE(FCNV_FP_BIAS_R, FCNV_FP_BIAS_R, bias_and_scale->bias_red);
 484         REG_UPDATE(FCNV_FP_BIAS_G, FCNV_FP_BIAS_G, bias_and_scale->bias_green);
 485         REG_UPDATE(FCNV_FP_BIAS_B, FCNV_FP_BIAS_B, bias_and_scale->bias_blue);
 486         REG_UPDATE(FCNV_FP_SCALE_R, FCNV_FP_SCALE_R, bias_and_scale->scale_red);
 487         REG_UPDATE(FCNV_FP_SCALE_G, FCNV_FP_SCALE_G, bias_and_scale->scale_green);
 488         REG_UPDATE(FCNV_FP_SCALE_B, FCNV_FP_SCALE_B, bias_and_scale->scale_blue);
 489 }
 490
 491 void dpp3_deferred_update(
 492         struct dpp *dpp_base)
 493 {
 494         int bypass_state;
 495         struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
 496
 497         if (dpp_base->deferred_reg_writes.bits.disable_dscl) {
 498                 REG_UPDATE(DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, 3);
 499                 dpp_base->deferred_reg_writes.bits.disable_dscl = false;
 500         }
 501
 502         if (dpp_base->deferred_reg_writes.bits.disable_gamcor) {
 503                 REG_GET(CM_GAMCOR_CONTROL, CM_GAMCOR_MODE_CURRENT, &bypass_state);
 504                 if (bypass_state == 0) {        // only program if bypass was latched
 505                         REG_UPDATE(CM_MEM_PWR_CTRL, GAMCOR_MEM_PWR_FORCE, 3);
 506                 } else
 507                         ASSERT(0); // LUT select was updated again before vupdate
 508                 dpp_base->deferred_reg_writes.bits.disable_gamcor = false;
 509         }
 510
 511         if (dpp_base->deferred_reg_writes.bits.disable_blnd_lut) {
 512                 REG_GET(CM_BLNDGAM_CONTROL, CM_BLNDGAM_MODE_CURRENT, &bypass_state);
 513                 if (bypass_state == 0) {        // only program if bypass was latched
 514                         REG_UPDATE(CM_MEM_PWR_CTRL, BLNDGAM_MEM_PWR_FORCE, 3);
 515                 } else
 516                         ASSERT(0); // LUT select was updated again before vupdate
 517                 dpp_base->deferred_reg_writes.bits.disable_blnd_lut = false;
 518         }
 519
 520         if (dpp_base->deferred_reg_writes.bits.disable_3dlut) {
 521                 REG_GET(CM_3DLUT_MODE, CM_3DLUT_MODE_CURRENT, &bypass_state);
 522                 if (bypass_state == 0) {        // only program if bypass was latched
 523                         REG_UPDATE(CM_MEM_PWR_CTRL2, HDR3DLUT_MEM_PWR_FORCE, 3);
 524                 } else
 525                         ASSERT(0); // LUT select was updated again before vupdate
 526                 dpp_base->deferred_reg_writes.bits.disable_3dlut = false;
 527         }
 528
 529         if (dpp_base->deferred_reg_writes.bits.disable_shaper) {
 530                 REG_GET(CM_SHAPER_CONTROL, CM_SHAPER_MODE_CURRENT, &bypass_state);
 531                 if (bypass_state == 0) {        // only program if bypass was latched
 532                         REG_UPDATE(CM_MEM_PWR_CTRL2, SHAPER_MEM_PWR_FORCE, 3);
 533                 } else
 534                         ASSERT(0); // LUT select was updated again before vupdate
 535                 dpp_base->deferred_reg_writes.bits.disable_shaper = false;
 536         }
 537 }
 538
 539 static void dpp3_power_on_blnd_lut(
 540         struct dpp *dpp_base,
 541         bool power_on)
 542 {
 543         struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
 544
 545         if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) {
 546                 if (power_on) {
 547                         REG_UPDATE(CM_MEM_PWR_CTRL, BLNDGAM_MEM_PWR_FORCE, 0);
 548                         REG_WAIT(CM_MEM_PWR_STATUS, BLNDGAM_MEM_PWR_STATE, 0, 1, 5);
 549                 } else {
 550                         dpp_base->ctx->dc->optimized_required = true;
 551                         dpp_base->deferred_reg_writes.bits.disable_blnd_lut = true;
 552                 }
 553         } else {
 554                 REG_SET(CM_MEM_PWR_CTRL, 0,
 555                                 BLNDGAM_MEM_PWR_FORCE, power_on == true ? 0 : 1);
 556         }
 557 }
 558
 559 static void dpp3_power_on_hdr3dlut(
 560         struct dpp *dpp_base,
 561         bool power_on)
 562 {
 563         struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
 564
 565         if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) {
 566                 if (power_on) {
 567                         REG_UPDATE(CM_MEM_PWR_CTRL2, HDR3DLUT_MEM_PWR_FORCE, 0);
 568                         REG_WAIT(CM_MEM_PWR_STATUS2, HDR3DLUT_MEM_PWR_STATE, 0, 1, 5);
 569                 } else {
 570                         dpp_base->ctx->dc->optimized_required = true;
 571                         dpp_base->deferred_reg_writes.bits.disable_3dlut = true;
 572                 }
 573         }
 574 }
 575
 576 static void dpp3_power_on_shaper(
 577         struct dpp *dpp_base,
 578         bool power_on)
 579 {
 580         struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
 581
 582         if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) {
 583                 if (power_on) {
 584                         REG_UPDATE(CM_MEM_PWR_CTRL2, SHAPER_MEM_PWR_FORCE, 0);
 585                         REG_WAIT(CM_MEM_PWR_STATUS2, SHAPER_MEM_PWR_STATE, 0, 1, 5);
 586                 } else {
 587                         dpp_base->ctx->dc->optimized_required = true;
 588                         dpp_base->deferred_reg_writes.bits.disable_shaper = true;
 589                 }
 590         }
 591 }
 592
 593 static void dpp3_configure_blnd_lut(
 594                 struct dpp *dpp_base,
 595                 bool is_ram_a)
 596 {
 597         struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
 598
 599         REG_UPDATE_2(CM_BLNDGAM_LUT_CONTROL,
 600                         CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 7,
 601                         CM_BLNDGAM_LUT_HOST_SEL, is_ram_a == true ? 0 : 1);
 602
 603         REG_SET(CM_BLNDGAM_LUT_INDEX, 0, CM_BLNDGAM_LUT_INDEX, 0);
 604 }
 605
 606 static void dpp3_program_blnd_pwl(
 607                 struct dpp *dpp_base,
 608                 const struct pwl_result_data *rgb,
 609                 uint32_t num)
 610 {
 611         uint32_t i;
 612         struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
 613         uint32_t last_base_value_red = rgb[num-1].red_reg + rgb[num-1].delta_red_reg;
 614         uint32_t last_base_value_green = rgb[num-1].green_reg + rgb[num-1].delta_green_reg;
 615         uint32_t last_base_value_blue = rgb[num-1].blue_reg + rgb[num-1].delta_blue_reg;
 616
 617         if (is_rgb_equal(rgb, num)) {
 618                 for (i = 0 ; i < num; i++)
 619                         REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].red_reg);
 620                 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_red);
 621         } else {
 622                 REG_UPDATE(CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 4);
 623                 for (i = 0 ; i < num; i++)
 624                         REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].red_reg);
 625                 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_red);
 626
 627                 REG_UPDATE(CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 2);
 628                 for (i = 0 ; i < num; i++)
 629                         REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].green_reg);
 630                 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_green);
 631
 632                 REG_UPDATE(CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 1);
 633                 for (i = 0 ; i < num; i++)
 634                         REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].blue_reg);
 635                 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_blue);
 636         }
 637 }
 638
 639 static void dcn3_dpp_cm_get_reg_field(
 640                 struct dcn3_dpp *dpp,
 641                 struct dcn3_xfer_func_reg *reg)
 642 {
 643         reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET;
 644         reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET;
 645         reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
 646         reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
 647         reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET;
 648         reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET;
 649         reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
 650         reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
 651
 652         reg->shifts.field_region_end = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_B;
 653         reg->masks.field_region_end = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_B;
 654         reg->shifts.field_region_end_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B;
 655         reg->masks.field_region_end_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B;
 656         reg->shifts.field_region_end_base = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B;
 657         reg->masks.field_region_end_base = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B;
 658         reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B;
 659         reg->masks.field_region_linear_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B;
 660         reg->shifts.exp_region_start = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_B;
 661         reg->masks.exp_region_start = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_B;
 662         reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B;
 663         reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B;
 664 }
 665
 666 /*program blnd lut RAM A*/
 667 static void dpp3_program_blnd_luta_settings(
 668                 struct dpp *dpp_base,
 669                 const struct pwl_params *params)
 670 {
 671         struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
 672         struct dcn3_xfer_func_reg gam_regs;
 673
 674         dcn3_dpp_cm_get_reg_field(dpp, &gam_regs);
 675
 676         gam_regs.start_cntl_b = REG(CM_BLNDGAM_RAMA_START_CNTL_B);
 677         gam_regs.start_cntl_g = REG(CM_BLNDGAM_RAMA_START_CNTL_G);
 678         gam_regs.start_cntl_r = REG(CM_BLNDGAM_RAMA_START_CNTL_R);
 679         gam_regs.start_slope_cntl_b = REG(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B);
 680         gam_regs.start_slope_cntl_g = REG(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G);
 681         gam_regs.start_slope_cntl_r = REG(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R);
 682         gam_regs.start_end_cntl1_b = REG(CM_BLNDGAM_RAMA_END_CNTL1_B);
 683         gam_regs.start_end_cntl2_b = REG(CM_BLNDGAM_RAMA_END_CNTL2_B);
 684         gam_regs.start_end_cntl1_g = REG(CM_BLNDGAM_RAMA_END_CNTL1_G);
 685         gam_regs.start_end_cntl2_g = REG(CM_BLNDGAM_RAMA_END_CNTL2_G);
 686         gam_regs.start_end_cntl1_r = REG(CM_BLNDGAM_RAMA_END_CNTL1_R);
 687         gam_regs.start_end_cntl2_r = REG(CM_BLNDGAM_RAMA_END_CNTL2_R);
 688         gam_regs.region_start = REG(CM_BLNDGAM_RAMA_REGION_0_1);
 689         gam_regs.region_end = REG(CM_BLNDGAM_RAMA_REGION_32_33);
 690
 691         cm_helper_program_gamcor_xfer_func(dpp->base.ctx, params, &gam_regs);
 692 }
 693
 694 /*program blnd lut RAM B*/
 695 static void dpp3_program_blnd_lutb_settings(
 696                 struct dpp *dpp_base,
 697                 const struct pwl_params *params)
 698 {
 699         struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
 700         struct dcn3_xfer_func_reg gam_regs;
 701
 702         dcn3_dpp_cm_get_reg_field(dpp, &gam_regs);
 703
 704         gam_regs.start_cntl_b = REG(CM_BLNDGAM_RAMB_START_CNTL_B);
 705         gam_regs.start_cntl_g = REG(CM_BLNDGAM_RAMB_START_CNTL_G);
 706         gam_regs.start_cntl_r = REG(CM_BLNDGAM_RAMB_START_CNTL_R);
 707         gam_regs.start_slope_cntl_b = REG(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B);
 708         gam_regs.start_slope_cntl_g = REG(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G);
 709         gam_regs.start_slope_cntl_r = REG(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R);
 710         gam_regs.start_end_cntl1_b = REG(CM_BLNDGAM_RAMB_END_CNTL1_B);
 711         gam_regs.start_end_cntl2_b = REG(CM_BLNDGAM_RAMB_END_CNTL2_B);
 712         gam_regs.start_end_cntl1_g = REG(CM_BLNDGAM_RAMB_END_CNTL1_G);
 713         gam_regs.start_end_cntl2_g = REG(CM_BLNDGAM_RAMB_END_CNTL2_G);
 714         gam_regs.start_end_cntl1_r = REG(CM_BLNDGAM_RAMB_END_CNTL1_R);
 715         gam_regs.start_end_cntl2_r = REG(CM_BLNDGAM_RAMB_END_CNTL2_R);
 716         gam_regs.region_start = REG(CM_BLNDGAM_RAMB_REGION_0_1);
 717         gam_regs.region_end = REG(CM_BLNDGAM_RAMB_REGION_32_33);
 718
 719         cm_helper_program_gamcor_xfer_func(dpp->base.ctx, params, &gam_regs);
 720 }
 721
 722 static enum dc_lut_mode dpp3_get_blndgam_current(struct dpp *dpp_base)
 723 {
 724         enum dc_lut_mode mode;
 725         uint32_t mode_current = 0;
 726         uint32_t in_use = 0;
 727
 728         struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
 729
 730         REG_GET(CM_BLNDGAM_CONTROL,
 731                         CM_BLNDGAM_MODE_CURRENT, &mode_current);
 732         REG_GET(CM_BLNDGAM_CONTROL,
 733                         CM_BLNDGAM_SELECT_CURRENT, &in_use);
 734
 735                 switch (mode_current) {
 736                 case 0:
 737                 case 1:
 738                         mode = LUT_BYPASS;
 739                         break;
 740
 741                 case 2:
 742                         if (in_use == 0)
 743                                 mode = LUT_RAM_A;
 744                         else
 745                                 mode = LUT_RAM_B;
 746                         break;
 747                 default:
 748                         mode = LUT_BYPASS;
 749                         break;
 750                 }
 751                 return mode;
 752 }
 753
 754 bool dpp3_program_blnd_lut(
 755         struct dpp *dpp_base, const struct pwl_params *params)
 756 {
 757         enum dc_lut_mode current_mode;
 758         enum dc_lut_mode next_mode;
 759         struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
 760
 761         if (params == NULL) {
 762                 REG_SET(CM_BLNDGAM_CONTROL, 0, CM_BLNDGAM_MODE, 0);
 763                 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm)
 764                         dpp3_power_on_blnd_lut(dpp_base, false);
 765                 return false;
 766         }
 767
 768         current_mode = dpp3_get_blndgam_current(dpp_base);
 769         if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_B)
 770                 next_mode = LUT_RAM_A;
 771         else
 772                 next_mode = LUT_RAM_B;
 773
 774         dpp3_power_on_blnd_lut(dpp_base, true);
 775         dpp3_configure_blnd_lut(dpp_base, next_mode == LUT_RAM_A);
 776
 777         if (next_mode == LUT_RAM_A)
 778                 dpp3_program_blnd_luta_settings(dpp_base, params);
 779         else
 780                 dpp3_program_blnd_lutb_settings(dpp_base, params);
 781
 782         dpp3_program_blnd_pwl(
 783                         dpp_base, params->rgb_resulted, params->hw_points_num);
 784
 785         REG_UPDATE_2(CM_BLNDGAM_CONTROL,
 786                         CM_BLNDGAM_MODE, 2,
 787                         CM_BLNDGAM_SELECT, next_mode == LUT_RAM_A ? 0 : 1);
 788
 789         return true;
 790 }
 791
 792
 793 static void dpp3_program_shaper_lut(
 794                 struct dpp *dpp_base,
 795                 const struct pwl_result_data *rgb,
 796                 uint32_t num)
 797 {
 798         uint32_t i, red, green, blue;
 799         uint32_t  red_delta, green_delta, blue_delta;
 800         uint32_t  red_value, green_value, blue_value;
 801
 802         struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
 803
 804         for (i = 0 ; i < num; i++) {
 805
 806                 red   = rgb[i].red_reg;
 807                 green = rgb[i].green_reg;
 808                 blue  = rgb[i].blue_reg;
 809
 810                 red_delta   = rgb[i].delta_red_reg;
 811                 green_delta = rgb[i].delta_green_reg;
 812                 blue_delta  = rgb[i].delta_blue_reg;
 813
 814                 red_value   = ((red_delta   & 0x3ff) << 14) | (red   & 0x3fff);
 815                 green_value = ((green_delta & 0x3ff) << 14) | (green & 0x3fff);
 816                 blue_value  = ((blue_delta  & 0x3ff) << 14) | (blue  & 0x3fff);
 817
 818                 REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, red_value);
 819                 REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, green_value);
 820                 REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, blue_value);
 821         }
 822
 823 }
 824
 825 static enum dc_lut_mode dpp3_get_shaper_current(struct dpp *dpp_base)
 826 {
 827         enum dc_lut_mode mode;
 828         uint32_t state_mode;
 829         struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
 830
 831         REG_GET(CM_SHAPER_CONTROL,
 832                         CM_SHAPER_MODE_CURRENT, &state_mode);
 833
 834                 switch (state_mode) {
 835                 case 0:
 836                         mode = LUT_BYPASS;
 837                         break;
 838                 case 1:
 839                         mode = LUT_RAM_A;
 840                         break;
 841                 case 2:
 842                         mode = LUT_RAM_B;
 843                         break;
 844                 default:
 845                         mode = LUT_BYPASS;
 846                         break;
 847                 }
 848                 return mode;
 849 }
 850
 851 static void dpp3_configure_shaper_lut(
 852                 struct dpp *dpp_base,
 853                 bool is_ram_a)
 854 {
 855         struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
 856
 857         REG_UPDATE(CM_SHAPER_LUT_WRITE_EN_MASK,
 858                         CM_SHAPER_LUT_WRITE_EN_MASK, 7);
 859         REG_UPDATE(CM_SHAPER_LUT_WRITE_EN_MASK,
 860                         CM_SHAPER_LUT_WRITE_SEL, is_ram_a == true ? 0:1);
 861         REG_SET(CM_SHAPER_LUT_INDEX, 0, CM_SHAPER_LUT_INDEX, 0);
 862 }
 863
 864 /*program shaper RAM A*/
 865
 866 static void dpp3_program_shaper_luta_settings(
 867                 struct dpp *dpp_base,
 868                 const struct pwl_params *params)
 869 {
 870         const struct gamma_curve *curve;
 871         struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
 872
 873         REG_SET_2(CM_SHAPER_RAMA_START_CNTL_B, 0,
 874                 CM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x,
 875                 CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);
 876         REG_SET_2(CM_SHAPER_RAMA_START_CNTL_G, 0,
 877                 CM_SHAPER_RAMA_EXP_REGION_START_G, params->corner_points[0].green.custom_float_x,
 878                 CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G, 0);
 879         REG_SET_2(CM_SHAPER_RAMA_START_CNTL_R, 0,
 880                 CM_SHAPER_RAMA_EXP_REGION_START_R, params->corner_points[0].red.custom_float_x,
 881                 CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R, 0);
 882
 883         REG_SET_2(CM_SHAPER_RAMA_END_CNTL_B, 0,
 884                 CM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x,
 885                 CM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y);
 886
 887         REG_SET_2(CM_SHAPER_RAMA_END_CNTL_G, 0,
 888                 CM_SHAPER_RAMA_EXP_REGION_END_G, params->corner_points[1].green.custom_float_x,
 889                 CM_SHAPER_RAMA_EXP_REGION_END_BASE_G, params->corner_points[1].green.custom_float_y);
 890
 891         REG_SET_2(CM_SHAPER_RAMA_END_CNTL_R, 0,
 892                 CM_SHAPER_RAMA_EXP_REGION_END_R, params->corner_points[1].red.custom_float_x,
 893                 CM_SHAPER_RAMA_EXP_REGION_END_BASE_R, params->corner_points[1].red.custom_float_y);
 894
 895         curve = params->arr_curve_points;
 896         REG_SET_4(CM_SHAPER_RAMA_REGION_0_1, 0,
 897                 CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 898                 CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 899                 CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 900                 CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 901
 902         curve += 2;
 903         REG_SET_4(CM_SHAPER_RAMA_REGION_2_3, 0,
 904                 CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET, curve[0].offset,
 905                 CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num,
 906                 CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET, curve[1].offset,
 907                 CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num);
 908
 909         curve += 2;
 910         REG_SET_4(CM_SHAPER_RAMA_REGION_4_5, 0,
 911                 CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET, curve[0].offset,
 912                 CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num,
 913                 CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET, curve[1].offset,
 914                 CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num);
 915
 916         curve += 2;
 917         REG_SET_4(CM_SHAPER_RAMA_REGION_6_7, 0,
 918                 CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET, curve[0].offset,
 919                 CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num,
 920                 CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET, curve[1].offset,
 921                 CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num);
 922
 923         curve += 2;
 924         REG_SET_4(CM_SHAPER_RAMA_REGION_8_9, 0,
 925                 CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET, curve[0].offset,
 926                 CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num,
 927                 CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET, curve[1].offset,
 928                 CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num);
 929
 930         curve += 2;
 931         REG_SET_4(CM_SHAPER_RAMA_REGION_10_11, 0,
 932                 CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET, curve[0].offset,
 933                 CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num,
 934                 CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET, curve[1].offset,
 935                 CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num);
 936
 937         curve += 2;
 938         REG_SET_4(CM_SHAPER_RAMA_REGION_12_13, 0,
 939                 CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET, curve[0].offset,
 940                 CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num,
 941                 CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET, curve[1].offset,
 942                 CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num);
 943
 944         curve += 2;
 945         REG_SET_4(CM_SHAPER_RAMA_REGION_14_15, 0,
 946                 CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET, curve[0].offset,
 947                 CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num,
 948                 CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET, curve[1].offset,
 949                 CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num);
 950
 951         curve += 2;
 952         REG_SET_4(CM_SHAPER_RAMA_REGION_16_17, 0,
 953                 CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET, curve[0].offset,
 954                 CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS, curve[0].segments_num,
 955                 CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET, curve[1].offset,
 956                 CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS, curve[1].segments_num);
 957
 958         curve += 2;
 959         REG_SET_4(CM_SHAPER_RAMA_REGION_18_19, 0,
 960                 CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET, curve[0].offset,
 961                 CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS, curve[0].segments_num,
 962                 CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET, curve[1].offset,
 963                 CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS, curve[1].segments_num);
 964
 965         curve += 2;
 966         REG_SET_4(CM_SHAPER_RAMA_REGION_20_21, 0,
 967                 CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET, curve[0].offset,
 968                 CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS, curve[0].segments_num,
 969                 CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET, curve[1].offset,
 970                 CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS, curve[1].segments_num);
 971
 972         curve += 2;
 973         REG_SET_4(CM_SHAPER_RAMA_REGION_22_23, 0,
 974                 CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET, curve[0].offset,
 975                 CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS, curve[0].segments_num,
 976                 CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET, curve[1].offset,
 977                 CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS, curve[1].segments_num);
 978
 979         curve += 2;
 980         REG_SET_4(CM_SHAPER_RAMA_REGION_24_25, 0,
 981                 CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET, curve[0].offset,
 982                 CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS, curve[0].segments_num,
 983                 CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET, curve[1].offset,
 984                 CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS, curve[1].segments_num);
 985
 986         curve += 2;
 987         REG_SET_4(CM_SHAPER_RAMA_REGION_26_27, 0,
 988                 CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET, curve[0].offset,
 989                 CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS, curve[0].segments_num,
 990                 CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET, curve[1].offset,
 991                 CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS, curve[1].segments_num);
 992
 993         curve += 2;
 994         REG_SET_4(CM_SHAPER_RAMA_REGION_28_29, 0,
 995                 CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET, curve[0].offset,
 996                 CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS, curve[0].segments_num,
 997                 CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET, curve[1].offset,
 998                 CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS, curve[1].segments_num);
 999
1000         curve += 2;
1001         REG_SET_4(CM_SHAPER_RAMA_REGION_30_31, 0,
1002                 CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET, curve[0].offset,
1003                 CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS, curve[0].segments_num,
1004                 CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET, curve[1].offset,
1005                 CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS, curve[1].segments_num);
1006
1007         curve += 2;
1008         REG_SET_4(CM_SHAPER_RAMA_REGION_32_33, 0,
1009                 CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET, curve[0].offset,
1010                 CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS, curve[0].segments_num,
1011                 CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET, curve[1].offset,
1012                 CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS, curve[1].segments_num);
1013 }
1014
1015 /*program shaper RAM B*/
1016 static void dpp3_program_shaper_lutb_settings(
1017                 struct dpp *dpp_base,
1018                 const struct pwl_params *params)
1019 {
1020         const struct gamma_curve *curve;
1021         struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1022
1023         REG_SET_2(CM_SHAPER_RAMB_START_CNTL_B, 0,
1024                 CM_SHAPER_RAMB_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x,
1025                 CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B, 0);
1026         REG_SET_2(CM_SHAPER_RAMB_START_CNTL_G, 0,
1027                 CM_SHAPER_RAMB_EXP_REGION_START_G, params->corner_points[0].green.custom_float_x,
1028                 CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G, 0);
1029         REG_SET_2(CM_SHAPER_RAMB_START_CNTL_R, 0,
1030                 CM_SHAPER_RAMB_EXP_REGION_START_R, params->corner_points[0].red.custom_float_x,
1031                 CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R, 0);
1032
1033         REG_SET_2(CM_SHAPER_RAMB_END_CNTL_B, 0,
1034                 CM_SHAPER_RAMB_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x,
1035                 CM_SHAPER_RAMB_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y);
1036
1037         REG_SET_2(CM_SHAPER_RAMB_END_CNTL_G, 0,
1038                 CM_SHAPER_RAMB_EXP_REGION_END_G, params->corner_points[1].green.custom_float_x,
1039                 CM_SHAPER_RAMB_EXP_REGION_END_BASE_G, params->corner_points[1].green.custom_float_y);
1040
1041         REG_SET_2(CM_SHAPER_RAMB_END_CNTL_R, 0,
1042                 CM_SHAPER_RAMB_EXP_REGION_END_R, params->corner_points[1].red.custom_float_x,
1043                 CM_SHAPER_RAMB_EXP_REGION_END_BASE_R, params->corner_points[1].red.custom_float_y);
1044
1045         curve = params->arr_curve_points;
1046         REG_SET_4(CM_SHAPER_RAMB_REGION_0_1, 0,
1047                 CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset,
1048                 CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
1049                 CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset,
1050                 CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
1051
1052         curve += 2;
1053         REG_SET_4(CM_SHAPER_RAMB_REGION_2_3, 0,
1054                 CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET, curve[0].offset,
1055                 CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num,
1056                 CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET, curve[1].offset,
1057                 CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num);
1058
1059         curve += 2;
1060         REG_SET_4(CM_SHAPER_RAMB_REGION_4_5, 0,
1061                 CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET, curve[0].offset,
1062                 CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num,
1063                 CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET, curve[1].offset,
1064                 CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num);
1065
1066         curve += 2;
1067         REG_SET_4(CM_SHAPER_RAMB_REGION_6_7, 0,
1068                 CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET, curve[0].offset,
1069                 CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num,
1070                 CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET, curve[1].offset,
1071                 CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num);
1072
1073         curve += 2;
1074         REG_SET_4(CM_SHAPER_RAMB_REGION_8_9, 0,
1075                 CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET, curve[0].offset,
1076                 CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num,
1077                 CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET, curve[1].offset,
1078                 CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num);
1079
1080         curve += 2;
1081         REG_SET_4(CM_SHAPER_RAMB_REGION_10_11, 0,
1082                 CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET, curve[0].offset,
1083                 CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num,
1084                 CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET, curve[1].offset,
1085                 CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num);
1086
1087         curve += 2;
1088         REG_SET_4(CM_SHAPER_RAMB_REGION_12_13, 0,
1089                 CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET, curve[0].offset,
1090                 CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num,
1091                 CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET, curve[1].offset,
1092                 CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num);
1093
1094         curve += 2;
1095         REG_SET_4(CM_SHAPER_RAMB_REGION_14_15, 0,
1096                 CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET, curve[0].offset,
1097                 CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num,
1098                 CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET, curve[1].offset,
1099                 CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num);
1100
1101         curve += 2;
1102         REG_SET_4(CM_SHAPER_RAMB_REGION_16_17, 0,
1103                 CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET, curve[0].offset,
1104                 CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS, curve[0].segments_num,
1105                 CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET, curve[1].offset,
1106                 CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS, curve[1].segments_num);
1107
1108         curve += 2;
1109         REG_SET_4(CM_SHAPER_RAMB_REGION_18_19, 0,
1110                 CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET, curve[0].offset,
1111                 CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS, curve[0].segments_num,
1112                 CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET, curve[1].offset,
1113                 CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS, curve[1].segments_num);
1114
1115         curve += 2;
1116         REG_SET_4(CM_SHAPER_RAMB_REGION_20_21, 0,
1117                 CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET, curve[0].offset,
1118                 CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS, curve[0].segments_num,
1119                 CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET, curve[1].offset,
1120                 CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS, curve[1].segments_num);
1121
1122         curve += 2;
1123         REG_SET_4(CM_SHAPER_RAMB_REGION_22_23, 0,
1124                 CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET, curve[0].offset,
1125                 CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS, curve[0].segments_num,
1126                 CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET, curve[1].offset,
1127                 CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS, curve[1].segments_num);
1128
1129         curve += 2;
1130         REG_SET_4(CM_SHAPER_RAMB_REGION_24_25, 0,
1131                 CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET, curve[0].offset,
1132                 CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS, curve[0].segments_num,
1133                 CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET, curve[1].offset,
1134                 CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS, curve[1].segments_num);
1135
1136         curve += 2;
1137         REG_SET_4(CM_SHAPER_RAMB_REGION_26_27, 0,
1138                 CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET, curve[0].offset,
1139                 CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS, curve[0].segments_num,
1140                 CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET, curve[1].offset,
1141                 CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS, curve[1].segments_num);
1142
1143         curve += 2;
1144         REG_SET_4(CM_SHAPER_RAMB_REGION_28_29, 0,
1145                 CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET, curve[0].offset,
1146                 CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS, curve[0].segments_num,
1147                 CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET, curve[1].offset,
1148                 CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS, curve[1].segments_num);
1149
1150         curve += 2;
1151         REG_SET_4(CM_SHAPER_RAMB_REGION_30_31, 0,
1152                 CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET, curve[0].offset,
1153                 CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS, curve[0].segments_num,
1154                 CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET, curve[1].offset,
1155                 CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS, curve[1].segments_num);
1156
1157         curve += 2;
1158         REG_SET_4(CM_SHAPER_RAMB_REGION_32_33, 0,
1159                 CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET, curve[0].offset,
1160                 CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS, curve[0].segments_num,
1161                 CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET, curve[1].offset,
1162                 CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS, curve[1].segments_num);
1163
1164 }
1165
1166
1167 bool dpp3_program_shaper(
1168                 struct dpp *dpp_base,
1169                 const struct pwl_params *params)
1170 {
1171         enum dc_lut_mode current_mode;
1172         enum dc_lut_mode next_mode;
1173
1174         struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1175
1176         if (params == NULL) {
1177                 REG_SET(CM_SHAPER_CONTROL, 0, CM_SHAPER_LUT_MODE, 0);
1178                 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm)
1179                         dpp3_power_on_shaper(dpp_base, false);
1180                 return false;
1181         }
1182
1183         if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm)
1184                 dpp3_power_on_shaper(dpp_base, true);
1185
1186         current_mode = dpp3_get_shaper_current(dpp_base);
1187
1188         if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A)
1189                 next_mode = LUT_RAM_B;
1190         else
1191                 next_mode = LUT_RAM_A;
1192
1193         dpp3_configure_shaper_lut(dpp_base, next_mode == LUT_RAM_A);
1194
1195         if (next_mode == LUT_RAM_A)
1196                 dpp3_program_shaper_luta_settings(dpp_base, params);
1197         else
1198                 dpp3_program_shaper_lutb_settings(dpp_base, params);
1199
1200         dpp3_program_shaper_lut(
1201                         dpp_base, params->rgb_resulted, params->hw_points_num);
1202
1203         REG_SET(CM_SHAPER_CONTROL, 0, CM_SHAPER_LUT_MODE, next_mode == LUT_RAM_A ? 1:2);
1204
1205         return true;
1206
1207 }
1208
1209 static enum dc_lut_mode get3dlut_config(
1210                         struct dpp *dpp_base,
1211                         bool *is_17x17x17,
1212                         bool *is_12bits_color_channel)
1213 {
1214         uint32_t i_mode, i_enable_10bits, lut_size;
1215         enum dc_lut_mode mode;
1216         struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1217
1218         REG_GET(CM_3DLUT_READ_WRITE_CONTROL,
1219                         CM_3DLUT_30BIT_EN, &i_enable_10bits);
1220         REG_GET(CM_3DLUT_MODE,
1221                         CM_3DLUT_MODE_CURRENT, &i_mode);
1222
1223         switch (i_mode) {
1224         case 0:
1225                 mode = LUT_BYPASS;
1226                 break;
1227         case 1:
1228                 mode = LUT_RAM_A;
1229                 break;
1230         case 2:
1231                 mode = LUT_RAM_B;
1232                 break;
1233         default:
1234                 mode = LUT_BYPASS;
1235                 break;
1236         }
1237         if (i_enable_10bits > 0)
1238                 *is_12bits_color_channel = false;
1239         else
1240                 *is_12bits_color_channel = true;
1241
1242         REG_GET(CM_3DLUT_MODE, CM_3DLUT_SIZE, &lut_size);
1243
1244         if (lut_size == 0)
1245                 *is_17x17x17 = true;
1246         else
1247                 *is_17x17x17 = false;
1248
1249         return mode;
1250 }
1251 /*
1252  * select ramA or ramB, or bypass
1253  * select color channel size 10 or 12 bits
1254  * select 3dlut size 17x17x17 or 9x9x9
1255  */
1256 static void dpp3_set_3dlut_mode(
1257                 struct dpp *dpp_base,
1258                 enum dc_lut_mode mode,
1259                 bool is_color_channel_12bits,
1260                 bool is_lut_size17x17x17)
1261 {
1262         uint32_t lut_mode;
1263         struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1264
1265         if (mode == LUT_BYPASS)
1266                 lut_mode = 0;
1267         else if (mode == LUT_RAM_A)
1268                 lut_mode = 1;
1269         else
1270                 lut_mode = 2;
1271
1272         REG_UPDATE_2(CM_3DLUT_MODE,
1273                         CM_3DLUT_MODE, lut_mode,
1274                         CM_3DLUT_SIZE, is_lut_size17x17x17 == true ? 0 : 1);
1275 }
1276
1277 static void dpp3_select_3dlut_ram(
1278                 struct dpp *dpp_base,
1279                 enum dc_lut_mode mode,
1280                 bool is_color_channel_12bits)
1281 {
1282         struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1283
1284         REG_UPDATE_2(CM_3DLUT_READ_WRITE_CONTROL,
1285                         CM_3DLUT_RAM_SEL, mode == LUT_RAM_A ? 0 : 1,
1286                         CM_3DLUT_30BIT_EN,
1287                         is_color_channel_12bits == true ? 0:1);
1288 }
1289
1290
1291
1292 static void dpp3_set3dlut_ram12(
1293                 struct dpp *dpp_base,
1294                 const struct dc_rgb *lut,
1295                 uint32_t entries)
1296 {
1297         uint32_t i, red, green, blue, red1, green1, blue1;
1298         struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1299
1300         for (i = 0 ; i < entries; i += 2) {
1301                 red   = lut[i].red<<4;
1302                 green = lut[i].green<<4;
1303                 blue  = lut[i].blue<<4;
1304                 red1   = lut[i+1].red<<4;
1305                 green1 = lut[i+1].green<<4;
1306                 blue1  = lut[i+1].blue<<4;
1307
1308                 REG_SET_2(CM_3DLUT_DATA, 0,
1309                                 CM_3DLUT_DATA0, red,
1310                                 CM_3DLUT_DATA1, red1);
1311
1312                 REG_SET_2(CM_3DLUT_DATA, 0,
1313                                 CM_3DLUT_DATA0, green,
1314                                 CM_3DLUT_DATA1, green1);
1315
1316                 REG_SET_2(CM_3DLUT_DATA, 0,
1317                                 CM_3DLUT_DATA0, blue,
1318                                 CM_3DLUT_DATA1, blue1);
1319
1320         }
1321 }
1322
1323 /*
1324  * load selected lut with 10 bits color channels
1325  */
1326 static void dpp3_set3dlut_ram10(
1327                 struct dpp *dpp_base,
1328                 const struct dc_rgb *lut,
1329                 uint32_t entries)
1330 {
1331         uint32_t i, red, green, blue, value;
1332         struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1333
1334         for (i = 0; i < entries; i++) {
1335                 red   = lut[i].red;
1336                 green = lut[i].green;
1337                 blue  = lut[i].blue;
1338
1339                 value = (red<<20) | (green<<10) | blue;
1340
1341                 REG_SET(CM_3DLUT_DATA_30BIT, 0, CM_3DLUT_DATA_30BIT, value);
1342         }
1343
1344 }
1345
1346
1347 static void dpp3_select_3dlut_ram_mask(
1348                 struct dpp *dpp_base,
1349                 uint32_t ram_selection_mask)
1350 {
1351         struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1352
1353         REG_UPDATE(CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_WRITE_EN_MASK,
1354                         ram_selection_mask);
1355         REG_SET(CM_3DLUT_INDEX, 0, CM_3DLUT_INDEX, 0);
1356 }
1357
1358 bool dpp3_program_3dlut(
1359                 struct dpp *dpp_base,
1360                 struct tetrahedral_params *params)
1361 {
1362         enum dc_lut_mode mode;
1363         bool is_17x17x17;
1364         bool is_12bits_color_channel;
1365         struct dc_rgb *lut0;
1366         struct dc_rgb *lut1;
1367         struct dc_rgb *lut2;
1368         struct dc_rgb *lut3;
1369         int lut_size0;
1370         int lut_size;
1371
1372         if (params == NULL) {
1373                 dpp3_set_3dlut_mode(dpp_base, LUT_BYPASS, false, false);
1374                 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm)
1375                         dpp3_power_on_hdr3dlut(dpp_base, false);
1376                 return false;
1377         }
1378
1379         if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm)
1380                 dpp3_power_on_hdr3dlut(dpp_base, true);
1381
1382         mode = get3dlut_config(dpp_base, &is_17x17x17, &is_12bits_color_channel);
1383
1384         if (mode == LUT_BYPASS || mode == LUT_RAM_B)
1385                 mode = LUT_RAM_A;
1386         else
1387                 mode = LUT_RAM_B;
1388
1389         is_17x17x17 = !params->use_tetrahedral_9;
1390         is_12bits_color_channel = params->use_12bits;
1391         if (is_17x17x17) {
1392                 lut0 = params->tetrahedral_17.lut0;
1393                 lut1 = params->tetrahedral_17.lut1;
1394                 lut2 = params->tetrahedral_17.lut2;
1395                 lut3 = params->tetrahedral_17.lut3;
1396                 lut_size0 = sizeof(params->tetrahedral_17.lut0)/
1397                                         sizeof(params->tetrahedral_17.lut0[0]);
1398                 lut_size  = sizeof(params->tetrahedral_17.lut1)/
1399                                         sizeof(params->tetrahedral_17.lut1[0]);
1400         } else {
1401                 lut0 = params->tetrahedral_9.lut0;
1402                 lut1 = params->tetrahedral_9.lut1;
1403                 lut2 = params->tetrahedral_9.lut2;
1404                 lut3 = params->tetrahedral_9.lut3;
1405                 lut_size0 = sizeof(params->tetrahedral_9.lut0)/
1406                                 sizeof(params->tetrahedral_9.lut0[0]);
1407                 lut_size  = sizeof(params->tetrahedral_9.lut1)/
1408                                 sizeof(params->tetrahedral_9.lut1[0]);
1409                 }
1410
1411         dpp3_select_3dlut_ram(dpp_base, mode,
1412                                 is_12bits_color_channel);
1413         dpp3_select_3dlut_ram_mask(dpp_base, 0x1);
1414         if (is_12bits_color_channel)
1415                 dpp3_set3dlut_ram12(dpp_base, lut0, lut_size0);
1416         else
1417                 dpp3_set3dlut_ram10(dpp_base, lut0, lut_size0);
1418
1419         dpp3_select_3dlut_ram_mask(dpp_base, 0x2);
1420         if (is_12bits_color_channel)
1421                 dpp3_set3dlut_ram12(dpp_base, lut1, lut_size);
1422         else
1423                 dpp3_set3dlut_ram10(dpp_base, lut1, lut_size);
1424
1425         dpp3_select_3dlut_ram_mask(dpp_base, 0x4);
1426         if (is_12bits_color_channel)
1427                 dpp3_set3dlut_ram12(dpp_base, lut2, lut_size);
1428         else
1429                 dpp3_set3dlut_ram10(dpp_base, lut2, lut_size);
1430
1431         dpp3_select_3dlut_ram_mask(dpp_base, 0x8);
1432         if (is_12bits_color_channel)
1433                 dpp3_set3dlut_ram12(dpp_base, lut3, lut_size);
1434         else
1435                 dpp3_set3dlut_ram10(dpp_base, lut3, lut_size);
1436
1437
1438         dpp3_set_3dlut_mode(dpp_base, mode, is_12bits_color_channel,
1439                                         is_17x17x17);
1440
1441         return true;
1442 }
1443 static struct dpp_funcs dcn30_dpp_funcs = {
1444         .dpp_program_gamcor_lut = dpp3_program_gamcor_lut,
1445         .dpp_read_state                 = dpp30_read_state,
1446         .dpp_reset                      = dpp_reset,
1447         .dpp_set_scaler                 = dpp1_dscl_set_scaler_manual_scale,
1448         .dpp_get_optimal_number_of_taps = dpp3_get_optimal_number_of_taps,
1449         .dpp_set_gamut_remap            = dpp3_cm_set_gamut_remap,
1450         .dpp_set_csc_adjustment         = NULL,
1451         .dpp_set_csc_default            = NULL,
1452         .dpp_program_regamma_pwl        = NULL,
1453         .dpp_set_pre_degam              = dpp3_set_pre_degam,
1454         .dpp_program_input_lut          = NULL,
1455         .dpp_full_bypass                = dpp1_full_bypass,
1456         .dpp_setup                      = dpp3_cnv_setup,
1457         .dpp_program_degamma_pwl        = NULL,
1458         .dpp_program_cm_dealpha = dpp3_program_cm_dealpha,
1459         .dpp_program_cm_bias = dpp3_program_cm_bias,
1460         .dpp_program_blnd_lut = dpp3_program_blnd_lut,
1461         .dpp_program_shaper_lut = dpp3_program_shaper,
1462         .dpp_program_3dlut = dpp3_program_3dlut,
1463         .dpp_deferred_update = dpp3_deferred_update,
1464         .dpp_program_bias_and_scale     = NULL,
1465         .dpp_cnv_set_alpha_keyer        = dpp2_cnv_set_alpha_keyer,
1466         .set_cursor_attributes          = dpp3_set_cursor_attributes,
1467         .set_cursor_position            = dpp1_set_cursor_position,
1468         .set_optional_cursor_attributes = dpp1_cnv_set_optional_cursor_attributes,
1469         .dpp_dppclk_control             = dpp1_dppclk_control,
1470         .dpp_set_hdr_multiplier         = dpp3_set_hdr_multiplier,
1471 };
1472
1473
1474 static struct dpp_caps dcn30_dpp_cap = {
1475         .dscl_data_proc_format = DSCL_DATA_PRCESSING_FLOAT_FORMAT,
1476         .dscl_calc_lb_num_partitions = dscl2_calc_lb_num_partitions,
1477 };
1478
1479 bool dpp3_construct(
1480         struct dcn3_dpp *dpp,
1481         struct dc_context *ctx,
1482         uint32_t inst,
1483         const struct dcn3_dpp_registers *tf_regs,
1484         const struct dcn3_dpp_shift *tf_shift,
1485         const struct dcn3_dpp_mask *tf_mask)
1486 {
1487         dpp->base.ctx = ctx;
1488
1489         dpp->base.inst = inst;
1490         dpp->base.funcs = &dcn30_dpp_funcs;
1491         dpp->base.caps = &dcn30_dpp_cap;
1492
1493         dpp->tf_regs = tf_regs;
1494         dpp->tf_shift = tf_shift;
1495         dpp->tf_mask = tf_mask;
1496
1497         return true;
1498 }
1499