2 * Copyright 2020 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
27 #include "dc_bios_types.h"
28 #include "dcn30_dio_stream_encoder.h"
29 #include "reg_helper.h"
30 #include "hw_shared.h"
31 #include "core_types.h"
32 #include <linux/delay.h>
36 enc1->base.ctx->logger
43 #define FN(reg_name, field_name) \
44 enc1->se_shift->field_name, enc1->se_mask->field_name
47 #define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000
53 static void enc3_update_hdmi_info_packet(
54 struct dcn10_stream_encoder *enc1,
55 uint32_t packet_index,
56 const struct dc_info_packet *info_packet)
58 uint32_t cont, send, line;
60 if (info_packet->valid) {
61 enc1->base.vpg->funcs->update_generic_info_packet(
67 /* enable transmission of packet(s) -
68 * packet transmission begins on the next frame */
70 /* send packet(s) every frame */
72 /* select line number to send packets on */
80 /* DP_SEC_GSP[x]_LINE_REFERENCE - keep default value REFER_TO_DP_SOF */
82 /* choose which generic packet control to use */
83 switch (packet_index) {
85 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
86 HDMI_GENERIC0_CONT, cont,
87 HDMI_GENERIC0_SEND, send);
88 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL1,
89 HDMI_GENERIC0_LINE, line);
92 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
93 HDMI_GENERIC1_CONT, cont,
94 HDMI_GENERIC1_SEND, send);
95 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL1,
96 HDMI_GENERIC1_LINE, line);
99 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
100 HDMI_GENERIC2_CONT, cont,
101 HDMI_GENERIC2_SEND, send);
102 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL2,
103 HDMI_GENERIC2_LINE, line);
106 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
107 HDMI_GENERIC3_CONT, cont,
108 HDMI_GENERIC3_SEND, send);
109 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL2,
110 HDMI_GENERIC3_LINE, line);
113 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
114 HDMI_GENERIC4_CONT, cont,
115 HDMI_GENERIC4_SEND, send);
116 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL3,
117 HDMI_GENERIC4_LINE, line);
120 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
121 HDMI_GENERIC5_CONT, cont,
122 HDMI_GENERIC5_SEND, send);
123 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL3,
124 HDMI_GENERIC5_LINE, line);
127 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
128 HDMI_GENERIC6_CONT, cont,
129 HDMI_GENERIC6_SEND, send);
130 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL4,
131 HDMI_GENERIC6_LINE, line);
134 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
135 HDMI_GENERIC7_CONT, cont,
136 HDMI_GENERIC7_SEND, send);
137 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL4,
138 HDMI_GENERIC7_LINE, line);
141 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL6,
142 HDMI_GENERIC8_CONT, cont,
143 HDMI_GENERIC8_SEND, send);
144 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL7,
145 HDMI_GENERIC8_LINE, line);
148 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL6,
149 HDMI_GENERIC9_CONT, cont,
150 HDMI_GENERIC9_SEND, send);
151 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL7,
152 HDMI_GENERIC9_LINE, line);
155 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL6,
156 HDMI_GENERIC10_CONT, cont,
157 HDMI_GENERIC10_SEND, send);
158 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL8,
159 HDMI_GENERIC10_LINE, line);
162 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL6,
163 HDMI_GENERIC11_CONT, cont,
164 HDMI_GENERIC11_SEND, send);
165 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL8,
166 HDMI_GENERIC11_LINE, line);
169 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL6,
170 HDMI_GENERIC12_CONT, cont,
171 HDMI_GENERIC12_SEND, send);
172 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL9,
173 HDMI_GENERIC12_LINE, line);
176 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL6,
177 HDMI_GENERIC13_CONT, cont,
178 HDMI_GENERIC13_SEND, send);
179 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL9,
180 HDMI_GENERIC13_LINE, line);
183 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL6,
184 HDMI_GENERIC14_CONT, cont,
185 HDMI_GENERIC14_SEND, send);
186 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL10,
187 HDMI_GENERIC14_LINE, line);
190 /* invalid HW packet index */
192 "Invalid HW packet index: %s()\n",
198 static void enc3_stream_encoder_update_hdmi_info_packets(
199 struct stream_encoder *enc,
200 const struct encoder_info_frame *info_frame)
202 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
204 /* for bring up, disable dp double TODO */
205 REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1);
206 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
208 /*Always add mandatory packets first followed by optional ones*/
209 enc3_update_hdmi_info_packet(enc1, 0, &info_frame->avi);
210 enc3_update_hdmi_info_packet(enc1, 5, &info_frame->hfvsif);
211 enc3_update_hdmi_info_packet(enc1, 2, &info_frame->gamut);
212 enc3_update_hdmi_info_packet(enc1, 1, &info_frame->vendor);
213 enc3_update_hdmi_info_packet(enc1, 3, &info_frame->spd);
214 enc3_update_hdmi_info_packet(enc1, 4, &info_frame->hdrsmd);
217 static void enc3_stream_encoder_stop_hdmi_info_packets(
218 struct stream_encoder *enc)
220 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
222 /* stop generic packets 0,1 on HDMI */
223 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0,
224 HDMI_GENERIC0_CONT, 0,
225 HDMI_GENERIC0_SEND, 0,
226 HDMI_GENERIC1_CONT, 0,
227 HDMI_GENERIC1_SEND, 0);
228 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL1, 0,
229 HDMI_GENERIC0_LINE, 0,
230 HDMI_GENERIC1_LINE, 0);
232 /* stop generic packets 2,3 on HDMI */
233 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0,
234 HDMI_GENERIC2_CONT, 0,
235 HDMI_GENERIC2_SEND, 0,
236 HDMI_GENERIC3_CONT, 0,
237 HDMI_GENERIC3_SEND, 0);
238 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL2, 0,
239 HDMI_GENERIC2_LINE, 0,
240 HDMI_GENERIC3_LINE, 0);
242 /* stop generic packets 4,5 on HDMI */
243 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0,
244 HDMI_GENERIC4_CONT, 0,
245 HDMI_GENERIC4_SEND, 0,
246 HDMI_GENERIC5_CONT, 0,
247 HDMI_GENERIC5_SEND, 0);
248 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL3, 0,
249 HDMI_GENERIC4_LINE, 0,
250 HDMI_GENERIC5_LINE, 0);
252 /* stop generic packets 6,7 on HDMI */
253 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0,
254 HDMI_GENERIC6_CONT, 0,
255 HDMI_GENERIC6_SEND, 0,
256 HDMI_GENERIC7_CONT, 0,
257 HDMI_GENERIC7_SEND, 0);
258 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL4, 0,
259 HDMI_GENERIC6_LINE, 0,
260 HDMI_GENERIC7_LINE, 0);
262 /* stop generic packets 8,9 on HDMI */
263 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL6, 0,
264 HDMI_GENERIC8_CONT, 0,
265 HDMI_GENERIC8_SEND, 0,
266 HDMI_GENERIC9_CONT, 0,
267 HDMI_GENERIC9_SEND, 0);
268 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL7, 0,
269 HDMI_GENERIC8_LINE, 0,
270 HDMI_GENERIC9_LINE, 0);
272 /* stop generic packets 10,11 on HDMI */
273 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL6, 0,
274 HDMI_GENERIC10_CONT, 0,
275 HDMI_GENERIC10_SEND, 0,
276 HDMI_GENERIC11_CONT, 0,
277 HDMI_GENERIC11_SEND, 0);
278 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL8, 0,
279 HDMI_GENERIC10_LINE, 0,
280 HDMI_GENERIC11_LINE, 0);
282 /* stop generic packets 12,13 on HDMI */
283 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL6, 0,
284 HDMI_GENERIC12_CONT, 0,
285 HDMI_GENERIC12_SEND, 0,
286 HDMI_GENERIC13_CONT, 0,
287 HDMI_GENERIC13_SEND, 0);
288 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL9, 0,
289 HDMI_GENERIC12_LINE, 0,
290 HDMI_GENERIC13_LINE, 0);
292 /* stop generic packet 14 on HDMI */
293 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL6, 0,
294 HDMI_GENERIC14_CONT, 0,
295 HDMI_GENERIC14_SEND, 0);
296 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL10,
297 HDMI_GENERIC14_LINE, 0);
300 /* Set DSC-related configuration.
301 * dsc_mode: 0 disables DSC, other values enable DSC in specified format
302 * sc_bytes_per_pixel: Bytes per pixel in u3.28 format
303 * dsc_slice_width: Slice width in pixels
305 static void enc3_dp_set_dsc_config(struct stream_encoder *enc,
306 enum optc_dsc_mode dsc_mode,
307 uint32_t dsc_bytes_per_pixel,
308 uint32_t dsc_slice_width)
310 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
312 REG_UPDATE_2(DP_DSC_CNTL,
313 DP_DSC_MODE, dsc_mode,
314 DP_DSC_SLICE_WIDTH, dsc_slice_width);
316 REG_SET(DP_DSC_BYTES_PER_PIXEL, 0,
317 DP_DSC_BYTES_PER_PIXEL, dsc_bytes_per_pixel);
321 static void enc3_dp_set_dsc_pps_info_packet(struct stream_encoder *enc,
323 uint8_t *dsc_packed_pps,
324 bool immediate_update)
326 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
329 struct dc_info_packet pps_sdp;
332 /* Configure for PPS packet size (128 bytes) */
333 REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP11_PPS, 1);
335 /* We need turn on clock before programming AFMT block
337 * TODO: We may not need this here anymore since update_generic_info_packet
338 * no longer touches AFMT
340 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
342 /* Load PPS into infoframe (SDP) registers */
343 pps_sdp.valid = true;
345 pps_sdp.hb1 = DC_DP_INFOFRAME_TYPE_PPS;
349 for (i = 0; i < 4; i++) {
350 memcpy(pps_sdp.sb, &dsc_packed_pps[i * 32], 32);
351 enc1->base.vpg->funcs->update_generic_info_packet(
358 /* SW should make sure VBID[6] update line number is bigger
359 * than PPS transmit line number
361 REG_UPDATE(DP_GSP11_CNTL,
362 DP_SEC_GSP11_LINE_NUM, 2);
363 REG_UPDATE_2(DP_MSA_VBID_MISC,
364 DP_VBID6_LINE_REFERENCE, 0,
365 DP_VBID6_LINE_NUM, 3);
367 /* Send PPS data at the line number specified above.
368 * DP spec requires PPS to be sent only when it changes, however since
369 * decoder has to be able to handle its change on every frame, we're
370 * sending it always (i.e. on every frame) to reduce the chance it'd be
371 * missed by decoder. If it turns out required to send PPS only when it
372 * changes, we can use DP_SEC_GSP11_SEND register.
374 REG_UPDATE(DP_GSP11_CNTL,
375 DP_SEC_GSP11_ENABLE, 1);
376 REG_UPDATE(DP_SEC_CNTL,
377 DP_SEC_STREAM_ENABLE, 1);
379 /* Disable Generic Stream Packet 11 (GSP) transmission */
380 REG_UPDATE(DP_GSP11_CNTL, DP_SEC_GSP11_ENABLE, 0);
381 REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP11_PPS, 0);
386 /* this function read dsc related register fields to be logged later in dcn10_log_hw_state
387 * into a dcn_dsc_state struct.
389 static void enc3_read_state(struct stream_encoder *enc, struct enc_state *s)
391 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
393 //if dsc is enabled, continue to read
394 REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode);
396 REG_GET(DP_DSC_CNTL, DP_DSC_SLICE_WIDTH, &s->dsc_slice_width);
397 REG_GET(DP_GSP11_CNTL, DP_SEC_GSP11_LINE_NUM, &s->sec_gsp_pps_line_num);
399 REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_REFERENCE, &s->vbid6_line_reference);
400 REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_NUM, &s->vbid6_line_num);
402 REG_GET(DP_GSP11_CNTL, DP_SEC_GSP11_ENABLE, &s->sec_gsp_pps_enable);
403 REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable);
407 static void enc3_stream_encoder_update_dp_info_packets(
408 struct stream_encoder *enc,
409 const struct encoder_info_frame *info_frame)
411 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
413 uint32_t dmdata_packet_enabled = 0;
415 if (info_frame->vsc.valid) {
416 enc->vpg->funcs->update_generic_info_packet(
422 if (info_frame->spd.valid) {
423 enc->vpg->funcs->update_generic_info_packet(
429 if (info_frame->hdrsmd.valid) {
430 enc->vpg->funcs->update_generic_info_packet(
436 /* packetIndex 4 is used for send immediate sdp message, and please
437 * use other packetIndex (such as 5,6) for other info packet
440 /* enable/disable transmission of packet(s).
441 * If enabled, packet transmission begins on the next frame
443 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid);
444 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid);
445 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid);
447 /* This bit is the master enable bit.
448 * When enabling secondary stream engine,
449 * this master bit must also be set.
450 * This register shared with audio info frame.
451 * Therefore we need to enable master bit
452 * if at least on of the fields is not 0
454 value = REG_READ(DP_SEC_CNTL);
456 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
458 /* check if dynamic metadata packet transmission is enabled */
459 REG_GET(DP_SEC_METADATA_TRANSMISSION,
460 DP_SEC_METADATA_PACKET_ENABLE, &dmdata_packet_enabled);
462 if (dmdata_packet_enabled)
463 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
466 static void enc3_dp_set_odm_combine(
467 struct stream_encoder *enc,
470 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
472 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_COMBINE, odm_combine);
475 /* setup stream encoder in dvi mode */
476 static void enc3_stream_encoder_dvi_set_stream_attribute(
477 struct stream_encoder *enc,
478 struct dc_crtc_timing *crtc_timing,
481 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
483 if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {
484 struct bp_encoder_control cntl = {0};
486 cntl.action = ENCODER_CONTROL_SETUP;
487 cntl.engine_id = enc1->base.id;
488 cntl.signal = is_dual_link ?
489 SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK;
490 cntl.enable_dp_audio = false;
491 cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10;
492 cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
494 if (enc1->base.bp->funcs->encoder_control(
495 enc1->base.bp, &cntl) != BP_RESULT_OK)
500 //Set pattern for clock channel, default vlue 0x63 does not work
501 REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F);
503 //DIG_BE_TMDS_DVI_MODE : TMDS-DVI mode is already set in link_encoder_setup
505 //DIG_SOURCE_SELECT is already set in dig_connect_to_otg
507 /* set DIG_START to 0x1 to reset FIFO */
508 REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);
511 /* write 0 to take the FIFO out of reset */
512 REG_UPDATE(DIG_FE_CNTL, DIG_START, 0);
516 ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB);
517 ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888);
518 enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing);
521 /* setup stream encoder in hdmi mode */
522 static void enc3_stream_encoder_hdmi_set_stream_attribute(
523 struct stream_encoder *enc,
524 struct dc_crtc_timing *crtc_timing,
525 int actual_pix_clk_khz,
528 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
530 if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {
531 struct bp_encoder_control cntl = {0};
533 cntl.action = ENCODER_CONTROL_SETUP;
534 cntl.engine_id = enc1->base.id;
535 cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
536 cntl.enable_dp_audio = enable_audio;
537 cntl.pixel_clock = actual_pix_clk_khz;
538 cntl.lanes_number = LANE_COUNT_FOUR;
540 if (enc1->base.bp->funcs->encoder_control(
541 enc1->base.bp, &cntl) != BP_RESULT_OK)
546 //Set pattern for clock channel, default vlue 0x63 does not work
547 REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F);
549 //DIG_BE_TMDS_HDMI_MODE : TMDS-HDMI mode is already set in link_encoder_setup
551 //DIG_SOURCE_SELECT is already set in dig_connect_to_otg
553 /* set DIG_START to 0x1 to reset FIFO */
554 REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);
557 /* write 0 to take the FIFO out of reset */
558 REG_UPDATE(DIG_FE_CNTL, DIG_START, 0);
562 /* Configure pixel encoding */
563 enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing);
565 /* setup HDMI engine */
566 REG_UPDATE_6(HDMI_CONTROL,
567 HDMI_PACKET_GEN_VERSION, 1,
568 HDMI_KEEPOUT_MODE, 1,
569 HDMI_DEEP_COLOR_ENABLE, 0,
570 HDMI_DATA_SCRAMBLE_EN, 0,
571 HDMI_NO_EXTRA_NULL_PACKET_FILLED, 1,
572 HDMI_CLOCK_CHANNEL_RATE, 0);
574 /* Configure color depth */
575 switch (crtc_timing->display_color_depth) {
576 case COLOR_DEPTH_888:
577 REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
579 case COLOR_DEPTH_101010:
580 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
581 REG_UPDATE_2(HDMI_CONTROL,
582 HDMI_DEEP_COLOR_DEPTH, 1,
583 HDMI_DEEP_COLOR_ENABLE, 0);
585 REG_UPDATE_2(HDMI_CONTROL,
586 HDMI_DEEP_COLOR_DEPTH, 1,
587 HDMI_DEEP_COLOR_ENABLE, 1);
590 case COLOR_DEPTH_121212:
591 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
592 REG_UPDATE_2(HDMI_CONTROL,
593 HDMI_DEEP_COLOR_DEPTH, 2,
594 HDMI_DEEP_COLOR_ENABLE, 0);
596 REG_UPDATE_2(HDMI_CONTROL,
597 HDMI_DEEP_COLOR_DEPTH, 2,
598 HDMI_DEEP_COLOR_ENABLE, 1);
601 case COLOR_DEPTH_161616:
602 REG_UPDATE_2(HDMI_CONTROL,
603 HDMI_DEEP_COLOR_DEPTH, 3,
604 HDMI_DEEP_COLOR_ENABLE, 1);
610 if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) {
611 /* enable HDMI data scrambler
612 * HDMI_CLOCK_CHANNEL_RATE_MORE_340M
613 * Clock channel frequency is 1/4 of character rate.
615 REG_UPDATE_2(HDMI_CONTROL,
616 HDMI_DATA_SCRAMBLE_EN, 1,
617 HDMI_CLOCK_CHANNEL_RATE, 1);
618 } else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) {
620 /* TODO: New feature for DCE11, still need to implement */
622 /* enable HDMI data scrambler
623 * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE
624 * Clock channel frequency is the same
627 REG_UPDATE_2(HDMI_CONTROL,
628 HDMI_DATA_SCRAMBLE_EN, 1,
629 HDMI_CLOCK_CHANNEL_RATE, 0);
633 /* Enable transmission of General Control packet on every frame */
634 REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL,
639 /* following belongs to audio */
640 /* Enable Audio InfoFrame packet transmission. */
641 REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
643 /* update double-buffered AUDIO_INFO registers immediately */
645 enc->afmt->funcs->audio_info_immediate_update(enc->afmt);
647 /* Select line number on which to send Audio InfoFrame packets */
648 REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,
651 /* set HDMI GC AVMUTE */
652 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);
655 static void enc3_audio_mute_control(
656 struct stream_encoder *enc,
660 enc->afmt->funcs->audio_mute_control(enc->afmt, mute);
663 static void enc3_se_dp_audio_setup(
664 struct stream_encoder *enc,
665 unsigned int az_inst,
666 struct audio_info *info)
669 enc->afmt->funcs->se_audio_setup(enc->afmt, az_inst, info);
672 #define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000
673 #define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1
675 static void enc3_se_setup_dp_audio(
676 struct stream_encoder *enc)
678 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
680 /* --- DP Audio packet configurations --- */
682 /* ATP Configuration */
683 REG_SET(DP_SEC_AUD_N, 0,
684 DP_SEC_AUD_N, DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT);
686 /* Async/auto-calc timestamp mode */
687 REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE,
688 DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC);
691 enc->afmt->funcs->setup_dp_audio(enc->afmt);
694 static void enc3_se_dp_audio_enable(
695 struct stream_encoder *enc)
697 enc1_se_enable_audio_clock(enc, true);
698 enc3_se_setup_dp_audio(enc);
699 enc1_se_enable_dp_audio(enc);
702 static void enc3_se_setup_hdmi_audio(
703 struct stream_encoder *enc,
704 const struct audio_crtc_info *crtc_info)
706 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
708 struct audio_clock_info audio_clock_info = {0};
710 /* Setup audio in AFMT - program AFMT block associated with DIO */
712 enc->afmt->funcs->setup_hdmi_audio(enc->afmt);
714 /* HDMI_AUDIO_PACKET_CONTROL */
715 REG_UPDATE(HDMI_AUDIO_PACKET_CONTROL,
716 HDMI_AUDIO_DELAY_EN, 1);
718 /* HDMI_ACR_PACKET_CONTROL */
719 REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL,
720 HDMI_ACR_AUTO_SEND, 1,
722 HDMI_ACR_AUDIO_PRIORITY, 0);
724 /* Program audio clock sample/regeneration parameters */
725 get_audio_clock_info(crtc_info->color_depth,
726 crtc_info->requested_pixel_clock_100Hz,
727 crtc_info->calculated_pixel_clock_100Hz,
730 "\n%s:Input::requested_pixel_clock_100Hz = %d" \
731 "calculated_pixel_clock_100Hz = %d \n", __func__, \
732 crtc_info->requested_pixel_clock_100Hz, \
733 crtc_info->calculated_pixel_clock_100Hz);
735 /* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */
736 REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz);
738 /* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */
739 REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz);
741 /* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */
742 REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz);
744 /* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */
745 REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz);
747 /* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */
748 REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz);
750 /* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */
751 REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz);
753 /* Video driver cannot know in advance which sample rate will
754 * be used by HD Audio driver
755 * HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is
756 * programmed below in interruppt callback
760 static void enc3_se_hdmi_audio_setup(
761 struct stream_encoder *enc,
762 unsigned int az_inst,
763 struct audio_info *info,
764 struct audio_crtc_info *audio_crtc_info)
766 enc1_se_enable_audio_clock(enc, true);
767 enc3_se_setup_hdmi_audio(enc, audio_crtc_info);
769 enc->afmt->funcs->se_audio_setup(enc->afmt, az_inst, info);
773 static const struct stream_encoder_funcs dcn30_str_enc_funcs = {
774 .dp_set_odm_combine =
775 enc3_dp_set_odm_combine,
776 .dp_set_stream_attribute =
777 enc2_stream_encoder_dp_set_stream_attribute,
778 .hdmi_set_stream_attribute =
779 enc3_stream_encoder_hdmi_set_stream_attribute,
780 .dvi_set_stream_attribute =
781 enc3_stream_encoder_dvi_set_stream_attribute,
782 .set_throttled_vcp_size =
783 enc1_stream_encoder_set_throttled_vcp_size,
784 .update_hdmi_info_packets =
785 enc3_stream_encoder_update_hdmi_info_packets,
786 .stop_hdmi_info_packets =
787 enc3_stream_encoder_stop_hdmi_info_packets,
788 .update_dp_info_packets =
789 enc3_stream_encoder_update_dp_info_packets,
790 .stop_dp_info_packets =
791 enc1_stream_encoder_stop_dp_info_packets,
793 enc1_stream_encoder_dp_blank,
795 enc2_stream_encoder_dp_unblank,
796 .audio_mute_control = enc3_audio_mute_control,
798 .dp_audio_setup = enc3_se_dp_audio_setup,
799 .dp_audio_enable = enc3_se_dp_audio_enable,
800 .dp_audio_disable = enc1_se_dp_audio_disable,
802 .hdmi_audio_setup = enc3_se_hdmi_audio_setup,
803 .hdmi_audio_disable = enc1_se_hdmi_audio_disable,
804 .setup_stereo_sync = enc1_setup_stereo_sync,
805 .set_avmute = enc1_stream_encoder_set_avmute,
806 .dig_connect_to_otg = enc1_dig_connect_to_otg,
807 .dig_source_otg = enc1_dig_source_otg,
809 .dp_get_pixel_format = enc1_stream_encoder_dp_get_pixel_format,
811 .enc_read_state = enc3_read_state,
812 .dp_set_dsc_config = enc3_dp_set_dsc_config,
813 .dp_set_dsc_pps_info_packet = enc3_dp_set_dsc_pps_info_packet,
814 .set_dynamic_metadata = enc2_set_dynamic_metadata,
815 .hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute,
817 .get_fifo_cal_average_level = enc2_get_fifo_cal_average_level,
820 void dcn30_dio_stream_encoder_construct(
821 struct dcn10_stream_encoder *enc1,
822 struct dc_context *ctx,
824 enum engine_id eng_id,
827 const struct dcn10_stream_enc_registers *regs,
828 const struct dcn10_stream_encoder_shift *se_shift,
829 const struct dcn10_stream_encoder_mask *se_mask)
831 enc1->base.funcs = &dcn30_str_enc_funcs;
832 enc1->base.ctx = ctx;
833 enc1->base.id = eng_id;
835 enc1->base.vpg = vpg;
836 enc1->base.afmt = afmt;
838 enc1->se_shift = se_shift;
839 enc1->se_mask = se_mask;
840 enc1->base.stream_enc_inst = vpg->inst;