2 * Copyright 2018 Advanced Micro Devices, Inc.
3 * Copyright 2019 Raptor Engineering, LLC
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
27 #include <linux/slab.h>
29 #include "dm_services.h"
32 #include "dcn21_init.h"
35 #include "include/irq_service_interface.h"
36 #include "dcn20/dcn20_resource.h"
39 #include "dcn10/dcn10_hubp.h"
40 #include "dcn10/dcn10_ipp.h"
41 #include "dcn20/dcn20_hubbub.h"
42 #include "dcn20/dcn20_mpc.h"
43 #include "dcn20/dcn20_hubp.h"
44 #include "dcn21_hubp.h"
45 #include "irq/dcn21/irq_service_dcn21.h"
46 #include "dcn20/dcn20_dpp.h"
47 #include "dcn20/dcn20_optc.h"
48 #include "dcn21/dcn21_hwseq.h"
49 #include "dce110/dce110_hw_sequencer.h"
50 #include "dcn20/dcn20_opp.h"
51 #include "dcn20/dcn20_dsc.h"
52 #include "dcn21/dcn21_link_encoder.h"
53 #include "dcn20/dcn20_stream_encoder.h"
54 #include "dce/dce_clock_source.h"
55 #include "dce/dce_audio.h"
56 #include "dce/dce_hwseq.h"
57 #include "virtual/virtual_stream_encoder.h"
58 #include "dce110/dce110_resource.h"
59 #include "dml/display_mode_vba.h"
60 #include "dcn20/dcn20_dccg.h"
61 #include "dcn21_hubbub.h"
62 #include "dcn10/dcn10_resource.h"
63 #include "dce110/dce110_resource.h"
65 #include "dcn20/dcn20_dwb.h"
66 #include "dcn20/dcn20_mmhubbub.h"
67 #include "dpcs/dpcs_2_1_0_offset.h"
68 #include "dpcs/dpcs_2_1_0_sh_mask.h"
70 #include "renoir_ip_offset.h"
71 #include "dcn/dcn_2_1_0_offset.h"
72 #include "dcn/dcn_2_1_0_sh_mask.h"
74 #include "nbio/nbio_7_0_offset.h"
76 #include "mmhub/mmhub_2_0_0_offset.h"
77 #include "mmhub/mmhub_2_0_0_sh_mask.h"
79 #include "reg_helper.h"
80 #include "dce/dce_abm.h"
81 #include "dce/dce_dmcu.h"
82 #include "dce/dce_aux.h"
83 #include "dce/dce_i2c.h"
84 #include "dcn21_resource.h"
85 #include "vm_helper.h"
86 #include "dcn20/dcn20_vmid.h"
87 #include "dce/dmub_psr.h"
89 #define SOC_BOUNDING_BOX_VALID false
90 #define DC_LOGGER_INIT(logger)
93 struct _vcs_dpi_ip_params_st dcn2_1_ip = {
97 .gpuvm_max_page_table_levels = 1,
98 .hostvm_max_page_table_levels = 4,
99 .hostvm_cached_page_table_levels = 2,
101 .rob_buffer_size_kbytes = 168,
102 .det_buffer_size_kbytes = 164,
103 .dpte_buffer_size_in_pte_reqs_luma = 44,
104 .dpte_buffer_size_in_pte_reqs_chroma = 42,//todo
105 .dpp_output_buffer_pixels = 2560,
106 .opp_output_buffer_lines = 1,
107 .pixel_chunk_size_kbytes = 8,
109 .max_page_table_levels = 4,
110 .pte_chunk_size_kbytes = 2,
111 .meta_chunk_size_kbytes = 2,
112 .writeback_chunk_size_kbytes = 2,
113 .line_buffer_size_bits = 789504,
114 .is_line_buffer_bpp_fixed = 0,
115 .line_buffer_fixed_bpp = 0,
116 .dcc_supported = true,
117 .max_line_buffer_lines = 12,
118 .writeback_luma_buffer_size_kbytes = 12,
119 .writeback_chroma_buffer_size_kbytes = 8,
120 .writeback_chroma_line_buffer_width_pixels = 4,
121 .writeback_max_hscl_ratio = 1,
122 .writeback_max_vscl_ratio = 1,
123 .writeback_min_hscl_ratio = 1,
124 .writeback_min_vscl_ratio = 1,
125 .writeback_max_hscl_taps = 12,
126 .writeback_max_vscl_taps = 12,
127 .writeback_line_buffer_luma_buffer_size = 0,
128 .writeback_line_buffer_chroma_buffer_size = 14643,
129 .cursor_buffer_size = 8,
130 .cursor_chunk_size = 2,
134 .max_dchub_pscl_bw_pix_per_clk = 4,
135 .max_pscl_lb_bw_pix_per_clk = 2,
136 .max_lb_vscl_bw_pix_per_clk = 4,
137 .max_vscl_hscl_bw_pix_per_clk = 4,
144 .dispclk_ramp_margin_percent = 1,
145 .underscan_factor = 1.10,
146 .min_vblank_lines = 32, //
147 .dppclk_delay_subtotal = 77, //
148 .dppclk_delay_scl_lb_only = 16,
149 .dppclk_delay_scl = 50,
150 .dppclk_delay_cnvc_formatter = 8,
151 .dppclk_delay_cnvc_cursor = 6,
152 .dispclk_delay_subtotal = 87, //
153 .dcfclk_cstate_latency = 10, // SRExitTime
154 .max_inter_dcn_tile_repeaters = 8,
156 .xfc_supported = false,
157 .xfc_fill_bw_overhead_percent = 10.0,
158 .xfc_fill_constant_bytes = 0,
160 .number_of_cursors = 1,
163 struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = {
168 .fabricclk_mhz = 400.0,
169 .dispclk_mhz = 600.0,
170 .dppclk_mhz = 400.00,
173 .dscclk_mhz = 205.67,
174 .dram_speed_mts = 1600.0,
178 .dcfclk_mhz = 464.52,
179 .fabricclk_mhz = 800.0,
180 .dispclk_mhz = 654.55,
181 .dppclk_mhz = 626.09,
184 .dscclk_mhz = 205.67,
185 .dram_speed_mts = 1600.0,
189 .dcfclk_mhz = 514.29,
190 .fabricclk_mhz = 933.0,
191 .dispclk_mhz = 757.89,
192 .dppclk_mhz = 685.71,
195 .dscclk_mhz = 287.67,
196 .dram_speed_mts = 1866.0,
200 .dcfclk_mhz = 576.00,
201 .fabricclk_mhz = 1067.0,
202 .dispclk_mhz = 847.06,
203 .dppclk_mhz = 757.89,
206 .dscclk_mhz = 318.334,
207 .dram_speed_mts = 2134.0,
211 .dcfclk_mhz = 626.09,
212 .fabricclk_mhz = 1200.0,
213 .dispclk_mhz = 900.00,
214 .dppclk_mhz = 847.06,
218 .dram_speed_mts = 2400.0,
222 .dcfclk_mhz = 685.71,
223 .fabricclk_mhz = 1333.0,
224 .dispclk_mhz = 1028.57,
225 .dppclk_mhz = 960.00,
228 .dscclk_mhz = 287.67,
229 .dram_speed_mts = 2666.0,
233 .dcfclk_mhz = 757.89,
234 .fabricclk_mhz = 1467.0,
235 .dispclk_mhz = 1107.69,
236 .dppclk_mhz = 1028.57,
239 .dscclk_mhz = 318.334,
240 .dram_speed_mts = 3200.0,
244 .dcfclk_mhz = 847.06,
245 .fabricclk_mhz = 1600.0,
246 .dispclk_mhz = 1395.0,
247 .dppclk_mhz = 1285.00,
248 .phyclk_mhz = 1325.0,
251 .dram_speed_mts = 4266.0,
253 /*Extra state, no dispclk ramping*/
256 .dcfclk_mhz = 847.06,
257 .fabricclk_mhz = 1600.0,
258 .dispclk_mhz = 1395.0,
259 .dppclk_mhz = 1285.0,
260 .phyclk_mhz = 1325.0,
263 .dram_speed_mts = 4266.0,
268 .sr_exit_time_us = 12.5,
269 .sr_enter_plus_exit_time_us = 17.0,
270 .urgent_latency_us = 4.0,
271 .urgent_latency_pixel_data_only_us = 4.0,
272 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
273 .urgent_latency_vm_data_only_us = 4.0,
274 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
275 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
276 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
277 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0,
278 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 75.0,
279 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
280 .max_avg_sdp_bw_use_normal_percent = 60.0,
281 .max_avg_dram_bw_use_normal_percent = 100.0,
282 .writeback_latency_us = 12.0,
283 .max_request_size_bytes = 256,
284 .dram_channel_width_bytes = 4,
285 .fabric_datapath_to_dcn_data_return_bytes = 32,
286 .dcn_downspread_percent = 0.5,
287 .downspread_percent = 0.5,
288 .dram_page_open_time_ns = 50.0,
289 .dram_rw_turnaround_time_ns = 17.5,
290 .dram_return_buffer_per_channel_bytes = 8192,
291 .round_trip_ping_latency_dcfclk_cycles = 128,
292 .urgent_out_of_order_return_per_channel_bytes = 4096,
293 .channel_interleave_bytes = 256,
296 .vmm_page_size_bytes = 4096,
297 .dram_clock_change_latency_us = 23.84,
298 .return_bus_width_bytes = 64,
299 .dispclk_dppclk_vco_speed_mhz = 3600,
300 .xfc_bus_transport_time_us = 4,
301 .xfc_xbuf_latency_tolerance_us = 4,
302 .use_urgent_burst_bw = 1,
307 #define MAX(X, Y) ((X) > (Y) ? (X) : (Y))
310 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
313 /* begin *********************
314 * macros to expend register list macro defined in HW object header file */
317 /* TODO awful hack. fixup dcn20_dwb.h */
319 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
321 #define BASE(seg) BASE_INNER(seg)
323 #define SR(reg_name)\
324 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
327 #define SRI(reg_name, block, id)\
328 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
329 mm ## block ## id ## _ ## reg_name
331 #define SRIR(var_name, reg_name, block, id)\
332 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
333 mm ## block ## id ## _ ## reg_name
335 #define SRII(reg_name, block, id)\
336 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
337 mm ## block ## id ## _ ## reg_name
339 #define DCCG_SRII(reg_name, block, id)\
340 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
341 mm ## block ## id ## _ ## reg_name
344 #define NBIO_BASE_INNER(seg) \
345 NBIF0_BASE__INST0_SEG ## seg
347 #define NBIO_BASE(seg) \
350 #define NBIO_SR(reg_name)\
351 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
355 #define MMHUB_BASE_INNER(seg) \
356 MMHUB_BASE__INST0_SEG ## seg
358 #define MMHUB_BASE(seg) \
359 MMHUB_BASE_INNER(seg)
361 #define MMHUB_SR(reg_name)\
362 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
365 #define clk_src_regs(index, pllid)\
367 CS_COMMON_REG_LIST_DCN2_1(index, pllid),\
370 static const struct dce110_clk_src_regs clk_src_regs[] = {
378 static const struct dce110_clk_src_shift cs_shift = {
379 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
382 static const struct dce110_clk_src_mask cs_mask = {
383 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
386 static const struct bios_registers bios_regs = {
387 NBIO_SR(BIOS_SCRATCH_3),
388 NBIO_SR(BIOS_SCRATCH_6)
391 static const struct dce_dmcu_registers dmcu_regs = {
392 DMCU_DCN20_REG_LIST()
395 static const struct dce_dmcu_shift dmcu_shift = {
396 DMCU_MASK_SH_LIST_DCN10(__SHIFT)
399 static const struct dce_dmcu_mask dmcu_mask = {
400 DMCU_MASK_SH_LIST_DCN10(_MASK)
403 static const struct dce_abm_registers abm_regs = {
407 static const struct dce_abm_shift abm_shift = {
408 ABM_MASK_SH_LIST_DCN20(__SHIFT)
411 static const struct dce_abm_mask abm_mask = {
412 ABM_MASK_SH_LIST_DCN20(_MASK)
415 #define audio_regs(id)\
417 AUD_COMMON_REG_LIST(id)\
420 static const struct dce_audio_registers audio_regs[] = {
429 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
430 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
431 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
432 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
434 static const struct dce_audio_shift audio_shift = {
435 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
438 static const struct dce_audio_mask audio_mask = {
439 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
442 static const struct dccg_registers dccg_regs = {
443 DCCG_COMMON_REG_LIST_DCN_BASE()
446 static const struct dccg_shift dccg_shift = {
447 DCCG_MASK_SH_LIST_DCN2(__SHIFT)
450 static const struct dccg_mask dccg_mask = {
451 DCCG_MASK_SH_LIST_DCN2(_MASK)
454 #define opp_regs(id)\
456 OPP_REG_LIST_DCN20(id),\
459 static const struct dcn20_opp_registers opp_regs[] = {
468 static const struct dcn20_opp_shift opp_shift = {
469 OPP_MASK_SH_LIST_DCN20(__SHIFT)
472 static const struct dcn20_opp_mask opp_mask = {
473 OPP_MASK_SH_LIST_DCN20(_MASK)
477 [id] = {TG_COMMON_REG_LIST_DCN2_0(id)}
479 static const struct dcn_optc_registers tg_regs[] = {
486 static const struct dcn_optc_shift tg_shift = {
487 TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
490 static const struct dcn_optc_mask tg_mask = {
491 TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
494 static const struct dcn20_mpc_registers mpc_regs = {
495 MPC_REG_LIST_DCN2_0(0),
496 MPC_REG_LIST_DCN2_0(1),
497 MPC_REG_LIST_DCN2_0(2),
498 MPC_REG_LIST_DCN2_0(3),
499 MPC_REG_LIST_DCN2_0(4),
500 MPC_REG_LIST_DCN2_0(5),
501 MPC_OUT_MUX_REG_LIST_DCN2_0(0),
502 MPC_OUT_MUX_REG_LIST_DCN2_0(1),
503 MPC_OUT_MUX_REG_LIST_DCN2_0(2),
504 MPC_OUT_MUX_REG_LIST_DCN2_0(3),
505 MPC_DBG_REG_LIST_DCN2_0()
508 static const struct dcn20_mpc_shift mpc_shift = {
509 MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT),
510 MPC_DEBUG_REG_LIST_SH_DCN20
513 static const struct dcn20_mpc_mask mpc_mask = {
514 MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK),
515 MPC_DEBUG_REG_LIST_MASK_DCN20
518 #define hubp_regs(id)\
520 HUBP_REG_LIST_DCN21(id)\
523 static const struct dcn_hubp2_registers hubp_regs[] = {
530 static const struct dcn_hubp2_shift hubp_shift = {
531 HUBP_MASK_SH_LIST_DCN21(__SHIFT)
534 static const struct dcn_hubp2_mask hubp_mask = {
535 HUBP_MASK_SH_LIST_DCN21(_MASK)
538 static const struct dcn_hubbub_registers hubbub_reg = {
539 HUBBUB_REG_LIST_DCN21()
542 static const struct dcn_hubbub_shift hubbub_shift = {
543 HUBBUB_MASK_SH_LIST_DCN21(__SHIFT)
546 static const struct dcn_hubbub_mask hubbub_mask = {
547 HUBBUB_MASK_SH_LIST_DCN21(_MASK)
551 #define vmid_regs(id)\
553 DCN20_VMID_REG_LIST(id)\
556 static const struct dcn_vmid_registers vmid_regs[] = {
575 static const struct dcn20_vmid_shift vmid_shifts = {
576 DCN20_VMID_MASK_SH_LIST(__SHIFT)
579 static const struct dcn20_vmid_mask vmid_masks = {
580 DCN20_VMID_MASK_SH_LIST(_MASK)
583 #define dsc_regsDCN20(id)\
585 DSC_REG_LIST_DCN20(id)\
588 static const struct dcn20_dsc_registers dsc_regs[] = {
597 static const struct dcn20_dsc_shift dsc_shift = {
598 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
601 static const struct dcn20_dsc_mask dsc_mask = {
602 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
605 #define ipp_regs(id)\
607 IPP_REG_LIST_DCN20(id),\
610 static const struct dcn10_ipp_registers ipp_regs[] = {
617 static const struct dcn10_ipp_shift ipp_shift = {
618 IPP_MASK_SH_LIST_DCN20(__SHIFT)
621 static const struct dcn10_ipp_mask ipp_mask = {
622 IPP_MASK_SH_LIST_DCN20(_MASK),
625 #define opp_regs(id)\
627 OPP_REG_LIST_DCN20(id),\
631 #define aux_engine_regs(id)\
633 AUX_COMMON_REG_LIST0(id), \
636 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
639 static const struct dce110_aux_registers aux_engine_regs[] = {
649 TF_REG_LIST_DCN20(id),\
650 TF_REG_LIST_DCN20_COMMON_APPEND(id),\
653 static const struct dcn2_dpp_registers tf_regs[] = {
660 static const struct dcn2_dpp_shift tf_shift = {
661 TF_REG_LIST_SH_MASK_DCN20(__SHIFT),
662 TF_DEBUG_REG_LIST_SH_DCN20
665 static const struct dcn2_dpp_mask tf_mask = {
666 TF_REG_LIST_SH_MASK_DCN20(_MASK),
667 TF_DEBUG_REG_LIST_MASK_DCN20
670 #define stream_enc_regs(id)\
672 SE_DCN2_REG_LIST(id)\
675 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
683 static const struct dce110_aux_registers_shift aux_shift = {
684 DCN_AUX_MASK_SH_LIST(__SHIFT)
687 static const struct dce110_aux_registers_mask aux_mask = {
688 DCN_AUX_MASK_SH_LIST(_MASK)
691 static const struct dcn10_stream_encoder_shift se_shift = {
692 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)
695 static const struct dcn10_stream_encoder_mask se_mask = {
696 SE_COMMON_MASK_SH_LIST_DCN20(_MASK)
699 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
701 static int dcn21_populate_dml_pipes_from_context(
702 struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes);
704 static struct input_pixel_processor *dcn21_ipp_create(
705 struct dc_context *ctx, uint32_t inst)
707 struct dcn10_ipp *ipp =
708 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);
715 dcn20_ipp_construct(ipp, ctx, inst,
716 &ipp_regs[inst], &ipp_shift, &ipp_mask);
720 static struct dpp *dcn21_dpp_create(
721 struct dc_context *ctx,
724 struct dcn20_dpp *dpp =
725 kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL);
730 if (dpp2_construct(dpp, ctx, inst,
731 &tf_regs[inst], &tf_shift, &tf_mask))
739 static struct dce_aux *dcn21_aux_engine_create(
740 struct dc_context *ctx,
743 struct aux_engine_dce110 *aux_engine =
744 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
749 dce110_aux_engine_construct(aux_engine, ctx, inst,
750 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
751 &aux_engine_regs[inst],
754 ctx->dc->caps.extended_aux_timeout_support);
756 return &aux_engine->base;
759 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
761 static const struct dce_i2c_registers i2c_hw_regs[] = {
769 static const struct dce_i2c_shift i2c_shifts = {
770 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
773 static const struct dce_i2c_mask i2c_masks = {
774 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
777 struct dce_i2c_hw *dcn21_i2c_hw_create(
778 struct dc_context *ctx,
781 struct dce_i2c_hw *dce_i2c_hw =
782 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
787 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
788 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
793 static const struct resource_caps res_cap_rn = {
794 .num_timing_generator = 4,
796 .num_video_plane = 4,
797 .num_audio = 4, // 4 audio endpoints. 4 audio streams
798 .num_stream_encoder = 5,
799 .num_pll = 5, // maybe 3 because the last two used for USB-c
807 static const struct resource_caps res_cap_rn_FPGA_4pipe = {
808 .num_timing_generator = 4,
810 .num_video_plane = 4,
812 .num_stream_encoder = 4,
819 static const struct resource_caps res_cap_rn_FPGA_2pipe_dsc = {
820 .num_timing_generator = 2,
822 .num_video_plane = 2,
824 .num_stream_encoder = 2,
832 static const struct dc_plane_cap plane_cap = {
833 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
834 .blends_with_above = true,
835 .blends_with_below = true,
836 .per_pixel_alpha = true,
838 .pixel_format_support = {
845 .max_upscale_factor = {
851 .max_downscale_factor = {
858 static const struct dc_debug_options debug_defaults_drv = {
859 .disable_dmcu = false,
860 .force_abm_enable = false,
861 .timing_trace = false,
863 .disable_pplib_clock_request = true,
864 .min_disp_clk_khz = 100000,
865 .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
866 .force_single_disp_pipe_split = false,
867 .disable_dcc = DCC_ENABLE,
869 .performance_trace = false,
870 .max_downscale_src_width = 4096,
871 .disable_pplib_wm_range = false,
872 .scl_reset_length10 = true,
873 .sanity_checks = true,
874 .disable_48mhz_pwrdwn = false,
875 .nv12_iflip_vm_wa = true,
876 .usbc_combo_phy_reset_wa = true
879 static const struct dc_debug_options debug_defaults_diags = {
880 .disable_dmcu = false,
881 .force_abm_enable = false,
882 .timing_trace = true,
884 .disable_dpp_power_gate = true,
885 .disable_hubp_power_gate = true,
886 .disable_clock_gate = true,
887 .disable_pplib_clock_request = true,
888 .disable_pplib_wm_range = true,
889 .disable_stutter = true,
890 .disable_48mhz_pwrdwn = true,
893 enum dcn20_clk_src_array_id {
897 DCN20_CLK_SRC_TOTAL_DCN21
900 static void dcn21_resource_destruct(struct dcn21_resource_pool *pool)
904 for (i = 0; i < pool->base.stream_enc_count; i++) {
905 if (pool->base.stream_enc[i] != NULL) {
906 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
907 pool->base.stream_enc[i] = NULL;
911 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
912 if (pool->base.dscs[i] != NULL)
913 dcn20_dsc_destroy(&pool->base.dscs[i]);
916 if (pool->base.mpc != NULL) {
917 kfree(TO_DCN20_MPC(pool->base.mpc));
918 pool->base.mpc = NULL;
920 if (pool->base.hubbub != NULL) {
921 kfree(pool->base.hubbub);
922 pool->base.hubbub = NULL;
924 for (i = 0; i < pool->base.pipe_count; i++) {
925 if (pool->base.dpps[i] != NULL)
926 dcn20_dpp_destroy(&pool->base.dpps[i]);
928 if (pool->base.ipps[i] != NULL)
929 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
931 if (pool->base.hubps[i] != NULL) {
932 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
933 pool->base.hubps[i] = NULL;
936 if (pool->base.irqs != NULL) {
937 dal_irq_service_destroy(&pool->base.irqs);
941 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
942 if (pool->base.engines[i] != NULL)
943 dce110_engine_destroy(&pool->base.engines[i]);
944 if (pool->base.hw_i2cs[i] != NULL) {
945 kfree(pool->base.hw_i2cs[i]);
946 pool->base.hw_i2cs[i] = NULL;
948 if (pool->base.sw_i2cs[i] != NULL) {
949 kfree(pool->base.sw_i2cs[i]);
950 pool->base.sw_i2cs[i] = NULL;
954 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
955 if (pool->base.opps[i] != NULL)
956 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
959 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
960 if (pool->base.timing_generators[i] != NULL) {
961 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
962 pool->base.timing_generators[i] = NULL;
966 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
967 if (pool->base.dwbc[i] != NULL) {
968 kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
969 pool->base.dwbc[i] = NULL;
971 if (pool->base.mcif_wb[i] != NULL) {
972 kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));
973 pool->base.mcif_wb[i] = NULL;
977 for (i = 0; i < pool->base.audio_count; i++) {
978 if (pool->base.audios[i])
979 dce_aud_destroy(&pool->base.audios[i]);
982 for (i = 0; i < pool->base.clk_src_count; i++) {
983 if (pool->base.clock_sources[i] != NULL) {
984 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
985 pool->base.clock_sources[i] = NULL;
989 if (pool->base.dp_clock_source != NULL) {
990 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
991 pool->base.dp_clock_source = NULL;
995 if (pool->base.abm != NULL)
996 dce_abm_destroy(&pool->base.abm);
998 if (pool->base.dmcu != NULL)
999 dce_dmcu_destroy(&pool->base.dmcu);
1001 if (pool->base.psr != NULL)
1002 dmub_psr_destroy(&pool->base.psr);
1004 if (pool->base.dccg != NULL)
1005 dcn_dccg_destroy(&pool->base.dccg);
1007 if (pool->base.pp_smu != NULL)
1008 dcn21_pp_smu_destroy(&pool->base.pp_smu);
1012 static void calculate_wm_set_for_vlevel(
1014 struct wm_range_table_entry *table_entry,
1015 struct dcn_watermarks *wm_set,
1016 struct display_mode_lib *dml,
1017 display_e2e_pipe_params_st *pipes,
1020 double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us;
1022 ASSERT(vlevel < dml->soc.num_states);
1023 /* only pipe 0 is read for voltage and dcf/soc clocks */
1024 pipes[0].clks_cfg.voltage = vlevel;
1025 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz;
1026 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz;
1028 dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us;
1029 dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us;
1030 dml->soc.sr_enter_plus_exit_time_us = table_entry->sr_enter_plus_exit_time_us;
1032 wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000;
1033 wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000;
1034 wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000;
1035 wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000;
1036 wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000;
1037 wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000;
1038 wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000;
1039 wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) * 1000;
1040 dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached;
1044 static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
1050 if (dc->bb_overrides.sr_exit_time_ns) {
1051 for (i = 0; i < WM_SET_COUNT; i++) {
1052 dc->clk_mgr->bw_params->wm_table.entries[i].sr_exit_time_us =
1053 dc->bb_overrides.sr_exit_time_ns / 1000.0;
1057 if (dc->bb_overrides.sr_enter_plus_exit_time_ns) {
1058 for (i = 0; i < WM_SET_COUNT; i++) {
1059 dc->clk_mgr->bw_params->wm_table.entries[i].sr_enter_plus_exit_time_us =
1060 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
1064 if (dc->bb_overrides.urgent_latency_ns) {
1065 bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
1068 if (dc->bb_overrides.dram_clock_change_latency_ns) {
1069 for (i = 0; i < WM_SET_COUNT; i++) {
1070 dc->clk_mgr->bw_params->wm_table.entries[i].pstate_latency_us =
1071 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
1078 void dcn21_calculate_wm(
1079 struct dc *dc, struct dc_state *context,
1080 display_e2e_pipe_params_st *pipes,
1082 int *pipe_split_from,
1085 int pipe_cnt, i, pipe_idx;
1086 int vlevel, vlevel_max;
1087 struct wm_range_table_entry *table_entry;
1088 struct clk_bw_params *bw_params = dc->clk_mgr->bw_params;
1092 patch_bounding_box(dc, &context->bw_ctx.dml.soc);
1094 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1095 if (!context->res_ctx.pipe_ctx[i].stream)
1098 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
1099 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb];
1101 if (pipe_split_from[i] < 0) {
1102 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
1103 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
1104 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
1105 pipes[pipe_cnt].pipe.dest.odm_combine =
1106 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_idx];
1108 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
1111 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
1112 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
1113 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])
1114 pipes[pipe_cnt].pipe.dest.odm_combine =
1115 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_split_from[i]];
1117 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
1122 if (pipe_cnt != pipe_idx) {
1123 if (dc->res_pool->funcs->populate_dml_pipes)
1124 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
1127 pipe_cnt = dcn21_populate_dml_pipes_from_context(dc,
1131 *out_pipe_cnt = pipe_cnt;
1133 vlevel_max = bw_params->clk_table.num_entries - 1;
1137 table_entry = &bw_params->wm_table.entries[WM_D];
1138 if (table_entry->wm_type == WM_TYPE_RETRAINING)
1141 vlevel = vlevel_max;
1142 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d,
1143 &context->bw_ctx.dml, pipes, pipe_cnt);
1145 table_entry = &bw_params->wm_table.entries[WM_C];
1146 vlevel = MIN(MAX(vlevel_req, 2), vlevel_max);
1147 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c,
1148 &context->bw_ctx.dml, pipes, pipe_cnt);
1150 table_entry = &bw_params->wm_table.entries[WM_B];
1151 vlevel = MIN(MAX(vlevel_req, 1), vlevel_max);
1152 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b,
1153 &context->bw_ctx.dml, pipes, pipe_cnt);
1156 table_entry = &bw_params->wm_table.entries[WM_A];
1157 vlevel = MIN(vlevel_req, vlevel_max);
1158 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a,
1159 &context->bw_ctx.dml, pipes, pipe_cnt);
1163 bool dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context,
1168 BW_VAL_TRACE_SETUP();
1171 int pipe_split_from[MAX_PIPES];
1173 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
1174 DC_LOGGER_INIT(dc->ctx->logger);
1176 BW_VAL_TRACE_COUNT();
1178 out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel);
1186 BW_VAL_TRACE_END_VOLTAGE_LEVEL();
1188 if (fast_validate) {
1189 BW_VAL_TRACE_SKIP(fast);
1193 dcn21_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel);
1194 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
1196 BW_VAL_TRACE_END_WATERMARKS();
1201 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
1202 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
1204 BW_VAL_TRACE_SKIP(fail);
1210 BW_VAL_TRACE_FINISH();
1214 static void dcn21_destroy_resource_pool(struct resource_pool **pool)
1216 struct dcn21_resource_pool *dcn21_pool = TO_DCN21_RES_POOL(*pool);
1218 dcn21_resource_destruct(dcn21_pool);
1223 static struct clock_source *dcn21_clock_source_create(
1224 struct dc_context *ctx,
1225 struct dc_bios *bios,
1226 enum clock_source_id id,
1227 const struct dce110_clk_src_regs *regs,
1230 struct dce110_clk_src *clk_src =
1231 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1236 if (dcn20_clk_src_construct(clk_src, ctx, bios, id,
1237 regs, &cs_shift, &cs_mask)) {
1238 clk_src->base.dp_clk_src = dp_clk_src;
1239 return &clk_src->base;
1242 BREAK_TO_DEBUGGER();
1246 static struct hubp *dcn21_hubp_create(
1247 struct dc_context *ctx,
1250 struct dcn21_hubp *hubp21 =
1251 kzalloc(sizeof(struct dcn21_hubp), GFP_KERNEL);
1256 if (hubp21_construct(hubp21, ctx, inst,
1257 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1258 return &hubp21->base;
1260 BREAK_TO_DEBUGGER();
1265 static struct hubbub *dcn21_hubbub_create(struct dc_context *ctx)
1269 struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub),
1275 hubbub21_construct(hubbub, ctx,
1280 for (i = 0; i < res_cap_rn.num_vmid; i++) {
1281 struct dcn20_vmid *vmid = &hubbub->vmid[i];
1285 vmid->regs = &vmid_regs[i];
1286 vmid->shifts = &vmid_shifts;
1287 vmid->masks = &vmid_masks;
1290 return &hubbub->base;
1293 struct output_pixel_processor *dcn21_opp_create(
1294 struct dc_context *ctx, uint32_t inst)
1296 struct dcn20_opp *opp =
1297 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
1300 BREAK_TO_DEBUGGER();
1304 dcn20_opp_construct(opp, ctx, inst,
1305 &opp_regs[inst], &opp_shift, &opp_mask);
1309 struct timing_generator *dcn21_timing_generator_create(
1310 struct dc_context *ctx,
1313 struct optc *tgn10 =
1314 kzalloc(sizeof(struct optc), GFP_KERNEL);
1319 tgn10->base.inst = instance;
1320 tgn10->base.ctx = ctx;
1322 tgn10->tg_regs = &tg_regs[instance];
1323 tgn10->tg_shift = &tg_shift;
1324 tgn10->tg_mask = &tg_mask;
1326 dcn20_timing_generator_init(tgn10);
1328 return &tgn10->base;
1331 struct mpc *dcn21_mpc_create(struct dc_context *ctx)
1333 struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc),
1339 dcn20_mpc_construct(mpc20, ctx,
1345 return &mpc20->base;
1348 static void read_dce_straps(
1349 struct dc_context *ctx,
1350 struct resource_straps *straps)
1352 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
1353 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1358 struct display_stream_compressor *dcn21_dsc_create(
1359 struct dc_context *ctx, uint32_t inst)
1361 struct dcn20_dsc *dsc =
1362 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1365 BREAK_TO_DEBUGGER();
1369 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1373 static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1375 struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool);
1376 struct clk_limit_table *clk_table = &bw_params->clk_table;
1377 unsigned int i, j, k;
1378 int closest_clk_lvl;
1380 // Default clock levels are used for diags, which may lead to overclocking.
1381 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) && !IS_DIAG_DC(dc->ctx->dce_environment)) {
1382 dcn2_1_ip.max_num_otg = pool->base.res_cap->num_timing_generator;
1383 dcn2_1_ip.max_num_dpp = pool->base.pipe_count;
1384 dcn2_1_soc.num_chans = bw_params->num_channels;
1386 /* Vmin: leave lowest DCN clocks, override with dcfclk, fclk, memclk from fuse */
1387 dcn2_1_soc.clock_limits[0].state = 0;
1388 dcn2_1_soc.clock_limits[0].dcfclk_mhz = clk_table->entries[0].dcfclk_mhz;
1389 dcn2_1_soc.clock_limits[0].fabricclk_mhz = clk_table->entries[0].fclk_mhz;
1390 dcn2_1_soc.clock_limits[0].socclk_mhz = clk_table->entries[0].socclk_mhz;
1391 dcn2_1_soc.clock_limits[0].dram_speed_mts = clk_table->entries[0].memclk_mhz * 2;
1394 * Other levels: find closest DCN clocks that fit the given clock limit using dcfclk
1398 closest_clk_lvl = -1;
1399 /* index currently being filled */
1401 for (i = 1; i < clk_table->num_entries; i++) {
1402 /* loop backwards, skip duplicate state*/
1403 for (j = dcn2_1_soc.num_states - 1; j >= k; j--) {
1404 if ((unsigned int) dcn2_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) {
1405 closest_clk_lvl = j;
1410 /* if found a lvl that fits, use the DCN clks from it, if not, go to next clk limit*/
1411 if (closest_clk_lvl != -1) {
1412 dcn2_1_soc.clock_limits[k].state = i;
1413 dcn2_1_soc.clock_limits[k].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
1414 dcn2_1_soc.clock_limits[k].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
1415 dcn2_1_soc.clock_limits[k].socclk_mhz = clk_table->entries[i].socclk_mhz;
1416 dcn2_1_soc.clock_limits[k].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;
1418 dcn2_1_soc.clock_limits[k].dispclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
1419 dcn2_1_soc.clock_limits[k].dppclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
1420 dcn2_1_soc.clock_limits[k].dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
1421 dcn2_1_soc.clock_limits[k].dscclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
1422 dcn2_1_soc.clock_limits[k].dtbclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
1423 dcn2_1_soc.clock_limits[k].phyclk_d18_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
1424 dcn2_1_soc.clock_limits[k].phyclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
1428 dcn2_1_soc.num_states = k;
1431 /* duplicate last level */
1432 dcn2_1_soc.clock_limits[dcn2_1_soc.num_states] = dcn2_1_soc.clock_limits[dcn2_1_soc.num_states - 1];
1433 dcn2_1_soc.clock_limits[dcn2_1_soc.num_states].state = dcn2_1_soc.num_states;
1435 dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);
1438 /* Temporary Place holder until we can get them from fuse */
1439 static struct dpm_clocks dummy_clocks = {
1441 {.Freq = 400, .Vol = 1},
1442 {.Freq = 483, .Vol = 1},
1443 {.Freq = 602, .Vol = 1},
1444 {.Freq = 738, .Vol = 1} },
1446 {.Freq = 300, .Vol = 1},
1447 {.Freq = 400, .Vol = 1},
1448 {.Freq = 400, .Vol = 1},
1449 {.Freq = 400, .Vol = 1} },
1451 {.Freq = 400, .Vol = 1},
1452 {.Freq = 800, .Vol = 1},
1453 {.Freq = 1067, .Vol = 1},
1454 {.Freq = 1600, .Vol = 1} },
1456 {.Freq = 800, .Vol = 1},
1457 {.Freq = 1600, .Vol = 1},
1458 {.Freq = 1067, .Vol = 1},
1459 {.Freq = 1600, .Vol = 1} },
1463 static enum pp_smu_status dummy_set_wm_ranges(struct pp_smu *pp,
1464 struct pp_smu_wm_range_sets *ranges)
1466 return PP_SMU_RESULT_OK;
1469 static enum pp_smu_status dummy_get_dpm_clock_table(struct pp_smu *pp,
1470 struct dpm_clocks *clock_table)
1472 *clock_table = dummy_clocks;
1473 return PP_SMU_RESULT_OK;
1476 static struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx)
1478 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
1483 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment) || IS_DIAG_DC(ctx->dce_environment)) {
1484 pp_smu->ctx.ver = PP_SMU_VER_RN;
1485 pp_smu->rn_funcs.get_dpm_clock_table = dummy_get_dpm_clock_table;
1486 pp_smu->rn_funcs.set_wm_ranges = dummy_set_wm_ranges;
1489 dm_pp_get_funcs(ctx, pp_smu);
1491 if (pp_smu->ctx.ver != PP_SMU_VER_RN)
1492 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs));
1498 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
1500 if (pp_smu && *pp_smu) {
1506 static struct audio *dcn21_create_audio(
1507 struct dc_context *ctx, unsigned int inst)
1509 return dce_audio_create(ctx, inst,
1510 &audio_regs[inst], &audio_shift, &audio_mask);
1513 static struct dc_cap_funcs cap_funcs = {
1514 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1517 struct stream_encoder *dcn21_stream_encoder_create(
1518 enum engine_id eng_id,
1519 struct dc_context *ctx)
1521 struct dcn10_stream_encoder *enc1 =
1522 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1527 dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
1528 &stream_enc_regs[eng_id],
1529 &se_shift, &se_mask);
1534 static const struct dce_hwseq_registers hwseq_reg = {
1535 HWSEQ_DCN21_REG_LIST()
1538 static const struct dce_hwseq_shift hwseq_shift = {
1539 HWSEQ_DCN21_MASK_SH_LIST(__SHIFT)
1542 static const struct dce_hwseq_mask hwseq_mask = {
1543 HWSEQ_DCN21_MASK_SH_LIST(_MASK)
1546 static struct dce_hwseq *dcn21_hwseq_create(
1547 struct dc_context *ctx)
1549 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1553 hws->regs = &hwseq_reg;
1554 hws->shifts = &hwseq_shift;
1555 hws->masks = &hwseq_mask;
1556 hws->wa.DEGVIDCN21 = true;
1557 hws->wa.disallow_self_refresh_during_multi_plane_transition = true;
1562 static const struct resource_create_funcs res_create_funcs = {
1563 .read_dce_straps = read_dce_straps,
1564 .create_audio = dcn21_create_audio,
1565 .create_stream_encoder = dcn21_stream_encoder_create,
1566 .create_hwseq = dcn21_hwseq_create,
1569 static const struct resource_create_funcs res_create_maximus_funcs = {
1570 .read_dce_straps = NULL,
1571 .create_audio = NULL,
1572 .create_stream_encoder = NULL,
1573 .create_hwseq = dcn21_hwseq_create,
1576 static const struct encoder_feature_support link_enc_feature = {
1577 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1578 .max_hdmi_pixel_clock = 600000,
1579 .hdmi_ycbcr420_supported = true,
1580 .dp_ycbcr420_supported = true,
1581 .fec_supported = true,
1582 .flags.bits.IS_HBR2_CAPABLE = true,
1583 .flags.bits.IS_HBR3_CAPABLE = true,
1584 .flags.bits.IS_TPS3_CAPABLE = true,
1585 .flags.bits.IS_TPS4_CAPABLE = true
1589 #define link_regs(id, phyid)\
1591 LE_DCN2_REG_LIST(id), \
1592 UNIPHY_DCN2_REG_LIST(phyid), \
1593 DPCS_DCN21_REG_LIST(id), \
1594 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
1597 static const struct dcn10_link_enc_registers link_enc_regs[] = {
1605 #define aux_regs(id)\
1607 DCN2_AUX_REG_LIST(id)\
1610 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
1618 #define hpd_regs(id)\
1623 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
1631 static const struct dcn10_link_enc_shift le_shift = {
1632 LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT),\
1633 DPCS_DCN21_MASK_SH_LIST(__SHIFT)
1636 static const struct dcn10_link_enc_mask le_mask = {
1637 LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\
1638 DPCS_DCN21_MASK_SH_LIST(_MASK)
1641 static int map_transmitter_id_to_phy_instance(
1642 enum transmitter transmitter)
1644 switch (transmitter) {
1645 case TRANSMITTER_UNIPHY_A:
1648 case TRANSMITTER_UNIPHY_B:
1651 case TRANSMITTER_UNIPHY_C:
1654 case TRANSMITTER_UNIPHY_D:
1657 case TRANSMITTER_UNIPHY_E:
1666 static struct link_encoder *dcn21_link_encoder_create(
1667 const struct encoder_init_data *enc_init_data)
1669 struct dcn21_link_encoder *enc21 =
1670 kzalloc(sizeof(struct dcn21_link_encoder), GFP_KERNEL);
1677 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
1679 dcn21_link_encoder_construct(enc21,
1682 &link_enc_regs[link_regs_id],
1683 &link_enc_aux_regs[enc_init_data->channel - 1],
1684 &link_enc_hpd_regs[enc_init_data->hpd_source],
1688 return &enc21->enc10.base;
1692 #define REG(reg_name) \
1693 (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
1695 static uint32_t read_pipe_fuses(struct dc_context *ctx)
1697 uint32_t value = REG_READ(CC_DC_PIPE_DIS);
1698 /* RV1 support max 4 pipes */
1699 value = value & 0xf;
1703 static int dcn21_populate_dml_pipes_from_context(
1704 struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes)
1706 uint32_t pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes);
1708 struct resource_context *res_ctx = &context->res_ctx;
1710 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1712 if (!res_ctx->pipe_ctx[i].stream)
1715 pipes[i].pipe.src.hostvm = 1;
1716 pipes[i].pipe.src.gpuvm = 1;
1722 enum dc_status dcn21_patch_unknown_plane_state(struct dc_plane_state *plane_state)
1724 enum dc_status result = DC_OK;
1726 if (plane_state->ctx->dc->debug.disable_dcc == DCC_ENABLE) {
1727 plane_state->dcc.enable = 1;
1728 /* align to our worst case block width */
1729 plane_state->dcc.meta_pitch = ((plane_state->src_rect.width + 1023) / 1024) * 1024;
1731 result = dcn20_patch_unknown_plane_state(plane_state);
1735 static struct resource_funcs dcn21_res_pool_funcs = {
1736 .destroy = dcn21_destroy_resource_pool,
1737 .link_enc_create = dcn21_link_encoder_create,
1738 .validate_bandwidth = dcn21_validate_bandwidth,
1739 .populate_dml_pipes = dcn21_populate_dml_pipes_from_context,
1740 .add_stream_to_ctx = dcn20_add_stream_to_ctx,
1741 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1742 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
1743 .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context,
1744 .patch_unknown_plane_state = dcn21_patch_unknown_plane_state,
1745 .set_mcif_arb_params = dcn20_set_mcif_arb_params,
1746 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1747 .update_bw_bounding_box = update_bw_bounding_box
1750 static bool dcn21_resource_construct(
1751 uint8_t num_virtual_links,
1753 struct dcn21_resource_pool *pool)
1756 struct dc_context *ctx = dc->ctx;
1757 struct irq_service_init_data init_data;
1758 uint32_t pipe_fuses = read_pipe_fuses(ctx);
1761 ctx->dc_bios->regs = &bios_regs;
1763 pool->base.res_cap = &res_cap_rn;
1765 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
1766 //pool->base.res_cap = &res_cap_nv10_FPGA_2pipe_dsc;
1767 pool->base.res_cap = &res_cap_rn_FPGA_4pipe;
1770 pool->base.funcs = &dcn21_res_pool_funcs;
1772 /*************************************************
1773 * Resource + asic cap harcoding *
1774 *************************************************/
1775 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1777 /* max pipe num for ASIC before check pipe fuses */
1778 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1780 dc->caps.max_downscale_ratio = 200;
1781 dc->caps.i2c_speed_in_khz = 100;
1782 dc->caps.max_cursor_size = 256;
1783 dc->caps.dmdata_alloc_size = 2048;
1784 dc->caps.hw_3d_lut = true;
1786 dc->caps.max_slave_planes = 1;
1787 dc->caps.post_blend_color_processing = true;
1788 dc->caps.force_dp_tps4_for_cp2520 = true;
1789 dc->caps.extended_aux_timeout_support = true;
1790 dc->caps.dmcub_support = true;
1791 dc->caps.is_apu = true;
1793 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1794 dc->debug = debug_defaults_drv;
1795 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
1796 pool->base.pipe_count = 4;
1797 dc->debug = debug_defaults_diags;
1799 dc->debug = debug_defaults_diags;
1801 // Init the vm_helper
1803 vm_helper_init(dc->vm_helper, 16);
1805 /*************************************************
1806 * Create resources *
1807 *************************************************/
1809 pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =
1810 dcn21_clock_source_create(ctx, ctx->dc_bios,
1811 CLOCK_SOURCE_COMBO_PHY_PLL0,
1812 &clk_src_regs[0], false);
1813 pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =
1814 dcn21_clock_source_create(ctx, ctx->dc_bios,
1815 CLOCK_SOURCE_COMBO_PHY_PLL1,
1816 &clk_src_regs[1], false);
1817 pool->base.clock_sources[DCN20_CLK_SRC_PLL2] =
1818 dcn21_clock_source_create(ctx, ctx->dc_bios,
1819 CLOCK_SOURCE_COMBO_PHY_PLL2,
1820 &clk_src_regs[2], false);
1822 pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN21;
1824 /* todo: not reuse phy_pll registers */
1825 pool->base.dp_clock_source =
1826 dcn21_clock_source_create(ctx, ctx->dc_bios,
1827 CLOCK_SOURCE_ID_DP_DTO,
1828 &clk_src_regs[0], true);
1830 for (i = 0; i < pool->base.clk_src_count; i++) {
1831 if (pool->base.clock_sources[i] == NULL) {
1832 dm_error("DC: failed to create clock sources!\n");
1833 BREAK_TO_DEBUGGER();
1838 pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1839 if (pool->base.dccg == NULL) {
1840 dm_error("DC: failed to create dccg!\n");
1841 BREAK_TO_DEBUGGER();
1845 pool->base.dmcu = dcn21_dmcu_create(ctx,
1849 if (pool->base.dmcu == NULL) {
1850 dm_error("DC: failed to create dmcu!\n");
1851 BREAK_TO_DEBUGGER();
1855 if (dc->debug.disable_dmcu) {
1856 pool->base.psr = dmub_psr_create(ctx);
1858 if (pool->base.psr == NULL) {
1859 dm_error("DC: failed to create psr obj!\n");
1860 BREAK_TO_DEBUGGER();
1865 pool->base.abm = dce_abm_create(ctx,
1869 if (pool->base.abm == NULL) {
1870 dm_error("DC: failed to create abm!\n");
1871 BREAK_TO_DEBUGGER();
1875 pool->base.pp_smu = dcn21_pp_smu_create(ctx);
1877 num_pipes = dcn2_1_ip.max_num_dpp;
1879 for (i = 0; i < dcn2_1_ip.max_num_dpp; i++)
1880 if (pipe_fuses & 1 << i)
1882 dcn2_1_ip.max_num_dpp = num_pipes;
1883 dcn2_1_ip.max_num_otg = num_pipes;
1885 dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);
1887 init_data.ctx = dc->ctx;
1888 pool->base.irqs = dal_irq_service_dcn21_create(&init_data);
1889 if (!pool->base.irqs)
1893 /* mem input -> ipp -> dpp -> opp -> TG */
1894 for (i = 0; i < pool->base.pipe_count; i++) {
1895 /* if pipe is disabled, skip instance of HW pipe,
1896 * i.e, skip ASIC register instance
1898 if ((pipe_fuses & (1 << i)) != 0)
1901 pool->base.hubps[j] = dcn21_hubp_create(ctx, i);
1902 if (pool->base.hubps[j] == NULL) {
1903 BREAK_TO_DEBUGGER();
1905 "DC: failed to create memory input!\n");
1909 pool->base.ipps[j] = dcn21_ipp_create(ctx, i);
1910 if (pool->base.ipps[j] == NULL) {
1911 BREAK_TO_DEBUGGER();
1913 "DC: failed to create input pixel processor!\n");
1917 pool->base.dpps[j] = dcn21_dpp_create(ctx, i);
1918 if (pool->base.dpps[j] == NULL) {
1919 BREAK_TO_DEBUGGER();
1921 "DC: failed to create dpps!\n");
1925 pool->base.opps[j] = dcn21_opp_create(ctx, i);
1926 if (pool->base.opps[j] == NULL) {
1927 BREAK_TO_DEBUGGER();
1929 "DC: failed to create output pixel processor!\n");
1933 pool->base.timing_generators[j] = dcn21_timing_generator_create(
1935 if (pool->base.timing_generators[j] == NULL) {
1936 BREAK_TO_DEBUGGER();
1937 dm_error("DC: failed to create tg!\n");
1943 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1944 pool->base.engines[i] = dcn21_aux_engine_create(ctx, i);
1945 if (pool->base.engines[i] == NULL) {
1946 BREAK_TO_DEBUGGER();
1948 "DC:failed to create aux engine!!\n");
1951 pool->base.hw_i2cs[i] = dcn21_i2c_hw_create(ctx, i);
1952 if (pool->base.hw_i2cs[i] == NULL) {
1953 BREAK_TO_DEBUGGER();
1955 "DC:failed to create hw i2c!!\n");
1958 pool->base.sw_i2cs[i] = NULL;
1961 pool->base.timing_generator_count = j;
1962 pool->base.pipe_count = j;
1963 pool->base.mpcc_count = j;
1965 pool->base.mpc = dcn21_mpc_create(ctx);
1966 if (pool->base.mpc == NULL) {
1967 BREAK_TO_DEBUGGER();
1968 dm_error("DC: failed to create mpc!\n");
1972 pool->base.hubbub = dcn21_hubbub_create(ctx);
1973 if (pool->base.hubbub == NULL) {
1974 BREAK_TO_DEBUGGER();
1975 dm_error("DC: failed to create hubbub!\n");
1979 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1980 pool->base.dscs[i] = dcn21_dsc_create(ctx, i);
1981 if (pool->base.dscs[i] == NULL) {
1982 BREAK_TO_DEBUGGER();
1983 dm_error("DC: failed to create display stream compressor %d!\n", i);
1988 if (!dcn20_dwbc_create(ctx, &pool->base)) {
1989 BREAK_TO_DEBUGGER();
1990 dm_error("DC: failed to create dwbc!\n");
1993 if (!dcn20_mmhubbub_create(ctx, &pool->base)) {
1994 BREAK_TO_DEBUGGER();
1995 dm_error("DC: failed to create mcif_wb!\n");
1999 if (!resource_construct(num_virtual_links, dc, &pool->base,
2000 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
2001 &res_create_funcs : &res_create_maximus_funcs)))
2004 dcn21_hw_sequencer_construct(dc);
2006 dc->caps.max_planes = pool->base.pipe_count;
2008 for (i = 0; i < dc->caps.max_planes; ++i)
2009 dc->caps.planes[i] = plane_cap;
2011 dc->cap_funcs = cap_funcs;
2017 dcn21_resource_destruct(pool);
2022 struct resource_pool *dcn21_create_resource_pool(
2023 const struct dc_init_data *init_data,
2026 struct dcn21_resource_pool *pool =
2027 kzalloc(sizeof(struct dcn21_resource_pool), GFP_KERNEL);
2032 if (dcn21_resource_construct(init_data->num_virtual_links, dc, pool))
2035 BREAK_TO_DEBUGGER();