drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c

   1 /*
   2 * Copyright 2018 Advanced Micro Devices, Inc.
   3  * Copyright 2019 Raptor Engineering, LLC
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: AMD
  24  *
  25  */
  26
  27 #include <linux/slab.h>
  28
  29 #include "dm_services.h"
  30 #include "dc.h"
  31
  32 #include "dcn21_init.h"
  33
  34 #include "resource.h"
  35 #include "include/irq_service_interface.h"
  36 #include "dcn20/dcn20_resource.h"
  37
  38 #include "clk_mgr.h"
  39 #include "dcn10/dcn10_hubp.h"
  40 #include "dcn10/dcn10_ipp.h"
  41 #include "dcn20/dcn20_hubbub.h"
  42 #include "dcn20/dcn20_mpc.h"
  43 #include "dcn20/dcn20_hubp.h"
  44 #include "dcn21_hubp.h"
  45 #include "irq/dcn21/irq_service_dcn21.h"
  46 #include "dcn20/dcn20_dpp.h"
  47 #include "dcn20/dcn20_optc.h"
  48 #include "dcn21/dcn21_hwseq.h"
  49 #include "dce110/dce110_hw_sequencer.h"
  50 #include "dcn20/dcn20_opp.h"
  51 #include "dcn20/dcn20_dsc.h"
  52 #include "dcn21/dcn21_link_encoder.h"
  53 #include "dcn20/dcn20_stream_encoder.h"
  54 #include "dce/dce_clock_source.h"
  55 #include "dce/dce_audio.h"
  56 #include "dce/dce_hwseq.h"
  57 #include "virtual/virtual_stream_encoder.h"
  58 #include "dce110/dce110_resource.h"
  59 #include "dml/display_mode_vba.h"
  60 #include "dcn20/dcn20_dccg.h"
  61 #include "dcn21/dcn21_dccg.h"
  62 #include "dcn21_hubbub.h"
  63 #include "dcn10/dcn10_resource.h"
  64 #include "dce110/dce110_resource.h"
  65 #include "dce/dce_panel_cntl.h"
  66
  67 #include "dcn20/dcn20_dwb.h"
  68 #include "dcn20/dcn20_mmhubbub.h"
  69 #include "dpcs/dpcs_2_1_0_offset.h"
  70 #include "dpcs/dpcs_2_1_0_sh_mask.h"
  71
  72 #include "renoir_ip_offset.h"
  73 #include "dcn/dcn_2_1_0_offset.h"
  74 #include "dcn/dcn_2_1_0_sh_mask.h"
  75
  76 #include "nbio/nbio_7_0_offset.h"
  77
  78 #include "mmhub/mmhub_2_0_0_offset.h"
  79 #include "mmhub/mmhub_2_0_0_sh_mask.h"
  80
  81 #include "reg_helper.h"
  82 #include "dce/dce_abm.h"
  83 #include "dce/dce_dmcu.h"
  84 #include "dce/dce_aux.h"
  85 #include "dce/dce_i2c.h"
  86 #include "dcn21_resource.h"
  87 #include "vm_helper.h"
  88 #include "dcn20/dcn20_vmid.h"
  89 #include "dce/dmub_psr.h"
  90 #include "dce/dmub_abm.h"
  91
  92 #define DC_LOGGER_INIT(logger)
  93
  94
  95 struct _vcs_dpi_ip_params_st dcn2_1_ip = {
  96         .odm_capable = 1,
  97         .gpuvm_enable = 1,
  98         .hostvm_enable = 1,
  99         .gpuvm_max_page_table_levels = 1,
 100         .hostvm_max_page_table_levels = 4,
 101         .hostvm_cached_page_table_levels = 2,
 102         .num_dsc = 3,
 103         .rob_buffer_size_kbytes = 168,
 104         .det_buffer_size_kbytes = 164,
 105         .dpte_buffer_size_in_pte_reqs_luma = 44,
 106         .dpte_buffer_size_in_pte_reqs_chroma = 42,//todo
 107         .dpp_output_buffer_pixels = 2560,
 108         .opp_output_buffer_lines = 1,
 109         .pixel_chunk_size_kbytes = 8,
 110         .pte_enable = 1,
 111         .max_page_table_levels = 4,
 112         .pte_chunk_size_kbytes = 2,
 113         .meta_chunk_size_kbytes = 2,
 114         .writeback_chunk_size_kbytes = 2,
 115         .line_buffer_size_bits = 789504,
 116         .is_line_buffer_bpp_fixed = 0,
 117         .line_buffer_fixed_bpp = 0,
 118         .dcc_supported = true,
 119         .max_line_buffer_lines = 12,
 120         .writeback_luma_buffer_size_kbytes = 12,
 121         .writeback_chroma_buffer_size_kbytes = 8,
 122         .writeback_chroma_line_buffer_width_pixels = 4,
 123         .writeback_max_hscl_ratio = 1,
 124         .writeback_max_vscl_ratio = 1,
 125         .writeback_min_hscl_ratio = 1,
 126         .writeback_min_vscl_ratio = 1,
 127         .writeback_max_hscl_taps = 12,
 128         .writeback_max_vscl_taps = 12,
 129         .writeback_line_buffer_luma_buffer_size = 0,
 130         .writeback_line_buffer_chroma_buffer_size = 14643,
 131         .cursor_buffer_size = 8,
 132         .cursor_chunk_size = 2,
 133         .max_num_otg = 4,
 134         .max_num_dpp = 4,
 135         .max_num_wb = 1,
 136         .max_dchub_pscl_bw_pix_per_clk = 4,
 137         .max_pscl_lb_bw_pix_per_clk = 2,
 138         .max_lb_vscl_bw_pix_per_clk = 4,
 139         .max_vscl_hscl_bw_pix_per_clk = 4,
 140         .max_hscl_ratio = 4,
 141         .max_vscl_ratio = 4,
 142         .hscl_mults = 4,
 143         .vscl_mults = 4,
 144         .max_hscl_taps = 8,
 145         .max_vscl_taps = 8,
 146         .dispclk_ramp_margin_percent = 1,
 147         .underscan_factor = 1.10,
 148         .min_vblank_lines = 32, //
 149         .dppclk_delay_subtotal = 77, //
 150         .dppclk_delay_scl_lb_only = 16,
 151         .dppclk_delay_scl = 50,
 152         .dppclk_delay_cnvc_formatter = 8,
 153         .dppclk_delay_cnvc_cursor = 6,
 154         .dispclk_delay_subtotal = 87, //
 155         .dcfclk_cstate_latency = 10, // SRExitTime
 156         .max_inter_dcn_tile_repeaters = 8,
 157
 158         .xfc_supported = false,
 159         .xfc_fill_bw_overhead_percent = 10.0,
 160         .xfc_fill_constant_bytes = 0,
 161         .ptoi_supported = 0,
 162         .number_of_cursors = 1,
 163 };
 164
 165 struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = {
 166         .clock_limits = {
 167                         {
 168                                 .state = 0,
 169                                 .dcfclk_mhz = 400.0,
 170                                 .fabricclk_mhz = 400.0,
 171                                 .dispclk_mhz = 600.0,
 172                                 .dppclk_mhz = 400.00,
 173                                 .phyclk_mhz = 600.0,
 174                                 .socclk_mhz = 278.0,
 175                                 .dscclk_mhz = 205.67,
 176                                 .dram_speed_mts = 1600.0,
 177                         },
 178                         {
 179                                 .state = 1,
 180                                 .dcfclk_mhz = 464.52,
 181                                 .fabricclk_mhz = 800.0,
 182                                 .dispclk_mhz = 654.55,
 183                                 .dppclk_mhz = 626.09,
 184                                 .phyclk_mhz = 600.0,
 185                                 .socclk_mhz = 278.0,
 186                                 .dscclk_mhz = 205.67,
 187                                 .dram_speed_mts = 1600.0,
 188                         },
 189                         {
 190                                 .state = 2,
 191                                 .dcfclk_mhz = 514.29,
 192                                 .fabricclk_mhz = 933.0,
 193                                 .dispclk_mhz = 757.89,
 194                                 .dppclk_mhz = 685.71,
 195                                 .phyclk_mhz = 600.0,
 196                                 .socclk_mhz = 278.0,
 197                                 .dscclk_mhz = 287.67,
 198                                 .dram_speed_mts = 1866.0,
 199                         },
 200                         {
 201                                 .state = 3,
 202                                 .dcfclk_mhz = 576.00,
 203                                 .fabricclk_mhz = 1067.0,
 204                                 .dispclk_mhz = 847.06,
 205                                 .dppclk_mhz = 757.89,
 206                                 .phyclk_mhz = 600.0,
 207                                 .socclk_mhz = 715.0,
 208                                 .dscclk_mhz = 318.334,
 209                                 .dram_speed_mts = 2134.0,
 210                         },
 211                         {
 212                                 .state = 4,
 213                                 .dcfclk_mhz = 626.09,
 214                                 .fabricclk_mhz = 1200.0,
 215                                 .dispclk_mhz = 900.00,
 216                                 .dppclk_mhz = 847.06,
 217                                 .phyclk_mhz = 810.0,
 218                                 .socclk_mhz = 953.0,
 219                                 .dscclk_mhz = 489.0,
 220                                 .dram_speed_mts = 2400.0,
 221                         },
 222                         {
 223                                 .state = 5,
 224                                 .dcfclk_mhz = 685.71,
 225                                 .fabricclk_mhz = 1333.0,
 226                                 .dispclk_mhz = 1028.57,
 227                                 .dppclk_mhz = 960.00,
 228                                 .phyclk_mhz = 810.0,
 229                                 .socclk_mhz = 278.0,
 230                                 .dscclk_mhz = 287.67,
 231                                 .dram_speed_mts = 2666.0,
 232                         },
 233                         {
 234                                 .state = 6,
 235                                 .dcfclk_mhz = 757.89,
 236                                 .fabricclk_mhz = 1467.0,
 237                                 .dispclk_mhz = 1107.69,
 238                                 .dppclk_mhz = 1028.57,
 239                                 .phyclk_mhz = 810.0,
 240                                 .socclk_mhz = 715.0,
 241                                 .dscclk_mhz = 318.334,
 242                                 .dram_speed_mts = 3200.0,
 243                         },
 244                         {
 245                                 .state = 7,
 246                                 .dcfclk_mhz = 847.06,
 247                                 .fabricclk_mhz = 1600.0,
 248                                 .dispclk_mhz = 1395.0,
 249                                 .dppclk_mhz = 1285.00,
 250                                 .phyclk_mhz = 1325.0,
 251                                 .socclk_mhz = 953.0,
 252                                 .dscclk_mhz = 489.0,
 253                                 .dram_speed_mts = 4266.0,
 254                         },
 255                         /*Extra state, no dispclk ramping*/
 256                         {
 257                                 .state = 8,
 258                                 .dcfclk_mhz = 847.06,
 259                                 .fabricclk_mhz = 1600.0,
 260                                 .dispclk_mhz = 1395.0,
 261                                 .dppclk_mhz = 1285.0,
 262                                 .phyclk_mhz = 1325.0,
 263                                 .socclk_mhz = 953.0,
 264                                 .dscclk_mhz = 489.0,
 265                                 .dram_speed_mts = 4266.0,
 266                         },
 267
 268                 },
 269
 270         .sr_exit_time_us = 12.5,
 271         .sr_enter_plus_exit_time_us = 17.0,
 272         .urgent_latency_us = 4.0,
 273         .urgent_latency_pixel_data_only_us = 4.0,
 274         .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
 275         .urgent_latency_vm_data_only_us = 4.0,
 276         .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
 277         .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
 278         .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
 279         .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0,
 280         .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 75.0,
 281         .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
 282         .max_avg_sdp_bw_use_normal_percent = 60.0,
 283         .max_avg_dram_bw_use_normal_percent = 100.0,
 284         .writeback_latency_us = 12.0,
 285         .max_request_size_bytes = 256,
 286         .dram_channel_width_bytes = 4,
 287         .fabric_datapath_to_dcn_data_return_bytes = 32,
 288         .dcn_downspread_percent = 0.5,
 289         .downspread_percent = 0.38,
 290         .dram_page_open_time_ns = 50.0,
 291         .dram_rw_turnaround_time_ns = 17.5,
 292         .dram_return_buffer_per_channel_bytes = 8192,
 293         .round_trip_ping_latency_dcfclk_cycles = 128,
 294         .urgent_out_of_order_return_per_channel_bytes = 4096,
 295         .channel_interleave_bytes = 256,
 296         .num_banks = 8,
 297         .num_chans = 4,
 298         .vmm_page_size_bytes = 4096,
 299         .dram_clock_change_latency_us = 11.72,
 300         .return_bus_width_bytes = 64,
 301         .dispclk_dppclk_vco_speed_mhz = 3600,
 302         .xfc_bus_transport_time_us = 4,
 303         .xfc_xbuf_latency_tolerance_us = 4,
 304         .use_urgent_burst_bw = 1,
 305         .num_states = 8
 306 };
 307
 308 #ifndef MAX
 309 #define MAX(X, Y) ((X) > (Y) ? (X) : (Y))
 310 #endif
 311 #ifndef MIN
 312 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
 313 #endif
 314
 315 /* begin *********************
 316  * macros to expend register list macro defined in HW object header file */
 317
 318 /* DCN */
 319 /* TODO awful hack. fixup dcn20_dwb.h */
 320 #undef BASE_INNER
 321 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
 322
 323 #define BASE(seg) BASE_INNER(seg)
 324
 325 #define SR(reg_name)\
 326                 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
 327                                         mm ## reg_name
 328
 329 #define SRI(reg_name, block, id)\
 330         .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 331                                         mm ## block ## id ## _ ## reg_name
 332
 333 #define SRIR(var_name, reg_name, block, id)\
 334         .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 335                                         mm ## block ## id ## _ ## reg_name
 336
 337 #define SRII(reg_name, block, id)\
 338         .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 339                                         mm ## block ## id ## _ ## reg_name
 340
 341 #define DCCG_SRII(reg_name, block, id)\
 342         .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 343                                         mm ## block ## id ## _ ## reg_name
 344
 345 #define VUPDATE_SRII(reg_name, block, id)\
 346         .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
 347                                         mm ## reg_name ## _ ## block ## id
 348
 349 /* NBIO */
 350 #define NBIO_BASE_INNER(seg) \
 351         NBIF0_BASE__INST0_SEG ## seg
 352
 353 #define NBIO_BASE(seg) \
 354         NBIO_BASE_INNER(seg)
 355
 356 #define NBIO_SR(reg_name)\
 357                 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
 358                                         mm ## reg_name
 359
 360 /* MMHUB */
 361 #define MMHUB_BASE_INNER(seg) \
 362         MMHUB_BASE__INST0_SEG ## seg
 363
 364 #define MMHUB_BASE(seg) \
 365         MMHUB_BASE_INNER(seg)
 366
 367 #define MMHUB_SR(reg_name)\
 368                 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
 369                                         mmMM ## reg_name
 370
 371 #define clk_src_regs(index, pllid)\
 372 [index] = {\
 373         CS_COMMON_REG_LIST_DCN2_1(index, pllid),\
 374 }
 375
 376 static const struct dce110_clk_src_regs clk_src_regs[] = {
 377         clk_src_regs(0, A),
 378         clk_src_regs(1, B),
 379         clk_src_regs(2, C),
 380         clk_src_regs(3, D),
 381         clk_src_regs(4, E),
 382 };
 383
 384 static const struct dce110_clk_src_shift cs_shift = {
 385                 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
 386 };
 387
 388 static const struct dce110_clk_src_mask cs_mask = {
 389                 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
 390 };
 391
 392 static const struct bios_registers bios_regs = {
 393                 NBIO_SR(BIOS_SCRATCH_3),
 394                 NBIO_SR(BIOS_SCRATCH_6)
 395 };
 396
 397 static const struct dce_dmcu_registers dmcu_regs = {
 398                 DMCU_DCN20_REG_LIST()
 399 };
 400
 401 static const struct dce_dmcu_shift dmcu_shift = {
 402                 DMCU_MASK_SH_LIST_DCN10(__SHIFT)
 403 };
 404
 405 static const struct dce_dmcu_mask dmcu_mask = {
 406                 DMCU_MASK_SH_LIST_DCN10(_MASK)
 407 };
 408
 409 static const struct dce_abm_registers abm_regs = {
 410                 ABM_DCN20_REG_LIST()
 411 };
 412
 413 static const struct dce_abm_shift abm_shift = {
 414                 ABM_MASK_SH_LIST_DCN20(__SHIFT)
 415 };
 416
 417 static const struct dce_abm_mask abm_mask = {
 418                 ABM_MASK_SH_LIST_DCN20(_MASK)
 419 };
 420
 421 #define audio_regs(id)\
 422 [id] = {\
 423                 AUD_COMMON_REG_LIST(id)\
 424 }
 425
 426 static const struct dce_audio_registers audio_regs[] = {
 427         audio_regs(0),
 428         audio_regs(1),
 429         audio_regs(2),
 430         audio_regs(3),
 431         audio_regs(4),
 432         audio_regs(5),
 433 };
 434
 435 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
 436                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
 437                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
 438                 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
 439
 440 static const struct dce_audio_shift audio_shift = {
 441                 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
 442 };
 443
 444 static const struct dce_audio_mask audio_mask = {
 445                 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
 446 };
 447
 448 static const struct dccg_registers dccg_regs = {
 449                 DCCG_COMMON_REG_LIST_DCN_BASE()
 450 };
 451
 452 static const struct dccg_shift dccg_shift = {
 453                 DCCG_MASK_SH_LIST_DCN2(__SHIFT)
 454 };
 455
 456 static const struct dccg_mask dccg_mask = {
 457                 DCCG_MASK_SH_LIST_DCN2(_MASK)
 458 };
 459
 460 #define opp_regs(id)\
 461 [id] = {\
 462         OPP_REG_LIST_DCN20(id),\
 463 }
 464
 465 static const struct dcn20_opp_registers opp_regs[] = {
 466         opp_regs(0),
 467         opp_regs(1),
 468         opp_regs(2),
 469         opp_regs(3),
 470         opp_regs(4),
 471         opp_regs(5),
 472 };
 473
 474 static const struct dcn20_opp_shift opp_shift = {
 475                 OPP_MASK_SH_LIST_DCN20(__SHIFT)
 476 };
 477
 478 static const struct dcn20_opp_mask opp_mask = {
 479                 OPP_MASK_SH_LIST_DCN20(_MASK)
 480 };
 481
 482 #define tg_regs(id)\
 483 [id] = {TG_COMMON_REG_LIST_DCN2_0(id)}
 484
 485 static const struct dcn_optc_registers tg_regs[] = {
 486         tg_regs(0),
 487         tg_regs(1),
 488         tg_regs(2),
 489         tg_regs(3)
 490 };
 491
 492 static const struct dcn_optc_shift tg_shift = {
 493         TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
 494 };
 495
 496 static const struct dcn_optc_mask tg_mask = {
 497         TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
 498 };
 499
 500 static const struct dcn20_mpc_registers mpc_regs = {
 501                 MPC_REG_LIST_DCN2_0(0),
 502                 MPC_REG_LIST_DCN2_0(1),
 503                 MPC_REG_LIST_DCN2_0(2),
 504                 MPC_REG_LIST_DCN2_0(3),
 505                 MPC_REG_LIST_DCN2_0(4),
 506                 MPC_REG_LIST_DCN2_0(5),
 507                 MPC_OUT_MUX_REG_LIST_DCN2_0(0),
 508                 MPC_OUT_MUX_REG_LIST_DCN2_0(1),
 509                 MPC_OUT_MUX_REG_LIST_DCN2_0(2),
 510                 MPC_OUT_MUX_REG_LIST_DCN2_0(3),
 511                 MPC_DBG_REG_LIST_DCN2_0()
 512 };
 513
 514 static const struct dcn20_mpc_shift mpc_shift = {
 515         MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT),
 516         MPC_DEBUG_REG_LIST_SH_DCN20
 517 };
 518
 519 static const struct dcn20_mpc_mask mpc_mask = {
 520         MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK),
 521         MPC_DEBUG_REG_LIST_MASK_DCN20
 522 };
 523
 524 #define hubp_regs(id)\
 525 [id] = {\
 526         HUBP_REG_LIST_DCN21(id)\
 527 }
 528
 529 static const struct dcn_hubp2_registers hubp_regs[] = {
 530                 hubp_regs(0),
 531                 hubp_regs(1),
 532                 hubp_regs(2),
 533                 hubp_regs(3)
 534 };
 535
 536 static const struct dcn_hubp2_shift hubp_shift = {
 537                 HUBP_MASK_SH_LIST_DCN21(__SHIFT)
 538 };
 539
 540 static const struct dcn_hubp2_mask hubp_mask = {
 541                 HUBP_MASK_SH_LIST_DCN21(_MASK)
 542 };
 543
 544 static const struct dcn_hubbub_registers hubbub_reg = {
 545                 HUBBUB_REG_LIST_DCN21()
 546 };
 547
 548 static const struct dcn_hubbub_shift hubbub_shift = {
 549                 HUBBUB_MASK_SH_LIST_DCN21(__SHIFT)
 550 };
 551
 552 static const struct dcn_hubbub_mask hubbub_mask = {
 553                 HUBBUB_MASK_SH_LIST_DCN21(_MASK)
 554 };
 555
 556
 557 #define vmid_regs(id)\
 558 [id] = {\
 559                 DCN20_VMID_REG_LIST(id)\
 560 }
 561
 562 static const struct dcn_vmid_registers vmid_regs[] = {
 563         vmid_regs(0),
 564         vmid_regs(1),
 565         vmid_regs(2),
 566         vmid_regs(3),
 567         vmid_regs(4),
 568         vmid_regs(5),
 569         vmid_regs(6),
 570         vmid_regs(7),
 571         vmid_regs(8),
 572         vmid_regs(9),
 573         vmid_regs(10),
 574         vmid_regs(11),
 575         vmid_regs(12),
 576         vmid_regs(13),
 577         vmid_regs(14),
 578         vmid_regs(15)
 579 };
 580
 581 static const struct dcn20_vmid_shift vmid_shifts = {
 582                 DCN20_VMID_MASK_SH_LIST(__SHIFT)
 583 };
 584
 585 static const struct dcn20_vmid_mask vmid_masks = {
 586                 DCN20_VMID_MASK_SH_LIST(_MASK)
 587 };
 588
 589 #define dsc_regsDCN20(id)\
 590 [id] = {\
 591         DSC_REG_LIST_DCN20(id)\
 592 }
 593
 594 static const struct dcn20_dsc_registers dsc_regs[] = {
 595         dsc_regsDCN20(0),
 596         dsc_regsDCN20(1),
 597         dsc_regsDCN20(2),
 598         dsc_regsDCN20(3),
 599         dsc_regsDCN20(4),
 600         dsc_regsDCN20(5)
 601 };
 602
 603 static const struct dcn20_dsc_shift dsc_shift = {
 604         DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
 605 };
 606
 607 static const struct dcn20_dsc_mask dsc_mask = {
 608         DSC_REG_LIST_SH_MASK_DCN20(_MASK)
 609 };
 610
 611 #define ipp_regs(id)\
 612 [id] = {\
 613         IPP_REG_LIST_DCN20(id),\
 614 }
 615
 616 static const struct dcn10_ipp_registers ipp_regs[] = {
 617         ipp_regs(0),
 618         ipp_regs(1),
 619         ipp_regs(2),
 620         ipp_regs(3),
 621 };
 622
 623 static const struct dcn10_ipp_shift ipp_shift = {
 624                 IPP_MASK_SH_LIST_DCN20(__SHIFT)
 625 };
 626
 627 static const struct dcn10_ipp_mask ipp_mask = {
 628                 IPP_MASK_SH_LIST_DCN20(_MASK),
 629 };
 630
 631 #define opp_regs(id)\
 632 [id] = {\
 633         OPP_REG_LIST_DCN20(id),\
 634 }
 635
 636
 637 #define aux_engine_regs(id)\
 638 [id] = {\
 639         AUX_COMMON_REG_LIST0(id), \
 640         .AUXN_IMPCAL = 0, \
 641         .AUXP_IMPCAL = 0, \
 642         .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
 643 }
 644
 645 static const struct dce110_aux_registers aux_engine_regs[] = {
 646                 aux_engine_regs(0),
 647                 aux_engine_regs(1),
 648                 aux_engine_regs(2),
 649                 aux_engine_regs(3),
 650                 aux_engine_regs(4),
 651 };
 652
 653 #define tf_regs(id)\
 654 [id] = {\
 655         TF_REG_LIST_DCN20(id),\
 656         TF_REG_LIST_DCN20_COMMON_APPEND(id),\
 657 }
 658
 659 static const struct dcn2_dpp_registers tf_regs[] = {
 660         tf_regs(0),
 661         tf_regs(1),
 662         tf_regs(2),
 663         tf_regs(3),
 664 };
 665
 666 static const struct dcn2_dpp_shift tf_shift = {
 667                 TF_REG_LIST_SH_MASK_DCN20(__SHIFT),
 668                 TF_DEBUG_REG_LIST_SH_DCN20
 669 };
 670
 671 static const struct dcn2_dpp_mask tf_mask = {
 672                 TF_REG_LIST_SH_MASK_DCN20(_MASK),
 673                 TF_DEBUG_REG_LIST_MASK_DCN20
 674 };
 675
 676 #define stream_enc_regs(id)\
 677 [id] = {\
 678         SE_DCN2_REG_LIST(id)\
 679 }
 680
 681 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
 682         stream_enc_regs(0),
 683         stream_enc_regs(1),
 684         stream_enc_regs(2),
 685         stream_enc_regs(3),
 686         stream_enc_regs(4),
 687 };
 688
 689 static const struct dce110_aux_registers_shift aux_shift = {
 690         DCN_AUX_MASK_SH_LIST(__SHIFT)
 691 };
 692
 693 static const struct dce110_aux_registers_mask aux_mask = {
 694         DCN_AUX_MASK_SH_LIST(_MASK)
 695 };
 696
 697 static const struct dcn10_stream_encoder_shift se_shift = {
 698                 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)
 699 };
 700
 701 static const struct dcn10_stream_encoder_mask se_mask = {
 702                 SE_COMMON_MASK_SH_LIST_DCN20(_MASK)
 703 };
 704
 705 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
 706
 707 static int dcn21_populate_dml_pipes_from_context(
 708                 struct dc *dc,
 709                 struct dc_state *context,
 710                 display_e2e_pipe_params_st *pipes,
 711                 bool fast_validate);
 712
 713 static struct input_pixel_processor *dcn21_ipp_create(
 714         struct dc_context *ctx, uint32_t inst)
 715 {
 716         struct dcn10_ipp *ipp =
 717                 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);
 718
 719         if (!ipp) {
 720                 BREAK_TO_DEBUGGER();
 721                 return NULL;
 722         }
 723
 724         dcn20_ipp_construct(ipp, ctx, inst,
 725                         &ipp_regs[inst], &ipp_shift, &ipp_mask);
 726         return &ipp->base;
 727 }
 728
 729 static struct dpp *dcn21_dpp_create(
 730         struct dc_context *ctx,
 731         uint32_t inst)
 732 {
 733         struct dcn20_dpp *dpp =
 734                 kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL);
 735
 736         if (!dpp)
 737                 return NULL;
 738
 739         if (dpp2_construct(dpp, ctx, inst,
 740                         &tf_regs[inst], &tf_shift, &tf_mask))
 741                 return &dpp->base;
 742
 743         BREAK_TO_DEBUGGER();
 744         kfree(dpp);
 745         return NULL;
 746 }
 747
 748 static struct dce_aux *dcn21_aux_engine_create(
 749         struct dc_context *ctx,
 750         uint32_t inst)
 751 {
 752         struct aux_engine_dce110 *aux_engine =
 753                 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
 754
 755         if (!aux_engine)
 756                 return NULL;
 757
 758         dce110_aux_engine_construct(aux_engine, ctx, inst,
 759                                     SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
 760                                     &aux_engine_regs[inst],
 761                                         &aux_mask,
 762                                         &aux_shift,
 763                                         ctx->dc->caps.extended_aux_timeout_support);
 764
 765         return &aux_engine->base;
 766 }
 767
 768 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
 769
 770 static const struct dce_i2c_registers i2c_hw_regs[] = {
 771                 i2c_inst_regs(1),
 772                 i2c_inst_regs(2),
 773                 i2c_inst_regs(3),
 774                 i2c_inst_regs(4),
 775                 i2c_inst_regs(5),
 776 };
 777
 778 static const struct dce_i2c_shift i2c_shifts = {
 779                 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
 780 };
 781
 782 static const struct dce_i2c_mask i2c_masks = {
 783                 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
 784 };
 785
 786 struct dce_i2c_hw *dcn21_i2c_hw_create(
 787         struct dc_context *ctx,
 788         uint32_t inst)
 789 {
 790         struct dce_i2c_hw *dce_i2c_hw =
 791                 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
 792
 793         if (!dce_i2c_hw)
 794                 return NULL;
 795
 796         dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
 797                                     &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
 798
 799         return dce_i2c_hw;
 800 }
 801
 802 static const struct resource_caps res_cap_rn = {
 803                 .num_timing_generator = 4,
 804                 .num_opp = 4,
 805                 .num_video_plane = 4,
 806                 .num_audio = 4, // 4 audio endpoints.  4 audio streams
 807                 .num_stream_encoder = 5,
 808                 .num_pll = 5,  // maybe 3 because the last two used for USB-c
 809                 .num_dwb = 1,
 810                 .num_ddc = 5,
 811                 .num_vmid = 16,
 812                 .num_dsc = 3,
 813 };
 814
 815 #ifdef DIAGS_BUILD
 816 static const struct resource_caps res_cap_rn_FPGA_4pipe = {
 817                 .num_timing_generator = 4,
 818                 .num_opp = 4,
 819                 .num_video_plane = 4,
 820                 .num_audio = 7,
 821                 .num_stream_encoder = 4,
 822                 .num_pll = 4,
 823                 .num_dwb = 1,
 824                 .num_ddc = 4,
 825                 .num_dsc = 0,
 826 };
 827
 828 static const struct resource_caps res_cap_rn_FPGA_2pipe_dsc = {
 829                 .num_timing_generator = 2,
 830                 .num_opp = 2,
 831                 .num_video_plane = 2,
 832                 .num_audio = 7,
 833                 .num_stream_encoder = 2,
 834                 .num_pll = 4,
 835                 .num_dwb = 1,
 836                 .num_ddc = 4,
 837                 .num_dsc = 2,
 838 };
 839 #endif
 840
 841 static const struct dc_plane_cap plane_cap = {
 842         .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
 843         .blends_with_above = true,
 844         .blends_with_below = true,
 845         .per_pixel_alpha = true,
 846
 847         .pixel_format_support = {
 848                         .argb8888 = true,
 849                         .nv12 = true,
 850                         .fp16 = true,
 851                         .p010 = true
 852         },
 853
 854         .max_upscale_factor = {
 855                         .argb8888 = 16000,
 856                         .nv12 = 16000,
 857                         .fp16 = 16000
 858         },
 859
 860         .max_downscale_factor = {
 861                         .argb8888 = 250,
 862                         .nv12 = 250,
 863                         .fp16 = 250
 864         },
 865         64,
 866         64
 867 };
 868
 869 static const struct dc_debug_options debug_defaults_drv = {
 870                 .disable_dmcu = false,
 871                 .force_abm_enable = false,
 872                 .timing_trace = false,
 873                 .clock_trace = true,
 874                 .disable_pplib_clock_request = true,
 875                 .min_disp_clk_khz = 100000,
 876                 .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
 877                 .force_single_disp_pipe_split = false,
 878                 .disable_dcc = DCC_ENABLE,
 879                 .vsr_support = true,
 880                 .performance_trace = false,
 881                 .max_downscale_src_width = 4096,
 882                 .disable_pplib_wm_range = false,
 883                 .scl_reset_length10 = true,
 884                 .sanity_checks = true,
 885                 .disable_48mhz_pwrdwn = false,
 886                 .usbc_combo_phy_reset_wa = true
 887 };
 888
 889 static const struct dc_debug_options debug_defaults_diags = {
 890                 .disable_dmcu = false,
 891                 .force_abm_enable = false,
 892                 .timing_trace = true,
 893                 .clock_trace = true,
 894                 .disable_dpp_power_gate = true,
 895                 .disable_hubp_power_gate = true,
 896                 .disable_clock_gate = true,
 897                 .disable_pplib_clock_request = true,
 898                 .disable_pplib_wm_range = true,
 899                 .disable_stutter = true,
 900                 .disable_48mhz_pwrdwn = true,
 901                 .disable_psr = true,
 902                 .enable_tri_buf = true
 903 };
 904
 905 enum dcn20_clk_src_array_id {
 906         DCN20_CLK_SRC_PLL0,
 907         DCN20_CLK_SRC_PLL1,
 908         DCN20_CLK_SRC_PLL2,
 909         DCN20_CLK_SRC_TOTAL_DCN21
 910 };
 911
 912 static void dcn21_resource_destruct(struct dcn21_resource_pool *pool)
 913 {
 914         unsigned int i;
 915
 916         for (i = 0; i < pool->base.stream_enc_count; i++) {
 917                 if (pool->base.stream_enc[i] != NULL) {
 918                         kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
 919                         pool->base.stream_enc[i] = NULL;
 920                 }
 921         }
 922
 923         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
 924                 if (pool->base.dscs[i] != NULL)
 925                         dcn20_dsc_destroy(&pool->base.dscs[i]);
 926         }
 927
 928         if (pool->base.mpc != NULL) {
 929                 kfree(TO_DCN20_MPC(pool->base.mpc));
 930                 pool->base.mpc = NULL;
 931         }
 932         if (pool->base.hubbub != NULL) {
 933                 kfree(pool->base.hubbub);
 934                 pool->base.hubbub = NULL;
 935         }
 936         for (i = 0; i < pool->base.pipe_count; i++) {
 937                 if (pool->base.dpps[i] != NULL)
 938                         dcn20_dpp_destroy(&pool->base.dpps[i]);
 939
 940                 if (pool->base.ipps[i] != NULL)
 941                         pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
 942
 943                 if (pool->base.hubps[i] != NULL) {
 944                         kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
 945                         pool->base.hubps[i] = NULL;
 946                 }
 947
 948                 if (pool->base.irqs != NULL) {
 949                         dal_irq_service_destroy(&pool->base.irqs);
 950                 }
 951         }
 952
 953         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
 954                 if (pool->base.engines[i] != NULL)
 955                         dce110_engine_destroy(&pool->base.engines[i]);
 956                 if (pool->base.hw_i2cs[i] != NULL) {
 957                         kfree(pool->base.hw_i2cs[i]);
 958                         pool->base.hw_i2cs[i] = NULL;
 959                 }
 960                 if (pool->base.sw_i2cs[i] != NULL) {
 961                         kfree(pool->base.sw_i2cs[i]);
 962                         pool->base.sw_i2cs[i] = NULL;
 963                 }
 964         }
 965
 966         for (i = 0; i < pool->base.res_cap->num_opp; i++) {
 967                 if (pool->base.opps[i] != NULL)
 968                         pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
 969         }
 970
 971         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
 972                 if (pool->base.timing_generators[i] != NULL)    {
 973                         kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
 974                         pool->base.timing_generators[i] = NULL;
 975                 }
 976         }
 977
 978         for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
 979                 if (pool->base.dwbc[i] != NULL) {
 980                         kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
 981                         pool->base.dwbc[i] = NULL;
 982                 }
 983                 if (pool->base.mcif_wb[i] != NULL) {
 984                         kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));
 985                         pool->base.mcif_wb[i] = NULL;
 986                 }
 987         }
 988
 989         for (i = 0; i < pool->base.audio_count; i++) {
 990                 if (pool->base.audios[i])
 991                         dce_aud_destroy(&pool->base.audios[i]);
 992         }
 993
 994         for (i = 0; i < pool->base.clk_src_count; i++) {
 995                 if (pool->base.clock_sources[i] != NULL) {
 996                         dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
 997                         pool->base.clock_sources[i] = NULL;
 998                 }
 999         }
1000
1001         if (pool->base.dp_clock_source != NULL) {
1002                 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1003                 pool->base.dp_clock_source = NULL;
1004         }
1005
1006         if (pool->base.abm != NULL) {
1007                 if (pool->base.abm->ctx->dc->config.disable_dmcu)
1008                         dmub_abm_destroy(&pool->base.abm);
1009                 else
1010                         dce_abm_destroy(&pool->base.abm);
1011         }
1012
1013         if (pool->base.dmcu != NULL)
1014                 dce_dmcu_destroy(&pool->base.dmcu);
1015
1016         if (pool->base.psr != NULL)
1017                 dmub_psr_destroy(&pool->base.psr);
1018
1019         if (pool->base.dccg != NULL)
1020                 dcn_dccg_destroy(&pool->base.dccg);
1021
1022         if (pool->base.pp_smu != NULL)
1023                 dcn21_pp_smu_destroy(&pool->base.pp_smu);
1024 }
1025
1026
1027 static void calculate_wm_set_for_vlevel(
1028                 int vlevel,
1029                 struct wm_range_table_entry *table_entry,
1030                 struct dcn_watermarks *wm_set,
1031                 struct display_mode_lib *dml,
1032                 display_e2e_pipe_params_st *pipes,
1033                 int pipe_cnt)
1034 {
1035         double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us;
1036
1037         ASSERT(vlevel < dml->soc.num_states);
1038         /* only pipe 0 is read for voltage and dcf/soc clocks */
1039         pipes[0].clks_cfg.voltage = vlevel;
1040         pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz;
1041         pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz;
1042
1043         dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us;
1044         dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us;
1045         dml->soc.sr_enter_plus_exit_time_us = table_entry->sr_enter_plus_exit_time_us;
1046
1047         wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000;
1048         wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000;
1049         wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000;
1050         wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000;
1051         wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000;
1052         wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000;
1053         wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000;
1054         wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) * 1000;
1055         dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached;
1056
1057 }
1058
1059 static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
1060 {
1061         int i;
1062
1063         DC_FP_START();
1064
1065         if (dc->bb_overrides.sr_exit_time_ns) {
1066                 for (i = 0; i < WM_SET_COUNT; i++) {
1067                           dc->clk_mgr->bw_params->wm_table.entries[i].sr_exit_time_us =
1068                                           dc->bb_overrides.sr_exit_time_ns / 1000.0;
1069                 }
1070         }
1071
1072         if (dc->bb_overrides.sr_enter_plus_exit_time_ns) {
1073                 for (i = 0; i < WM_SET_COUNT; i++) {
1074                           dc->clk_mgr->bw_params->wm_table.entries[i].sr_enter_plus_exit_time_us =
1075                                           dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
1076                 }
1077         }
1078
1079         if (dc->bb_overrides.urgent_latency_ns) {
1080                 bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
1081         }
1082
1083         if (dc->bb_overrides.dram_clock_change_latency_ns) {
1084                 for (i = 0; i < WM_SET_COUNT; i++) {
1085                         dc->clk_mgr->bw_params->wm_table.entries[i].pstate_latency_us =
1086                                 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
1087                 }
1088         }
1089
1090         DC_FP_END();
1091 }
1092
1093 void dcn21_calculate_wm(
1094                 struct dc *dc, struct dc_state *context,
1095                 display_e2e_pipe_params_st *pipes,
1096                 int *out_pipe_cnt,
1097                 int *pipe_split_from,
1098                 int vlevel_req,
1099                 bool fast_validate)
1100 {
1101         int pipe_cnt, i, pipe_idx;
1102         int vlevel, vlevel_max;
1103         struct wm_range_table_entry *table_entry;
1104         struct clk_bw_params *bw_params = dc->clk_mgr->bw_params;
1105
1106         ASSERT(bw_params);
1107
1108         patch_bounding_box(dc, &context->bw_ctx.dml.soc);
1109
1110         for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1111                         if (!context->res_ctx.pipe_ctx[i].stream)
1112                                 continue;
1113
1114                         pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
1115                         pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb];
1116
1117                         if (pipe_split_from[i] < 0) {
1118                                 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
1119                                                 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
1120                                 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
1121                                         pipes[pipe_cnt].pipe.dest.odm_combine =
1122                                                         context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_idx];
1123                                 else
1124                                         pipes[pipe_cnt].pipe.dest.odm_combine = 0;
1125                                 pipe_idx++;
1126                         } else {
1127                                 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
1128                                                 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
1129                                 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])
1130                                         pipes[pipe_cnt].pipe.dest.odm_combine =
1131                                                         context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_split_from[i]];
1132                                 else
1133                                         pipes[pipe_cnt].pipe.dest.odm_combine = 0;
1134                         }
1135                         pipe_cnt++;
1136         }
1137
1138         if (pipe_cnt != pipe_idx) {
1139                 if (dc->res_pool->funcs->populate_dml_pipes)
1140                         pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
1141                                 context, pipes, fast_validate);
1142                 else
1143                         pipe_cnt = dcn21_populate_dml_pipes_from_context(dc,
1144                                 context, pipes, fast_validate);
1145         }
1146
1147         *out_pipe_cnt = pipe_cnt;
1148
1149         vlevel_max = bw_params->clk_table.num_entries - 1;
1150
1151
1152         /* WM Set D */
1153         table_entry = &bw_params->wm_table.entries[WM_D];
1154         if (table_entry->wm_type == WM_TYPE_RETRAINING)
1155                 vlevel = 0;
1156         else
1157                 vlevel = vlevel_max;
1158         calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d,
1159                                                 &context->bw_ctx.dml, pipes, pipe_cnt);
1160         /* WM Set C */
1161         table_entry = &bw_params->wm_table.entries[WM_C];
1162         vlevel = MIN(MAX(vlevel_req, 3), vlevel_max);
1163         calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c,
1164                                                 &context->bw_ctx.dml, pipes, pipe_cnt);
1165         /* WM Set B */
1166         table_entry = &bw_params->wm_table.entries[WM_B];
1167         vlevel = MIN(MAX(vlevel_req, 2), vlevel_max);
1168         calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b,
1169                                                 &context->bw_ctx.dml, pipes, pipe_cnt);
1170
1171         /* WM Set A */
1172         table_entry = &bw_params->wm_table.entries[WM_A];
1173         vlevel = MIN(vlevel_req, vlevel_max);
1174         calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a,
1175                                                 &context->bw_ctx.dml, pipes, pipe_cnt);
1176 }
1177
1178
1179 static bool dcn21_fast_validate_bw(
1180                 struct dc *dc,
1181                 struct dc_state *context,
1182                 display_e2e_pipe_params_st *pipes,
1183                 int *pipe_cnt_out,
1184                 int *pipe_split_from,
1185                 int *vlevel_out,
1186                 bool fast_validate)
1187 {
1188         bool out = false;
1189         int split[MAX_PIPES] = { 0 };
1190         int pipe_cnt, i, pipe_idx, vlevel;
1191
1192         ASSERT(pipes);
1193         if (!pipes)
1194                 return false;
1195
1196         dcn20_merge_pipes_for_validate(dc, context);
1197
1198         pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
1199
1200         *pipe_cnt_out = pipe_cnt;
1201
1202         if (!pipe_cnt) {
1203                 out = true;
1204                 goto validate_out;
1205         }
1206         /*
1207          * DML favors voltage over p-state, but we're more interested in
1208          * supporting p-state over voltage. We can't support p-state in
1209          * prefetch mode > 0 so try capping the prefetch mode to start.
1210          */
1211         context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
1212                                 dm_allow_self_refresh_and_mclk_switch;
1213         vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
1214
1215         if (vlevel > context->bw_ctx.dml.soc.num_states) {
1216                 /*
1217                  * If mode is unsupported or there's still no p-state support then
1218                  * fall back to favoring voltage.
1219                  *
1220                  * We don't actually support prefetch mode 2, so require that we
1221                  * at least support prefetch mode 1.
1222                  */
1223                 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
1224                                         dm_allow_self_refresh;
1225                 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
1226                 if (vlevel > context->bw_ctx.dml.soc.num_states)
1227                         goto validate_fail;
1228         }
1229
1230         vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, NULL);
1231
1232         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1233                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1234                 struct pipe_ctx *mpo_pipe = pipe->bottom_pipe;
1235                 struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
1236
1237                 if (!pipe->stream)
1238                         continue;
1239
1240                 /* We only support full screen mpo with ODM */
1241                 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled
1242                                 && pipe->plane_state && mpo_pipe
1243                                 && memcmp(&mpo_pipe->plane_res.scl_data.recout,
1244                                                 &pipe->plane_res.scl_data.recout,
1245                                                 sizeof(struct rect)) != 0) {
1246                         ASSERT(mpo_pipe->plane_state != pipe->plane_state);
1247                         goto validate_fail;
1248                 }
1249                 pipe_idx++;
1250         }
1251
1252         /*initialize pipe_just_split_from to invalid idx*/
1253         for (i = 0; i < MAX_PIPES; i++)
1254                 pipe_split_from[i] = -1;
1255
1256         for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
1257                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1258                 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
1259
1260                 if (!pipe->stream || pipe_split_from[i] >= 0)
1261                         continue;
1262
1263                 pipe_idx++;
1264
1265                 if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
1266                         hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
1267                         ASSERT(hsplit_pipe);
1268                         if (!dcn20_split_stream_for_odm(
1269                                         dc, &context->res_ctx,
1270                                         pipe, hsplit_pipe))
1271                                 goto validate_fail;
1272                         pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
1273                         dcn20_build_mapped_resource(dc, context, pipe->stream);
1274                 }
1275
1276                 if (!pipe->plane_state)
1277                         continue;
1278                 /* Skip 2nd half of already split pipe */
1279                 if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state)
1280                         continue;
1281
1282                 if (split[i] == 2) {
1283                         if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) {
1284                                 /* pipe not split previously needs split */
1285                                 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
1286                                 ASSERT(hsplit_pipe);
1287                                 if (!hsplit_pipe) {
1288                                         context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] *= 2;
1289                                         continue;
1290                                 }
1291                                 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
1292                                         if (!dcn20_split_stream_for_odm(
1293                                                         dc, &context->res_ctx,
1294                                                         pipe, hsplit_pipe))
1295                                                 goto validate_fail;
1296                                         dcn20_build_mapped_resource(dc, context, pipe->stream);
1297                                 } else {
1298                                         dcn20_split_stream_for_mpc(
1299                                                         &context->res_ctx, dc->res_pool,
1300                                                         pipe, hsplit_pipe);
1301                                         resource_build_scaling_params(pipe);
1302                                         resource_build_scaling_params(hsplit_pipe);
1303                                 }
1304                                 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
1305                         }
1306                 } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
1307                         /* merge should already have been done */
1308                         ASSERT(0);
1309                 }
1310         }
1311         /* Actual dsc count per stream dsc validation*/
1312         if (!dcn20_validate_dsc(dc, context)) {
1313                 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] =
1314                                 DML_FAIL_DSC_VALIDATION_FAILURE;
1315                 goto validate_fail;
1316         }
1317
1318         *vlevel_out = vlevel;
1319
1320         out = true;
1321         goto validate_out;
1322
1323 validate_fail:
1324         out = false;
1325
1326 validate_out:
1327         return out;
1328 }
1329
1330 bool dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context,
1331                 bool fast_validate)
1332 {
1333         bool out = false;
1334
1335         BW_VAL_TRACE_SETUP();
1336
1337         int vlevel = 0;
1338         int pipe_split_from[MAX_PIPES];
1339         int pipe_cnt = 0;
1340         display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
1341         DC_LOGGER_INIT(dc->ctx->logger);
1342
1343         BW_VAL_TRACE_COUNT();
1344
1345         /*Unsafe due to current pipe merge and split logic*/
1346         ASSERT(context != dc->current_state);
1347
1348         out = dcn21_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel, fast_validate);
1349
1350         if (pipe_cnt == 0)
1351                 goto validate_out;
1352
1353         if (!out)
1354                 goto validate_fail;
1355
1356         BW_VAL_TRACE_END_VOLTAGE_LEVEL();
1357
1358         if (fast_validate) {
1359                 BW_VAL_TRACE_SKIP(fast);
1360                 goto validate_out;
1361         }
1362
1363         dcn21_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, fast_validate);
1364         dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
1365
1366         BW_VAL_TRACE_END_WATERMARKS();
1367
1368         goto validate_out;
1369
1370 validate_fail:
1371         DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
1372                 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
1373
1374         BW_VAL_TRACE_SKIP(fail);
1375         out = false;
1376
1377 validate_out:
1378         kfree(pipes);
1379
1380         BW_VAL_TRACE_FINISH();
1381
1382         return out;
1383 }
1384 static void dcn21_destroy_resource_pool(struct resource_pool **pool)
1385 {
1386         struct dcn21_resource_pool *dcn21_pool = TO_DCN21_RES_POOL(*pool);
1387
1388         dcn21_resource_destruct(dcn21_pool);
1389         kfree(dcn21_pool);
1390         *pool = NULL;
1391 }
1392
1393 static struct clock_source *dcn21_clock_source_create(
1394                 struct dc_context *ctx,
1395                 struct dc_bios *bios,
1396                 enum clock_source_id id,
1397                 const struct dce110_clk_src_regs *regs,
1398                 bool dp_clk_src)
1399 {
1400         struct dce110_clk_src *clk_src =
1401                 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1402
1403         if (!clk_src)
1404                 return NULL;
1405
1406         if (dcn20_clk_src_construct(clk_src, ctx, bios, id,
1407                         regs, &cs_shift, &cs_mask)) {
1408                 clk_src->base.dp_clk_src = dp_clk_src;
1409                 return &clk_src->base;
1410         }
1411
1412         BREAK_TO_DEBUGGER();
1413         return NULL;
1414 }
1415
1416 static struct hubp *dcn21_hubp_create(
1417         struct dc_context *ctx,
1418         uint32_t inst)
1419 {
1420         struct dcn21_hubp *hubp21 =
1421                 kzalloc(sizeof(struct dcn21_hubp), GFP_KERNEL);
1422
1423         if (!hubp21)
1424                 return NULL;
1425
1426         if (hubp21_construct(hubp21, ctx, inst,
1427                         &hubp_regs[inst], &hubp_shift, &hubp_mask))
1428                 return &hubp21->base;
1429
1430         BREAK_TO_DEBUGGER();
1431         kfree(hubp21);
1432         return NULL;
1433 }
1434
1435 static struct hubbub *dcn21_hubbub_create(struct dc_context *ctx)
1436 {
1437         int i;
1438
1439         struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub),
1440                                           GFP_KERNEL);
1441
1442         if (!hubbub)
1443                 return NULL;
1444
1445         hubbub21_construct(hubbub, ctx,
1446                         &hubbub_reg,
1447                         &hubbub_shift,
1448                         &hubbub_mask);
1449
1450         for (i = 0; i < res_cap_rn.num_vmid; i++) {
1451                 struct dcn20_vmid *vmid = &hubbub->vmid[i];
1452
1453                 vmid->ctx = ctx;
1454
1455                 vmid->regs = &vmid_regs[i];
1456                 vmid->shifts = &vmid_shifts;
1457                 vmid->masks = &vmid_masks;
1458         }
1459         hubbub->num_vmid = res_cap_rn.num_vmid;
1460
1461         return &hubbub->base;
1462 }
1463
1464 struct output_pixel_processor *dcn21_opp_create(
1465         struct dc_context *ctx, uint32_t inst)
1466 {
1467         struct dcn20_opp *opp =
1468                 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
1469
1470         if (!opp) {
1471                 BREAK_TO_DEBUGGER();
1472                 return NULL;
1473         }
1474
1475         dcn20_opp_construct(opp, ctx, inst,
1476                         &opp_regs[inst], &opp_shift, &opp_mask);
1477         return &opp->base;
1478 }
1479
1480 struct timing_generator *dcn21_timing_generator_create(
1481                 struct dc_context *ctx,
1482                 uint32_t instance)
1483 {
1484         struct optc *tgn10 =
1485                 kzalloc(sizeof(struct optc), GFP_KERNEL);
1486
1487         if (!tgn10)
1488                 return NULL;
1489
1490         tgn10->base.inst = instance;
1491         tgn10->base.ctx = ctx;
1492
1493         tgn10->tg_regs = &tg_regs[instance];
1494         tgn10->tg_shift = &tg_shift;
1495         tgn10->tg_mask = &tg_mask;
1496
1497         dcn20_timing_generator_init(tgn10);
1498
1499         return &tgn10->base;
1500 }
1501
1502 struct mpc *dcn21_mpc_create(struct dc_context *ctx)
1503 {
1504         struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc),
1505                                           GFP_KERNEL);
1506
1507         if (!mpc20)
1508                 return NULL;
1509
1510         dcn20_mpc_construct(mpc20, ctx,
1511                         &mpc_regs,
1512                         &mpc_shift,
1513                         &mpc_mask,
1514                         6);
1515
1516         return &mpc20->base;
1517 }
1518
1519 static void read_dce_straps(
1520         struct dc_context *ctx,
1521         struct resource_straps *straps)
1522 {
1523         generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
1524                 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1525
1526 }
1527
1528
1529 struct display_stream_compressor *dcn21_dsc_create(
1530         struct dc_context *ctx, uint32_t inst)
1531 {
1532         struct dcn20_dsc *dsc =
1533                 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1534
1535         if (!dsc) {
1536                 BREAK_TO_DEBUGGER();
1537                 return NULL;
1538         }
1539
1540         dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1541         return &dsc->base;
1542 }
1543
1544 static struct _vcs_dpi_voltage_scaling_st construct_low_pstate_lvl(struct clk_limit_table *clk_table, unsigned int high_voltage_lvl)
1545 {
1546         struct _vcs_dpi_voltage_scaling_st low_pstate_lvl;
1547         int i;
1548
1549         low_pstate_lvl.state = 1;
1550         low_pstate_lvl.dcfclk_mhz = clk_table->entries[0].dcfclk_mhz;
1551         low_pstate_lvl.fabricclk_mhz = clk_table->entries[0].fclk_mhz;
1552         low_pstate_lvl.socclk_mhz = clk_table->entries[0].socclk_mhz;
1553         low_pstate_lvl.dram_speed_mts = clk_table->entries[0].memclk_mhz * 2;
1554
1555         low_pstate_lvl.dispclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dispclk_mhz;
1556         low_pstate_lvl.dppclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dppclk_mhz;
1557         low_pstate_lvl.dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[high_voltage_lvl].dram_bw_per_chan_gbps;
1558         low_pstate_lvl.dscclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dscclk_mhz;
1559         low_pstate_lvl.dtbclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dtbclk_mhz;
1560         low_pstate_lvl.phyclk_d18_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].phyclk_d18_mhz;
1561         low_pstate_lvl.phyclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].phyclk_mhz;
1562
1563         for (i = clk_table->num_entries; i > 1; i--)
1564                 clk_table->entries[i] = clk_table->entries[i-1];
1565         clk_table->entries[1] = clk_table->entries[0];
1566         clk_table->num_entries++;
1567
1568         return low_pstate_lvl;
1569 }
1570
1571 static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1572 {
1573         struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool);
1574         struct clk_limit_table *clk_table = &bw_params->clk_table;
1575         struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
1576         unsigned int i, closest_clk_lvl = 0, k = 0;
1577         int j;
1578
1579         dcn2_1_ip.max_num_otg = pool->base.res_cap->num_timing_generator;
1580         dcn2_1_ip.max_num_dpp = pool->base.pipe_count;
1581         dcn2_1_soc.num_chans = bw_params->num_channels;
1582
1583         ASSERT(clk_table->num_entries);
1584         for (i = 0; i < clk_table->num_entries; i++) {
1585                 /* loop backwards*/
1586                 for (closest_clk_lvl = 0, j = dcn2_1_soc.num_states - 1; j >= 0; j--) {
1587                         if ((unsigned int) dcn2_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) {
1588                                 closest_clk_lvl = j;
1589                                 break;
1590                         }
1591                 }
1592
1593                 /* clk_table[1] is reserved for min DF PState.  skip here to fill in later. */
1594                 if (i == 1)
1595                         k++;
1596
1597                 clock_limits[k].state = k;
1598                 clock_limits[k].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
1599                 clock_limits[k].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
1600                 clock_limits[k].socclk_mhz = clk_table->entries[i].socclk_mhz;
1601                 clock_limits[k].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;
1602
1603                 clock_limits[k].dispclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
1604                 clock_limits[k].dppclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
1605                 clock_limits[k].dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
1606                 clock_limits[k].dscclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
1607                 clock_limits[k].dtbclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
1608                 clock_limits[k].phyclk_d18_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
1609                 clock_limits[k].phyclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
1610
1611                 k++;
1612         }
1613         for (i = 0; i < clk_table->num_entries + 1; i++)
1614                 dcn2_1_soc.clock_limits[i] = clock_limits[i];
1615         if (clk_table->num_entries) {
1616                 dcn2_1_soc.num_states = clk_table->num_entries + 1;
1617                 /* duplicate last level */
1618                 dcn2_1_soc.clock_limits[dcn2_1_soc.num_states] = dcn2_1_soc.clock_limits[dcn2_1_soc.num_states - 1];
1619                 dcn2_1_soc.clock_limits[dcn2_1_soc.num_states].state = dcn2_1_soc.num_states;
1620                 /* fill in min DF PState */
1621                 dcn2_1_soc.clock_limits[1] = construct_low_pstate_lvl(clk_table, closest_clk_lvl);
1622         }
1623
1624         dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);
1625 }
1626
1627 static struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx)
1628 {
1629         struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
1630
1631         if (!pp_smu)
1632                 return pp_smu;
1633
1634         dm_pp_get_funcs(ctx, pp_smu);
1635
1636         if (pp_smu->ctx.ver != PP_SMU_VER_RN)
1637                 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs));
1638
1639
1640         return pp_smu;
1641 }
1642
1643 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
1644 {
1645         if (pp_smu && *pp_smu) {
1646                 kfree(*pp_smu);
1647                 *pp_smu = NULL;
1648         }
1649 }
1650
1651 static struct audio *dcn21_create_audio(
1652                 struct dc_context *ctx, unsigned int inst)
1653 {
1654         return dce_audio_create(ctx, inst,
1655                         &audio_regs[inst], &audio_shift, &audio_mask);
1656 }
1657
1658 static struct dc_cap_funcs cap_funcs = {
1659         .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1660 };
1661
1662 struct stream_encoder *dcn21_stream_encoder_create(
1663         enum engine_id eng_id,
1664         struct dc_context *ctx)
1665 {
1666         struct dcn10_stream_encoder *enc1 =
1667                 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1668
1669         if (!enc1)
1670                 return NULL;
1671
1672         dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
1673                                         &stream_enc_regs[eng_id],
1674                                         &se_shift, &se_mask);
1675
1676         return &enc1->base;
1677 }
1678
1679 static const struct dce_hwseq_registers hwseq_reg = {
1680                 HWSEQ_DCN21_REG_LIST()
1681 };
1682
1683 static const struct dce_hwseq_shift hwseq_shift = {
1684                 HWSEQ_DCN21_MASK_SH_LIST(__SHIFT)
1685 };
1686
1687 static const struct dce_hwseq_mask hwseq_mask = {
1688                 HWSEQ_DCN21_MASK_SH_LIST(_MASK)
1689 };
1690
1691 static struct dce_hwseq *dcn21_hwseq_create(
1692         struct dc_context *ctx)
1693 {
1694         struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1695
1696         if (hws) {
1697                 hws->ctx = ctx;
1698                 hws->regs = &hwseq_reg;
1699                 hws->shifts = &hwseq_shift;
1700                 hws->masks = &hwseq_mask;
1701                 hws->wa.DEGVIDCN21 = true;
1702                 hws->wa.disallow_self_refresh_during_multi_plane_transition = true;
1703         }
1704         return hws;
1705 }
1706
1707 static const struct resource_create_funcs res_create_funcs = {
1708         .read_dce_straps = read_dce_straps,
1709         .create_audio = dcn21_create_audio,
1710         .create_stream_encoder = dcn21_stream_encoder_create,
1711         .create_hwseq = dcn21_hwseq_create,
1712 };
1713
1714 static const struct resource_create_funcs res_create_maximus_funcs = {
1715         .read_dce_straps = NULL,
1716         .create_audio = NULL,
1717         .create_stream_encoder = NULL,
1718         .create_hwseq = dcn21_hwseq_create,
1719 };
1720
1721 static const struct encoder_feature_support link_enc_feature = {
1722                 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1723                 .max_hdmi_pixel_clock = 600000,
1724                 .hdmi_ycbcr420_supported = true,
1725                 .dp_ycbcr420_supported = true,
1726                 .fec_supported = true,
1727                 .flags.bits.IS_HBR2_CAPABLE = true,
1728                 .flags.bits.IS_HBR3_CAPABLE = true,
1729                 .flags.bits.IS_TPS3_CAPABLE = true,
1730                 .flags.bits.IS_TPS4_CAPABLE = true
1731 };
1732
1733
1734 #define link_regs(id, phyid)\
1735 [id] = {\
1736         LE_DCN2_REG_LIST(id), \
1737         UNIPHY_DCN2_REG_LIST(phyid), \
1738         DPCS_DCN21_REG_LIST(id), \
1739         SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
1740 }
1741
1742 static const struct dcn10_link_enc_registers link_enc_regs[] = {
1743         link_regs(0, A),
1744         link_regs(1, B),
1745         link_regs(2, C),
1746         link_regs(3, D),
1747         link_regs(4, E),
1748 };
1749
1750 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
1751         { DCN_PANEL_CNTL_REG_LIST() }
1752 };
1753
1754 static const struct dce_panel_cntl_shift panel_cntl_shift = {
1755         DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
1756 };
1757
1758 static const struct dce_panel_cntl_mask panel_cntl_mask = {
1759         DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
1760 };
1761
1762 #define aux_regs(id)\
1763 [id] = {\
1764         DCN2_AUX_REG_LIST(id)\
1765 }
1766
1767 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
1768                 aux_regs(0),
1769                 aux_regs(1),
1770                 aux_regs(2),
1771                 aux_regs(3),
1772                 aux_regs(4)
1773 };
1774
1775 #define hpd_regs(id)\
1776 [id] = {\
1777         HPD_REG_LIST(id)\
1778 }
1779
1780 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
1781                 hpd_regs(0),
1782                 hpd_regs(1),
1783                 hpd_regs(2),
1784                 hpd_regs(3),
1785                 hpd_regs(4)
1786 };
1787
1788 static const struct dcn10_link_enc_shift le_shift = {
1789         LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT),\
1790         DPCS_DCN21_MASK_SH_LIST(__SHIFT)
1791 };
1792
1793 static const struct dcn10_link_enc_mask le_mask = {
1794         LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\
1795         DPCS_DCN21_MASK_SH_LIST(_MASK)
1796 };
1797
1798 static int map_transmitter_id_to_phy_instance(
1799         enum transmitter transmitter)
1800 {
1801         switch (transmitter) {
1802         case TRANSMITTER_UNIPHY_A:
1803                 return 0;
1804         break;
1805         case TRANSMITTER_UNIPHY_B:
1806                 return 1;
1807         break;
1808         case TRANSMITTER_UNIPHY_C:
1809                 return 2;
1810         break;
1811         case TRANSMITTER_UNIPHY_D:
1812                 return 3;
1813         break;
1814         case TRANSMITTER_UNIPHY_E:
1815                 return 4;
1816         break;
1817         default:
1818                 ASSERT(0);
1819                 return 0;
1820         }
1821 }
1822
1823 static struct link_encoder *dcn21_link_encoder_create(
1824         const struct encoder_init_data *enc_init_data)
1825 {
1826         struct dcn21_link_encoder *enc21 =
1827                 kzalloc(sizeof(struct dcn21_link_encoder), GFP_KERNEL);
1828         int link_regs_id;
1829
1830         if (!enc21)
1831                 return NULL;
1832
1833         link_regs_id =
1834                 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
1835
1836         dcn21_link_encoder_construct(enc21,
1837                                       enc_init_data,
1838                                       &link_enc_feature,
1839                                       &link_enc_regs[link_regs_id],
1840                                       &link_enc_aux_regs[enc_init_data->channel - 1],
1841                                       &link_enc_hpd_regs[enc_init_data->hpd_source],
1842                                       &le_shift,
1843                                       &le_mask);
1844
1845         return &enc21->enc10.base;
1846 }
1847
1848 static struct panel_cntl *dcn21_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1849 {
1850         struct dce_panel_cntl *panel_cntl =
1851                 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
1852
1853         if (!panel_cntl)
1854                 return NULL;
1855
1856         dce_panel_cntl_construct(panel_cntl,
1857                         init_data,
1858                         &panel_cntl_regs[init_data->inst],
1859                         &panel_cntl_shift,
1860                         &panel_cntl_mask);
1861
1862         return &panel_cntl->base;
1863 }
1864
1865 #define CTX ctx
1866
1867 #define REG(reg_name) \
1868         (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
1869
1870 static uint32_t read_pipe_fuses(struct dc_context *ctx)
1871 {
1872         uint32_t value = REG_READ(CC_DC_PIPE_DIS);
1873         /* RV1 support max 4 pipes */
1874         value = value & 0xf;
1875         return value;
1876 }
1877
1878 static int dcn21_populate_dml_pipes_from_context(
1879                 struct dc *dc,
1880                 struct dc_state *context,
1881                 display_e2e_pipe_params_st *pipes,
1882                 bool fast_validate)
1883 {
1884         uint32_t pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
1885         int i;
1886
1887         for (i = 0; i < pipe_cnt; i++) {
1888
1889                 pipes[i].pipe.src.hostvm = dc->res_pool->hubbub->riommu_active;
1890                 pipes[i].pipe.src.gpuvm = 1;
1891         }
1892
1893         return pipe_cnt;
1894 }
1895
1896 enum dc_status dcn21_patch_unknown_plane_state(struct dc_plane_state *plane_state)
1897 {
1898         enum dc_status result = DC_OK;
1899
1900         if (plane_state->ctx->dc->debug.disable_dcc == DCC_ENABLE) {
1901                 plane_state->dcc.enable = 1;
1902                 /* align to our worst case block width */
1903                 plane_state->dcc.meta_pitch = ((plane_state->src_rect.width + 1023) / 1024) * 1024;
1904         }
1905         result = dcn20_patch_unknown_plane_state(plane_state);
1906         return result;
1907 }
1908
1909 static const struct resource_funcs dcn21_res_pool_funcs = {
1910         .destroy = dcn21_destroy_resource_pool,
1911         .link_enc_create = dcn21_link_encoder_create,
1912         .panel_cntl_create = dcn21_panel_cntl_create,
1913         .validate_bandwidth = dcn21_validate_bandwidth,
1914         .populate_dml_pipes = dcn21_populate_dml_pipes_from_context,
1915         .add_stream_to_ctx = dcn20_add_stream_to_ctx,
1916         .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1917         .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1918         .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
1919         .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context,
1920         .patch_unknown_plane_state = dcn21_patch_unknown_plane_state,
1921         .set_mcif_arb_params = dcn20_set_mcif_arb_params,
1922         .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1923         .update_bw_bounding_box = update_bw_bounding_box
1924 };
1925
1926 static bool dcn21_resource_construct(
1927         uint8_t num_virtual_links,
1928         struct dc *dc,
1929         struct dcn21_resource_pool *pool)
1930 {
1931         int i, j;
1932         struct dc_context *ctx = dc->ctx;
1933         struct irq_service_init_data init_data;
1934         uint32_t pipe_fuses = read_pipe_fuses(ctx);
1935         uint32_t num_pipes;
1936
1937         ctx->dc_bios->regs = &bios_regs;
1938
1939         pool->base.res_cap = &res_cap_rn;
1940 #ifdef DIAGS_BUILD
1941         if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
1942                 //pool->base.res_cap = &res_cap_nv10_FPGA_2pipe_dsc;
1943                 pool->base.res_cap = &res_cap_rn_FPGA_4pipe;
1944 #endif
1945
1946         pool->base.funcs = &dcn21_res_pool_funcs;
1947
1948         /*************************************************
1949          *  Resource + asic cap harcoding                *
1950          *************************************************/
1951         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1952
1953         /* max pipe num for ASIC before check pipe fuses */
1954         pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1955
1956         dc->caps.max_downscale_ratio = 200;
1957         dc->caps.i2c_speed_in_khz = 100;
1958         dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by default*/
1959         dc->caps.max_cursor_size = 256;
1960         dc->caps.min_horizontal_blanking_period = 80;
1961         dc->caps.dmdata_alloc_size = 2048;
1962
1963         dc->caps.max_slave_planes = 1;
1964         dc->caps.post_blend_color_processing = true;
1965         dc->caps.force_dp_tps4_for_cp2520 = true;
1966         dc->caps.extended_aux_timeout_support = true;
1967         dc->caps.dmcub_support = true;
1968         dc->caps.is_apu = true;
1969
1970         /* Color pipeline capabilities */
1971         dc->caps.color.dpp.dcn_arch = 1;
1972         dc->caps.color.dpp.input_lut_shared = 0;
1973         dc->caps.color.dpp.icsc = 1;
1974         dc->caps.color.dpp.dgam_ram = 1;
1975         dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1976         dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1977         dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;
1978         dc->caps.color.dpp.dgam_rom_caps.pq = 0;
1979         dc->caps.color.dpp.dgam_rom_caps.hlg = 0;
1980         dc->caps.color.dpp.post_csc = 0;
1981         dc->caps.color.dpp.gamma_corr = 0;
1982         dc->caps.color.dpp.dgam_rom_for_yuv = 1;
1983
1984         dc->caps.color.dpp.hw_3d_lut = 1;
1985         dc->caps.color.dpp.ogam_ram = 1;
1986         // no OGAM ROM on DCN2
1987         dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1988         dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1989         dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1990         dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1991         dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1992         dc->caps.color.dpp.ocsc = 0;
1993
1994         dc->caps.color.mpc.gamut_remap = 0;
1995         dc->caps.color.mpc.num_3dluts = 0;
1996         dc->caps.color.mpc.shared_3d_lut = 0;
1997         dc->caps.color.mpc.ogam_ram = 1;
1998         dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1999         dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
2000         dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
2001         dc->caps.color.mpc.ogam_rom_caps.pq = 0;
2002         dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
2003         dc->caps.color.mpc.ocsc = 1;
2004
2005         if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
2006                 dc->debug = debug_defaults_drv;
2007         else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
2008                 pool->base.pipe_count = 4;
2009                 dc->debug = debug_defaults_diags;
2010         } else
2011                 dc->debug = debug_defaults_diags;
2012
2013         // Init the vm_helper
2014         if (dc->vm_helper)
2015                 vm_helper_init(dc->vm_helper, 16);
2016
2017         /*************************************************
2018          *  Create resources                             *
2019          *************************************************/
2020
2021         pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =
2022                         dcn21_clock_source_create(ctx, ctx->dc_bios,
2023                                 CLOCK_SOURCE_COMBO_PHY_PLL0,
2024                                 &clk_src_regs[0], false);
2025         pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =
2026                         dcn21_clock_source_create(ctx, ctx->dc_bios,
2027                                 CLOCK_SOURCE_COMBO_PHY_PLL1,
2028                                 &clk_src_regs[1], false);
2029         pool->base.clock_sources[DCN20_CLK_SRC_PLL2] =
2030                         dcn21_clock_source_create(ctx, ctx->dc_bios,
2031                                 CLOCK_SOURCE_COMBO_PHY_PLL2,
2032                                 &clk_src_regs[2], false);
2033
2034         pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN21;
2035
2036         /* todo: not reuse phy_pll registers */
2037         pool->base.dp_clock_source =
2038                         dcn21_clock_source_create(ctx, ctx->dc_bios,
2039                                 CLOCK_SOURCE_ID_DP_DTO,
2040                                 &clk_src_regs[0], true);
2041
2042         for (i = 0; i < pool->base.clk_src_count; i++) {
2043                 if (pool->base.clock_sources[i] == NULL) {
2044                         dm_error("DC: failed to create clock sources!\n");
2045                         BREAK_TO_DEBUGGER();
2046                         goto create_fail;
2047                 }
2048         }
2049
2050         pool->base.dccg = dccg21_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2051         if (pool->base.dccg == NULL) {
2052                 dm_error("DC: failed to create dccg!\n");
2053                 BREAK_TO_DEBUGGER();
2054                 goto create_fail;
2055         }
2056
2057         if (!dc->config.disable_dmcu) {
2058                 pool->base.dmcu = dcn21_dmcu_create(ctx,
2059                                 &dmcu_regs,
2060                                 &dmcu_shift,
2061                                 &dmcu_mask);
2062                 if (pool->base.dmcu == NULL) {
2063                         dm_error("DC: failed to create dmcu!\n");
2064                         BREAK_TO_DEBUGGER();
2065                         goto create_fail;
2066                 }
2067
2068                 dc->debug.dmub_command_table = false;
2069         }
2070
2071         if (dc->config.disable_dmcu) {
2072                 pool->base.psr = dmub_psr_create(ctx);
2073
2074                 if (pool->base.psr == NULL) {
2075                         dm_error("DC: failed to create psr obj!\n");
2076                         BREAK_TO_DEBUGGER();
2077                         goto create_fail;
2078                 }
2079         }
2080
2081         if (dc->config.disable_dmcu)
2082                 pool->base.abm = dmub_abm_create(ctx,
2083                         &abm_regs,
2084                         &abm_shift,
2085                         &abm_mask);
2086         else
2087                 pool->base.abm = dce_abm_create(ctx,
2088                         &abm_regs,
2089                         &abm_shift,
2090                         &abm_mask);
2091
2092         pool->base.pp_smu = dcn21_pp_smu_create(ctx);
2093
2094         num_pipes = dcn2_1_ip.max_num_dpp;
2095
2096         for (i = 0; i < dcn2_1_ip.max_num_dpp; i++)
2097                 if (pipe_fuses & 1 << i)
2098                         num_pipes--;
2099         dcn2_1_ip.max_num_dpp = num_pipes;
2100         dcn2_1_ip.max_num_otg = num_pipes;
2101
2102         dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);
2103
2104         init_data.ctx = dc->ctx;
2105         pool->base.irqs = dal_irq_service_dcn21_create(&init_data);
2106         if (!pool->base.irqs)
2107                 goto create_fail;
2108
2109         j = 0;
2110         /* mem input -> ipp -> dpp -> opp -> TG */
2111         for (i = 0; i < pool->base.pipe_count; i++) {
2112                 /* if pipe is disabled, skip instance of HW pipe,
2113                  * i.e, skip ASIC register instance
2114                  */
2115                 if ((pipe_fuses & (1 << i)) != 0)
2116                         continue;
2117
2118                 pool->base.hubps[j] = dcn21_hubp_create(ctx, i);
2119                 if (pool->base.hubps[j] == NULL) {
2120                         BREAK_TO_DEBUGGER();
2121                         dm_error(
2122                                 "DC: failed to create memory input!\n");
2123                         goto create_fail;
2124                 }
2125
2126                 pool->base.ipps[j] = dcn21_ipp_create(ctx, i);
2127                 if (pool->base.ipps[j] == NULL) {
2128                         BREAK_TO_DEBUGGER();
2129                         dm_error(
2130                                 "DC: failed to create input pixel processor!\n");
2131                         goto create_fail;
2132                 }
2133
2134                 pool->base.dpps[j] = dcn21_dpp_create(ctx, i);
2135                 if (pool->base.dpps[j] == NULL) {
2136                         BREAK_TO_DEBUGGER();
2137                         dm_error(
2138                                 "DC: failed to create dpps!\n");
2139                         goto create_fail;
2140                 }
2141
2142                 pool->base.opps[j] = dcn21_opp_create(ctx, i);
2143                 if (pool->base.opps[j] == NULL) {
2144                         BREAK_TO_DEBUGGER();
2145                         dm_error(
2146                                 "DC: failed to create output pixel processor!\n");
2147                         goto create_fail;
2148                 }
2149
2150                 pool->base.timing_generators[j] = dcn21_timing_generator_create(
2151                                 ctx, i);
2152                 if (pool->base.timing_generators[j] == NULL) {
2153                         BREAK_TO_DEBUGGER();
2154                         dm_error("DC: failed to create tg!\n");
2155                         goto create_fail;
2156                 }
2157                 j++;
2158         }
2159
2160         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2161                 pool->base.engines[i] = dcn21_aux_engine_create(ctx, i);
2162                 if (pool->base.engines[i] == NULL) {
2163                         BREAK_TO_DEBUGGER();
2164                         dm_error(
2165                                 "DC:failed to create aux engine!!\n");
2166                         goto create_fail;
2167                 }
2168                 pool->base.hw_i2cs[i] = dcn21_i2c_hw_create(ctx, i);
2169                 if (pool->base.hw_i2cs[i] == NULL) {
2170                         BREAK_TO_DEBUGGER();
2171                         dm_error(
2172                                 "DC:failed to create hw i2c!!\n");
2173                         goto create_fail;
2174                 }
2175                 pool->base.sw_i2cs[i] = NULL;
2176         }
2177
2178         pool->base.timing_generator_count = j;
2179         pool->base.pipe_count = j;
2180         pool->base.mpcc_count = j;
2181
2182         pool->base.mpc = dcn21_mpc_create(ctx);
2183         if (pool->base.mpc == NULL) {
2184                 BREAK_TO_DEBUGGER();
2185                 dm_error("DC: failed to create mpc!\n");
2186                 goto create_fail;
2187         }
2188
2189         pool->base.hubbub = dcn21_hubbub_create(ctx);
2190         if (pool->base.hubbub == NULL) {
2191                 BREAK_TO_DEBUGGER();
2192                 dm_error("DC: failed to create hubbub!\n");
2193                 goto create_fail;
2194         }
2195
2196         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2197                 pool->base.dscs[i] = dcn21_dsc_create(ctx, i);
2198                 if (pool->base.dscs[i] == NULL) {
2199                         BREAK_TO_DEBUGGER();
2200                         dm_error("DC: failed to create display stream compressor %d!\n", i);
2201                         goto create_fail;
2202                 }
2203         }
2204
2205         if (!dcn20_dwbc_create(ctx, &pool->base)) {
2206                 BREAK_TO_DEBUGGER();
2207                 dm_error("DC: failed to create dwbc!\n");
2208                 goto create_fail;
2209         }
2210         if (!dcn20_mmhubbub_create(ctx, &pool->base)) {
2211                 BREAK_TO_DEBUGGER();
2212                 dm_error("DC: failed to create mcif_wb!\n");
2213                 goto create_fail;
2214         }
2215
2216         if (!resource_construct(num_virtual_links, dc, &pool->base,
2217                         (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
2218                         &res_create_funcs : &res_create_maximus_funcs)))
2219                         goto create_fail;
2220
2221         dcn21_hw_sequencer_construct(dc);
2222
2223         dc->caps.max_planes =  pool->base.pipe_count;
2224
2225         for (i = 0; i < dc->caps.max_planes; ++i)
2226                 dc->caps.planes[i] = plane_cap;
2227
2228         dc->cap_funcs = cap_funcs;
2229
2230         return true;
2231
2232 create_fail:
2233
2234         dcn21_resource_destruct(pool);
2235
2236         return false;
2237 }
2238
2239 struct resource_pool *dcn21_create_resource_pool(
2240                 const struct dc_init_data *init_data,
2241                 struct dc *dc)
2242 {
2243         struct dcn21_resource_pool *pool =
2244                 kzalloc(sizeof(struct dcn21_resource_pool), GFP_KERNEL);
2245
2246         if (!pool)
2247                 return NULL;
2248
2249         if (dcn21_resource_construct(init_data->num_virtual_links, dc, pool))
2250                 return &pool->base;
2251
2252         BREAK_TO_DEBUGGER();
2253         kfree(pool);
2254         return NULL;
2255 }