drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c

   1 /*
   2 * Copyright 2018 Advanced Micro Devices, Inc.
   3  * Copyright 2019 Raptor Engineering, LLC
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: AMD
  24  *
  25  */
  26
  27 #include <linux/slab.h>
  28
  29 #include "dm_services.h"
  30 #include "dc.h"
  31
  32 #include "dcn21_init.h"
  33
  34 #include "resource.h"
  35 #include "include/irq_service_interface.h"
  36 #include "dcn20/dcn20_resource.h"
  37
  38 #include "clk_mgr.h"
  39 #include "dcn10/dcn10_hubp.h"
  40 #include "dcn10/dcn10_ipp.h"
  41 #include "dcn20/dcn20_hubbub.h"
  42 #include "dcn20/dcn20_mpc.h"
  43 #include "dcn20/dcn20_hubp.h"
  44 #include "dcn21_hubp.h"
  45 #include "irq/dcn21/irq_service_dcn21.h"
  46 #include "dcn20/dcn20_dpp.h"
  47 #include "dcn20/dcn20_optc.h"
  48 #include "dcn21/dcn21_hwseq.h"
  49 #include "dce110/dce110_hw_sequencer.h"
  50 #include "dcn20/dcn20_opp.h"
  51 #include "dcn20/dcn20_dsc.h"
  52 #include "dcn21/dcn21_link_encoder.h"
  53 #include "dcn20/dcn20_stream_encoder.h"
  54 #include "dce/dce_clock_source.h"
  55 #include "dce/dce_audio.h"
  56 #include "dce/dce_hwseq.h"
  57 #include "virtual/virtual_stream_encoder.h"
  58 #include "dce110/dce110_resource.h"
  59 #include "dml/display_mode_vba.h"
  60 #include "dcn20/dcn20_dccg.h"
  61 #include "dcn21_hubbub.h"
  62 #include "dcn10/dcn10_resource.h"
  63 #include "dce110/dce110_resource.h"
  64
  65 #include "dcn20/dcn20_dwb.h"
  66 #include "dcn20/dcn20_mmhubbub.h"
  67 #include "dpcs/dpcs_2_1_0_offset.h"
  68 #include "dpcs/dpcs_2_1_0_sh_mask.h"
  69
  70 #include "renoir_ip_offset.h"
  71 #include "dcn/dcn_2_1_0_offset.h"
  72 #include "dcn/dcn_2_1_0_sh_mask.h"
  73
  74 #include "nbio/nbio_7_0_offset.h"
  75
  76 #include "mmhub/mmhub_2_0_0_offset.h"
  77 #include "mmhub/mmhub_2_0_0_sh_mask.h"
  78
  79 #include "reg_helper.h"
  80 #include "dce/dce_abm.h"
  81 #include "dce/dce_dmcu.h"
  82 #include "dce/dce_aux.h"
  83 #include "dce/dce_i2c.h"
  84 #include "dcn21_resource.h"
  85 #include "vm_helper.h"
  86 #include "dcn20/dcn20_vmid.h"
  87 #include "dce/dmub_psr.h"
  88
  89 #define SOC_BOUNDING_BOX_VALID false
  90 #define DC_LOGGER_INIT(logger)
  91
  92
  93 struct _vcs_dpi_ip_params_st dcn2_1_ip = {
  94         .odm_capable = 1,
  95         .gpuvm_enable = 1,
  96         .hostvm_enable = 1,
  97         .gpuvm_max_page_table_levels = 1,
  98         .hostvm_max_page_table_levels = 4,
  99         .hostvm_cached_page_table_levels = 2,
 100         .num_dsc = 3,
 101         .rob_buffer_size_kbytes = 168,
 102         .det_buffer_size_kbytes = 164,
 103         .dpte_buffer_size_in_pte_reqs_luma = 44,
 104         .dpte_buffer_size_in_pte_reqs_chroma = 42,//todo
 105         .dpp_output_buffer_pixels = 2560,
 106         .opp_output_buffer_lines = 1,
 107         .pixel_chunk_size_kbytes = 8,
 108         .pte_enable = 1,
 109         .max_page_table_levels = 4,
 110         .pte_chunk_size_kbytes = 2,
 111         .meta_chunk_size_kbytes = 2,
 112         .writeback_chunk_size_kbytes = 2,
 113         .line_buffer_size_bits = 789504,
 114         .is_line_buffer_bpp_fixed = 0,
 115         .line_buffer_fixed_bpp = 0,
 116         .dcc_supported = true,
 117         .max_line_buffer_lines = 12,
 118         .writeback_luma_buffer_size_kbytes = 12,
 119         .writeback_chroma_buffer_size_kbytes = 8,
 120         .writeback_chroma_line_buffer_width_pixels = 4,
 121         .writeback_max_hscl_ratio = 1,
 122         .writeback_max_vscl_ratio = 1,
 123         .writeback_min_hscl_ratio = 1,
 124         .writeback_min_vscl_ratio = 1,
 125         .writeback_max_hscl_taps = 12,
 126         .writeback_max_vscl_taps = 12,
 127         .writeback_line_buffer_luma_buffer_size = 0,
 128         .writeback_line_buffer_chroma_buffer_size = 14643,
 129         .cursor_buffer_size = 8,
 130         .cursor_chunk_size = 2,
 131         .max_num_otg = 4,
 132         .max_num_dpp = 4,
 133         .max_num_wb = 1,
 134         .max_dchub_pscl_bw_pix_per_clk = 4,
 135         .max_pscl_lb_bw_pix_per_clk = 2,
 136         .max_lb_vscl_bw_pix_per_clk = 4,
 137         .max_vscl_hscl_bw_pix_per_clk = 4,
 138         .max_hscl_ratio = 4,
 139         .max_vscl_ratio = 4,
 140         .hscl_mults = 4,
 141         .vscl_mults = 4,
 142         .max_hscl_taps = 8,
 143         .max_vscl_taps = 8,
 144         .dispclk_ramp_margin_percent = 1,
 145         .underscan_factor = 1.10,
 146         .min_vblank_lines = 32, //
 147         .dppclk_delay_subtotal = 77, //
 148         .dppclk_delay_scl_lb_only = 16,
 149         .dppclk_delay_scl = 50,
 150         .dppclk_delay_cnvc_formatter = 8,
 151         .dppclk_delay_cnvc_cursor = 6,
 152         .dispclk_delay_subtotal = 87, //
 153         .dcfclk_cstate_latency = 10, // SRExitTime
 154         .max_inter_dcn_tile_repeaters = 8,
 155
 156         .xfc_supported = false,
 157         .xfc_fill_bw_overhead_percent = 10.0,
 158         .xfc_fill_constant_bytes = 0,
 159         .ptoi_supported = 0
 160 };
 161
 162 struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = {
 163         .clock_limits = {
 164                         {
 165                                 .state = 0,
 166                                 .dcfclk_mhz = 400.0,
 167                                 .fabricclk_mhz = 400.0,
 168                                 .dispclk_mhz = 600.0,
 169                                 .dppclk_mhz = 400.00,
 170                                 .phyclk_mhz = 600.0,
 171                                 .socclk_mhz = 278.0,
 172                                 .dscclk_mhz = 205.67,
 173                                 .dram_speed_mts = 1600.0,
 174                         },
 175                         {
 176                                 .state = 1,
 177                                 .dcfclk_mhz = 464.52,
 178                                 .fabricclk_mhz = 800.0,
 179                                 .dispclk_mhz = 654.55,
 180                                 .dppclk_mhz = 626.09,
 181                                 .phyclk_mhz = 600.0,
 182                                 .socclk_mhz = 278.0,
 183                                 .dscclk_mhz = 205.67,
 184                                 .dram_speed_mts = 1600.0,
 185                         },
 186                         {
 187                                 .state = 2,
 188                                 .dcfclk_mhz = 514.29,
 189                                 .fabricclk_mhz = 933.0,
 190                                 .dispclk_mhz = 757.89,
 191                                 .dppclk_mhz = 685.71,
 192                                 .phyclk_mhz = 600.0,
 193                                 .socclk_mhz = 278.0,
 194                                 .dscclk_mhz = 287.67,
 195                                 .dram_speed_mts = 1866.0,
 196                         },
 197                         {
 198                                 .state = 3,
 199                                 .dcfclk_mhz = 576.00,
 200                                 .fabricclk_mhz = 1067.0,
 201                                 .dispclk_mhz = 847.06,
 202                                 .dppclk_mhz = 757.89,
 203                                 .phyclk_mhz = 600.0,
 204                                 .socclk_mhz = 715.0,
 205                                 .dscclk_mhz = 318.334,
 206                                 .dram_speed_mts = 2134.0,
 207                         },
 208                         {
 209                                 .state = 4,
 210                                 .dcfclk_mhz = 626.09,
 211                                 .fabricclk_mhz = 1200.0,
 212                                 .dispclk_mhz = 900.00,
 213                                 .dppclk_mhz = 847.06,
 214                                 .phyclk_mhz = 810.0,
 215                                 .socclk_mhz = 953.0,
 216                                 .dscclk_mhz = 489.0,
 217                                 .dram_speed_mts = 2400.0,
 218                         },
 219                         {
 220                                 .state = 5,
 221                                 .dcfclk_mhz = 685.71,
 222                                 .fabricclk_mhz = 1333.0,
 223                                 .dispclk_mhz = 1028.57,
 224                                 .dppclk_mhz = 960.00,
 225                                 .phyclk_mhz = 810.0,
 226                                 .socclk_mhz = 278.0,
 227                                 .dscclk_mhz = 287.67,
 228                                 .dram_speed_mts = 2666.0,
 229                         },
 230                         {
 231                                 .state = 6,
 232                                 .dcfclk_mhz = 757.89,
 233                                 .fabricclk_mhz = 1467.0,
 234                                 .dispclk_mhz = 1107.69,
 235                                 .dppclk_mhz = 1028.57,
 236                                 .phyclk_mhz = 810.0,
 237                                 .socclk_mhz = 715.0,
 238                                 .dscclk_mhz = 318.334,
 239                                 .dram_speed_mts = 3200.0,
 240                         },
 241                         {
 242                                 .state = 7,
 243                                 .dcfclk_mhz = 847.06,
 244                                 .fabricclk_mhz = 1600.0,
 245                                 .dispclk_mhz = 1395.0,
 246                                 .dppclk_mhz = 1285.00,
 247                                 .phyclk_mhz = 1325.0,
 248                                 .socclk_mhz = 953.0,
 249                                 .dscclk_mhz = 489.0,
 250                                 .dram_speed_mts = 4266.0,
 251                         },
 252                         /*Extra state, no dispclk ramping*/
 253                         {
 254                                 .state = 8,
 255                                 .dcfclk_mhz = 847.06,
 256                                 .fabricclk_mhz = 1600.0,
 257                                 .dispclk_mhz = 1395.0,
 258                                 .dppclk_mhz = 1285.0,
 259                                 .phyclk_mhz = 1325.0,
 260                                 .socclk_mhz = 953.0,
 261                                 .dscclk_mhz = 489.0,
 262                                 .dram_speed_mts = 4266.0,
 263                         },
 264
 265                 },
 266
 267         .sr_exit_time_us = 12.5,
 268         .sr_enter_plus_exit_time_us = 17.0,
 269         .urgent_latency_us = 4.0,
 270         .urgent_latency_pixel_data_only_us = 4.0,
 271         .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
 272         .urgent_latency_vm_data_only_us = 4.0,
 273         .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
 274         .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
 275         .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
 276         .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0,
 277         .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 75.0,
 278         .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
 279         .max_avg_sdp_bw_use_normal_percent = 60.0,
 280         .max_avg_dram_bw_use_normal_percent = 100.0,
 281         .writeback_latency_us = 12.0,
 282         .max_request_size_bytes = 256,
 283         .dram_channel_width_bytes = 4,
 284         .fabric_datapath_to_dcn_data_return_bytes = 32,
 285         .dcn_downspread_percent = 0.5,
 286         .downspread_percent = 0.5,
 287         .dram_page_open_time_ns = 50.0,
 288         .dram_rw_turnaround_time_ns = 17.5,
 289         .dram_return_buffer_per_channel_bytes = 8192,
 290         .round_trip_ping_latency_dcfclk_cycles = 128,
 291         .urgent_out_of_order_return_per_channel_bytes = 4096,
 292         .channel_interleave_bytes = 256,
 293         .num_banks = 8,
 294         .num_chans = 4,
 295         .vmm_page_size_bytes = 4096,
 296         .dram_clock_change_latency_us = 23.84,
 297         .return_bus_width_bytes = 64,
 298         .dispclk_dppclk_vco_speed_mhz = 3600,
 299         .xfc_bus_transport_time_us = 4,
 300         .xfc_xbuf_latency_tolerance_us = 4,
 301         .use_urgent_burst_bw = 1,
 302         .num_states = 9
 303 };
 304
 305 #ifndef MAX
 306 #define MAX(X, Y) ((X) > (Y) ? (X) : (Y))
 307 #endif
 308 #ifndef MIN
 309 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
 310 #endif
 311
 312 /* begin *********************
 313  * macros to expend register list macro defined in HW object header file */
 314
 315 /* DCN */
 316 /* TODO awful hack. fixup dcn20_dwb.h */
 317 #undef BASE_INNER
 318 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
 319
 320 #define BASE(seg) BASE_INNER(seg)
 321
 322 #define SR(reg_name)\
 323                 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
 324                                         mm ## reg_name
 325
 326 #define SRI(reg_name, block, id)\
 327         .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 328                                         mm ## block ## id ## _ ## reg_name
 329
 330 #define SRIR(var_name, reg_name, block, id)\
 331         .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 332                                         mm ## block ## id ## _ ## reg_name
 333
 334 #define SRII(reg_name, block, id)\
 335         .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 336                                         mm ## block ## id ## _ ## reg_name
 337
 338 #define DCCG_SRII(reg_name, block, id)\
 339         .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 340                                         mm ## block ## id ## _ ## reg_name
 341
 342 /* NBIO */
 343 #define NBIO_BASE_INNER(seg) \
 344         NBIF0_BASE__INST0_SEG ## seg
 345
 346 #define NBIO_BASE(seg) \
 347         NBIO_BASE_INNER(seg)
 348
 349 #define NBIO_SR(reg_name)\
 350                 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
 351                                         mm ## reg_name
 352
 353 /* MMHUB */
 354 #define MMHUB_BASE_INNER(seg) \
 355         MMHUB_BASE__INST0_SEG ## seg
 356
 357 #define MMHUB_BASE(seg) \
 358         MMHUB_BASE_INNER(seg)
 359
 360 #define MMHUB_SR(reg_name)\
 361                 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
 362                                         mmMM ## reg_name
 363
 364 #define clk_src_regs(index, pllid)\
 365 [index] = {\
 366         CS_COMMON_REG_LIST_DCN2_1(index, pllid),\
 367 }
 368
 369 static const struct dce110_clk_src_regs clk_src_regs[] = {
 370         clk_src_regs(0, A),
 371         clk_src_regs(1, B),
 372         clk_src_regs(2, C),
 373         clk_src_regs(3, D),
 374         clk_src_regs(4, E),
 375 };
 376
 377 static const struct dce110_clk_src_shift cs_shift = {
 378                 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
 379 };
 380
 381 static const struct dce110_clk_src_mask cs_mask = {
 382                 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
 383 };
 384
 385 static const struct bios_registers bios_regs = {
 386                 NBIO_SR(BIOS_SCRATCH_3),
 387                 NBIO_SR(BIOS_SCRATCH_6)
 388 };
 389
 390 static const struct dce_dmcu_registers dmcu_regs = {
 391                 DMCU_DCN20_REG_LIST()
 392 };
 393
 394 static const struct dce_dmcu_shift dmcu_shift = {
 395                 DMCU_MASK_SH_LIST_DCN10(__SHIFT)
 396 };
 397
 398 static const struct dce_dmcu_mask dmcu_mask = {
 399                 DMCU_MASK_SH_LIST_DCN10(_MASK)
 400 };
 401
 402 static const struct dce_abm_registers abm_regs = {
 403                 ABM_DCN20_REG_LIST()
 404 };
 405
 406 static const struct dce_abm_shift abm_shift = {
 407                 ABM_MASK_SH_LIST_DCN20(__SHIFT)
 408 };
 409
 410 static const struct dce_abm_mask abm_mask = {
 411                 ABM_MASK_SH_LIST_DCN20(_MASK)
 412 };
 413
 414 #define audio_regs(id)\
 415 [id] = {\
 416                 AUD_COMMON_REG_LIST(id)\
 417 }
 418
 419 static const struct dce_audio_registers audio_regs[] = {
 420         audio_regs(0),
 421         audio_regs(1),
 422         audio_regs(2),
 423         audio_regs(3),
 424         audio_regs(4),
 425         audio_regs(5),
 426 };
 427
 428 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
 429                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
 430                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
 431                 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
 432
 433 static const struct dce_audio_shift audio_shift = {
 434                 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
 435 };
 436
 437 static const struct dce_audio_mask audio_mask = {
 438                 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
 439 };
 440
 441 static const struct dccg_registers dccg_regs = {
 442                 DCCG_COMMON_REG_LIST_DCN_BASE()
 443 };
 444
 445 static const struct dccg_shift dccg_shift = {
 446                 DCCG_MASK_SH_LIST_DCN2(__SHIFT)
 447 };
 448
 449 static const struct dccg_mask dccg_mask = {
 450                 DCCG_MASK_SH_LIST_DCN2(_MASK)
 451 };
 452
 453 #define opp_regs(id)\
 454 [id] = {\
 455         OPP_REG_LIST_DCN20(id),\
 456 }
 457
 458 static const struct dcn20_opp_registers opp_regs[] = {
 459         opp_regs(0),
 460         opp_regs(1),
 461         opp_regs(2),
 462         opp_regs(3),
 463         opp_regs(4),
 464         opp_regs(5),
 465 };
 466
 467 static const struct dcn20_opp_shift opp_shift = {
 468                 OPP_MASK_SH_LIST_DCN20(__SHIFT)
 469 };
 470
 471 static const struct dcn20_opp_mask opp_mask = {
 472                 OPP_MASK_SH_LIST_DCN20(_MASK)
 473 };
 474
 475 #define tg_regs(id)\
 476 [id] = {TG_COMMON_REG_LIST_DCN2_0(id)}
 477
 478 static const struct dcn_optc_registers tg_regs[] = {
 479         tg_regs(0),
 480         tg_regs(1),
 481         tg_regs(2),
 482         tg_regs(3)
 483 };
 484
 485 static const struct dcn_optc_shift tg_shift = {
 486         TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
 487 };
 488
 489 static const struct dcn_optc_mask tg_mask = {
 490         TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
 491 };
 492
 493 static const struct dcn20_mpc_registers mpc_regs = {
 494                 MPC_REG_LIST_DCN2_0(0),
 495                 MPC_REG_LIST_DCN2_0(1),
 496                 MPC_REG_LIST_DCN2_0(2),
 497                 MPC_REG_LIST_DCN2_0(3),
 498                 MPC_REG_LIST_DCN2_0(4),
 499                 MPC_REG_LIST_DCN2_0(5),
 500                 MPC_OUT_MUX_REG_LIST_DCN2_0(0),
 501                 MPC_OUT_MUX_REG_LIST_DCN2_0(1),
 502                 MPC_OUT_MUX_REG_LIST_DCN2_0(2),
 503                 MPC_OUT_MUX_REG_LIST_DCN2_0(3),
 504                 MPC_DBG_REG_LIST_DCN2_0()
 505 };
 506
 507 static const struct dcn20_mpc_shift mpc_shift = {
 508         MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT),
 509         MPC_DEBUG_REG_LIST_SH_DCN20
 510 };
 511
 512 static const struct dcn20_mpc_mask mpc_mask = {
 513         MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK),
 514         MPC_DEBUG_REG_LIST_MASK_DCN20
 515 };
 516
 517 #define hubp_regs(id)\
 518 [id] = {\
 519         HUBP_REG_LIST_DCN21(id)\
 520 }
 521
 522 static const struct dcn_hubp2_registers hubp_regs[] = {
 523                 hubp_regs(0),
 524                 hubp_regs(1),
 525                 hubp_regs(2),
 526                 hubp_regs(3)
 527 };
 528
 529 static const struct dcn_hubp2_shift hubp_shift = {
 530                 HUBP_MASK_SH_LIST_DCN21(__SHIFT)
 531 };
 532
 533 static const struct dcn_hubp2_mask hubp_mask = {
 534                 HUBP_MASK_SH_LIST_DCN21(_MASK)
 535 };
 536
 537 static const struct dcn_hubbub_registers hubbub_reg = {
 538                 HUBBUB_REG_LIST_DCN21()
 539 };
 540
 541 static const struct dcn_hubbub_shift hubbub_shift = {
 542                 HUBBUB_MASK_SH_LIST_DCN21(__SHIFT)
 543 };
 544
 545 static const struct dcn_hubbub_mask hubbub_mask = {
 546                 HUBBUB_MASK_SH_LIST_DCN21(_MASK)
 547 };
 548
 549
 550 #define vmid_regs(id)\
 551 [id] = {\
 552                 DCN20_VMID_REG_LIST(id)\
 553 }
 554
 555 static const struct dcn_vmid_registers vmid_regs[] = {
 556         vmid_regs(0),
 557         vmid_regs(1),
 558         vmid_regs(2),
 559         vmid_regs(3),
 560         vmid_regs(4),
 561         vmid_regs(5),
 562         vmid_regs(6),
 563         vmid_regs(7),
 564         vmid_regs(8),
 565         vmid_regs(9),
 566         vmid_regs(10),
 567         vmid_regs(11),
 568         vmid_regs(12),
 569         vmid_regs(13),
 570         vmid_regs(14),
 571         vmid_regs(15)
 572 };
 573
 574 static const struct dcn20_vmid_shift vmid_shifts = {
 575                 DCN20_VMID_MASK_SH_LIST(__SHIFT)
 576 };
 577
 578 static const struct dcn20_vmid_mask vmid_masks = {
 579                 DCN20_VMID_MASK_SH_LIST(_MASK)
 580 };
 581
 582 #define dsc_regsDCN20(id)\
 583 [id] = {\
 584         DSC_REG_LIST_DCN20(id)\
 585 }
 586
 587 static const struct dcn20_dsc_registers dsc_regs[] = {
 588         dsc_regsDCN20(0),
 589         dsc_regsDCN20(1),
 590         dsc_regsDCN20(2),
 591         dsc_regsDCN20(3),
 592         dsc_regsDCN20(4),
 593         dsc_regsDCN20(5)
 594 };
 595
 596 static const struct dcn20_dsc_shift dsc_shift = {
 597         DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
 598 };
 599
 600 static const struct dcn20_dsc_mask dsc_mask = {
 601         DSC_REG_LIST_SH_MASK_DCN20(_MASK)
 602 };
 603
 604 #define ipp_regs(id)\
 605 [id] = {\
 606         IPP_REG_LIST_DCN20(id),\
 607 }
 608
 609 static const struct dcn10_ipp_registers ipp_regs[] = {
 610         ipp_regs(0),
 611         ipp_regs(1),
 612         ipp_regs(2),
 613         ipp_regs(3),
 614 };
 615
 616 static const struct dcn10_ipp_shift ipp_shift = {
 617                 IPP_MASK_SH_LIST_DCN20(__SHIFT)
 618 };
 619
 620 static const struct dcn10_ipp_mask ipp_mask = {
 621                 IPP_MASK_SH_LIST_DCN20(_MASK),
 622 };
 623
 624 #define opp_regs(id)\
 625 [id] = {\
 626         OPP_REG_LIST_DCN20(id),\
 627 }
 628
 629
 630 #define aux_engine_regs(id)\
 631 [id] = {\
 632         AUX_COMMON_REG_LIST0(id), \
 633         .AUXN_IMPCAL = 0, \
 634         .AUXP_IMPCAL = 0, \
 635         .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
 636 }
 637
 638 static const struct dce110_aux_registers aux_engine_regs[] = {
 639                 aux_engine_regs(0),
 640                 aux_engine_regs(1),
 641                 aux_engine_regs(2),
 642                 aux_engine_regs(3),
 643                 aux_engine_regs(4),
 644 };
 645
 646 #define tf_regs(id)\
 647 [id] = {\
 648         TF_REG_LIST_DCN20(id),\
 649         TF_REG_LIST_DCN20_COMMON_APPEND(id),\
 650 }
 651
 652 static const struct dcn2_dpp_registers tf_regs[] = {
 653         tf_regs(0),
 654         tf_regs(1),
 655         tf_regs(2),
 656         tf_regs(3),
 657 };
 658
 659 static const struct dcn2_dpp_shift tf_shift = {
 660                 TF_REG_LIST_SH_MASK_DCN20(__SHIFT),
 661                 TF_DEBUG_REG_LIST_SH_DCN20
 662 };
 663
 664 static const struct dcn2_dpp_mask tf_mask = {
 665                 TF_REG_LIST_SH_MASK_DCN20(_MASK),
 666                 TF_DEBUG_REG_LIST_MASK_DCN20
 667 };
 668
 669 #define stream_enc_regs(id)\
 670 [id] = {\
 671         SE_DCN2_REG_LIST(id)\
 672 }
 673
 674 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
 675         stream_enc_regs(0),
 676         stream_enc_regs(1),
 677         stream_enc_regs(2),
 678         stream_enc_regs(3),
 679         stream_enc_regs(4),
 680 };
 681
 682 static const struct dce110_aux_registers_shift aux_shift = {
 683         DCN_AUX_MASK_SH_LIST(__SHIFT)
 684 };
 685
 686 static const struct dce110_aux_registers_mask aux_mask = {
 687         DCN_AUX_MASK_SH_LIST(_MASK)
 688 };
 689
 690 static const struct dcn10_stream_encoder_shift se_shift = {
 691                 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)
 692 };
 693
 694 static const struct dcn10_stream_encoder_mask se_mask = {
 695                 SE_COMMON_MASK_SH_LIST_DCN20(_MASK)
 696 };
 697
 698 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
 699
 700 static int dcn21_populate_dml_pipes_from_context(
 701                 struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes);
 702
 703 static struct input_pixel_processor *dcn21_ipp_create(
 704         struct dc_context *ctx, uint32_t inst)
 705 {
 706         struct dcn10_ipp *ipp =
 707                 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);
 708
 709         if (!ipp) {
 710                 BREAK_TO_DEBUGGER();
 711                 return NULL;
 712         }
 713
 714         dcn20_ipp_construct(ipp, ctx, inst,
 715                         &ipp_regs[inst], &ipp_shift, &ipp_mask);
 716         return &ipp->base;
 717 }
 718
 719 static struct dpp *dcn21_dpp_create(
 720         struct dc_context *ctx,
 721         uint32_t inst)
 722 {
 723         struct dcn20_dpp *dpp =
 724                 kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL);
 725
 726         if (!dpp)
 727                 return NULL;
 728
 729         if (dpp2_construct(dpp, ctx, inst,
 730                         &tf_regs[inst], &tf_shift, &tf_mask))
 731                 return &dpp->base;
 732
 733         BREAK_TO_DEBUGGER();
 734         kfree(dpp);
 735         return NULL;
 736 }
 737
 738 static struct dce_aux *dcn21_aux_engine_create(
 739         struct dc_context *ctx,
 740         uint32_t inst)
 741 {
 742         struct aux_engine_dce110 *aux_engine =
 743                 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
 744
 745         if (!aux_engine)
 746                 return NULL;
 747
 748         dce110_aux_engine_construct(aux_engine, ctx, inst,
 749                                     SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
 750                                     &aux_engine_regs[inst],
 751                                         &aux_mask,
 752                                         &aux_shift,
 753                                         ctx->dc->caps.extended_aux_timeout_support);
 754
 755         return &aux_engine->base;
 756 }
 757
 758 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
 759
 760 static const struct dce_i2c_registers i2c_hw_regs[] = {
 761                 i2c_inst_regs(1),
 762                 i2c_inst_regs(2),
 763                 i2c_inst_regs(3),
 764                 i2c_inst_regs(4),
 765                 i2c_inst_regs(5),
 766 };
 767
 768 static const struct dce_i2c_shift i2c_shifts = {
 769                 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
 770 };
 771
 772 static const struct dce_i2c_mask i2c_masks = {
 773                 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
 774 };
 775
 776 struct dce_i2c_hw *dcn21_i2c_hw_create(
 777         struct dc_context *ctx,
 778         uint32_t inst)
 779 {
 780         struct dce_i2c_hw *dce_i2c_hw =
 781                 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
 782
 783         if (!dce_i2c_hw)
 784                 return NULL;
 785
 786         dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
 787                                     &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
 788
 789         return dce_i2c_hw;
 790 }
 791
 792 static const struct resource_caps res_cap_rn = {
 793                 .num_timing_generator = 4,
 794                 .num_opp = 4,
 795                 .num_video_plane = 4,
 796                 .num_audio = 4, // 4 audio endpoints.  4 audio streams
 797                 .num_stream_encoder = 5,
 798                 .num_pll = 5,  // maybe 3 because the last two used for USB-c
 799                 .num_dwb = 1,
 800                 .num_ddc = 5,
 801                 .num_vmid = 1,
 802                 .num_dsc = 3,
 803 };
 804
 805 #ifdef DIAGS_BUILD
 806 static const struct resource_caps res_cap_rn_FPGA_4pipe = {
 807                 .num_timing_generator = 4,
 808                 .num_opp = 4,
 809                 .num_video_plane = 4,
 810                 .num_audio = 7,
 811                 .num_stream_encoder = 4,
 812                 .num_pll = 4,
 813                 .num_dwb = 1,
 814                 .num_ddc = 4,
 815                 .num_dsc = 0,
 816 };
 817
 818 static const struct resource_caps res_cap_rn_FPGA_2pipe_dsc = {
 819                 .num_timing_generator = 2,
 820                 .num_opp = 2,
 821                 .num_video_plane = 2,
 822                 .num_audio = 7,
 823                 .num_stream_encoder = 2,
 824                 .num_pll = 4,
 825                 .num_dwb = 1,
 826                 .num_ddc = 4,
 827                 .num_dsc = 2,
 828 };
 829 #endif
 830
 831 static const struct dc_plane_cap plane_cap = {
 832         .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
 833         .blends_with_above = true,
 834         .blends_with_below = true,
 835         .per_pixel_alpha = true,
 836
 837         .pixel_format_support = {
 838                         .argb8888 = true,
 839                         .nv12 = true,
 840                         .fp16 = true
 841         },
 842
 843         .max_upscale_factor = {
 844                         .argb8888 = 16000,
 845                         .nv12 = 16000,
 846                         .fp16 = 16000
 847         },
 848
 849         .max_downscale_factor = {
 850                         .argb8888 = 250,
 851                         .nv12 = 250,
 852                         .fp16 = 250
 853         }
 854 };
 855
 856 static const struct dc_debug_options debug_defaults_drv = {
 857                 .disable_dmcu = true,
 858                 .force_abm_enable = false,
 859                 .timing_trace = false,
 860                 .clock_trace = true,
 861                 .disable_pplib_clock_request = true,
 862                 .min_disp_clk_khz = 100000,
 863                 .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
 864                 .force_single_disp_pipe_split = false,
 865                 .disable_dcc = DCC_ENABLE,
 866                 .vsr_support = true,
 867                 .performance_trace = false,
 868                 .max_downscale_src_width = 4096,
 869                 .disable_pplib_wm_range = false,
 870                 .scl_reset_length10 = true,
 871                 .sanity_checks = true,
 872                 .disable_48mhz_pwrdwn = false,
 873                 .nv12_iflip_vm_wa = true,
 874                 .usbc_combo_phy_reset_wa = true
 875 };
 876
 877 static const struct dc_debug_options debug_defaults_diags = {
 878                 .disable_dmcu = true,
 879                 .force_abm_enable = false,
 880                 .timing_trace = true,
 881                 .clock_trace = true,
 882                 .disable_dpp_power_gate = true,
 883                 .disable_hubp_power_gate = true,
 884                 .disable_clock_gate = true,
 885                 .disable_pplib_clock_request = true,
 886                 .disable_pplib_wm_range = true,
 887                 .disable_stutter = true,
 888                 .disable_48mhz_pwrdwn = true,
 889 };
 890
 891 enum dcn20_clk_src_array_id {
 892         DCN20_CLK_SRC_PLL0,
 893         DCN20_CLK_SRC_PLL1,
 894         DCN20_CLK_SRC_PLL2,
 895         DCN20_CLK_SRC_TOTAL_DCN21
 896 };
 897
 898 static void dcn21_resource_destruct(struct dcn21_resource_pool *pool)
 899 {
 900         unsigned int i;
 901
 902         for (i = 0; i < pool->base.stream_enc_count; i++) {
 903                 if (pool->base.stream_enc[i] != NULL) {
 904                         kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
 905                         pool->base.stream_enc[i] = NULL;
 906                 }
 907         }
 908
 909         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
 910                 if (pool->base.dscs[i] != NULL)
 911                         dcn20_dsc_destroy(&pool->base.dscs[i]);
 912         }
 913
 914         if (pool->base.mpc != NULL) {
 915                 kfree(TO_DCN20_MPC(pool->base.mpc));
 916                 pool->base.mpc = NULL;
 917         }
 918         if (pool->base.hubbub != NULL) {
 919                 kfree(pool->base.hubbub);
 920                 pool->base.hubbub = NULL;
 921         }
 922         for (i = 0; i < pool->base.pipe_count; i++) {
 923                 if (pool->base.dpps[i] != NULL)
 924                         dcn20_dpp_destroy(&pool->base.dpps[i]);
 925
 926                 if (pool->base.ipps[i] != NULL)
 927                         pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
 928
 929                 if (pool->base.hubps[i] != NULL) {
 930                         kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
 931                         pool->base.hubps[i] = NULL;
 932                 }
 933
 934                 if (pool->base.irqs != NULL) {
 935                         dal_irq_service_destroy(&pool->base.irqs);
 936                 }
 937         }
 938
 939         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
 940                 if (pool->base.engines[i] != NULL)
 941                         dce110_engine_destroy(&pool->base.engines[i]);
 942                 if (pool->base.hw_i2cs[i] != NULL) {
 943                         kfree(pool->base.hw_i2cs[i]);
 944                         pool->base.hw_i2cs[i] = NULL;
 945                 }
 946                 if (pool->base.sw_i2cs[i] != NULL) {
 947                         kfree(pool->base.sw_i2cs[i]);
 948                         pool->base.sw_i2cs[i] = NULL;
 949                 }
 950         }
 951
 952         for (i = 0; i < pool->base.res_cap->num_opp; i++) {
 953                 if (pool->base.opps[i] != NULL)
 954                         pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
 955         }
 956
 957         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
 958                 if (pool->base.timing_generators[i] != NULL)    {
 959                         kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
 960                         pool->base.timing_generators[i] = NULL;
 961                 }
 962         }
 963
 964         for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
 965                 if (pool->base.dwbc[i] != NULL) {
 966                         kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
 967                         pool->base.dwbc[i] = NULL;
 968                 }
 969                 if (pool->base.mcif_wb[i] != NULL) {
 970                         kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));
 971                         pool->base.mcif_wb[i] = NULL;
 972                 }
 973         }
 974
 975         for (i = 0; i < pool->base.audio_count; i++) {
 976                 if (pool->base.audios[i])
 977                         dce_aud_destroy(&pool->base.audios[i]);
 978         }
 979
 980         for (i = 0; i < pool->base.clk_src_count; i++) {
 981                 if (pool->base.clock_sources[i] != NULL) {
 982                         dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
 983                         pool->base.clock_sources[i] = NULL;
 984                 }
 985         }
 986
 987         if (pool->base.dp_clock_source != NULL) {
 988                 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
 989                 pool->base.dp_clock_source = NULL;
 990         }
 991
 992
 993         if (pool->base.abm != NULL)
 994                 dce_abm_destroy(&pool->base.abm);
 995
 996         if (pool->base.dmcu != NULL)
 997                 dce_dmcu_destroy(&pool->base.dmcu);
 998
 999         if (pool->base.psr != NULL)
1000                 dmub_psr_destroy(&pool->base.psr);
1001
1002         if (pool->base.dccg != NULL)
1003                 dcn_dccg_destroy(&pool->base.dccg);
1004
1005         if (pool->base.pp_smu != NULL)
1006                 dcn21_pp_smu_destroy(&pool->base.pp_smu);
1007 }
1008
1009
1010 static void calculate_wm_set_for_vlevel(
1011                 int vlevel,
1012                 struct wm_range_table_entry *table_entry,
1013                 struct dcn_watermarks *wm_set,
1014                 struct display_mode_lib *dml,
1015                 display_e2e_pipe_params_st *pipes,
1016                 int pipe_cnt)
1017 {
1018         double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us;
1019
1020         ASSERT(vlevel < dml->soc.num_states);
1021         /* only pipe 0 is read for voltage and dcf/soc clocks */
1022         pipes[0].clks_cfg.voltage = vlevel;
1023         pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz;
1024         pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz;
1025
1026         dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us;
1027         dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us;
1028         dml->soc.sr_enter_plus_exit_time_us = table_entry->sr_enter_plus_exit_time_us;
1029
1030         wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000;
1031         wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000;
1032         wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000;
1033         wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000;
1034         wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000;
1035         wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000;
1036         wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000;
1037         wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) * 1000;
1038         dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached;
1039
1040 }
1041
1042 static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
1043 {
1044         int i;
1045
1046         DC_FP_START();
1047
1048         if (dc->bb_overrides.sr_exit_time_ns) {
1049                 for (i = 0; i < WM_SET_COUNT; i++) {
1050                           dc->clk_mgr->bw_params->wm_table.entries[i].sr_exit_time_us =
1051                                           dc->bb_overrides.sr_exit_time_ns / 1000.0;
1052                 }
1053         }
1054
1055         if (dc->bb_overrides.sr_enter_plus_exit_time_ns) {
1056                 for (i = 0; i < WM_SET_COUNT; i++) {
1057                           dc->clk_mgr->bw_params->wm_table.entries[i].sr_enter_plus_exit_time_us =
1058                                           dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
1059                 }
1060         }
1061
1062         if (dc->bb_overrides.urgent_latency_ns) {
1063                 bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
1064         }
1065
1066         if (dc->bb_overrides.dram_clock_change_latency_ns) {
1067                 for (i = 0; i < WM_SET_COUNT; i++) {
1068                         dc->clk_mgr->bw_params->wm_table.entries[i].pstate_latency_us =
1069                                 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
1070                 }
1071         }
1072
1073         DC_FP_END();
1074 }
1075
1076 void dcn21_calculate_wm(
1077                 struct dc *dc, struct dc_state *context,
1078                 display_e2e_pipe_params_st *pipes,
1079                 int *out_pipe_cnt,
1080                 int *pipe_split_from,
1081                 int vlevel_req)
1082 {
1083         int pipe_cnt, i, pipe_idx;
1084         int vlevel, vlevel_max;
1085         struct wm_range_table_entry *table_entry;
1086         struct clk_bw_params *bw_params = dc->clk_mgr->bw_params;
1087
1088         ASSERT(bw_params);
1089
1090         patch_bounding_box(dc, &context->bw_ctx.dml.soc);
1091
1092         for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1093                         if (!context->res_ctx.pipe_ctx[i].stream)
1094                                 continue;
1095
1096                         pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
1097                         pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb];
1098
1099                         if (pipe_split_from[i] < 0) {
1100                                 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
1101                                                 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
1102                                 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
1103                                         pipes[pipe_cnt].pipe.dest.odm_combine =
1104                                                         context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_idx];
1105                                 else
1106                                         pipes[pipe_cnt].pipe.dest.odm_combine = 0;
1107                                 pipe_idx++;
1108                         } else {
1109                                 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
1110                                                 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
1111                                 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])
1112                                         pipes[pipe_cnt].pipe.dest.odm_combine =
1113                                                         context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_split_from[i]];
1114                                 else
1115                                         pipes[pipe_cnt].pipe.dest.odm_combine = 0;
1116                         }
1117                         pipe_cnt++;
1118         }
1119
1120         if (pipe_cnt != pipe_idx) {
1121                 if (dc->res_pool->funcs->populate_dml_pipes)
1122                         pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
1123                                 context, pipes);
1124                 else
1125                         pipe_cnt = dcn21_populate_dml_pipes_from_context(dc,
1126                                 context, pipes);
1127         }
1128
1129         *out_pipe_cnt = pipe_cnt;
1130
1131         vlevel_max = bw_params->clk_table.num_entries - 1;
1132
1133
1134         /* WM Set D */
1135         table_entry = &bw_params->wm_table.entries[WM_D];
1136         if (table_entry->wm_type == WM_TYPE_RETRAINING)
1137                 vlevel = 0;
1138         else
1139                 vlevel = vlevel_max;
1140         calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d,
1141                                                 &context->bw_ctx.dml, pipes, pipe_cnt);
1142         /* WM Set C */
1143         table_entry = &bw_params->wm_table.entries[WM_C];
1144         vlevel = MIN(MAX(vlevel_req, 2), vlevel_max);
1145         calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c,
1146                                                 &context->bw_ctx.dml, pipes, pipe_cnt);
1147         /* WM Set B */
1148         table_entry = &bw_params->wm_table.entries[WM_B];
1149         vlevel = MIN(MAX(vlevel_req, 1), vlevel_max);
1150         calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b,
1151                                                 &context->bw_ctx.dml, pipes, pipe_cnt);
1152
1153         /* WM Set A */
1154         table_entry = &bw_params->wm_table.entries[WM_A];
1155         vlevel = MIN(vlevel_req, vlevel_max);
1156         calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a,
1157                                                 &context->bw_ctx.dml, pipes, pipe_cnt);
1158 }
1159
1160
1161 bool dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context,
1162                 bool fast_validate)
1163 {
1164         bool out = false;
1165
1166         BW_VAL_TRACE_SETUP();
1167
1168         int vlevel = 0;
1169         int pipe_split_from[MAX_PIPES];
1170         int pipe_cnt = 0;
1171         display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
1172         DC_LOGGER_INIT(dc->ctx->logger);
1173
1174         BW_VAL_TRACE_COUNT();
1175
1176         out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel);
1177
1178         if (pipe_cnt == 0)
1179                 goto validate_out;
1180
1181         if (!out)
1182                 goto validate_fail;
1183
1184         BW_VAL_TRACE_END_VOLTAGE_LEVEL();
1185
1186         if (fast_validate) {
1187                 BW_VAL_TRACE_SKIP(fast);
1188                 goto validate_out;
1189         }
1190
1191         dcn21_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel);
1192         dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
1193
1194         BW_VAL_TRACE_END_WATERMARKS();
1195
1196         goto validate_out;
1197
1198 validate_fail:
1199         DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
1200                 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
1201
1202         BW_VAL_TRACE_SKIP(fail);
1203         out = false;
1204
1205 validate_out:
1206         kfree(pipes);
1207
1208         BW_VAL_TRACE_FINISH();
1209
1210         return out;
1211 }
1212 static void dcn21_destroy_resource_pool(struct resource_pool **pool)
1213 {
1214         struct dcn21_resource_pool *dcn21_pool = TO_DCN21_RES_POOL(*pool);
1215
1216         dcn21_resource_destruct(dcn21_pool);
1217         kfree(dcn21_pool);
1218         *pool = NULL;
1219 }
1220
1221 static struct clock_source *dcn21_clock_source_create(
1222                 struct dc_context *ctx,
1223                 struct dc_bios *bios,
1224                 enum clock_source_id id,
1225                 const struct dce110_clk_src_regs *regs,
1226                 bool dp_clk_src)
1227 {
1228         struct dce110_clk_src *clk_src =
1229                 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1230
1231         if (!clk_src)
1232                 return NULL;
1233
1234         if (dcn20_clk_src_construct(clk_src, ctx, bios, id,
1235                         regs, &cs_shift, &cs_mask)) {
1236                 clk_src->base.dp_clk_src = dp_clk_src;
1237                 return &clk_src->base;
1238         }
1239
1240         BREAK_TO_DEBUGGER();
1241         return NULL;
1242 }
1243
1244 static struct hubp *dcn21_hubp_create(
1245         struct dc_context *ctx,
1246         uint32_t inst)
1247 {
1248         struct dcn21_hubp *hubp21 =
1249                 kzalloc(sizeof(struct dcn21_hubp), GFP_KERNEL);
1250
1251         if (!hubp21)
1252                 return NULL;
1253
1254         if (hubp21_construct(hubp21, ctx, inst,
1255                         &hubp_regs[inst], &hubp_shift, &hubp_mask))
1256                 return &hubp21->base;
1257
1258         BREAK_TO_DEBUGGER();
1259         kfree(hubp21);
1260         return NULL;
1261 }
1262
1263 static struct hubbub *dcn21_hubbub_create(struct dc_context *ctx)
1264 {
1265         int i;
1266
1267         struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub),
1268                                           GFP_KERNEL);
1269
1270         if (!hubbub)
1271                 return NULL;
1272
1273         hubbub21_construct(hubbub, ctx,
1274                         &hubbub_reg,
1275                         &hubbub_shift,
1276                         &hubbub_mask);
1277
1278         for (i = 0; i < res_cap_rn.num_vmid; i++) {
1279                 struct dcn20_vmid *vmid = &hubbub->vmid[i];
1280
1281                 vmid->ctx = ctx;
1282
1283                 vmid->regs = &vmid_regs[i];
1284                 vmid->shifts = &vmid_shifts;
1285                 vmid->masks = &vmid_masks;
1286         }
1287
1288         return &hubbub->base;
1289 }
1290
1291 struct output_pixel_processor *dcn21_opp_create(
1292         struct dc_context *ctx, uint32_t inst)
1293 {
1294         struct dcn20_opp *opp =
1295                 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
1296
1297         if (!opp) {
1298                 BREAK_TO_DEBUGGER();
1299                 return NULL;
1300         }
1301
1302         dcn20_opp_construct(opp, ctx, inst,
1303                         &opp_regs[inst], &opp_shift, &opp_mask);
1304         return &opp->base;
1305 }
1306
1307 struct timing_generator *dcn21_timing_generator_create(
1308                 struct dc_context *ctx,
1309                 uint32_t instance)
1310 {
1311         struct optc *tgn10 =
1312                 kzalloc(sizeof(struct optc), GFP_KERNEL);
1313
1314         if (!tgn10)
1315                 return NULL;
1316
1317         tgn10->base.inst = instance;
1318         tgn10->base.ctx = ctx;
1319
1320         tgn10->tg_regs = &tg_regs[instance];
1321         tgn10->tg_shift = &tg_shift;
1322         tgn10->tg_mask = &tg_mask;
1323
1324         dcn20_timing_generator_init(tgn10);
1325
1326         return &tgn10->base;
1327 }
1328
1329 struct mpc *dcn21_mpc_create(struct dc_context *ctx)
1330 {
1331         struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc),
1332                                           GFP_KERNEL);
1333
1334         if (!mpc20)
1335                 return NULL;
1336
1337         dcn20_mpc_construct(mpc20, ctx,
1338                         &mpc_regs,
1339                         &mpc_shift,
1340                         &mpc_mask,
1341                         6);
1342
1343         return &mpc20->base;
1344 }
1345
1346 static void read_dce_straps(
1347         struct dc_context *ctx,
1348         struct resource_straps *straps)
1349 {
1350         generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
1351                 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1352
1353 }
1354
1355
1356 struct display_stream_compressor *dcn21_dsc_create(
1357         struct dc_context *ctx, uint32_t inst)
1358 {
1359         struct dcn20_dsc *dsc =
1360                 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1361
1362         if (!dsc) {
1363                 BREAK_TO_DEBUGGER();
1364                 return NULL;
1365         }
1366
1367         dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1368         return &dsc->base;
1369 }
1370
1371 static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1372 {
1373         struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool);
1374         struct clk_limit_table *clk_table = &bw_params->clk_table;
1375         unsigned int i, j, k;
1376         int closest_clk_lvl;
1377
1378         // diags does not retrieve proper values from SMU
1379         // cap states to 5 and make state 5 the max state
1380         if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) || IS_DIAG_DC(dc->ctx->dce_environment)) {
1381                 dcn2_1_soc.num_states = 5;
1382
1383                 dcn2_1_soc.clock_limits[5].state = 5;
1384                 dcn2_1_soc.clock_limits[5].dcfclk_mhz = 810.0;
1385                 dcn2_1_soc.clock_limits[5].fabricclk_mhz = 1600.0;
1386                 dcn2_1_soc.clock_limits[5].dispclk_mhz = 1395.0;
1387                 dcn2_1_soc.clock_limits[5].dppclk_mhz = 1285.0;
1388                 dcn2_1_soc.clock_limits[5].phyclk_mhz = 1325.0;
1389                 dcn2_1_soc.clock_limits[5].socclk_mhz = 953.0;
1390                 dcn2_1_soc.clock_limits[5].dscclk_mhz = 489.0;
1391                 dcn2_1_soc.clock_limits[5].dram_speed_mts = 4266.0;
1392         } else {
1393                 dcn2_1_ip.max_num_otg = pool->base.res_cap->num_timing_generator;
1394                 dcn2_1_ip.max_num_dpp = pool->base.pipe_count;
1395                 dcn2_1_soc.num_chans = bw_params->num_channels;
1396
1397                 /* Vmin: leave lowest DCN clocks, override with dcfclk, fclk, memclk from fuse */
1398                 dcn2_1_soc.clock_limits[0].state = 0;
1399                 dcn2_1_soc.clock_limits[0].dcfclk_mhz = clk_table->entries[0].dcfclk_mhz;
1400                 dcn2_1_soc.clock_limits[0].fabricclk_mhz = clk_table->entries[0].fclk_mhz;
1401                 dcn2_1_soc.clock_limits[0].socclk_mhz = clk_table->entries[0].socclk_mhz;
1402                 dcn2_1_soc.clock_limits[0].dram_speed_mts = clk_table->entries[0].memclk_mhz * 2;
1403
1404                 /*
1405                  * Other levels: find cloest DCN clocks that fit the given clock limit using dcfclk
1406                  * as indicater
1407                  */
1408
1409                 closest_clk_lvl = -1;
1410                 /* index currently being filled */
1411                 k = 1;
1412                 for (i = 1; i < clk_table->num_entries; i++) {
1413                         /* loop backwards, skip duplicate state, +1 because SMU has precision issue */
1414                         for (j = dcn2_1_soc.num_states - 2; j >= k; j--) {
1415                                 if ((unsigned int) dcn2_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) {
1416                                         closest_clk_lvl = j;
1417                                         break;
1418                                 }
1419                         }
1420
1421                         /* if found a lvl that fits, use the DCN clks from it, if not, go to next clk limit*/
1422                         if (closest_clk_lvl != -1) {
1423                                 dcn2_1_soc.clock_limits[k].state = i;
1424                                 dcn2_1_soc.clock_limits[k].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
1425                                 dcn2_1_soc.clock_limits[k].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
1426                                 dcn2_1_soc.clock_limits[k].socclk_mhz = clk_table->entries[i].socclk_mhz;
1427                                 dcn2_1_soc.clock_limits[k].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;
1428
1429                                 dcn2_1_soc.clock_limits[k].dispclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
1430                                 dcn2_1_soc.clock_limits[k].dppclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
1431                                 dcn2_1_soc.clock_limits[k].dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
1432                                 dcn2_1_soc.clock_limits[k].dscclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
1433                                 dcn2_1_soc.clock_limits[k].dtbclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
1434                                 dcn2_1_soc.clock_limits[k].phyclk_d18_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
1435                                 dcn2_1_soc.clock_limits[k].phyclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
1436                                 k++;
1437                         }
1438                 }
1439
1440                 /* duplicate last level */
1441                 dcn2_1_soc.clock_limits[k] = dcn2_1_soc.clock_limits[k - 1];
1442                 dcn2_1_soc.clock_limits[k].state = k;
1443                 dcn2_1_soc.num_states = k + 1;
1444         }
1445
1446         dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);
1447 }
1448
1449 /* Temporary Place holder until we can get them from fuse */
1450 static struct dpm_clocks dummy_clocks = {
1451                 .DcfClocks = {
1452                                 {.Freq = 400, .Vol = 1},
1453                                 {.Freq = 483, .Vol = 1},
1454                                 {.Freq = 602, .Vol = 1},
1455                                 {.Freq = 738, .Vol = 1} },
1456                 .SocClocks = {
1457                                 {.Freq = 300, .Vol = 1},
1458                                 {.Freq = 400, .Vol = 1},
1459                                 {.Freq = 400, .Vol = 1},
1460                                 {.Freq = 400, .Vol = 1} },
1461                 .FClocks = {
1462                                 {.Freq = 400, .Vol = 1},
1463                                 {.Freq = 800, .Vol = 1},
1464                                 {.Freq = 1067, .Vol = 1},
1465                                 {.Freq = 1600, .Vol = 1} },
1466                 .MemClocks = {
1467                                 {.Freq = 800, .Vol = 1},
1468                                 {.Freq = 1600, .Vol = 1},
1469                                 {.Freq = 1067, .Vol = 1},
1470                                 {.Freq = 1600, .Vol = 1} },
1471
1472 };
1473
1474 static enum pp_smu_status dummy_set_wm_ranges(struct pp_smu *pp,
1475                 struct pp_smu_wm_range_sets *ranges)
1476 {
1477         return PP_SMU_RESULT_OK;
1478 }
1479
1480 static enum pp_smu_status dummy_get_dpm_clock_table(struct pp_smu *pp,
1481                 struct dpm_clocks *clock_table)
1482 {
1483         *clock_table = dummy_clocks;
1484         return PP_SMU_RESULT_OK;
1485 }
1486
1487 static struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx)
1488 {
1489         struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
1490
1491         if (!pp_smu)
1492                 return pp_smu;
1493
1494         if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment) || IS_DIAG_DC(ctx->dce_environment)) {
1495                 pp_smu->ctx.ver = PP_SMU_VER_RN;
1496                 pp_smu->rn_funcs.get_dpm_clock_table = dummy_get_dpm_clock_table;
1497                 pp_smu->rn_funcs.set_wm_ranges = dummy_set_wm_ranges;
1498         } else {
1499
1500                 dm_pp_get_funcs(ctx, pp_smu);
1501
1502                 if (pp_smu->ctx.ver != PP_SMU_VER_RN)
1503                         pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs));
1504         }
1505
1506         return pp_smu;
1507 }
1508
1509 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
1510 {
1511         if (pp_smu && *pp_smu) {
1512                 kfree(*pp_smu);
1513                 *pp_smu = NULL;
1514         }
1515 }
1516
1517 static struct audio *dcn21_create_audio(
1518                 struct dc_context *ctx, unsigned int inst)
1519 {
1520         return dce_audio_create(ctx, inst,
1521                         &audio_regs[inst], &audio_shift, &audio_mask);
1522 }
1523
1524 static struct dc_cap_funcs cap_funcs = {
1525         .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1526 };
1527
1528 struct stream_encoder *dcn21_stream_encoder_create(
1529         enum engine_id eng_id,
1530         struct dc_context *ctx)
1531 {
1532         struct dcn10_stream_encoder *enc1 =
1533                 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1534
1535         if (!enc1)
1536                 return NULL;
1537
1538         dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
1539                                         &stream_enc_regs[eng_id],
1540                                         &se_shift, &se_mask);
1541
1542         return &enc1->base;
1543 }
1544
1545 static const struct dce_hwseq_registers hwseq_reg = {
1546                 HWSEQ_DCN21_REG_LIST()
1547 };
1548
1549 static const struct dce_hwseq_shift hwseq_shift = {
1550                 HWSEQ_DCN21_MASK_SH_LIST(__SHIFT)
1551 };
1552
1553 static const struct dce_hwseq_mask hwseq_mask = {
1554                 HWSEQ_DCN21_MASK_SH_LIST(_MASK)
1555 };
1556
1557 static struct dce_hwseq *dcn21_hwseq_create(
1558         struct dc_context *ctx)
1559 {
1560         struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1561
1562         if (hws) {
1563                 hws->ctx = ctx;
1564                 hws->regs = &hwseq_reg;
1565                 hws->shifts = &hwseq_shift;
1566                 hws->masks = &hwseq_mask;
1567                 hws->wa.DEGVIDCN21 = true;
1568                 hws->wa.disallow_self_refresh_during_multi_plane_transition = true;
1569         }
1570         return hws;
1571 }
1572
1573 static const struct resource_create_funcs res_create_funcs = {
1574         .read_dce_straps = read_dce_straps,
1575         .create_audio = dcn21_create_audio,
1576         .create_stream_encoder = dcn21_stream_encoder_create,
1577         .create_hwseq = dcn21_hwseq_create,
1578 };
1579
1580 static const struct resource_create_funcs res_create_maximus_funcs = {
1581         .read_dce_straps = NULL,
1582         .create_audio = NULL,
1583         .create_stream_encoder = NULL,
1584         .create_hwseq = dcn21_hwseq_create,
1585 };
1586
1587 static const struct encoder_feature_support link_enc_feature = {
1588                 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1589                 .max_hdmi_pixel_clock = 600000,
1590                 .hdmi_ycbcr420_supported = true,
1591                 .dp_ycbcr420_supported = true,
1592                 .flags.bits.IS_HBR2_CAPABLE = true,
1593                 .flags.bits.IS_HBR3_CAPABLE = true,
1594                 .flags.bits.IS_TPS3_CAPABLE = true,
1595                 .flags.bits.IS_TPS4_CAPABLE = true
1596 };
1597
1598
1599 #define link_regs(id, phyid)\
1600 [id] = {\
1601         LE_DCN2_REG_LIST(id), \
1602         UNIPHY_DCN2_REG_LIST(phyid), \
1603         DPCS_DCN21_REG_LIST(id), \
1604         SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
1605 }
1606
1607 static const struct dcn10_link_enc_registers link_enc_regs[] = {
1608         link_regs(0, A),
1609         link_regs(1, B),
1610         link_regs(2, C),
1611         link_regs(3, D),
1612         link_regs(4, E),
1613 };
1614
1615 #define aux_regs(id)\
1616 [id] = {\
1617         DCN2_AUX_REG_LIST(id)\
1618 }
1619
1620 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
1621                 aux_regs(0),
1622                 aux_regs(1),
1623                 aux_regs(2),
1624                 aux_regs(3),
1625                 aux_regs(4)
1626 };
1627
1628 #define hpd_regs(id)\
1629 [id] = {\
1630         HPD_REG_LIST(id)\
1631 }
1632
1633 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
1634                 hpd_regs(0),
1635                 hpd_regs(1),
1636                 hpd_regs(2),
1637                 hpd_regs(3),
1638                 hpd_regs(4)
1639 };
1640
1641 static const struct dcn10_link_enc_shift le_shift = {
1642         LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT),\
1643         DPCS_DCN21_MASK_SH_LIST(__SHIFT)
1644 };
1645
1646 static const struct dcn10_link_enc_mask le_mask = {
1647         LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\
1648         DPCS_DCN21_MASK_SH_LIST(_MASK)
1649 };
1650
1651 static int map_transmitter_id_to_phy_instance(
1652         enum transmitter transmitter)
1653 {
1654         switch (transmitter) {
1655         case TRANSMITTER_UNIPHY_A:
1656                 return 0;
1657         break;
1658         case TRANSMITTER_UNIPHY_B:
1659                 return 1;
1660         break;
1661         case TRANSMITTER_UNIPHY_C:
1662                 return 2;
1663         break;
1664         case TRANSMITTER_UNIPHY_D:
1665                 return 3;
1666         break;
1667         case TRANSMITTER_UNIPHY_E:
1668                 return 4;
1669         break;
1670         default:
1671                 ASSERT(0);
1672                 return 0;
1673         }
1674 }
1675
1676 static struct link_encoder *dcn21_link_encoder_create(
1677         const struct encoder_init_data *enc_init_data)
1678 {
1679         struct dcn21_link_encoder *enc21 =
1680                 kzalloc(sizeof(struct dcn21_link_encoder), GFP_KERNEL);
1681         int link_regs_id;
1682
1683         if (!enc21)
1684                 return NULL;
1685
1686         link_regs_id =
1687                 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
1688
1689         dcn21_link_encoder_construct(enc21,
1690                                       enc_init_data,
1691                                       &link_enc_feature,
1692                                       &link_enc_regs[link_regs_id],
1693                                       &link_enc_aux_regs[enc_init_data->channel - 1],
1694                                       &link_enc_hpd_regs[enc_init_data->hpd_source],
1695                                       &le_shift,
1696                                       &le_mask);
1697
1698         return &enc21->enc10.base;
1699 }
1700 #define CTX ctx
1701
1702 #define REG(reg_name) \
1703         (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
1704
1705 static uint32_t read_pipe_fuses(struct dc_context *ctx)
1706 {
1707         uint32_t value = REG_READ(CC_DC_PIPE_DIS);
1708         /* RV1 support max 4 pipes */
1709         value = value & 0xf;
1710         return value;
1711 }
1712
1713 static int dcn21_populate_dml_pipes_from_context(
1714                 struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes)
1715 {
1716         uint32_t pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes);
1717         int i;
1718         struct resource_context *res_ctx = &context->res_ctx;
1719
1720         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1721
1722                 if (!res_ctx->pipe_ctx[i].stream)
1723                         continue;
1724
1725                 pipes[i].pipe.src.hostvm = 1;
1726                 pipes[i].pipe.src.gpuvm = 1;
1727         }
1728
1729         return pipe_cnt;
1730 }
1731
1732 static struct resource_funcs dcn21_res_pool_funcs = {
1733         .destroy = dcn21_destroy_resource_pool,
1734         .link_enc_create = dcn21_link_encoder_create,
1735         .validate_bandwidth = dcn21_validate_bandwidth,
1736         .populate_dml_pipes = dcn21_populate_dml_pipes_from_context,
1737         .add_stream_to_ctx = dcn20_add_stream_to_ctx,
1738         .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1739         .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
1740         .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context,
1741         .get_default_swizzle_mode = dcn20_get_default_swizzle_mode,
1742         .set_mcif_arb_params = dcn20_set_mcif_arb_params,
1743         .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1744         .update_bw_bounding_box = update_bw_bounding_box
1745 };
1746
1747 static bool dcn21_resource_construct(
1748         uint8_t num_virtual_links,
1749         struct dc *dc,
1750         struct dcn21_resource_pool *pool)
1751 {
1752         int i, j;
1753         struct dc_context *ctx = dc->ctx;
1754         struct irq_service_init_data init_data;
1755         uint32_t pipe_fuses = read_pipe_fuses(ctx);
1756         uint32_t num_pipes;
1757
1758         ctx->dc_bios->regs = &bios_regs;
1759
1760         pool->base.res_cap = &res_cap_rn;
1761 #ifdef DIAGS_BUILD
1762         if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
1763                 //pool->base.res_cap = &res_cap_nv10_FPGA_2pipe_dsc;
1764                 pool->base.res_cap = &res_cap_rn_FPGA_4pipe;
1765 #endif
1766
1767         pool->base.funcs = &dcn21_res_pool_funcs;
1768
1769         /*************************************************
1770          *  Resource + asic cap harcoding                *
1771          *************************************************/
1772         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1773
1774         /* max pipe num for ASIC before check pipe fuses */
1775         pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1776
1777         dc->caps.max_downscale_ratio = 200;
1778         dc->caps.i2c_speed_in_khz = 100;
1779         dc->caps.max_cursor_size = 256;
1780         dc->caps.dmdata_alloc_size = 2048;
1781         dc->caps.hw_3d_lut = true;
1782
1783         dc->caps.max_slave_planes = 1;
1784         dc->caps.post_blend_color_processing = true;
1785         dc->caps.force_dp_tps4_for_cp2520 = true;
1786         dc->caps.extended_aux_timeout_support = true;
1787         dc->caps.dmcub_support = true;
1788
1789         if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1790                 dc->debug = debug_defaults_drv;
1791         else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
1792                 pool->base.pipe_count = 4;
1793                 dc->debug = debug_defaults_diags;
1794         } else
1795                 dc->debug = debug_defaults_diags;
1796
1797         // Init the vm_helper
1798         if (dc->vm_helper)
1799                 vm_helper_init(dc->vm_helper, 16);
1800
1801         /*************************************************
1802          *  Create resources                             *
1803          *************************************************/
1804
1805         pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =
1806                         dcn21_clock_source_create(ctx, ctx->dc_bios,
1807                                 CLOCK_SOURCE_COMBO_PHY_PLL0,
1808                                 &clk_src_regs[0], false);
1809         pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =
1810                         dcn21_clock_source_create(ctx, ctx->dc_bios,
1811                                 CLOCK_SOURCE_COMBO_PHY_PLL1,
1812                                 &clk_src_regs[1], false);
1813         pool->base.clock_sources[DCN20_CLK_SRC_PLL2] =
1814                         dcn21_clock_source_create(ctx, ctx->dc_bios,
1815                                 CLOCK_SOURCE_COMBO_PHY_PLL2,
1816                                 &clk_src_regs[2], false);
1817
1818         pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN21;
1819
1820         /* todo: not reuse phy_pll registers */
1821         pool->base.dp_clock_source =
1822                         dcn21_clock_source_create(ctx, ctx->dc_bios,
1823                                 CLOCK_SOURCE_ID_DP_DTO,
1824                                 &clk_src_regs[0], true);
1825
1826         for (i = 0; i < pool->base.clk_src_count; i++) {
1827                 if (pool->base.clock_sources[i] == NULL) {
1828                         dm_error("DC: failed to create clock sources!\n");
1829                         BREAK_TO_DEBUGGER();
1830                         goto create_fail;
1831                 }
1832         }
1833
1834         pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1835         if (pool->base.dccg == NULL) {
1836                 dm_error("DC: failed to create dccg!\n");
1837                 BREAK_TO_DEBUGGER();
1838                 goto create_fail;
1839         }
1840
1841         pool->base.dmcu = dcn21_dmcu_create(ctx,
1842                         &dmcu_regs,
1843                         &dmcu_shift,
1844                         &dmcu_mask);
1845         if (pool->base.dmcu == NULL) {
1846                 dm_error("DC: failed to create dmcu!\n");
1847                 BREAK_TO_DEBUGGER();
1848                 goto create_fail;
1849         }
1850
1851         if (dc->config.psr_on_dmub) {
1852                 pool->base.psr = dmub_psr_create(ctx);
1853
1854                 if (pool->base.psr == NULL) {
1855                         dm_error("DC: failed to create psr obj!\n");
1856                         BREAK_TO_DEBUGGER();
1857                         goto create_fail;
1858                 }
1859         }
1860
1861         pool->base.abm = dce_abm_create(ctx,
1862                         &abm_regs,
1863                         &abm_shift,
1864                         &abm_mask);
1865         if (pool->base.abm == NULL) {
1866                 dm_error("DC: failed to create abm!\n");
1867                 BREAK_TO_DEBUGGER();
1868                 goto create_fail;
1869         }
1870
1871         pool->base.pp_smu = dcn21_pp_smu_create(ctx);
1872
1873         num_pipes = dcn2_1_ip.max_num_dpp;
1874
1875         for (i = 0; i < dcn2_1_ip.max_num_dpp; i++)
1876                 if (pipe_fuses & 1 << i)
1877                         num_pipes--;
1878         dcn2_1_ip.max_num_dpp = num_pipes;
1879         dcn2_1_ip.max_num_otg = num_pipes;
1880
1881         dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);
1882
1883         init_data.ctx = dc->ctx;
1884         pool->base.irqs = dal_irq_service_dcn21_create(&init_data);
1885         if (!pool->base.irqs)
1886                 goto create_fail;
1887
1888         j = 0;
1889         /* mem input -> ipp -> dpp -> opp -> TG */
1890         for (i = 0; i < pool->base.pipe_count; i++) {
1891                 /* if pipe is disabled, skip instance of HW pipe,
1892                  * i.e, skip ASIC register instance
1893                  */
1894                 if ((pipe_fuses & (1 << i)) != 0)
1895                         continue;
1896
1897                 pool->base.hubps[j] = dcn21_hubp_create(ctx, i);
1898                 if (pool->base.hubps[j] == NULL) {
1899                         BREAK_TO_DEBUGGER();
1900                         dm_error(
1901                                 "DC: failed to create memory input!\n");
1902                         goto create_fail;
1903                 }
1904
1905                 pool->base.ipps[j] = dcn21_ipp_create(ctx, i);
1906                 if (pool->base.ipps[j] == NULL) {
1907                         BREAK_TO_DEBUGGER();
1908                         dm_error(
1909                                 "DC: failed to create input pixel processor!\n");
1910                         goto create_fail;
1911                 }
1912
1913                 pool->base.dpps[j] = dcn21_dpp_create(ctx, i);
1914                 if (pool->base.dpps[j] == NULL) {
1915                         BREAK_TO_DEBUGGER();
1916                         dm_error(
1917                                 "DC: failed to create dpps!\n");
1918                         goto create_fail;
1919                 }
1920
1921                 pool->base.opps[j] = dcn21_opp_create(ctx, i);
1922                 if (pool->base.opps[j] == NULL) {
1923                         BREAK_TO_DEBUGGER();
1924                         dm_error(
1925                                 "DC: failed to create output pixel processor!\n");
1926                         goto create_fail;
1927                 }
1928
1929                 pool->base.timing_generators[j] = dcn21_timing_generator_create(
1930                                 ctx, i);
1931                 if (pool->base.timing_generators[j] == NULL) {
1932                         BREAK_TO_DEBUGGER();
1933                         dm_error("DC: failed to create tg!\n");
1934                         goto create_fail;
1935                 }
1936                 j++;
1937         }
1938
1939         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1940                 pool->base.engines[i] = dcn21_aux_engine_create(ctx, i);
1941                 if (pool->base.engines[i] == NULL) {
1942                         BREAK_TO_DEBUGGER();
1943                         dm_error(
1944                                 "DC:failed to create aux engine!!\n");
1945                         goto create_fail;
1946                 }
1947                 pool->base.hw_i2cs[i] = dcn21_i2c_hw_create(ctx, i);
1948                 if (pool->base.hw_i2cs[i] == NULL) {
1949                         BREAK_TO_DEBUGGER();
1950                         dm_error(
1951                                 "DC:failed to create hw i2c!!\n");
1952                         goto create_fail;
1953                 }
1954                 pool->base.sw_i2cs[i] = NULL;
1955         }
1956
1957         pool->base.timing_generator_count = j;
1958         pool->base.pipe_count = j;
1959         pool->base.mpcc_count = j;
1960
1961         pool->base.mpc = dcn21_mpc_create(ctx);
1962         if (pool->base.mpc == NULL) {
1963                 BREAK_TO_DEBUGGER();
1964                 dm_error("DC: failed to create mpc!\n");
1965                 goto create_fail;
1966         }
1967
1968         pool->base.hubbub = dcn21_hubbub_create(ctx);
1969         if (pool->base.hubbub == NULL) {
1970                 BREAK_TO_DEBUGGER();
1971                 dm_error("DC: failed to create hubbub!\n");
1972                 goto create_fail;
1973         }
1974
1975         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1976                 pool->base.dscs[i] = dcn21_dsc_create(ctx, i);
1977                 if (pool->base.dscs[i] == NULL) {
1978                         BREAK_TO_DEBUGGER();
1979                         dm_error("DC: failed to create display stream compressor %d!\n", i);
1980                         goto create_fail;
1981                 }
1982         }
1983
1984         if (!dcn20_dwbc_create(ctx, &pool->base)) {
1985                 BREAK_TO_DEBUGGER();
1986                 dm_error("DC: failed to create dwbc!\n");
1987                 goto create_fail;
1988         }
1989         if (!dcn20_mmhubbub_create(ctx, &pool->base)) {
1990                 BREAK_TO_DEBUGGER();
1991                 dm_error("DC: failed to create mcif_wb!\n");
1992                 goto create_fail;
1993         }
1994
1995         if (!resource_construct(num_virtual_links, dc, &pool->base,
1996                         (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
1997                         &res_create_funcs : &res_create_maximus_funcs)))
1998                         goto create_fail;
1999
2000         dcn21_hw_sequencer_construct(dc);
2001
2002         dc->caps.max_planes =  pool->base.pipe_count;
2003
2004         for (i = 0; i < dc->caps.max_planes; ++i)
2005                 dc->caps.planes[i] = plane_cap;
2006
2007         dc->cap_funcs = cap_funcs;
2008
2009         return true;
2010
2011 create_fail:
2012
2013         dcn21_resource_destruct(pool);
2014
2015         return false;
2016 }
2017
2018 struct resource_pool *dcn21_create_resource_pool(
2019                 const struct dc_init_data *init_data,
2020                 struct dc *dc)
2021 {
2022         struct dcn21_resource_pool *pool =
2023                 kzalloc(sizeof(struct dcn21_resource_pool), GFP_KERNEL);
2024
2025         if (!pool)
2026                 return NULL;
2027
2028         if (dcn21_resource_construct(init_data->num_virtual_links, dc, pool))
2029                 return &pool->base;
2030
2031         BREAK_TO_DEBUGGER();
2032         kfree(pool);
2033         return NULL;
2034 }