2 * Copyright 2018 Advanced Micro Devices, Inc.
3 * Copyright 2019 Raptor Engineering, LLC
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
27 #include <linux/slab.h>
29 #include "dm_services.h"
32 #include "dcn21_init.h"
35 #include "include/irq_service_interface.h"
36 #include "dcn20/dcn20_resource.h"
37 #include "dcn21/dcn21_resource.h"
39 #include "dml/dcn20/dcn20_fpu.h"
42 #include "dcn10/dcn10_hubp.h"
43 #include "dcn10/dcn10_ipp.h"
44 #include "dcn20/dcn20_hubbub.h"
45 #include "dcn20/dcn20_mpc.h"
46 #include "dcn20/dcn20_hubp.h"
47 #include "dcn21_hubp.h"
48 #include "irq/dcn21/irq_service_dcn21.h"
49 #include "dcn20/dcn20_dpp.h"
50 #include "dcn20/dcn20_optc.h"
51 #include "dcn21/dcn21_hwseq.h"
52 #include "dce110/dce110_hw_sequencer.h"
53 #include "dcn20/dcn20_opp.h"
54 #include "dcn20/dcn20_dsc.h"
55 #include "dcn21/dcn21_link_encoder.h"
56 #include "dcn20/dcn20_stream_encoder.h"
57 #include "dce/dce_clock_source.h"
58 #include "dce/dce_audio.h"
59 #include "dce/dce_hwseq.h"
60 #include "virtual/virtual_stream_encoder.h"
61 #include "dml/display_mode_vba.h"
62 #include "dcn20/dcn20_dccg.h"
63 #include "dcn21/dcn21_dccg.h"
64 #include "dcn21_hubbub.h"
65 #include "dcn10/dcn10_resource.h"
66 #include "dce/dce_panel_cntl.h"
68 #include "dcn20/dcn20_dwb.h"
69 #include "dcn20/dcn20_mmhubbub.h"
70 #include "dpcs/dpcs_2_1_0_offset.h"
71 #include "dpcs/dpcs_2_1_0_sh_mask.h"
73 #include "renoir_ip_offset.h"
74 #include "dcn/dcn_2_1_0_offset.h"
75 #include "dcn/dcn_2_1_0_sh_mask.h"
77 #include "nbio/nbio_7_0_offset.h"
79 #include "mmhub/mmhub_2_0_0_offset.h"
80 #include "mmhub/mmhub_2_0_0_sh_mask.h"
82 #include "reg_helper.h"
83 #include "dce/dce_abm.h"
84 #include "dce/dce_dmcu.h"
85 #include "dce/dce_aux.h"
86 #include "dce/dce_i2c.h"
87 #include "dcn21_resource.h"
88 #include "vm_helper.h"
89 #include "dcn20/dcn20_vmid.h"
90 #include "dce/dmub_psr.h"
91 #include "dce/dmub_abm.h"
93 /* begin *********************
94 * macros to expend register list macro defined in HW object header file */
97 /* TODO awful hack. fixup dcn20_dwb.h */
99 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
101 #define BASE(seg) BASE_INNER(seg)
103 #define SR(reg_name)\
104 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
107 #define SRI(reg_name, block, id)\
108 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
109 mm ## block ## id ## _ ## reg_name
111 #define SRIR(var_name, reg_name, block, id)\
112 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
113 mm ## block ## id ## _ ## reg_name
115 #define SRII(reg_name, block, id)\
116 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
117 mm ## block ## id ## _ ## reg_name
119 #define DCCG_SRII(reg_name, block, id)\
120 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
121 mm ## block ## id ## _ ## reg_name
123 #define VUPDATE_SRII(reg_name, block, id)\
124 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
125 mm ## reg_name ## _ ## block ## id
128 #define NBIO_BASE_INNER(seg) \
129 NBIF0_BASE__INST0_SEG ## seg
131 #define NBIO_BASE(seg) \
134 #define NBIO_SR(reg_name)\
135 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
139 #define MMHUB_BASE_INNER(seg) \
140 MMHUB_BASE__INST0_SEG ## seg
142 #define MMHUB_BASE(seg) \
143 MMHUB_BASE_INNER(seg)
145 #define MMHUB_SR(reg_name)\
146 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
149 #define clk_src_regs(index, pllid)\
151 CS_COMMON_REG_LIST_DCN2_1(index, pllid),\
154 static const struct dce110_clk_src_regs clk_src_regs[] = {
162 static const struct dce110_clk_src_shift cs_shift = {
163 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
166 static const struct dce110_clk_src_mask cs_mask = {
167 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
170 static const struct bios_registers bios_regs = {
171 NBIO_SR(BIOS_SCRATCH_3),
172 NBIO_SR(BIOS_SCRATCH_6)
175 static const struct dce_dmcu_registers dmcu_regs = {
176 DMCU_DCN20_REG_LIST()
179 static const struct dce_dmcu_shift dmcu_shift = {
180 DMCU_MASK_SH_LIST_DCN10(__SHIFT)
183 static const struct dce_dmcu_mask dmcu_mask = {
184 DMCU_MASK_SH_LIST_DCN10(_MASK)
187 static const struct dce_abm_registers abm_regs = {
191 static const struct dce_abm_shift abm_shift = {
192 ABM_MASK_SH_LIST_DCN20(__SHIFT)
195 static const struct dce_abm_mask abm_mask = {
196 ABM_MASK_SH_LIST_DCN20(_MASK)
199 #define audio_regs(id)\
201 AUD_COMMON_REG_LIST(id)\
204 static const struct dce_audio_registers audio_regs[] = {
213 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
214 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
215 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
216 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
218 static const struct dce_audio_shift audio_shift = {
219 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
222 static const struct dce_audio_mask audio_mask = {
223 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
226 static const struct dccg_registers dccg_regs = {
227 DCCG_COMMON_REG_LIST_DCN_BASE()
230 static const struct dccg_shift dccg_shift = {
231 DCCG_MASK_SH_LIST_DCN2_1(__SHIFT)
234 static const struct dccg_mask dccg_mask = {
235 DCCG_MASK_SH_LIST_DCN2_1(_MASK)
238 #define opp_regs(id)\
240 OPP_REG_LIST_DCN20(id),\
243 static const struct dcn20_opp_registers opp_regs[] = {
252 static const struct dcn20_opp_shift opp_shift = {
253 OPP_MASK_SH_LIST_DCN20(__SHIFT)
256 static const struct dcn20_opp_mask opp_mask = {
257 OPP_MASK_SH_LIST_DCN20(_MASK)
261 [id] = {TG_COMMON_REG_LIST_DCN2_0(id)}
263 static const struct dcn_optc_registers tg_regs[] = {
270 static const struct dcn_optc_shift tg_shift = {
271 TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
274 static const struct dcn_optc_mask tg_mask = {
275 TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
278 static const struct dcn20_mpc_registers mpc_regs = {
279 MPC_REG_LIST_DCN2_0(0),
280 MPC_REG_LIST_DCN2_0(1),
281 MPC_REG_LIST_DCN2_0(2),
282 MPC_REG_LIST_DCN2_0(3),
283 MPC_REG_LIST_DCN2_0(4),
284 MPC_REG_LIST_DCN2_0(5),
285 MPC_OUT_MUX_REG_LIST_DCN2_0(0),
286 MPC_OUT_MUX_REG_LIST_DCN2_0(1),
287 MPC_OUT_MUX_REG_LIST_DCN2_0(2),
288 MPC_OUT_MUX_REG_LIST_DCN2_0(3),
289 MPC_DBG_REG_LIST_DCN2_0()
292 static const struct dcn20_mpc_shift mpc_shift = {
293 MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT),
294 MPC_DEBUG_REG_LIST_SH_DCN20
297 static const struct dcn20_mpc_mask mpc_mask = {
298 MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK),
299 MPC_DEBUG_REG_LIST_MASK_DCN20
302 #define hubp_regs(id)\
304 HUBP_REG_LIST_DCN21(id)\
307 static const struct dcn_hubp2_registers hubp_regs[] = {
314 static const struct dcn_hubp2_shift hubp_shift = {
315 HUBP_MASK_SH_LIST_DCN21(__SHIFT)
318 static const struct dcn_hubp2_mask hubp_mask = {
319 HUBP_MASK_SH_LIST_DCN21(_MASK)
322 static const struct dcn_hubbub_registers hubbub_reg = {
323 HUBBUB_REG_LIST_DCN21()
326 static const struct dcn_hubbub_shift hubbub_shift = {
327 HUBBUB_MASK_SH_LIST_DCN21(__SHIFT)
330 static const struct dcn_hubbub_mask hubbub_mask = {
331 HUBBUB_MASK_SH_LIST_DCN21(_MASK)
335 #define vmid_regs(id)\
337 DCN20_VMID_REG_LIST(id)\
340 static const struct dcn_vmid_registers vmid_regs[] = {
359 static const struct dcn20_vmid_shift vmid_shifts = {
360 DCN20_VMID_MASK_SH_LIST(__SHIFT)
363 static const struct dcn20_vmid_mask vmid_masks = {
364 DCN20_VMID_MASK_SH_LIST(_MASK)
367 #define dsc_regsDCN20(id)\
369 DSC_REG_LIST_DCN20(id)\
372 static const struct dcn20_dsc_registers dsc_regs[] = {
381 static const struct dcn20_dsc_shift dsc_shift = {
382 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
385 static const struct dcn20_dsc_mask dsc_mask = {
386 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
389 #define ipp_regs(id)\
391 IPP_REG_LIST_DCN20(id),\
394 static const struct dcn10_ipp_registers ipp_regs[] = {
401 static const struct dcn10_ipp_shift ipp_shift = {
402 IPP_MASK_SH_LIST_DCN20(__SHIFT)
405 static const struct dcn10_ipp_mask ipp_mask = {
406 IPP_MASK_SH_LIST_DCN20(_MASK),
409 #define opp_regs(id)\
411 OPP_REG_LIST_DCN20(id),\
415 #define aux_engine_regs(id)\
417 AUX_COMMON_REG_LIST0(id), \
420 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
423 static const struct dce110_aux_registers aux_engine_regs[] = {
433 TF_REG_LIST_DCN20(id),\
434 TF_REG_LIST_DCN20_COMMON_APPEND(id),\
437 static const struct dcn2_dpp_registers tf_regs[] = {
444 static const struct dcn2_dpp_shift tf_shift = {
445 TF_REG_LIST_SH_MASK_DCN20(__SHIFT),
446 TF_DEBUG_REG_LIST_SH_DCN20
449 static const struct dcn2_dpp_mask tf_mask = {
450 TF_REG_LIST_SH_MASK_DCN20(_MASK),
451 TF_DEBUG_REG_LIST_MASK_DCN20
454 #define stream_enc_regs(id)\
456 SE_DCN2_REG_LIST(id)\
459 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
467 static const struct dce110_aux_registers_shift aux_shift = {
468 DCN_AUX_MASK_SH_LIST(__SHIFT)
471 static const struct dce110_aux_registers_mask aux_mask = {
472 DCN_AUX_MASK_SH_LIST(_MASK)
475 static const struct dcn10_stream_encoder_shift se_shift = {
476 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)
479 static const struct dcn10_stream_encoder_mask se_mask = {
480 SE_COMMON_MASK_SH_LIST_DCN20(_MASK)
483 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
485 static struct input_pixel_processor *dcn21_ipp_create(
486 struct dc_context *ctx, uint32_t inst)
488 struct dcn10_ipp *ipp =
489 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);
496 dcn20_ipp_construct(ipp, ctx, inst,
497 &ipp_regs[inst], &ipp_shift, &ipp_mask);
501 static struct dpp *dcn21_dpp_create(
502 struct dc_context *ctx,
505 struct dcn20_dpp *dpp =
506 kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL);
511 if (dpp2_construct(dpp, ctx, inst,
512 &tf_regs[inst], &tf_shift, &tf_mask))
520 static struct dce_aux *dcn21_aux_engine_create(
521 struct dc_context *ctx,
524 struct aux_engine_dce110 *aux_engine =
525 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
530 dce110_aux_engine_construct(aux_engine, ctx, inst,
531 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
532 &aux_engine_regs[inst],
535 ctx->dc->caps.extended_aux_timeout_support);
537 return &aux_engine->base;
540 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
542 static const struct dce_i2c_registers i2c_hw_regs[] = {
550 static const struct dce_i2c_shift i2c_shifts = {
551 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
554 static const struct dce_i2c_mask i2c_masks = {
555 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
558 static struct dce_i2c_hw *dcn21_i2c_hw_create(struct dc_context *ctx,
561 struct dce_i2c_hw *dce_i2c_hw =
562 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
567 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
568 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
573 static const struct resource_caps res_cap_rn = {
574 .num_timing_generator = 4,
576 .num_video_plane = 4,
577 .num_audio = 4, // 4 audio endpoints. 4 audio streams
578 .num_stream_encoder = 5,
579 .num_pll = 5, // maybe 3 because the last two used for USB-c
587 static const struct resource_caps res_cap_rn_FPGA_4pipe = {
588 .num_timing_generator = 4,
590 .num_video_plane = 4,
592 .num_stream_encoder = 4,
599 static const struct resource_caps res_cap_rn_FPGA_2pipe_dsc = {
600 .num_timing_generator = 2,
602 .num_video_plane = 2,
604 .num_stream_encoder = 2,
612 static const struct dc_plane_cap plane_cap = {
613 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
614 .blends_with_above = true,
615 .blends_with_below = true,
616 .per_pixel_alpha = true,
618 .pixel_format_support = {
625 .max_upscale_factor = {
631 .max_downscale_factor = {
640 static const struct dc_debug_options debug_defaults_drv = {
641 .disable_dmcu = false,
642 .force_abm_enable = false,
643 .timing_trace = false,
645 .disable_pplib_clock_request = true,
646 .min_disp_clk_khz = 100000,
647 .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
648 .force_single_disp_pipe_split = false,
649 .disable_dcc = DCC_ENABLE,
651 .performance_trace = false,
652 .max_downscale_src_width = 4096,
653 .disable_pplib_wm_range = false,
654 .scl_reset_length10 = true,
655 .sanity_checks = true,
656 .disable_48mhz_pwrdwn = false,
657 .usbc_combo_phy_reset_wa = true,
658 .dmub_command_table = true,
660 .optimize_edp_link_rate = true
663 static const struct dc_debug_options debug_defaults_diags = {
664 .disable_dmcu = false,
665 .force_abm_enable = false,
666 .timing_trace = true,
668 .disable_dpp_power_gate = true,
669 .disable_hubp_power_gate = true,
670 .disable_clock_gate = true,
671 .disable_pplib_clock_request = true,
672 .disable_pplib_wm_range = true,
673 .disable_stutter = true,
674 .disable_48mhz_pwrdwn = true,
676 .enable_tri_buf = true,
680 enum dcn20_clk_src_array_id {
686 DCN20_CLK_SRC_TOTAL_DCN21
689 static void dcn21_resource_destruct(struct dcn21_resource_pool *pool)
693 for (i = 0; i < pool->base.stream_enc_count; i++) {
694 if (pool->base.stream_enc[i] != NULL) {
695 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
696 pool->base.stream_enc[i] = NULL;
700 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
701 if (pool->base.dscs[i] != NULL)
702 dcn20_dsc_destroy(&pool->base.dscs[i]);
705 if (pool->base.mpc != NULL) {
706 kfree(TO_DCN20_MPC(pool->base.mpc));
707 pool->base.mpc = NULL;
709 if (pool->base.hubbub != NULL) {
710 kfree(pool->base.hubbub);
711 pool->base.hubbub = NULL;
713 for (i = 0; i < pool->base.pipe_count; i++) {
714 if (pool->base.dpps[i] != NULL)
715 dcn20_dpp_destroy(&pool->base.dpps[i]);
717 if (pool->base.ipps[i] != NULL)
718 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
720 if (pool->base.hubps[i] != NULL) {
721 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
722 pool->base.hubps[i] = NULL;
725 if (pool->base.irqs != NULL) {
726 dal_irq_service_destroy(&pool->base.irqs);
730 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
731 if (pool->base.engines[i] != NULL)
732 dce110_engine_destroy(&pool->base.engines[i]);
733 if (pool->base.hw_i2cs[i] != NULL) {
734 kfree(pool->base.hw_i2cs[i]);
735 pool->base.hw_i2cs[i] = NULL;
737 if (pool->base.sw_i2cs[i] != NULL) {
738 kfree(pool->base.sw_i2cs[i]);
739 pool->base.sw_i2cs[i] = NULL;
743 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
744 if (pool->base.opps[i] != NULL)
745 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
748 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
749 if (pool->base.timing_generators[i] != NULL) {
750 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
751 pool->base.timing_generators[i] = NULL;
755 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
756 if (pool->base.dwbc[i] != NULL) {
757 kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
758 pool->base.dwbc[i] = NULL;
760 if (pool->base.mcif_wb[i] != NULL) {
761 kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));
762 pool->base.mcif_wb[i] = NULL;
766 for (i = 0; i < pool->base.audio_count; i++) {
767 if (pool->base.audios[i])
768 dce_aud_destroy(&pool->base.audios[i]);
771 for (i = 0; i < pool->base.clk_src_count; i++) {
772 if (pool->base.clock_sources[i] != NULL) {
773 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
774 pool->base.clock_sources[i] = NULL;
778 if (pool->base.dp_clock_source != NULL) {
779 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
780 pool->base.dp_clock_source = NULL;
783 if (pool->base.abm != NULL) {
784 if (pool->base.abm->ctx->dc->config.disable_dmcu)
785 dmub_abm_destroy(&pool->base.abm);
787 dce_abm_destroy(&pool->base.abm);
790 if (pool->base.dmcu != NULL)
791 dce_dmcu_destroy(&pool->base.dmcu);
793 if (pool->base.psr != NULL)
794 dmub_psr_destroy(&pool->base.psr);
796 if (pool->base.dccg != NULL)
797 dcn_dccg_destroy(&pool->base.dccg);
799 if (pool->base.pp_smu != NULL)
800 dcn21_pp_smu_destroy(&pool->base.pp_smu);
803 bool dcn21_fast_validate_bw(struct dc *dc,
804 struct dc_state *context,
805 display_e2e_pipe_params_st *pipes,
807 int *pipe_split_from,
812 int split[MAX_PIPES] = { 0 };
813 int pipe_cnt, i, pipe_idx, vlevel;
819 dcn20_merge_pipes_for_validate(dc, context);
822 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
825 *pipe_cnt_out = pipe_cnt;
832 * DML favors voltage over p-state, but we're more interested in
833 * supporting p-state over voltage. We can't support p-state in
834 * prefetch mode > 0 so try capping the prefetch mode to start.
836 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
837 dm_allow_self_refresh_and_mclk_switch;
838 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
840 if (vlevel > context->bw_ctx.dml.soc.num_states) {
842 * If mode is unsupported or there's still no p-state support then
843 * fall back to favoring voltage.
845 * We don't actually support prefetch mode 2, so require that we
846 * at least support prefetch mode 1.
848 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
849 dm_allow_self_refresh;
850 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
851 if (vlevel > context->bw_ctx.dml.soc.num_states)
855 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, NULL);
857 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
858 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
859 struct pipe_ctx *mpo_pipe = pipe->bottom_pipe;
860 struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
865 /* We only support full screen mpo with ODM */
866 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled
867 && pipe->plane_state && mpo_pipe
868 && memcmp(&mpo_pipe->plane_res.scl_data.recout,
869 &pipe->plane_res.scl_data.recout,
870 sizeof(struct rect)) != 0) {
871 ASSERT(mpo_pipe->plane_state != pipe->plane_state);
877 /*initialize pipe_just_split_from to invalid idx*/
878 for (i = 0; i < MAX_PIPES; i++)
879 pipe_split_from[i] = -1;
881 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
882 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
883 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
885 if (!pipe->stream || pipe_split_from[i] >= 0)
890 if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
891 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
893 if (!dcn20_split_stream_for_odm(
894 dc, &context->res_ctx,
897 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
898 dcn20_build_mapped_resource(dc, context, pipe->stream);
901 if (!pipe->plane_state)
903 /* Skip 2nd half of already split pipe */
904 if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state)
908 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) {
909 /* pipe not split previously needs split */
910 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
914 dcn20_fpu_adjust_dppclk(&context->bw_ctx.dml.vba, vlevel, context->bw_ctx.dml.vba.maxMpcComb, pipe_idx, true);
918 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
919 if (!dcn20_split_stream_for_odm(
920 dc, &context->res_ctx,
923 dcn20_build_mapped_resource(dc, context, pipe->stream);
925 dcn20_split_stream_for_mpc(
926 &context->res_ctx, dc->res_pool,
928 resource_build_scaling_params(pipe);
929 resource_build_scaling_params(hsplit_pipe);
931 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
933 } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
934 /* merge should already have been done */
938 /* Actual dsc count per stream dsc validation*/
939 if (!dcn20_validate_dsc(dc, context)) {
940 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] =
941 DML_FAIL_DSC_VALIDATION_FAILURE;
945 *vlevel_out = vlevel;
958 * Some of the functions further below use the FPU, so we need to wrap this
959 * with DC_FP_START()/DC_FP_END(). Use the same approach as for
960 * dcn20_validate_bandwidth in dcn20_resource.c.
962 static bool dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context,
965 bool voltage_supported;
967 voltage_supported = dcn21_validate_bandwidth_fp(dc, context, fast_validate);
969 return voltage_supported;
972 static void dcn21_destroy_resource_pool(struct resource_pool **pool)
974 struct dcn21_resource_pool *dcn21_pool = TO_DCN21_RES_POOL(*pool);
976 dcn21_resource_destruct(dcn21_pool);
981 static struct clock_source *dcn21_clock_source_create(
982 struct dc_context *ctx,
983 struct dc_bios *bios,
984 enum clock_source_id id,
985 const struct dce110_clk_src_regs *regs,
988 struct dce110_clk_src *clk_src =
989 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
994 if (dcn20_clk_src_construct(clk_src, ctx, bios, id,
995 regs, &cs_shift, &cs_mask)) {
996 clk_src->base.dp_clk_src = dp_clk_src;
997 return &clk_src->base;
1000 BREAK_TO_DEBUGGER();
1004 static struct hubp *dcn21_hubp_create(
1005 struct dc_context *ctx,
1008 struct dcn21_hubp *hubp21 =
1009 kzalloc(sizeof(struct dcn21_hubp), GFP_KERNEL);
1014 if (hubp21_construct(hubp21, ctx, inst,
1015 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1016 return &hubp21->base;
1018 BREAK_TO_DEBUGGER();
1023 static struct hubbub *dcn21_hubbub_create(struct dc_context *ctx)
1027 struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub),
1033 hubbub21_construct(hubbub, ctx,
1038 for (i = 0; i < res_cap_rn.num_vmid; i++) {
1039 struct dcn20_vmid *vmid = &hubbub->vmid[i];
1043 vmid->regs = &vmid_regs[i];
1044 vmid->shifts = &vmid_shifts;
1045 vmid->masks = &vmid_masks;
1047 hubbub->num_vmid = res_cap_rn.num_vmid;
1049 return &hubbub->base;
1052 static struct output_pixel_processor *dcn21_opp_create(struct dc_context *ctx,
1055 struct dcn20_opp *opp =
1056 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
1059 BREAK_TO_DEBUGGER();
1063 dcn20_opp_construct(opp, ctx, inst,
1064 &opp_regs[inst], &opp_shift, &opp_mask);
1068 static struct timing_generator *dcn21_timing_generator_create(struct dc_context *ctx,
1071 struct optc *tgn10 =
1072 kzalloc(sizeof(struct optc), GFP_KERNEL);
1077 tgn10->base.inst = instance;
1078 tgn10->base.ctx = ctx;
1080 tgn10->tg_regs = &tg_regs[instance];
1081 tgn10->tg_shift = &tg_shift;
1082 tgn10->tg_mask = &tg_mask;
1084 dcn20_timing_generator_init(tgn10);
1086 return &tgn10->base;
1089 static struct mpc *dcn21_mpc_create(struct dc_context *ctx)
1091 struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc),
1097 dcn20_mpc_construct(mpc20, ctx,
1103 return &mpc20->base;
1106 static void read_dce_straps(
1107 struct dc_context *ctx,
1108 struct resource_straps *straps)
1110 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
1111 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1116 static struct display_stream_compressor *dcn21_dsc_create(struct dc_context *ctx,
1119 struct dcn20_dsc *dsc =
1120 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1123 BREAK_TO_DEBUGGER();
1127 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1131 static struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx)
1133 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
1138 dm_pp_get_funcs(ctx, pp_smu);
1140 if (pp_smu->ctx.ver != PP_SMU_VER_RN)
1141 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs));
1147 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
1149 if (pp_smu && *pp_smu) {
1155 static struct audio *dcn21_create_audio(
1156 struct dc_context *ctx, unsigned int inst)
1158 return dce_audio_create(ctx, inst,
1159 &audio_regs[inst], &audio_shift, &audio_mask);
1162 static struct dc_cap_funcs cap_funcs = {
1163 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1166 static struct stream_encoder *dcn21_stream_encoder_create(enum engine_id eng_id,
1167 struct dc_context *ctx)
1169 struct dcn10_stream_encoder *enc1 =
1170 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1175 dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
1176 &stream_enc_regs[eng_id],
1177 &se_shift, &se_mask);
1182 static const struct dce_hwseq_registers hwseq_reg = {
1183 HWSEQ_DCN21_REG_LIST()
1186 static const struct dce_hwseq_shift hwseq_shift = {
1187 HWSEQ_DCN21_MASK_SH_LIST(__SHIFT)
1190 static const struct dce_hwseq_mask hwseq_mask = {
1191 HWSEQ_DCN21_MASK_SH_LIST(_MASK)
1194 static struct dce_hwseq *dcn21_hwseq_create(
1195 struct dc_context *ctx)
1197 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1201 hws->regs = &hwseq_reg;
1202 hws->shifts = &hwseq_shift;
1203 hws->masks = &hwseq_mask;
1204 hws->wa.DEGVIDCN21 = true;
1205 hws->wa.disallow_self_refresh_during_multi_plane_transition = true;
1210 static const struct resource_create_funcs res_create_funcs = {
1211 .read_dce_straps = read_dce_straps,
1212 .create_audio = dcn21_create_audio,
1213 .create_stream_encoder = dcn21_stream_encoder_create,
1214 .create_hwseq = dcn21_hwseq_create,
1217 static const struct resource_create_funcs res_create_maximus_funcs = {
1218 .read_dce_straps = NULL,
1219 .create_audio = NULL,
1220 .create_stream_encoder = NULL,
1221 .create_hwseq = dcn21_hwseq_create,
1224 static const struct encoder_feature_support link_enc_feature = {
1225 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1226 .max_hdmi_pixel_clock = 600000,
1227 .hdmi_ycbcr420_supported = true,
1228 .dp_ycbcr420_supported = true,
1229 .fec_supported = true,
1230 .flags.bits.IS_HBR2_CAPABLE = true,
1231 .flags.bits.IS_HBR3_CAPABLE = true,
1232 .flags.bits.IS_TPS3_CAPABLE = true,
1233 .flags.bits.IS_TPS4_CAPABLE = true
1237 #define link_regs(id, phyid)\
1239 LE_DCN2_REG_LIST(id), \
1240 UNIPHY_DCN2_REG_LIST(phyid), \
1241 DPCS_DCN21_REG_LIST(id), \
1242 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
1245 static const struct dcn10_link_enc_registers link_enc_regs[] = {
1253 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
1254 { DCN_PANEL_CNTL_REG_LIST() }
1257 static const struct dce_panel_cntl_shift panel_cntl_shift = {
1258 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
1261 static const struct dce_panel_cntl_mask panel_cntl_mask = {
1262 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
1265 #define aux_regs(id)\
1267 DCN2_AUX_REG_LIST(id)\
1270 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
1278 #define hpd_regs(id)\
1283 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
1291 static const struct dcn10_link_enc_shift le_shift = {
1292 LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT),\
1293 DPCS_DCN21_MASK_SH_LIST(__SHIFT)
1296 static const struct dcn10_link_enc_mask le_mask = {
1297 LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\
1298 DPCS_DCN21_MASK_SH_LIST(_MASK)
1301 static int map_transmitter_id_to_phy_instance(
1302 enum transmitter transmitter)
1304 switch (transmitter) {
1305 case TRANSMITTER_UNIPHY_A:
1308 case TRANSMITTER_UNIPHY_B:
1311 case TRANSMITTER_UNIPHY_C:
1314 case TRANSMITTER_UNIPHY_D:
1317 case TRANSMITTER_UNIPHY_E:
1326 static struct link_encoder *dcn21_link_encoder_create(
1327 const struct encoder_init_data *enc_init_data)
1329 struct dcn21_link_encoder *enc21 =
1330 kzalloc(sizeof(struct dcn21_link_encoder), GFP_KERNEL);
1337 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
1339 dcn21_link_encoder_construct(enc21,
1342 &link_enc_regs[link_regs_id],
1343 &link_enc_aux_regs[enc_init_data->channel - 1],
1344 &link_enc_hpd_regs[enc_init_data->hpd_source],
1348 return &enc21->enc10.base;
1351 static struct panel_cntl *dcn21_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1353 struct dce_panel_cntl *panel_cntl =
1354 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
1359 dce_panel_cntl_construct(panel_cntl,
1361 &panel_cntl_regs[init_data->inst],
1365 return &panel_cntl->base;
1370 #define REG(reg_name) \
1371 (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
1373 static uint32_t read_pipe_fuses(struct dc_context *ctx)
1375 uint32_t value = REG_READ(CC_DC_PIPE_DIS);
1376 /* RV1 support max 4 pipes */
1377 value = value & 0xf;
1381 static enum dc_status dcn21_patch_unknown_plane_state(struct dc_plane_state *plane_state)
1383 enum dc_status result = DC_OK;
1385 if (plane_state->ctx->dc->debug.disable_dcc == DCC_ENABLE) {
1386 plane_state->dcc.enable = 1;
1387 /* align to our worst case block width */
1388 plane_state->dcc.meta_pitch = ((plane_state->src_rect.width + 1023) / 1024) * 1024;
1390 result = dcn20_patch_unknown_plane_state(plane_state);
1394 static const struct resource_funcs dcn21_res_pool_funcs = {
1395 .destroy = dcn21_destroy_resource_pool,
1396 .link_enc_create = dcn21_link_encoder_create,
1397 .panel_cntl_create = dcn21_panel_cntl_create,
1398 .validate_bandwidth = dcn21_validate_bandwidth,
1399 .populate_dml_pipes = dcn21_populate_dml_pipes_from_context,
1400 .add_stream_to_ctx = dcn20_add_stream_to_ctx,
1401 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1402 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1403 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
1404 .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context,
1405 .patch_unknown_plane_state = dcn21_patch_unknown_plane_state,
1406 .set_mcif_arb_params = dcn20_set_mcif_arb_params,
1407 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1408 .update_bw_bounding_box = dcn21_update_bw_bounding_box,
1411 static bool dcn21_resource_construct(
1412 uint8_t num_virtual_links,
1414 struct dcn21_resource_pool *pool)
1417 struct dc_context *ctx = dc->ctx;
1418 struct irq_service_init_data init_data;
1419 uint32_t pipe_fuses = read_pipe_fuses(ctx);
1422 ctx->dc_bios->regs = &bios_regs;
1424 pool->base.res_cap = &res_cap_rn;
1426 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
1427 //pool->base.res_cap = &res_cap_nv10_FPGA_2pipe_dsc;
1428 pool->base.res_cap = &res_cap_rn_FPGA_4pipe;
1431 pool->base.funcs = &dcn21_res_pool_funcs;
1433 /*************************************************
1434 * Resource + asic cap harcoding *
1435 *************************************************/
1436 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1438 /* max pipe num for ASIC before check pipe fuses */
1439 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1441 dc->caps.max_downscale_ratio = 200;
1442 dc->caps.i2c_speed_in_khz = 100;
1443 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by default*/
1444 dc->caps.max_cursor_size = 256;
1445 dc->caps.min_horizontal_blanking_period = 80;
1446 dc->caps.dmdata_alloc_size = 2048;
1448 dc->caps.max_slave_planes = 1;
1449 dc->caps.max_slave_yuv_planes = 1;
1450 dc->caps.max_slave_rgb_planes = 1;
1451 dc->caps.post_blend_color_processing = true;
1452 dc->caps.force_dp_tps4_for_cp2520 = true;
1453 dc->caps.extended_aux_timeout_support = true;
1454 dc->caps.dmcub_support = true;
1455 dc->caps.is_apu = true;
1457 /* Color pipeline capabilities */
1458 dc->caps.color.dpp.dcn_arch = 1;
1459 dc->caps.color.dpp.input_lut_shared = 0;
1460 dc->caps.color.dpp.icsc = 1;
1461 dc->caps.color.dpp.dgam_ram = 1;
1462 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1463 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1464 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;
1465 dc->caps.color.dpp.dgam_rom_caps.pq = 0;
1466 dc->caps.color.dpp.dgam_rom_caps.hlg = 0;
1467 dc->caps.color.dpp.post_csc = 0;
1468 dc->caps.color.dpp.gamma_corr = 0;
1469 dc->caps.color.dpp.dgam_rom_for_yuv = 1;
1471 dc->caps.color.dpp.hw_3d_lut = 1;
1472 dc->caps.color.dpp.ogam_ram = 1;
1473 // no OGAM ROM on DCN2
1474 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1475 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1476 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1477 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1478 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1479 dc->caps.color.dpp.ocsc = 0;
1481 dc->caps.color.mpc.gamut_remap = 0;
1482 dc->caps.color.mpc.num_3dluts = 0;
1483 dc->caps.color.mpc.shared_3d_lut = 0;
1484 dc->caps.color.mpc.ogam_ram = 1;
1485 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1486 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1487 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1488 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1489 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1490 dc->caps.color.mpc.ocsc = 1;
1492 dc->caps.hdmi_frl_pcon_support = true;
1494 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1495 dc->debug = debug_defaults_drv;
1496 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
1497 pool->base.pipe_count = 4;
1498 dc->debug = debug_defaults_diags;
1500 dc->debug = debug_defaults_diags;
1502 // Init the vm_helper
1504 vm_helper_init(dc->vm_helper, 16);
1506 /*************************************************
1507 * Create resources *
1508 *************************************************/
1510 pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =
1511 dcn21_clock_source_create(ctx, ctx->dc_bios,
1512 CLOCK_SOURCE_COMBO_PHY_PLL0,
1513 &clk_src_regs[0], false);
1514 pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =
1515 dcn21_clock_source_create(ctx, ctx->dc_bios,
1516 CLOCK_SOURCE_COMBO_PHY_PLL1,
1517 &clk_src_regs[1], false);
1518 pool->base.clock_sources[DCN20_CLK_SRC_PLL2] =
1519 dcn21_clock_source_create(ctx, ctx->dc_bios,
1520 CLOCK_SOURCE_COMBO_PHY_PLL2,
1521 &clk_src_regs[2], false);
1522 pool->base.clock_sources[DCN20_CLK_SRC_PLL3] =
1523 dcn21_clock_source_create(ctx, ctx->dc_bios,
1524 CLOCK_SOURCE_COMBO_PHY_PLL3,
1525 &clk_src_regs[3], false);
1526 pool->base.clock_sources[DCN20_CLK_SRC_PLL4] =
1527 dcn21_clock_source_create(ctx, ctx->dc_bios,
1528 CLOCK_SOURCE_COMBO_PHY_PLL4,
1529 &clk_src_regs[4], false);
1531 pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN21;
1533 /* todo: not reuse phy_pll registers */
1534 pool->base.dp_clock_source =
1535 dcn21_clock_source_create(ctx, ctx->dc_bios,
1536 CLOCK_SOURCE_ID_DP_DTO,
1537 &clk_src_regs[0], true);
1539 for (i = 0; i < pool->base.clk_src_count; i++) {
1540 if (pool->base.clock_sources[i] == NULL) {
1541 dm_error("DC: failed to create clock sources!\n");
1542 BREAK_TO_DEBUGGER();
1547 pool->base.dccg = dccg21_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1548 if (pool->base.dccg == NULL) {
1549 dm_error("DC: failed to create dccg!\n");
1550 BREAK_TO_DEBUGGER();
1554 if (!dc->config.disable_dmcu) {
1555 pool->base.dmcu = dcn21_dmcu_create(ctx,
1559 if (pool->base.dmcu == NULL) {
1560 dm_error("DC: failed to create dmcu!\n");
1561 BREAK_TO_DEBUGGER();
1565 dc->debug.dmub_command_table = false;
1568 if (dc->config.disable_dmcu) {
1569 pool->base.psr = dmub_psr_create(ctx);
1571 if (pool->base.psr == NULL) {
1572 dm_error("DC: failed to create psr obj!\n");
1573 BREAK_TO_DEBUGGER();
1578 if (dc->config.disable_dmcu)
1579 pool->base.abm = dmub_abm_create(ctx,
1584 pool->base.abm = dce_abm_create(ctx,
1589 pool->base.pp_smu = dcn21_pp_smu_create(ctx);
1591 num_pipes = dcn2_1_ip.max_num_dpp;
1593 for (i = 0; i < dcn2_1_ip.max_num_dpp; i++)
1594 if (pipe_fuses & 1 << i)
1596 dcn2_1_ip.max_num_dpp = num_pipes;
1597 dcn2_1_ip.max_num_otg = num_pipes;
1599 dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);
1601 init_data.ctx = dc->ctx;
1602 pool->base.irqs = dal_irq_service_dcn21_create(&init_data);
1603 if (!pool->base.irqs)
1607 /* mem input -> ipp -> dpp -> opp -> TG */
1608 for (i = 0; i < pool->base.pipe_count; i++) {
1609 /* if pipe is disabled, skip instance of HW pipe,
1610 * i.e, skip ASIC register instance
1612 if ((pipe_fuses & (1 << i)) != 0)
1615 pool->base.hubps[j] = dcn21_hubp_create(ctx, i);
1616 if (pool->base.hubps[j] == NULL) {
1617 BREAK_TO_DEBUGGER();
1619 "DC: failed to create memory input!\n");
1623 pool->base.ipps[j] = dcn21_ipp_create(ctx, i);
1624 if (pool->base.ipps[j] == NULL) {
1625 BREAK_TO_DEBUGGER();
1627 "DC: failed to create input pixel processor!\n");
1631 pool->base.dpps[j] = dcn21_dpp_create(ctx, i);
1632 if (pool->base.dpps[j] == NULL) {
1633 BREAK_TO_DEBUGGER();
1635 "DC: failed to create dpps!\n");
1639 pool->base.opps[j] = dcn21_opp_create(ctx, i);
1640 if (pool->base.opps[j] == NULL) {
1641 BREAK_TO_DEBUGGER();
1643 "DC: failed to create output pixel processor!\n");
1647 pool->base.timing_generators[j] = dcn21_timing_generator_create(
1649 if (pool->base.timing_generators[j] == NULL) {
1650 BREAK_TO_DEBUGGER();
1651 dm_error("DC: failed to create tg!\n");
1657 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1658 pool->base.engines[i] = dcn21_aux_engine_create(ctx, i);
1659 if (pool->base.engines[i] == NULL) {
1660 BREAK_TO_DEBUGGER();
1662 "DC:failed to create aux engine!!\n");
1665 pool->base.hw_i2cs[i] = dcn21_i2c_hw_create(ctx, i);
1666 if (pool->base.hw_i2cs[i] == NULL) {
1667 BREAK_TO_DEBUGGER();
1669 "DC:failed to create hw i2c!!\n");
1672 pool->base.sw_i2cs[i] = NULL;
1675 pool->base.timing_generator_count = j;
1676 pool->base.pipe_count = j;
1677 pool->base.mpcc_count = j;
1679 pool->base.mpc = dcn21_mpc_create(ctx);
1680 if (pool->base.mpc == NULL) {
1681 BREAK_TO_DEBUGGER();
1682 dm_error("DC: failed to create mpc!\n");
1686 pool->base.hubbub = dcn21_hubbub_create(ctx);
1687 if (pool->base.hubbub == NULL) {
1688 BREAK_TO_DEBUGGER();
1689 dm_error("DC: failed to create hubbub!\n");
1693 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1694 pool->base.dscs[i] = dcn21_dsc_create(ctx, i);
1695 if (pool->base.dscs[i] == NULL) {
1696 BREAK_TO_DEBUGGER();
1697 dm_error("DC: failed to create display stream compressor %d!\n", i);
1702 if (!dcn20_dwbc_create(ctx, &pool->base)) {
1703 BREAK_TO_DEBUGGER();
1704 dm_error("DC: failed to create dwbc!\n");
1707 if (!dcn20_mmhubbub_create(ctx, &pool->base)) {
1708 BREAK_TO_DEBUGGER();
1709 dm_error("DC: failed to create mcif_wb!\n");
1713 if (!resource_construct(num_virtual_links, dc, &pool->base,
1714 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
1715 &res_create_funcs : &res_create_maximus_funcs)))
1718 dcn21_hw_sequencer_construct(dc);
1720 dc->caps.max_planes = pool->base.pipe_count;
1722 for (i = 0; i < dc->caps.max_planes; ++i)
1723 dc->caps.planes[i] = plane_cap;
1725 dc->cap_funcs = cap_funcs;
1731 dcn21_resource_destruct(pool);
1736 struct resource_pool *dcn21_create_resource_pool(
1737 const struct dc_init_data *init_data,
1740 struct dcn21_resource_pool *pool =
1741 kzalloc(sizeof(struct dcn21_resource_pool), GFP_KERNEL);
1746 if (dcn21_resource_construct(init_data->num_virtual_links, dc, pool))
1749 BREAK_TO_DEBUGGER();