2 * Copyright 2018 Advanced Micro Devices, Inc.
3 * Copyright 2019 Raptor Engineering, LLC
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
27 #include <linux/slab.h>
29 #include "dm_services.h"
32 #include "dcn21_init.h"
35 #include "include/irq_service_interface.h"
36 #include "dcn20/dcn20_resource.h"
39 #include "dcn10/dcn10_hubp.h"
40 #include "dcn10/dcn10_ipp.h"
41 #include "dcn20/dcn20_hubbub.h"
42 #include "dcn20/dcn20_mpc.h"
43 #include "dcn20/dcn20_hubp.h"
44 #include "dcn21_hubp.h"
45 #include "irq/dcn21/irq_service_dcn21.h"
46 #include "dcn20/dcn20_dpp.h"
47 #include "dcn20/dcn20_optc.h"
48 #include "dcn21/dcn21_hwseq.h"
49 #include "dce110/dce110_hw_sequencer.h"
50 #include "dcn20/dcn20_opp.h"
51 #include "dcn20/dcn20_dsc.h"
52 #include "dcn21/dcn21_link_encoder.h"
53 #include "dcn20/dcn20_stream_encoder.h"
54 #include "dce/dce_clock_source.h"
55 #include "dce/dce_audio.h"
56 #include "dce/dce_hwseq.h"
57 #include "virtual/virtual_stream_encoder.h"
58 #include "dce110/dce110_resource.h"
59 #include "dml/display_mode_vba.h"
60 #include "dcn20/dcn20_dccg.h"
61 #include "dcn21_hubbub.h"
62 #include "dcn10/dcn10_resource.h"
64 #include "dcn20/dcn20_dwb.h"
65 #include "dcn20/dcn20_mmhubbub.h"
66 #include "dpcs/dpcs_2_1_0_offset.h"
67 #include "dpcs/dpcs_2_1_0_sh_mask.h"
69 #include "renoir_ip_offset.h"
70 #include "dcn/dcn_2_1_0_offset.h"
71 #include "dcn/dcn_2_1_0_sh_mask.h"
73 #include "nbio/nbio_7_0_offset.h"
75 #include "mmhub/mmhub_2_0_0_offset.h"
76 #include "mmhub/mmhub_2_0_0_sh_mask.h"
78 #include "reg_helper.h"
79 #include "dce/dce_abm.h"
80 #include "dce/dce_dmcu.h"
81 #include "dce/dce_aux.h"
82 #include "dce/dce_i2c.h"
83 #include "dcn21_resource.h"
84 #include "vm_helper.h"
85 #include "dcn20/dcn20_vmid.h"
86 #include "../dce/dmub_psr.h"
88 #define SOC_BOUNDING_BOX_VALID false
89 #define DC_LOGGER_INIT(logger)
92 struct _vcs_dpi_ip_params_st dcn2_1_ip = {
96 .gpuvm_max_page_table_levels = 1,
97 .hostvm_max_page_table_levels = 4,
98 .hostvm_cached_page_table_levels = 2,
100 .rob_buffer_size_kbytes = 168,
101 .det_buffer_size_kbytes = 164,
102 .dpte_buffer_size_in_pte_reqs_luma = 44,
103 .dpte_buffer_size_in_pte_reqs_chroma = 42,//todo
104 .dpp_output_buffer_pixels = 2560,
105 .opp_output_buffer_lines = 1,
106 .pixel_chunk_size_kbytes = 8,
108 .max_page_table_levels = 4,
109 .pte_chunk_size_kbytes = 2,
110 .meta_chunk_size_kbytes = 2,
111 .writeback_chunk_size_kbytes = 2,
112 .line_buffer_size_bits = 789504,
113 .is_line_buffer_bpp_fixed = 0,
114 .line_buffer_fixed_bpp = 0,
115 .dcc_supported = true,
116 .max_line_buffer_lines = 12,
117 .writeback_luma_buffer_size_kbytes = 12,
118 .writeback_chroma_buffer_size_kbytes = 8,
119 .writeback_chroma_line_buffer_width_pixels = 4,
120 .writeback_max_hscl_ratio = 1,
121 .writeback_max_vscl_ratio = 1,
122 .writeback_min_hscl_ratio = 1,
123 .writeback_min_vscl_ratio = 1,
124 .writeback_max_hscl_taps = 12,
125 .writeback_max_vscl_taps = 12,
126 .writeback_line_buffer_luma_buffer_size = 0,
127 .writeback_line_buffer_chroma_buffer_size = 14643,
128 .cursor_buffer_size = 8,
129 .cursor_chunk_size = 2,
133 .max_dchub_pscl_bw_pix_per_clk = 4,
134 .max_pscl_lb_bw_pix_per_clk = 2,
135 .max_lb_vscl_bw_pix_per_clk = 4,
136 .max_vscl_hscl_bw_pix_per_clk = 4,
143 .dispclk_ramp_margin_percent = 1,
144 .underscan_factor = 1.10,
145 .min_vblank_lines = 32, //
146 .dppclk_delay_subtotal = 77, //
147 .dppclk_delay_scl_lb_only = 16,
148 .dppclk_delay_scl = 50,
149 .dppclk_delay_cnvc_formatter = 8,
150 .dppclk_delay_cnvc_cursor = 6,
151 .dispclk_delay_subtotal = 87, //
152 .dcfclk_cstate_latency = 10, // SRExitTime
153 .max_inter_dcn_tile_repeaters = 8,
155 .xfc_supported = false,
156 .xfc_fill_bw_overhead_percent = 10.0,
157 .xfc_fill_constant_bytes = 0,
161 struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = {
166 .fabricclk_mhz = 600.0,
167 .dispclk_mhz = 618.0,
171 .dscclk_mhz = 205.67,
172 .dram_speed_mts = 1600.0,
177 .fabricclk_mhz = 600.0,
178 .dispclk_mhz = 618.0,
182 .dscclk_mhz = 205.67,
183 .dram_speed_mts = 1600.0,
188 .fabricclk_mhz = 1066.0,
189 .dispclk_mhz = 888.0,
193 .dscclk_mhz = 287.67,
194 .dram_speed_mts = 2133.0,
199 .fabricclk_mhz = 1600.0,
200 .dispclk_mhz = 1015.0,
201 .dppclk_mhz = 1015.0,
204 .dscclk_mhz = 318.334,
205 .dram_speed_mts = 4266.0,
210 .fabricclk_mhz = 1600.0,
211 .dispclk_mhz = 1395.0,
212 .dppclk_mhz = 1285.0,
213 .phyclk_mhz = 1325.0,
216 .dram_speed_mts = 4266.0,
218 /*Extra state, no dispclk ramping*/
222 .fabricclk_mhz = 1600.0,
223 .dispclk_mhz = 1395.0,
224 .dppclk_mhz = 1285.0,
225 .phyclk_mhz = 1325.0,
228 .dram_speed_mts = 4266.0,
233 .sr_exit_time_us = 12.5,
234 .sr_enter_plus_exit_time_us = 17.0,
235 .urgent_latency_us = 4.0,
236 .urgent_latency_pixel_data_only_us = 4.0,
237 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
238 .urgent_latency_vm_data_only_us = 4.0,
239 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
240 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
241 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
242 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0,
243 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 75.0,
244 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
245 .max_avg_sdp_bw_use_normal_percent = 60.0,
246 .max_avg_dram_bw_use_normal_percent = 100.0,
247 .writeback_latency_us = 12.0,
248 .max_request_size_bytes = 256,
249 .dram_channel_width_bytes = 4,
250 .fabric_datapath_to_dcn_data_return_bytes = 32,
251 .dcn_downspread_percent = 0.5,
252 .downspread_percent = 0.5,
253 .dram_page_open_time_ns = 50.0,
254 .dram_rw_turnaround_time_ns = 17.5,
255 .dram_return_buffer_per_channel_bytes = 8192,
256 .round_trip_ping_latency_dcfclk_cycles = 128,
257 .urgent_out_of_order_return_per_channel_bytes = 4096,
258 .channel_interleave_bytes = 256,
261 .vmm_page_size_bytes = 4096,
262 .dram_clock_change_latency_us = 23.84,
263 .return_bus_width_bytes = 64,
264 .dispclk_dppclk_vco_speed_mhz = 3600,
265 .xfc_bus_transport_time_us = 4,
266 .xfc_xbuf_latency_tolerance_us = 4,
267 .use_urgent_burst_bw = 1,
272 #define MAX(X, Y) ((X) > (Y) ? (X) : (Y))
275 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
278 /* begin *********************
279 * macros to expend register list macro defined in HW object header file */
282 /* TODO awful hack. fixup dcn20_dwb.h */
284 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
286 #define BASE(seg) BASE_INNER(seg)
288 #define SR(reg_name)\
289 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
292 #define SRI(reg_name, block, id)\
293 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
294 mm ## block ## id ## _ ## reg_name
296 #define SRIR(var_name, reg_name, block, id)\
297 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
298 mm ## block ## id ## _ ## reg_name
300 #define SRII(reg_name, block, id)\
301 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
302 mm ## block ## id ## _ ## reg_name
304 #define DCCG_SRII(reg_name, block, id)\
305 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
306 mm ## block ## id ## _ ## reg_name
309 #define NBIO_BASE_INNER(seg) \
310 NBIF0_BASE__INST0_SEG ## seg
312 #define NBIO_BASE(seg) \
315 #define NBIO_SR(reg_name)\
316 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
320 #define MMHUB_BASE_INNER(seg) \
321 MMHUB_BASE__INST0_SEG ## seg
323 #define MMHUB_BASE(seg) \
324 MMHUB_BASE_INNER(seg)
326 #define MMHUB_SR(reg_name)\
327 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
330 #define clk_src_regs(index, pllid)\
332 CS_COMMON_REG_LIST_DCN2_1(index, pllid),\
335 static const struct dce110_clk_src_regs clk_src_regs[] = {
343 static const struct dce110_clk_src_shift cs_shift = {
344 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
347 static const struct dce110_clk_src_mask cs_mask = {
348 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
351 static const struct bios_registers bios_regs = {
352 NBIO_SR(BIOS_SCRATCH_3),
353 NBIO_SR(BIOS_SCRATCH_6)
356 static const struct dce_dmcu_registers dmcu_regs = {
357 DMCU_DCN20_REG_LIST()
360 static const struct dce_dmcu_shift dmcu_shift = {
361 DMCU_MASK_SH_LIST_DCN10(__SHIFT)
364 static const struct dce_dmcu_mask dmcu_mask = {
365 DMCU_MASK_SH_LIST_DCN10(_MASK)
368 static const struct dce_abm_registers abm_regs = {
372 static const struct dce_abm_shift abm_shift = {
373 ABM_MASK_SH_LIST_DCN20(__SHIFT)
376 static const struct dce_abm_mask abm_mask = {
377 ABM_MASK_SH_LIST_DCN20(_MASK)
380 #define audio_regs(id)\
382 AUD_COMMON_REG_LIST(id)\
385 static const struct dce_audio_registers audio_regs[] = {
394 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
395 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
396 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
397 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
399 static const struct dce_audio_shift audio_shift = {
400 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
403 static const struct dce_audio_mask audio_mask = {
404 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
407 static const struct dccg_registers dccg_regs = {
408 DCCG_COMMON_REG_LIST_DCN_BASE()
411 static const struct dccg_shift dccg_shift = {
412 DCCG_MASK_SH_LIST_DCN2(__SHIFT)
415 static const struct dccg_mask dccg_mask = {
416 DCCG_MASK_SH_LIST_DCN2(_MASK)
419 #define opp_regs(id)\
421 OPP_REG_LIST_DCN20(id),\
424 static const struct dcn20_opp_registers opp_regs[] = {
433 static const struct dcn20_opp_shift opp_shift = {
434 OPP_MASK_SH_LIST_DCN20(__SHIFT)
437 static const struct dcn20_opp_mask opp_mask = {
438 OPP_MASK_SH_LIST_DCN20(_MASK)
442 [id] = {TG_COMMON_REG_LIST_DCN2_0(id)}
444 static const struct dcn_optc_registers tg_regs[] = {
451 static const struct dcn_optc_shift tg_shift = {
452 TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
455 static const struct dcn_optc_mask tg_mask = {
456 TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
459 static const struct dcn20_mpc_registers mpc_regs = {
460 MPC_REG_LIST_DCN2_0(0),
461 MPC_REG_LIST_DCN2_0(1),
462 MPC_REG_LIST_DCN2_0(2),
463 MPC_REG_LIST_DCN2_0(3),
464 MPC_REG_LIST_DCN2_0(4),
465 MPC_REG_LIST_DCN2_0(5),
466 MPC_OUT_MUX_REG_LIST_DCN2_0(0),
467 MPC_OUT_MUX_REG_LIST_DCN2_0(1),
468 MPC_OUT_MUX_REG_LIST_DCN2_0(2),
469 MPC_OUT_MUX_REG_LIST_DCN2_0(3),
470 MPC_DBG_REG_LIST_DCN2_0()
473 static const struct dcn20_mpc_shift mpc_shift = {
474 MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT),
475 MPC_DEBUG_REG_LIST_SH_DCN20
478 static const struct dcn20_mpc_mask mpc_mask = {
479 MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK),
480 MPC_DEBUG_REG_LIST_MASK_DCN20
483 #define hubp_regs(id)\
485 HUBP_REG_LIST_DCN21(id)\
488 static const struct dcn_hubp2_registers hubp_regs[] = {
495 static const struct dcn_hubp2_shift hubp_shift = {
496 HUBP_MASK_SH_LIST_DCN21(__SHIFT)
499 static const struct dcn_hubp2_mask hubp_mask = {
500 HUBP_MASK_SH_LIST_DCN21(_MASK)
503 static const struct dcn_hubbub_registers hubbub_reg = {
504 HUBBUB_REG_LIST_DCN21()
507 static const struct dcn_hubbub_shift hubbub_shift = {
508 HUBBUB_MASK_SH_LIST_DCN21(__SHIFT)
511 static const struct dcn_hubbub_mask hubbub_mask = {
512 HUBBUB_MASK_SH_LIST_DCN21(_MASK)
516 #define vmid_regs(id)\
518 DCN20_VMID_REG_LIST(id)\
521 static const struct dcn_vmid_registers vmid_regs[] = {
540 static const struct dcn20_vmid_shift vmid_shifts = {
541 DCN20_VMID_MASK_SH_LIST(__SHIFT)
544 static const struct dcn20_vmid_mask vmid_masks = {
545 DCN20_VMID_MASK_SH_LIST(_MASK)
548 #define dsc_regsDCN20(id)\
550 DSC_REG_LIST_DCN20(id)\
553 static const struct dcn20_dsc_registers dsc_regs[] = {
562 static const struct dcn20_dsc_shift dsc_shift = {
563 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
566 static const struct dcn20_dsc_mask dsc_mask = {
567 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
570 #define ipp_regs(id)\
572 IPP_REG_LIST_DCN20(id),\
575 static const struct dcn10_ipp_registers ipp_regs[] = {
582 static const struct dcn10_ipp_shift ipp_shift = {
583 IPP_MASK_SH_LIST_DCN20(__SHIFT)
586 static const struct dcn10_ipp_mask ipp_mask = {
587 IPP_MASK_SH_LIST_DCN20(_MASK),
590 #define opp_regs(id)\
592 OPP_REG_LIST_DCN20(id),\
596 #define aux_engine_regs(id)\
598 AUX_COMMON_REG_LIST0(id), \
601 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
604 static const struct dce110_aux_registers aux_engine_regs[] = {
614 TF_REG_LIST_DCN20(id),\
615 TF_REG_LIST_DCN20_COMMON_APPEND(id),\
618 static const struct dcn2_dpp_registers tf_regs[] = {
625 static const struct dcn2_dpp_shift tf_shift = {
626 TF_REG_LIST_SH_MASK_DCN20(__SHIFT),
627 TF_DEBUG_REG_LIST_SH_DCN20
630 static const struct dcn2_dpp_mask tf_mask = {
631 TF_REG_LIST_SH_MASK_DCN20(_MASK),
632 TF_DEBUG_REG_LIST_MASK_DCN20
635 #define stream_enc_regs(id)\
637 SE_DCN2_REG_LIST(id)\
640 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
648 static const struct dce110_aux_registers_shift aux_shift = {
649 DCN_AUX_MASK_SH_LIST(__SHIFT)
652 static const struct dce110_aux_registers_mask aux_mask = {
653 DCN_AUX_MASK_SH_LIST(_MASK)
656 static const struct dcn10_stream_encoder_shift se_shift = {
657 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)
660 static const struct dcn10_stream_encoder_mask se_mask = {
661 SE_COMMON_MASK_SH_LIST_DCN20(_MASK)
664 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
666 static int dcn21_populate_dml_pipes_from_context(
667 struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes);
669 static struct input_pixel_processor *dcn21_ipp_create(
670 struct dc_context *ctx, uint32_t inst)
672 struct dcn10_ipp *ipp =
673 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);
680 dcn20_ipp_construct(ipp, ctx, inst,
681 &ipp_regs[inst], &ipp_shift, &ipp_mask);
685 static struct dpp *dcn21_dpp_create(
686 struct dc_context *ctx,
689 struct dcn20_dpp *dpp =
690 kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL);
695 if (dpp2_construct(dpp, ctx, inst,
696 &tf_regs[inst], &tf_shift, &tf_mask))
704 static struct dce_aux *dcn21_aux_engine_create(
705 struct dc_context *ctx,
708 struct aux_engine_dce110 *aux_engine =
709 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
714 dce110_aux_engine_construct(aux_engine, ctx, inst,
715 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
716 &aux_engine_regs[inst],
719 ctx->dc->caps.extended_aux_timeout_support);
721 return &aux_engine->base;
724 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
726 static const struct dce_i2c_registers i2c_hw_regs[] = {
734 static const struct dce_i2c_shift i2c_shifts = {
735 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
738 static const struct dce_i2c_mask i2c_masks = {
739 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
742 struct dce_i2c_hw *dcn21_i2c_hw_create(
743 struct dc_context *ctx,
746 struct dce_i2c_hw *dce_i2c_hw =
747 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
752 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
753 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
758 static const struct resource_caps res_cap_rn = {
759 .num_timing_generator = 4,
761 .num_video_plane = 4,
762 .num_audio = 4, // 4 audio endpoints. 4 audio streams
763 .num_stream_encoder = 5,
764 .num_pll = 5, // maybe 3 because the last two used for USB-c
772 static const struct resource_caps res_cap_rn_FPGA_4pipe = {
773 .num_timing_generator = 4,
775 .num_video_plane = 4,
777 .num_stream_encoder = 4,
784 static const struct resource_caps res_cap_rn_FPGA_2pipe_dsc = {
785 .num_timing_generator = 2,
787 .num_video_plane = 2,
789 .num_stream_encoder = 2,
797 static const struct dc_plane_cap plane_cap = {
798 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
799 .blends_with_above = true,
800 .blends_with_below = true,
801 .per_pixel_alpha = true,
803 .pixel_format_support = {
809 .max_upscale_factor = {
815 .max_downscale_factor = {
822 static const struct dc_debug_options debug_defaults_drv = {
823 .disable_dmcu = true,
824 .force_abm_enable = false,
825 .timing_trace = false,
827 .disable_pplib_clock_request = true,
828 .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
829 .force_single_disp_pipe_split = false,
830 .disable_dcc = DCC_ENABLE,
832 .performance_trace = false,
833 .max_downscale_src_width = 4096,
834 .disable_pplib_wm_range = false,
835 .scl_reset_length10 = true,
836 .sanity_checks = true,
837 .disable_48mhz_pwrdwn = false,
838 .nv12_iflip_vm_wa = true,
839 .usbc_combo_phy_reset_wa = true
842 static const struct dc_debug_options debug_defaults_diags = {
843 .disable_dmcu = true,
844 .force_abm_enable = false,
845 .timing_trace = true,
847 .disable_dpp_power_gate = true,
848 .disable_hubp_power_gate = true,
849 .disable_clock_gate = true,
850 .disable_pplib_clock_request = true,
851 .disable_pplib_wm_range = true,
852 .disable_stutter = true,
853 .disable_48mhz_pwrdwn = true,
856 enum dcn20_clk_src_array_id {
859 DCN20_CLK_SRC_TOTAL_DCN21
862 static void dcn21_resource_destruct(struct dcn21_resource_pool *pool)
866 for (i = 0; i < pool->base.stream_enc_count; i++) {
867 if (pool->base.stream_enc[i] != NULL) {
868 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
869 pool->base.stream_enc[i] = NULL;
873 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
874 if (pool->base.dscs[i] != NULL)
875 dcn20_dsc_destroy(&pool->base.dscs[i]);
878 if (pool->base.mpc != NULL) {
879 kfree(TO_DCN20_MPC(pool->base.mpc));
880 pool->base.mpc = NULL;
882 if (pool->base.hubbub != NULL) {
883 kfree(pool->base.hubbub);
884 pool->base.hubbub = NULL;
886 for (i = 0; i < pool->base.pipe_count; i++) {
887 if (pool->base.dpps[i] != NULL)
888 dcn20_dpp_destroy(&pool->base.dpps[i]);
890 if (pool->base.ipps[i] != NULL)
891 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
893 if (pool->base.hubps[i] != NULL) {
894 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
895 pool->base.hubps[i] = NULL;
898 if (pool->base.irqs != NULL) {
899 dal_irq_service_destroy(&pool->base.irqs);
903 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
904 if (pool->base.engines[i] != NULL)
905 dce110_engine_destroy(&pool->base.engines[i]);
906 if (pool->base.hw_i2cs[i] != NULL) {
907 kfree(pool->base.hw_i2cs[i]);
908 pool->base.hw_i2cs[i] = NULL;
910 if (pool->base.sw_i2cs[i] != NULL) {
911 kfree(pool->base.sw_i2cs[i]);
912 pool->base.sw_i2cs[i] = NULL;
916 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
917 if (pool->base.opps[i] != NULL)
918 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
921 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
922 if (pool->base.timing_generators[i] != NULL) {
923 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
924 pool->base.timing_generators[i] = NULL;
928 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
929 if (pool->base.dwbc[i] != NULL) {
930 kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
931 pool->base.dwbc[i] = NULL;
933 if (pool->base.mcif_wb[i] != NULL) {
934 kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));
935 pool->base.mcif_wb[i] = NULL;
939 for (i = 0; i < pool->base.audio_count; i++) {
940 if (pool->base.audios[i])
941 dce_aud_destroy(&pool->base.audios[i]);
944 for (i = 0; i < pool->base.clk_src_count; i++) {
945 if (pool->base.clock_sources[i] != NULL) {
946 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
947 pool->base.clock_sources[i] = NULL;
951 if (pool->base.dp_clock_source != NULL) {
952 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
953 pool->base.dp_clock_source = NULL;
957 if (pool->base.abm != NULL)
958 dce_abm_destroy(&pool->base.abm);
960 if (pool->base.dmcu != NULL)
961 dce_dmcu_destroy(&pool->base.dmcu);
963 if (pool->base.dccg != NULL)
964 dcn_dccg_destroy(&pool->base.dccg);
966 if (pool->base.pp_smu != NULL)
967 dcn21_pp_smu_destroy(&pool->base.pp_smu);
971 static void calculate_wm_set_for_vlevel(
973 struct wm_range_table_entry *table_entry,
974 struct dcn_watermarks *wm_set,
975 struct display_mode_lib *dml,
976 display_e2e_pipe_params_st *pipes,
979 double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us;
981 ASSERT(vlevel < dml->soc.num_states);
982 /* only pipe 0 is read for voltage and dcf/soc clocks */
983 pipes[0].clks_cfg.voltage = vlevel;
984 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz;
985 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz;
987 dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us;
988 dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us;
989 dml->soc.sr_enter_plus_exit_time_us = table_entry->sr_enter_plus_exit_time_us;
991 wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000;
992 wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000;
993 wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000;
994 wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000;
995 wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000;
996 wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000;
997 wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000;
998 wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) * 1000;
999 dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached;
1003 static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
1009 if (dc->bb_overrides.sr_exit_time_ns) {
1010 for (i = 0; i < WM_SET_COUNT; i++) {
1011 dc->clk_mgr->bw_params->wm_table.entries[i].sr_exit_time_us =
1012 dc->bb_overrides.sr_exit_time_ns / 1000.0;
1016 if (dc->bb_overrides.sr_enter_plus_exit_time_ns) {
1017 for (i = 0; i < WM_SET_COUNT; i++) {
1018 dc->clk_mgr->bw_params->wm_table.entries[i].sr_enter_plus_exit_time_us =
1019 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
1023 if (dc->bb_overrides.urgent_latency_ns) {
1024 bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
1027 if (dc->bb_overrides.dram_clock_change_latency_ns) {
1028 for (i = 0; i < WM_SET_COUNT; i++) {
1029 dc->clk_mgr->bw_params->wm_table.entries[i].pstate_latency_us =
1030 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
1037 void dcn21_calculate_wm(
1038 struct dc *dc, struct dc_state *context,
1039 display_e2e_pipe_params_st *pipes,
1041 int *pipe_split_from,
1044 int pipe_cnt, i, pipe_idx;
1045 int vlevel, vlevel_max;
1046 struct wm_range_table_entry *table_entry;
1047 struct clk_bw_params *bw_params = dc->clk_mgr->bw_params;
1051 patch_bounding_box(dc, &context->bw_ctx.dml.soc);
1053 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1054 if (!context->res_ctx.pipe_ctx[i].stream)
1057 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
1058 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb];
1060 if (pipe_split_from[i] < 0) {
1061 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
1062 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
1063 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
1064 pipes[pipe_cnt].pipe.dest.odm_combine =
1065 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_idx];
1067 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
1070 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
1071 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
1072 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])
1073 pipes[pipe_cnt].pipe.dest.odm_combine =
1074 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_split_from[i]];
1076 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
1081 if (pipe_cnt != pipe_idx) {
1082 if (dc->res_pool->funcs->populate_dml_pipes)
1083 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
1086 pipe_cnt = dcn21_populate_dml_pipes_from_context(dc,
1090 *out_pipe_cnt = pipe_cnt;
1092 vlevel_max = bw_params->clk_table.num_entries - 1;
1096 table_entry = &bw_params->wm_table.entries[WM_D];
1097 if (table_entry->wm_type == WM_TYPE_RETRAINING)
1100 vlevel = vlevel_max;
1101 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d,
1102 &context->bw_ctx.dml, pipes, pipe_cnt);
1104 table_entry = &bw_params->wm_table.entries[WM_C];
1105 vlevel = MIN(MAX(vlevel_req, 2), vlevel_max);
1106 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c,
1107 &context->bw_ctx.dml, pipes, pipe_cnt);
1109 table_entry = &bw_params->wm_table.entries[WM_B];
1110 vlevel = MIN(MAX(vlevel_req, 1), vlevel_max);
1111 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b,
1112 &context->bw_ctx.dml, pipes, pipe_cnt);
1115 table_entry = &bw_params->wm_table.entries[WM_A];
1116 vlevel = MIN(vlevel_req, vlevel_max);
1117 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a,
1118 &context->bw_ctx.dml, pipes, pipe_cnt);
1122 bool dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context,
1127 BW_VAL_TRACE_SETUP();
1130 int pipe_split_from[MAX_PIPES];
1132 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
1133 DC_LOGGER_INIT(dc->ctx->logger);
1135 BW_VAL_TRACE_COUNT();
1137 out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel);
1145 BW_VAL_TRACE_END_VOLTAGE_LEVEL();
1147 if (fast_validate) {
1148 BW_VAL_TRACE_SKIP(fast);
1152 dcn21_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel);
1153 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
1155 BW_VAL_TRACE_END_WATERMARKS();
1160 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
1161 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
1163 BW_VAL_TRACE_SKIP(fail);
1169 BW_VAL_TRACE_FINISH();
1173 static void dcn21_destroy_resource_pool(struct resource_pool **pool)
1175 struct dcn21_resource_pool *dcn21_pool = TO_DCN21_RES_POOL(*pool);
1177 dcn21_resource_destruct(dcn21_pool);
1182 static struct clock_source *dcn21_clock_source_create(
1183 struct dc_context *ctx,
1184 struct dc_bios *bios,
1185 enum clock_source_id id,
1186 const struct dce110_clk_src_regs *regs,
1189 struct dce110_clk_src *clk_src =
1190 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1195 if (dcn20_clk_src_construct(clk_src, ctx, bios, id,
1196 regs, &cs_shift, &cs_mask)) {
1197 clk_src->base.dp_clk_src = dp_clk_src;
1198 return &clk_src->base;
1201 BREAK_TO_DEBUGGER();
1205 static struct hubp *dcn21_hubp_create(
1206 struct dc_context *ctx,
1209 struct dcn21_hubp *hubp21 =
1210 kzalloc(sizeof(struct dcn21_hubp), GFP_KERNEL);
1215 if (hubp21_construct(hubp21, ctx, inst,
1216 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1217 return &hubp21->base;
1219 BREAK_TO_DEBUGGER();
1224 static struct hubbub *dcn21_hubbub_create(struct dc_context *ctx)
1228 struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub),
1234 hubbub21_construct(hubbub, ctx,
1239 for (i = 0; i < res_cap_rn.num_vmid; i++) {
1240 struct dcn20_vmid *vmid = &hubbub->vmid[i];
1244 vmid->regs = &vmid_regs[i];
1245 vmid->shifts = &vmid_shifts;
1246 vmid->masks = &vmid_masks;
1249 return &hubbub->base;
1252 struct output_pixel_processor *dcn21_opp_create(
1253 struct dc_context *ctx, uint32_t inst)
1255 struct dcn20_opp *opp =
1256 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
1259 BREAK_TO_DEBUGGER();
1263 dcn20_opp_construct(opp, ctx, inst,
1264 &opp_regs[inst], &opp_shift, &opp_mask);
1268 struct timing_generator *dcn21_timing_generator_create(
1269 struct dc_context *ctx,
1272 struct optc *tgn10 =
1273 kzalloc(sizeof(struct optc), GFP_KERNEL);
1278 tgn10->base.inst = instance;
1279 tgn10->base.ctx = ctx;
1281 tgn10->tg_regs = &tg_regs[instance];
1282 tgn10->tg_shift = &tg_shift;
1283 tgn10->tg_mask = &tg_mask;
1285 dcn20_timing_generator_init(tgn10);
1287 return &tgn10->base;
1290 struct mpc *dcn21_mpc_create(struct dc_context *ctx)
1292 struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc),
1298 dcn20_mpc_construct(mpc20, ctx,
1304 return &mpc20->base;
1307 static void read_dce_straps(
1308 struct dc_context *ctx,
1309 struct resource_straps *straps)
1311 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
1312 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1317 struct display_stream_compressor *dcn21_dsc_create(
1318 struct dc_context *ctx, uint32_t inst)
1320 struct dcn20_dsc *dsc =
1321 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1324 BREAK_TO_DEBUGGER();
1328 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1332 static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1334 struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool);
1335 struct clk_limit_table *clk_table = &bw_params->clk_table;
1338 dcn2_1_ip.max_num_otg = pool->base.res_cap->num_timing_generator;
1339 dcn2_1_ip.max_num_dpp = pool->base.pipe_count;
1340 dcn2_1_soc.num_chans = bw_params->num_channels;
1342 for (i = 0; i < clk_table->num_entries; i++) {
1344 dcn2_1_soc.clock_limits[i].state = i;
1345 dcn2_1_soc.clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
1346 dcn2_1_soc.clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
1347 dcn2_1_soc.clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
1348 dcn2_1_soc.clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;
1350 dcn2_1_soc.clock_limits[i] = dcn2_1_soc.clock_limits[i - 1];
1351 dcn2_1_soc.num_states = i;
1353 // diags does not retrieve proper values from SMU, do not update DML instance for diags
1354 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) && !IS_DIAG_DC(dc->ctx->dce_environment))
1355 dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);
1358 /* Temporary Place holder until we can get them from fuse */
1359 static struct dpm_clocks dummy_clocks = {
1361 {.Freq = 400, .Vol = 1},
1362 {.Freq = 483, .Vol = 1},
1363 {.Freq = 602, .Vol = 1},
1364 {.Freq = 738, .Vol = 1} },
1366 {.Freq = 300, .Vol = 1},
1367 {.Freq = 400, .Vol = 1},
1368 {.Freq = 400, .Vol = 1},
1369 {.Freq = 400, .Vol = 1} },
1371 {.Freq = 400, .Vol = 1},
1372 {.Freq = 800, .Vol = 1},
1373 {.Freq = 1067, .Vol = 1},
1374 {.Freq = 1600, .Vol = 1} },
1376 {.Freq = 800, .Vol = 1},
1377 {.Freq = 1600, .Vol = 1},
1378 {.Freq = 1067, .Vol = 1},
1379 {.Freq = 1600, .Vol = 1} },
1383 static enum pp_smu_status dummy_set_wm_ranges(struct pp_smu *pp,
1384 struct pp_smu_wm_range_sets *ranges)
1386 return PP_SMU_RESULT_OK;
1389 static enum pp_smu_status dummy_get_dpm_clock_table(struct pp_smu *pp,
1390 struct dpm_clocks *clock_table)
1392 *clock_table = dummy_clocks;
1393 return PP_SMU_RESULT_OK;
1396 static struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx)
1398 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
1403 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment) || IS_DIAG_DC(ctx->dce_environment)) {
1404 pp_smu->ctx.ver = PP_SMU_VER_RN;
1405 pp_smu->rn_funcs.get_dpm_clock_table = dummy_get_dpm_clock_table;
1406 pp_smu->rn_funcs.set_wm_ranges = dummy_set_wm_ranges;
1409 dm_pp_get_funcs(ctx, pp_smu);
1411 if (pp_smu->ctx.ver != PP_SMU_VER_RN)
1412 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs));
1418 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
1420 if (pp_smu && *pp_smu) {
1426 static struct audio *dcn21_create_audio(
1427 struct dc_context *ctx, unsigned int inst)
1429 return dce_audio_create(ctx, inst,
1430 &audio_regs[inst], &audio_shift, &audio_mask);
1433 static struct dc_cap_funcs cap_funcs = {
1434 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1437 struct stream_encoder *dcn21_stream_encoder_create(
1438 enum engine_id eng_id,
1439 struct dc_context *ctx)
1441 struct dcn10_stream_encoder *enc1 =
1442 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1447 dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
1448 &stream_enc_regs[eng_id],
1449 &se_shift, &se_mask);
1454 static const struct dce_hwseq_registers hwseq_reg = {
1455 HWSEQ_DCN21_REG_LIST()
1458 static const struct dce_hwseq_shift hwseq_shift = {
1459 HWSEQ_DCN21_MASK_SH_LIST(__SHIFT)
1462 static const struct dce_hwseq_mask hwseq_mask = {
1463 HWSEQ_DCN21_MASK_SH_LIST(_MASK)
1466 static struct dce_hwseq *dcn21_hwseq_create(
1467 struct dc_context *ctx)
1469 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1473 hws->regs = &hwseq_reg;
1474 hws->shifts = &hwseq_shift;
1475 hws->masks = &hwseq_mask;
1476 hws->wa.DEGVIDCN21 = true;
1481 static const struct resource_create_funcs res_create_funcs = {
1482 .read_dce_straps = read_dce_straps,
1483 .create_audio = dcn21_create_audio,
1484 .create_stream_encoder = dcn21_stream_encoder_create,
1485 .create_hwseq = dcn21_hwseq_create,
1488 static const struct resource_create_funcs res_create_maximus_funcs = {
1489 .read_dce_straps = NULL,
1490 .create_audio = NULL,
1491 .create_stream_encoder = NULL,
1492 .create_hwseq = dcn21_hwseq_create,
1495 static const struct encoder_feature_support link_enc_feature = {
1496 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1497 .max_hdmi_pixel_clock = 600000,
1498 .hdmi_ycbcr420_supported = true,
1499 .dp_ycbcr420_supported = true,
1500 .flags.bits.IS_HBR2_CAPABLE = true,
1501 .flags.bits.IS_HBR3_CAPABLE = true,
1502 .flags.bits.IS_TPS3_CAPABLE = true,
1503 .flags.bits.IS_TPS4_CAPABLE = true
1507 #define link_regs(id, phyid)\
1509 LE_DCN2_REG_LIST(id), \
1510 UNIPHY_DCN2_REG_LIST(phyid), \
1511 DPCS_DCN21_REG_LIST(id), \
1512 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
1515 static const struct dcn10_link_enc_registers link_enc_regs[] = {
1523 #define aux_regs(id)\
1525 DCN2_AUX_REG_LIST(id)\
1528 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
1536 #define hpd_regs(id)\
1541 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
1549 static const struct dcn10_link_enc_shift le_shift = {
1550 LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT),\
1551 DPCS_DCN21_MASK_SH_LIST(__SHIFT)
1554 static const struct dcn10_link_enc_mask le_mask = {
1555 LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\
1556 DPCS_DCN21_MASK_SH_LIST(_MASK)
1559 static int map_transmitter_id_to_phy_instance(
1560 enum transmitter transmitter)
1562 switch (transmitter) {
1563 case TRANSMITTER_UNIPHY_A:
1566 case TRANSMITTER_UNIPHY_B:
1569 case TRANSMITTER_UNIPHY_C:
1572 case TRANSMITTER_UNIPHY_D:
1575 case TRANSMITTER_UNIPHY_E:
1584 static struct link_encoder *dcn21_link_encoder_create(
1585 const struct encoder_init_data *enc_init_data)
1587 struct dcn21_link_encoder *enc21 =
1588 kzalloc(sizeof(struct dcn21_link_encoder), GFP_KERNEL);
1595 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
1597 dcn21_link_encoder_construct(enc21,
1600 &link_enc_regs[link_regs_id],
1601 &link_enc_aux_regs[enc_init_data->channel - 1],
1602 &link_enc_hpd_regs[enc_init_data->hpd_source],
1606 return &enc21->enc10.base;
1610 #define REG(reg_name) \
1611 (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
1613 static uint32_t read_pipe_fuses(struct dc_context *ctx)
1615 uint32_t value = REG_READ(CC_DC_PIPE_DIS);
1616 /* RV1 support max 4 pipes */
1617 value = value & 0xf;
1621 static int dcn21_populate_dml_pipes_from_context(
1622 struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes)
1624 uint32_t pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes);
1626 struct resource_context *res_ctx = &context->res_ctx;
1628 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1630 if (!res_ctx->pipe_ctx[i].stream)
1633 pipes[i].pipe.src.hostvm = 1;
1634 pipes[i].pipe.src.gpuvm = 1;
1640 static struct resource_funcs dcn21_res_pool_funcs = {
1641 .destroy = dcn21_destroy_resource_pool,
1642 .link_enc_create = dcn21_link_encoder_create,
1643 .validate_bandwidth = dcn21_validate_bandwidth,
1644 .populate_dml_pipes = dcn21_populate_dml_pipes_from_context,
1645 .add_stream_to_ctx = dcn20_add_stream_to_ctx,
1646 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1647 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
1648 .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context,
1649 .get_default_swizzle_mode = dcn20_get_default_swizzle_mode,
1650 .set_mcif_arb_params = dcn20_set_mcif_arb_params,
1651 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1652 .update_bw_bounding_box = update_bw_bounding_box
1655 static bool dcn21_resource_construct(
1656 uint8_t num_virtual_links,
1658 struct dcn21_resource_pool *pool)
1661 struct dc_context *ctx = dc->ctx;
1662 struct irq_service_init_data init_data;
1663 uint32_t pipe_fuses = read_pipe_fuses(ctx);
1666 ctx->dc_bios->regs = &bios_regs;
1668 pool->base.res_cap = &res_cap_rn;
1670 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
1671 //pool->base.res_cap = &res_cap_nv10_FPGA_2pipe_dsc;
1672 pool->base.res_cap = &res_cap_rn_FPGA_4pipe;
1675 pool->base.funcs = &dcn21_res_pool_funcs;
1677 /*************************************************
1678 * Resource + asic cap harcoding *
1679 *************************************************/
1680 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1682 /* max pipe num for ASIC before check pipe fuses */
1683 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1685 dc->caps.max_downscale_ratio = 200;
1686 dc->caps.i2c_speed_in_khz = 100;
1687 dc->caps.max_cursor_size = 256;
1688 dc->caps.dmdata_alloc_size = 2048;
1689 dc->caps.hw_3d_lut = true;
1691 dc->caps.max_slave_planes = 1;
1692 dc->caps.post_blend_color_processing = true;
1693 dc->caps.force_dp_tps4_for_cp2520 = true;
1694 dc->caps.extended_aux_timeout_support = true;
1695 dc->caps.dmcub_support = true;
1697 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1698 dc->debug = debug_defaults_drv;
1699 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
1700 pool->base.pipe_count = 4;
1701 dc->debug = debug_defaults_diags;
1703 dc->debug = debug_defaults_diags;
1705 // Init the vm_helper
1707 vm_helper_init(dc->vm_helper, 16);
1709 /*************************************************
1710 * Create resources *
1711 *************************************************/
1713 pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =
1714 dcn21_clock_source_create(ctx, ctx->dc_bios,
1715 CLOCK_SOURCE_COMBO_PHY_PLL0,
1716 &clk_src_regs[0], false);
1717 pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =
1718 dcn21_clock_source_create(ctx, ctx->dc_bios,
1719 CLOCK_SOURCE_COMBO_PHY_PLL1,
1720 &clk_src_regs[1], false);
1722 pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN21;
1724 /* todo: not reuse phy_pll registers */
1725 pool->base.dp_clock_source =
1726 dcn21_clock_source_create(ctx, ctx->dc_bios,
1727 CLOCK_SOURCE_ID_DP_DTO,
1728 &clk_src_regs[0], true);
1730 for (i = 0; i < pool->base.clk_src_count; i++) {
1731 if (pool->base.clock_sources[i] == NULL) {
1732 dm_error("DC: failed to create clock sources!\n");
1733 BREAK_TO_DEBUGGER();
1738 pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1739 if (pool->base.dccg == NULL) {
1740 dm_error("DC: failed to create dccg!\n");
1741 BREAK_TO_DEBUGGER();
1745 pool->base.dmcu = dcn21_dmcu_create(ctx,
1749 if (pool->base.dmcu == NULL) {
1750 dm_error("DC: failed to create dmcu!\n");
1751 BREAK_TO_DEBUGGER();
1755 // Leave as NULL to not affect current dmcu psr programming sequence
1756 // Will be uncommented when functionality is confirmed to be working
1757 pool->base.psr = NULL;
1759 pool->base.abm = dce_abm_create(ctx,
1763 if (pool->base.abm == NULL) {
1764 dm_error("DC: failed to create abm!\n");
1765 BREAK_TO_DEBUGGER();
1769 pool->base.pp_smu = dcn21_pp_smu_create(ctx);
1771 num_pipes = dcn2_1_ip.max_num_dpp;
1773 for (i = 0; i < dcn2_1_ip.max_num_dpp; i++)
1774 if (pipe_fuses & 1 << i)
1776 dcn2_1_ip.max_num_dpp = num_pipes;
1777 dcn2_1_ip.max_num_otg = num_pipes;
1779 dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);
1781 init_data.ctx = dc->ctx;
1782 pool->base.irqs = dal_irq_service_dcn21_create(&init_data);
1783 if (!pool->base.irqs)
1787 /* mem input -> ipp -> dpp -> opp -> TG */
1788 for (i = 0; i < pool->base.pipe_count; i++) {
1789 /* if pipe is disabled, skip instance of HW pipe,
1790 * i.e, skip ASIC register instance
1792 if ((pipe_fuses & (1 << i)) != 0)
1795 pool->base.hubps[j] = dcn21_hubp_create(ctx, i);
1796 if (pool->base.hubps[j] == NULL) {
1797 BREAK_TO_DEBUGGER();
1799 "DC: failed to create memory input!\n");
1803 pool->base.ipps[j] = dcn21_ipp_create(ctx, i);
1804 if (pool->base.ipps[j] == NULL) {
1805 BREAK_TO_DEBUGGER();
1807 "DC: failed to create input pixel processor!\n");
1811 pool->base.dpps[j] = dcn21_dpp_create(ctx, i);
1812 if (pool->base.dpps[j] == NULL) {
1813 BREAK_TO_DEBUGGER();
1815 "DC: failed to create dpps!\n");
1819 pool->base.opps[j] = dcn21_opp_create(ctx, i);
1820 if (pool->base.opps[j] == NULL) {
1821 BREAK_TO_DEBUGGER();
1823 "DC: failed to create output pixel processor!\n");
1827 pool->base.timing_generators[j] = dcn21_timing_generator_create(
1829 if (pool->base.timing_generators[j] == NULL) {
1830 BREAK_TO_DEBUGGER();
1831 dm_error("DC: failed to create tg!\n");
1837 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1838 pool->base.engines[i] = dcn21_aux_engine_create(ctx, i);
1839 if (pool->base.engines[i] == NULL) {
1840 BREAK_TO_DEBUGGER();
1842 "DC:failed to create aux engine!!\n");
1845 pool->base.hw_i2cs[i] = dcn21_i2c_hw_create(ctx, i);
1846 if (pool->base.hw_i2cs[i] == NULL) {
1847 BREAK_TO_DEBUGGER();
1849 "DC:failed to create hw i2c!!\n");
1852 pool->base.sw_i2cs[i] = NULL;
1855 pool->base.timing_generator_count = j;
1856 pool->base.pipe_count = j;
1857 pool->base.mpcc_count = j;
1859 pool->base.mpc = dcn21_mpc_create(ctx);
1860 if (pool->base.mpc == NULL) {
1861 BREAK_TO_DEBUGGER();
1862 dm_error("DC: failed to create mpc!\n");
1866 pool->base.hubbub = dcn21_hubbub_create(ctx);
1867 if (pool->base.hubbub == NULL) {
1868 BREAK_TO_DEBUGGER();
1869 dm_error("DC: failed to create hubbub!\n");
1873 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1874 pool->base.dscs[i] = dcn21_dsc_create(ctx, i);
1875 if (pool->base.dscs[i] == NULL) {
1876 BREAK_TO_DEBUGGER();
1877 dm_error("DC: failed to create display stream compressor %d!\n", i);
1882 if (!dcn20_dwbc_create(ctx, &pool->base)) {
1883 BREAK_TO_DEBUGGER();
1884 dm_error("DC: failed to create dwbc!\n");
1887 if (!dcn20_mmhubbub_create(ctx, &pool->base)) {
1888 BREAK_TO_DEBUGGER();
1889 dm_error("DC: failed to create mcif_wb!\n");
1893 if (!resource_construct(num_virtual_links, dc, &pool->base,
1894 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
1895 &res_create_funcs : &res_create_maximus_funcs)))
1898 dcn21_hw_sequencer_construct(dc);
1900 dc->caps.max_planes = pool->base.pipe_count;
1902 for (i = 0; i < dc->caps.max_planes; ++i)
1903 dc->caps.planes[i] = plane_cap;
1905 dc->cap_funcs = cap_funcs;
1911 dcn21_resource_destruct(pool);
1916 struct resource_pool *dcn21_create_resource_pool(
1917 const struct dc_init_data *init_data,
1920 struct dcn21_resource_pool *pool =
1921 kzalloc(sizeof(struct dcn21_resource_pool), GFP_KERNEL);
1926 if (dcn21_resource_construct(init_data->num_virtual_links, dc, pool))
1929 BREAK_TO_DEBUGGER();