drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.h

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #ifndef DAL_DC_DCN20_DCN20_VMID_H_
  27 #define DAL_DC_DCN20_DCN20_VMID_H_
  28
  29 #include "vmid.h"
  30
  31 #define BASE_INNER(seg) \
  32         DCE_BASE__INST0_SEG ## seg
  33
  34 #define BASE(seg) \
  35         BASE_INNER(seg)
  36
  37 #define DCN20_VMID_REG_LIST(id)\
  38         SRI(CNTL, DCN_VM_CONTEXT, id),\
  39         SRI(PAGE_TABLE_BASE_ADDR_HI32, DCN_VM_CONTEXT, id),\
  40         SRI(PAGE_TABLE_BASE_ADDR_LO32, DCN_VM_CONTEXT, id),\
  41         SRI(PAGE_TABLE_START_ADDR_HI32, DCN_VM_CONTEXT, id),\
  42         SRI(PAGE_TABLE_START_ADDR_LO32, DCN_VM_CONTEXT, id),\
  43         SRI(PAGE_TABLE_END_ADDR_HI32, DCN_VM_CONTEXT, id),\
  44         SRI(PAGE_TABLE_END_ADDR_LO32, DCN_VM_CONTEXT, id)
  45
  46 #define DCN20_VMID_MASK_SH_LIST(mask_sh)\
  47         SF(DCN_VM_CONTEXT0_CNTL, VM_CONTEXT0_PAGE_TABLE_DEPTH, mask_sh),\
  48         SF(DCN_VM_CONTEXT0_CNTL, VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE, mask_sh),\
  49         SF(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\
  50         SF(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\
  51         SF(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4, mask_sh),\
  52         SF(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32, mask_sh),\
  53         SF(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4, mask_sh),\
  54         SF(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32, mask_sh)
  55
  56 #define DCN20_VMID_REG_FIELD_LIST(type)\
  57         type VM_CONTEXT0_PAGE_TABLE_DEPTH;\
  58         type VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE;\
  59         type VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32;\
  60         type VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32;\
  61         type VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4;\
  62         type VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32;\
  63         type VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4;\
  64         type VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32
  65
  66 struct dcn20_vmid_shift {
  67         DCN20_VMID_REG_FIELD_LIST(uint8_t);
  68 };
  69
  70 struct dcn20_vmid_mask {
  71         DCN20_VMID_REG_FIELD_LIST(uint32_t);
  72 };
  73
  74 struct dcn20_vmid {
  75         struct dc_context *ctx;
  76         const struct dcn_vmid_registers *regs;
  77         const struct dcn20_vmid_shift *shifts;
  78         const struct dcn20_vmid_mask *masks;
  79 };
  80
  81 void dcn20_vmid_setup(struct dcn20_vmid *vmid, const struct dcn_vmid_page_table_config *config);
  82
  83 #endif /* DAL_DC_DCN20_DCN20_VMID_H_ */