2 * Copyright 2016 Advanced Micro Devices, Inc.
3 * Copyright 2019 Raptor Engineering, LLC
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
27 #include <linux/slab.h>
29 #include "dm_services.h"
32 #include "dcn20_init.h"
35 #include "include/irq_service_interface.h"
36 #include "dcn20/dcn20_resource.h"
38 #include "dcn10/dcn10_hubp.h"
39 #include "dcn10/dcn10_ipp.h"
40 #include "dcn20_hubbub.h"
41 #include "dcn20_mpc.h"
42 #include "dcn20_hubp.h"
43 #include "irq/dcn20/irq_service_dcn20.h"
44 #include "dcn20_dpp.h"
45 #include "dcn20_optc.h"
46 #include "dcn20_hwseq.h"
47 #include "dce110/dce110_hw_sequencer.h"
48 #include "dcn10/dcn10_resource.h"
49 #include "dcn20_opp.h"
51 #include "dcn20_dsc.h"
53 #include "dcn20_link_encoder.h"
54 #include "dcn20_stream_encoder.h"
55 #include "dce/dce_clock_source.h"
56 #include "dce/dce_audio.h"
57 #include "dce/dce_hwseq.h"
58 #include "virtual/virtual_stream_encoder.h"
59 #include "dce110/dce110_resource.h"
60 #include "dml/display_mode_vba.h"
61 #include "dcn20_dccg.h"
62 #include "dcn20_vmid.h"
63 #include "dc_link_ddc.h"
64 #include "dce/dce_panel_cntl.h"
66 #include "navi10_ip_offset.h"
68 #include "dcn/dcn_2_0_0_offset.h"
69 #include "dcn/dcn_2_0_0_sh_mask.h"
70 #include "dpcs/dpcs_2_0_0_offset.h"
71 #include "dpcs/dpcs_2_0_0_sh_mask.h"
73 #include "nbio/nbio_2_3_offset.h"
75 #include "dcn20/dcn20_dwb.h"
76 #include "dcn20/dcn20_mmhubbub.h"
78 #include "mmhub/mmhub_2_0_0_offset.h"
79 #include "mmhub/mmhub_2_0_0_sh_mask.h"
81 #include "reg_helper.h"
82 #include "dce/dce_abm.h"
83 #include "dce/dce_dmcu.h"
84 #include "dce/dce_aux.h"
85 #include "dce/dce_i2c.h"
86 #include "vm_helper.h"
88 #include "amdgpu_socbb.h"
90 #define DC_LOGGER_INIT(logger)
92 struct _vcs_dpi_ip_params_st dcn2_0_ip = {
96 .gpuvm_max_page_table_levels = 4,
97 .hostvm_max_page_table_levels = 4,
98 .hostvm_cached_page_table_levels = 0,
99 .pte_group_size_bytes = 2048,
101 .rob_buffer_size_kbytes = 168,
102 .det_buffer_size_kbytes = 164,
103 .dpte_buffer_size_in_pte_reqs_luma = 84,
104 .pde_proc_buffer_size_64k_reqs = 48,
105 .dpp_output_buffer_pixels = 2560,
106 .opp_output_buffer_lines = 1,
107 .pixel_chunk_size_kbytes = 8,
108 .pte_chunk_size_kbytes = 2,
109 .meta_chunk_size_kbytes = 2,
110 .writeback_chunk_size_kbytes = 2,
111 .line_buffer_size_bits = 789504,
112 .is_line_buffer_bpp_fixed = 0,
113 .line_buffer_fixed_bpp = 0,
114 .dcc_supported = true,
115 .max_line_buffer_lines = 12,
116 .writeback_luma_buffer_size_kbytes = 12,
117 .writeback_chroma_buffer_size_kbytes = 8,
118 .writeback_chroma_line_buffer_width_pixels = 4,
119 .writeback_max_hscl_ratio = 1,
120 .writeback_max_vscl_ratio = 1,
121 .writeback_min_hscl_ratio = 1,
122 .writeback_min_vscl_ratio = 1,
123 .writeback_max_hscl_taps = 12,
124 .writeback_max_vscl_taps = 12,
125 .writeback_line_buffer_luma_buffer_size = 0,
126 .writeback_line_buffer_chroma_buffer_size = 14643,
127 .cursor_buffer_size = 8,
128 .cursor_chunk_size = 2,
132 .max_dchub_pscl_bw_pix_per_clk = 4,
133 .max_pscl_lb_bw_pix_per_clk = 2,
134 .max_lb_vscl_bw_pix_per_clk = 4,
135 .max_vscl_hscl_bw_pix_per_clk = 4,
142 .dispclk_ramp_margin_percent = 1,
143 .underscan_factor = 1.10,
144 .min_vblank_lines = 32, //
145 .dppclk_delay_subtotal = 77, //
146 .dppclk_delay_scl_lb_only = 16,
147 .dppclk_delay_scl = 50,
148 .dppclk_delay_cnvc_formatter = 8,
149 .dppclk_delay_cnvc_cursor = 6,
150 .dispclk_delay_subtotal = 87, //
151 .dcfclk_cstate_latency = 10, // SRExitTime
152 .max_inter_dcn_tile_repeaters = 8,
153 .xfc_supported = true,
154 .xfc_fill_bw_overhead_percent = 10.0,
155 .xfc_fill_constant_bytes = 0,
156 .number_of_cursors = 1,
159 static struct _vcs_dpi_ip_params_st dcn2_0_nv14_ip = {
163 .gpuvm_max_page_table_levels = 4,
164 .hostvm_max_page_table_levels = 4,
165 .hostvm_cached_page_table_levels = 0,
167 .rob_buffer_size_kbytes = 168,
168 .det_buffer_size_kbytes = 164,
169 .dpte_buffer_size_in_pte_reqs_luma = 84,
170 .dpte_buffer_size_in_pte_reqs_chroma = 42,//todo
171 .dpp_output_buffer_pixels = 2560,
172 .opp_output_buffer_lines = 1,
173 .pixel_chunk_size_kbytes = 8,
175 .max_page_table_levels = 4,
176 .pte_chunk_size_kbytes = 2,
177 .meta_chunk_size_kbytes = 2,
178 .writeback_chunk_size_kbytes = 2,
179 .line_buffer_size_bits = 789504,
180 .is_line_buffer_bpp_fixed = 0,
181 .line_buffer_fixed_bpp = 0,
182 .dcc_supported = true,
183 .max_line_buffer_lines = 12,
184 .writeback_luma_buffer_size_kbytes = 12,
185 .writeback_chroma_buffer_size_kbytes = 8,
186 .writeback_chroma_line_buffer_width_pixels = 4,
187 .writeback_max_hscl_ratio = 1,
188 .writeback_max_vscl_ratio = 1,
189 .writeback_min_hscl_ratio = 1,
190 .writeback_min_vscl_ratio = 1,
191 .writeback_max_hscl_taps = 12,
192 .writeback_max_vscl_taps = 12,
193 .writeback_line_buffer_luma_buffer_size = 0,
194 .writeback_line_buffer_chroma_buffer_size = 14643,
195 .cursor_buffer_size = 8,
196 .cursor_chunk_size = 2,
200 .max_dchub_pscl_bw_pix_per_clk = 4,
201 .max_pscl_lb_bw_pix_per_clk = 2,
202 .max_lb_vscl_bw_pix_per_clk = 4,
203 .max_vscl_hscl_bw_pix_per_clk = 4,
210 .dispclk_ramp_margin_percent = 1,
211 .underscan_factor = 1.10,
212 .min_vblank_lines = 32, //
213 .dppclk_delay_subtotal = 77, //
214 .dppclk_delay_scl_lb_only = 16,
215 .dppclk_delay_scl = 50,
216 .dppclk_delay_cnvc_formatter = 8,
217 .dppclk_delay_cnvc_cursor = 6,
218 .dispclk_delay_subtotal = 87, //
219 .dcfclk_cstate_latency = 10, // SRExitTime
220 .max_inter_dcn_tile_repeaters = 8,
221 .xfc_supported = true,
222 .xfc_fill_bw_overhead_percent = 10.0,
223 .xfc_fill_constant_bytes = 0,
225 .number_of_cursors = 1,
228 static struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc = {
229 /* Defaults that get patched on driver load from firmware. */
234 .fabricclk_mhz = 560.0,
235 .dispclk_mhz = 513.0,
240 .dram_speed_mts = 8960.0,
245 .fabricclk_mhz = 694.0,
246 .dispclk_mhz = 642.0,
251 .dram_speed_mts = 11104.0,
256 .fabricclk_mhz = 875.0,
257 .dispclk_mhz = 734.0,
262 .dram_speed_mts = 14000.0,
266 .dcfclk_mhz = 1000.0,
267 .fabricclk_mhz = 1000.0,
268 .dispclk_mhz = 1100.0,
269 .dppclk_mhz = 1100.0,
271 .socclk_mhz = 1000.0,
273 .dram_speed_mts = 16000.0,
277 .dcfclk_mhz = 1200.0,
278 .fabricclk_mhz = 1200.0,
279 .dispclk_mhz = 1284.0,
280 .dppclk_mhz = 1284.0,
282 .socclk_mhz = 1200.0,
284 .dram_speed_mts = 16000.0,
286 /*Extra state, no dispclk ramping*/
289 .dcfclk_mhz = 1200.0,
290 .fabricclk_mhz = 1200.0,
291 .dispclk_mhz = 1284.0,
292 .dppclk_mhz = 1284.0,
294 .socclk_mhz = 1200.0,
296 .dram_speed_mts = 16000.0,
300 .sr_exit_time_us = 8.6,
301 .sr_enter_plus_exit_time_us = 10.9,
302 .urgent_latency_us = 4.0,
303 .urgent_latency_pixel_data_only_us = 4.0,
304 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
305 .urgent_latency_vm_data_only_us = 4.0,
306 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
307 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
308 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
309 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0,
310 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0,
311 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
312 .max_avg_sdp_bw_use_normal_percent = 40.0,
313 .max_avg_dram_bw_use_normal_percent = 40.0,
314 .writeback_latency_us = 12.0,
315 .ideal_dram_bw_after_urgent_percent = 40.0,
316 .max_request_size_bytes = 256,
317 .dram_channel_width_bytes = 2,
318 .fabric_datapath_to_dcn_data_return_bytes = 64,
319 .dcn_downspread_percent = 0.5,
320 .downspread_percent = 0.38,
321 .dram_page_open_time_ns = 50.0,
322 .dram_rw_turnaround_time_ns = 17.5,
323 .dram_return_buffer_per_channel_bytes = 8192,
324 .round_trip_ping_latency_dcfclk_cycles = 131,
325 .urgent_out_of_order_return_per_channel_bytes = 256,
326 .channel_interleave_bytes = 256,
329 .vmm_page_size_bytes = 4096,
330 .dram_clock_change_latency_us = 404.0,
331 .dummy_pstate_latency_us = 5.0,
332 .writeback_dram_clock_change_latency_us = 23.0,
333 .return_bus_width_bytes = 64,
334 .dispclk_dppclk_vco_speed_mhz = 3850,
335 .xfc_bus_transport_time_us = 20,
336 .xfc_xbuf_latency_tolerance_us = 4,
337 .use_urgent_burst_bw = 0
340 static struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv14_soc = {
345 .fabricclk_mhz = 560.0,
346 .dispclk_mhz = 513.0,
351 .dram_speed_mts = 8960.0,
356 .fabricclk_mhz = 694.0,
357 .dispclk_mhz = 642.0,
362 .dram_speed_mts = 11104.0,
367 .fabricclk_mhz = 875.0,
368 .dispclk_mhz = 734.0,
373 .dram_speed_mts = 14000.0,
377 .dcfclk_mhz = 1000.0,
378 .fabricclk_mhz = 1000.0,
379 .dispclk_mhz = 1100.0,
380 .dppclk_mhz = 1100.0,
382 .socclk_mhz = 1000.0,
384 .dram_speed_mts = 16000.0,
388 .dcfclk_mhz = 1200.0,
389 .fabricclk_mhz = 1200.0,
390 .dispclk_mhz = 1284.0,
391 .dppclk_mhz = 1284.0,
393 .socclk_mhz = 1200.0,
395 .dram_speed_mts = 16000.0,
397 /*Extra state, no dispclk ramping*/
400 .dcfclk_mhz = 1200.0,
401 .fabricclk_mhz = 1200.0,
402 .dispclk_mhz = 1284.0,
403 .dppclk_mhz = 1284.0,
405 .socclk_mhz = 1200.0,
407 .dram_speed_mts = 16000.0,
411 .sr_exit_time_us = 11.6,
412 .sr_enter_plus_exit_time_us = 13.9,
413 .urgent_latency_us = 4.0,
414 .urgent_latency_pixel_data_only_us = 4.0,
415 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
416 .urgent_latency_vm_data_only_us = 4.0,
417 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
418 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
419 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
420 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0,
421 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0,
422 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
423 .max_avg_sdp_bw_use_normal_percent = 40.0,
424 .max_avg_dram_bw_use_normal_percent = 40.0,
425 .writeback_latency_us = 12.0,
426 .ideal_dram_bw_after_urgent_percent = 40.0,
427 .max_request_size_bytes = 256,
428 .dram_channel_width_bytes = 2,
429 .fabric_datapath_to_dcn_data_return_bytes = 64,
430 .dcn_downspread_percent = 0.5,
431 .downspread_percent = 0.38,
432 .dram_page_open_time_ns = 50.0,
433 .dram_rw_turnaround_time_ns = 17.5,
434 .dram_return_buffer_per_channel_bytes = 8192,
435 .round_trip_ping_latency_dcfclk_cycles = 131,
436 .urgent_out_of_order_return_per_channel_bytes = 256,
437 .channel_interleave_bytes = 256,
440 .vmm_page_size_bytes = 4096,
441 .dram_clock_change_latency_us = 404.0,
442 .dummy_pstate_latency_us = 5.0,
443 .writeback_dram_clock_change_latency_us = 23.0,
444 .return_bus_width_bytes = 64,
445 .dispclk_dppclk_vco_speed_mhz = 3850,
446 .xfc_bus_transport_time_us = 20,
447 .xfc_xbuf_latency_tolerance_us = 4,
448 .use_urgent_burst_bw = 0
451 static struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv12_soc = { 0 };
453 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
454 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f
455 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
456 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f
457 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
458 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f
459 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
460 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f
461 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
462 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f
463 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
464 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f
465 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
466 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f
467 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
471 enum dcn20_clk_src_array_id {
481 /* begin *********************
482 * macros to expend register list macro defined in HW object header file */
485 /* TODO awful hack. fixup dcn20_dwb.h */
487 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
489 #define BASE(seg) BASE_INNER(seg)
491 #define SR(reg_name)\
492 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
495 #define SRI(reg_name, block, id)\
496 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
497 mm ## block ## id ## _ ## reg_name
499 #define SRIR(var_name, reg_name, block, id)\
500 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
501 mm ## block ## id ## _ ## reg_name
503 #define SRII(reg_name, block, id)\
504 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
505 mm ## block ## id ## _ ## reg_name
507 #define DCCG_SRII(reg_name, block, id)\
508 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
509 mm ## block ## id ## _ ## reg_name
511 #define VUPDATE_SRII(reg_name, block, id)\
512 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
513 mm ## reg_name ## _ ## block ## id
516 #define NBIO_BASE_INNER(seg) \
517 NBIO_BASE__INST0_SEG ## seg
519 #define NBIO_BASE(seg) \
522 #define NBIO_SR(reg_name)\
523 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
527 #define MMHUB_BASE_INNER(seg) \
528 MMHUB_BASE__INST0_SEG ## seg
530 #define MMHUB_BASE(seg) \
531 MMHUB_BASE_INNER(seg)
533 #define MMHUB_SR(reg_name)\
534 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
537 static const struct bios_registers bios_regs = {
538 NBIO_SR(BIOS_SCRATCH_3),
539 NBIO_SR(BIOS_SCRATCH_6)
542 #define clk_src_regs(index, pllid)\
544 CS_COMMON_REG_LIST_DCN2_0(index, pllid),\
547 static const struct dce110_clk_src_regs clk_src_regs[] = {
556 static const struct dce110_clk_src_shift cs_shift = {
557 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
560 static const struct dce110_clk_src_mask cs_mask = {
561 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
564 static const struct dce_dmcu_registers dmcu_regs = {
565 DMCU_DCN10_REG_LIST()
568 static const struct dce_dmcu_shift dmcu_shift = {
569 DMCU_MASK_SH_LIST_DCN10(__SHIFT)
572 static const struct dce_dmcu_mask dmcu_mask = {
573 DMCU_MASK_SH_LIST_DCN10(_MASK)
576 static const struct dce_abm_registers abm_regs = {
580 static const struct dce_abm_shift abm_shift = {
581 ABM_MASK_SH_LIST_DCN20(__SHIFT)
584 static const struct dce_abm_mask abm_mask = {
585 ABM_MASK_SH_LIST_DCN20(_MASK)
588 #define audio_regs(id)\
590 AUD_COMMON_REG_LIST(id)\
593 static const struct dce_audio_registers audio_regs[] = {
603 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
604 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
605 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
606 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
608 static const struct dce_audio_shift audio_shift = {
609 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
612 static const struct dce_audio_mask audio_mask = {
613 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
616 #define stream_enc_regs(id)\
618 SE_DCN2_REG_LIST(id)\
621 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
630 static const struct dcn10_stream_encoder_shift se_shift = {
631 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)
634 static const struct dcn10_stream_encoder_mask se_mask = {
635 SE_COMMON_MASK_SH_LIST_DCN20(_MASK)
639 #define aux_regs(id)\
641 DCN2_AUX_REG_LIST(id)\
644 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
653 #define hpd_regs(id)\
658 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
667 #define link_regs(id, phyid)\
669 LE_DCN10_REG_LIST(id), \
670 UNIPHY_DCN2_REG_LIST(phyid), \
671 DPCS_DCN2_REG_LIST(id), \
672 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
675 static const struct dcn10_link_enc_registers link_enc_regs[] = {
684 static const struct dcn10_link_enc_shift le_shift = {
685 LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT),\
686 DPCS_DCN2_MASK_SH_LIST(__SHIFT)
689 static const struct dcn10_link_enc_mask le_mask = {
690 LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\
691 DPCS_DCN2_MASK_SH_LIST(_MASK)
694 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
695 { DCN_PANEL_CNTL_REG_LIST() }
698 static const struct dce_panel_cntl_shift panel_cntl_shift = {
699 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
702 static const struct dce_panel_cntl_mask panel_cntl_mask = {
703 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
706 #define ipp_regs(id)\
708 IPP_REG_LIST_DCN20(id),\
711 static const struct dcn10_ipp_registers ipp_regs[] = {
720 static const struct dcn10_ipp_shift ipp_shift = {
721 IPP_MASK_SH_LIST_DCN20(__SHIFT)
724 static const struct dcn10_ipp_mask ipp_mask = {
725 IPP_MASK_SH_LIST_DCN20(_MASK),
728 #define opp_regs(id)\
730 OPP_REG_LIST_DCN20(id),\
733 static const struct dcn20_opp_registers opp_regs[] = {
742 static const struct dcn20_opp_shift opp_shift = {
743 OPP_MASK_SH_LIST_DCN20(__SHIFT)
746 static const struct dcn20_opp_mask opp_mask = {
747 OPP_MASK_SH_LIST_DCN20(_MASK)
750 #define aux_engine_regs(id)\
752 AUX_COMMON_REG_LIST0(id), \
755 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
758 static const struct dce110_aux_registers aux_engine_regs[] = {
769 TF_REG_LIST_DCN20(id),\
770 TF_REG_LIST_DCN20_COMMON_APPEND(id),\
773 static const struct dcn2_dpp_registers tf_regs[] = {
782 static const struct dcn2_dpp_shift tf_shift = {
783 TF_REG_LIST_SH_MASK_DCN20(__SHIFT),
784 TF_DEBUG_REG_LIST_SH_DCN20
787 static const struct dcn2_dpp_mask tf_mask = {
788 TF_REG_LIST_SH_MASK_DCN20(_MASK),
789 TF_DEBUG_REG_LIST_MASK_DCN20
792 #define dwbc_regs_dcn2(id)\
794 DWBC_COMMON_REG_LIST_DCN2_0(id),\
797 static const struct dcn20_dwbc_registers dwbc20_regs[] = {
801 static const struct dcn20_dwbc_shift dwbc20_shift = {
802 DWBC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
805 static const struct dcn20_dwbc_mask dwbc20_mask = {
806 DWBC_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
809 #define mcif_wb_regs_dcn2(id)\
811 MCIF_WB_COMMON_REG_LIST_DCN2_0(id),\
814 static const struct dcn20_mmhubbub_registers mcif_wb20_regs[] = {
815 mcif_wb_regs_dcn2(0),
818 static const struct dcn20_mmhubbub_shift mcif_wb20_shift = {
819 MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
822 static const struct dcn20_mmhubbub_mask mcif_wb20_mask = {
823 MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
826 static const struct dcn20_mpc_registers mpc_regs = {
827 MPC_REG_LIST_DCN2_0(0),
828 MPC_REG_LIST_DCN2_0(1),
829 MPC_REG_LIST_DCN2_0(2),
830 MPC_REG_LIST_DCN2_0(3),
831 MPC_REG_LIST_DCN2_0(4),
832 MPC_REG_LIST_DCN2_0(5),
833 MPC_OUT_MUX_REG_LIST_DCN2_0(0),
834 MPC_OUT_MUX_REG_LIST_DCN2_0(1),
835 MPC_OUT_MUX_REG_LIST_DCN2_0(2),
836 MPC_OUT_MUX_REG_LIST_DCN2_0(3),
837 MPC_OUT_MUX_REG_LIST_DCN2_0(4),
838 MPC_OUT_MUX_REG_LIST_DCN2_0(5),
839 MPC_DBG_REG_LIST_DCN2_0()
842 static const struct dcn20_mpc_shift mpc_shift = {
843 MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT),
844 MPC_DEBUG_REG_LIST_SH_DCN20
847 static const struct dcn20_mpc_mask mpc_mask = {
848 MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK),
849 MPC_DEBUG_REG_LIST_MASK_DCN20
853 [id] = {TG_COMMON_REG_LIST_DCN2_0(id)}
856 static const struct dcn_optc_registers tg_regs[] = {
865 static const struct dcn_optc_shift tg_shift = {
866 TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
869 static const struct dcn_optc_mask tg_mask = {
870 TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
873 #define hubp_regs(id)\
875 HUBP_REG_LIST_DCN20(id)\
878 static const struct dcn_hubp2_registers hubp_regs[] = {
887 static const struct dcn_hubp2_shift hubp_shift = {
888 HUBP_MASK_SH_LIST_DCN20(__SHIFT)
891 static const struct dcn_hubp2_mask hubp_mask = {
892 HUBP_MASK_SH_LIST_DCN20(_MASK)
895 static const struct dcn_hubbub_registers hubbub_reg = {
896 HUBBUB_REG_LIST_DCN20(0)
899 static const struct dcn_hubbub_shift hubbub_shift = {
900 HUBBUB_MASK_SH_LIST_DCN20(__SHIFT)
903 static const struct dcn_hubbub_mask hubbub_mask = {
904 HUBBUB_MASK_SH_LIST_DCN20(_MASK)
907 #define vmid_regs(id)\
909 DCN20_VMID_REG_LIST(id)\
912 static const struct dcn_vmid_registers vmid_regs[] = {
931 static const struct dcn20_vmid_shift vmid_shifts = {
932 DCN20_VMID_MASK_SH_LIST(__SHIFT)
935 static const struct dcn20_vmid_mask vmid_masks = {
936 DCN20_VMID_MASK_SH_LIST(_MASK)
939 static const struct dce110_aux_registers_shift aux_shift = {
940 DCN_AUX_MASK_SH_LIST(__SHIFT)
943 static const struct dce110_aux_registers_mask aux_mask = {
944 DCN_AUX_MASK_SH_LIST(_MASK)
947 static int map_transmitter_id_to_phy_instance(
948 enum transmitter transmitter)
950 switch (transmitter) {
951 case TRANSMITTER_UNIPHY_A:
954 case TRANSMITTER_UNIPHY_B:
957 case TRANSMITTER_UNIPHY_C:
960 case TRANSMITTER_UNIPHY_D:
963 case TRANSMITTER_UNIPHY_E:
966 case TRANSMITTER_UNIPHY_F:
975 #define dsc_regsDCN20(id)\
977 DSC_REG_LIST_DCN20(id)\
980 static const struct dcn20_dsc_registers dsc_regs[] = {
989 static const struct dcn20_dsc_shift dsc_shift = {
990 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
993 static const struct dcn20_dsc_mask dsc_mask = {
994 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
997 static const struct dccg_registers dccg_regs = {
1001 static const struct dccg_shift dccg_shift = {
1002 DCCG_MASK_SH_LIST_DCN2(__SHIFT)
1005 static const struct dccg_mask dccg_mask = {
1006 DCCG_MASK_SH_LIST_DCN2(_MASK)
1009 static const struct resource_caps res_cap_nv10 = {
1010 .num_timing_generator = 6,
1012 .num_video_plane = 6,
1014 .num_stream_encoder = 6,
1022 static const struct dc_plane_cap plane_cap = {
1023 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
1024 .blends_with_above = true,
1025 .blends_with_below = true,
1026 .per_pixel_alpha = true,
1028 .pixel_format_support = {
1035 .max_upscale_factor = {
1041 .max_downscale_factor = {
1049 static const struct resource_caps res_cap_nv14 = {
1050 .num_timing_generator = 5,
1052 .num_video_plane = 5,
1054 .num_stream_encoder = 5,
1062 static const struct dc_debug_options debug_defaults_drv = {
1063 .disable_dmcu = false,
1064 .force_abm_enable = false,
1065 .timing_trace = false,
1066 .clock_trace = true,
1067 .disable_pplib_clock_request = true,
1068 .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
1069 .force_single_disp_pipe_split = false,
1070 .disable_dcc = DCC_ENABLE,
1071 .vsr_support = true,
1072 .performance_trace = false,
1073 .max_downscale_src_width = 5120,/*upto 5K*/
1074 .disable_pplib_wm_range = false,
1075 .scl_reset_length10 = true,
1076 .sanity_checks = false,
1077 .underflow_assert_delay_us = 0xFFFFFFFF,
1080 static const struct dc_debug_options debug_defaults_diags = {
1081 .disable_dmcu = false,
1082 .force_abm_enable = false,
1083 .timing_trace = true,
1084 .clock_trace = true,
1085 .disable_dpp_power_gate = true,
1086 .disable_hubp_power_gate = true,
1087 .disable_clock_gate = true,
1088 .disable_pplib_clock_request = true,
1089 .disable_pplib_wm_range = true,
1090 .disable_stutter = true,
1091 .scl_reset_length10 = true,
1092 .underflow_assert_delay_us = 0xFFFFFFFF,
1093 .enable_tri_buf = true,
1096 void dcn20_dpp_destroy(struct dpp **dpp)
1098 kfree(TO_DCN20_DPP(*dpp));
1102 struct dpp *dcn20_dpp_create(
1103 struct dc_context *ctx,
1106 struct dcn20_dpp *dpp =
1107 kzalloc(sizeof(struct dcn20_dpp), GFP_ATOMIC);
1112 if (dpp2_construct(dpp, ctx, inst,
1113 &tf_regs[inst], &tf_shift, &tf_mask))
1116 BREAK_TO_DEBUGGER();
1121 struct input_pixel_processor *dcn20_ipp_create(
1122 struct dc_context *ctx, uint32_t inst)
1124 struct dcn10_ipp *ipp =
1125 kzalloc(sizeof(struct dcn10_ipp), GFP_ATOMIC);
1128 BREAK_TO_DEBUGGER();
1132 dcn20_ipp_construct(ipp, ctx, inst,
1133 &ipp_regs[inst], &ipp_shift, &ipp_mask);
1138 struct output_pixel_processor *dcn20_opp_create(
1139 struct dc_context *ctx, uint32_t inst)
1141 struct dcn20_opp *opp =
1142 kzalloc(sizeof(struct dcn20_opp), GFP_ATOMIC);
1145 BREAK_TO_DEBUGGER();
1149 dcn20_opp_construct(opp, ctx, inst,
1150 &opp_regs[inst], &opp_shift, &opp_mask);
1154 struct dce_aux *dcn20_aux_engine_create(
1155 struct dc_context *ctx,
1158 struct aux_engine_dce110 *aux_engine =
1159 kzalloc(sizeof(struct aux_engine_dce110), GFP_ATOMIC);
1164 dce110_aux_engine_construct(aux_engine, ctx, inst,
1165 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
1166 &aux_engine_regs[inst],
1169 ctx->dc->caps.extended_aux_timeout_support);
1171 return &aux_engine->base;
1173 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
1175 static const struct dce_i2c_registers i2c_hw_regs[] = {
1184 static const struct dce_i2c_shift i2c_shifts = {
1185 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
1188 static const struct dce_i2c_mask i2c_masks = {
1189 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
1192 struct dce_i2c_hw *dcn20_i2c_hw_create(
1193 struct dc_context *ctx,
1196 struct dce_i2c_hw *dce_i2c_hw =
1197 kzalloc(sizeof(struct dce_i2c_hw), GFP_ATOMIC);
1202 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
1203 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
1207 struct mpc *dcn20_mpc_create(struct dc_context *ctx)
1209 struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc),
1215 dcn20_mpc_construct(mpc20, ctx,
1221 return &mpc20->base;
1224 struct hubbub *dcn20_hubbub_create(struct dc_context *ctx)
1227 struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub),
1233 hubbub2_construct(hubbub, ctx,
1238 for (i = 0; i < res_cap_nv10.num_vmid; i++) {
1239 struct dcn20_vmid *vmid = &hubbub->vmid[i];
1243 vmid->regs = &vmid_regs[i];
1244 vmid->shifts = &vmid_shifts;
1245 vmid->masks = &vmid_masks;
1248 return &hubbub->base;
1251 struct timing_generator *dcn20_timing_generator_create(
1252 struct dc_context *ctx,
1255 struct optc *tgn10 =
1256 kzalloc(sizeof(struct optc), GFP_ATOMIC);
1261 tgn10->base.inst = instance;
1262 tgn10->base.ctx = ctx;
1264 tgn10->tg_regs = &tg_regs[instance];
1265 tgn10->tg_shift = &tg_shift;
1266 tgn10->tg_mask = &tg_mask;
1268 dcn20_timing_generator_init(tgn10);
1270 return &tgn10->base;
1273 static const struct encoder_feature_support link_enc_feature = {
1274 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1275 .max_hdmi_pixel_clock = 600000,
1276 .hdmi_ycbcr420_supported = true,
1277 .dp_ycbcr420_supported = true,
1278 .fec_supported = true,
1279 .flags.bits.IS_HBR2_CAPABLE = true,
1280 .flags.bits.IS_HBR3_CAPABLE = true,
1281 .flags.bits.IS_TPS3_CAPABLE = true,
1282 .flags.bits.IS_TPS4_CAPABLE = true
1285 struct link_encoder *dcn20_link_encoder_create(
1286 const struct encoder_init_data *enc_init_data)
1288 struct dcn20_link_encoder *enc20 =
1289 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1296 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
1298 dcn20_link_encoder_construct(enc20,
1301 &link_enc_regs[link_regs_id],
1302 &link_enc_aux_regs[enc_init_data->channel - 1],
1303 &link_enc_hpd_regs[enc_init_data->hpd_source],
1307 return &enc20->enc10.base;
1310 static struct panel_cntl *dcn20_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1312 struct dce_panel_cntl *panel_cntl =
1313 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
1318 dce_panel_cntl_construct(panel_cntl,
1320 &panel_cntl_regs[init_data->inst],
1324 return &panel_cntl->base;
1327 static struct clock_source *dcn20_clock_source_create(
1328 struct dc_context *ctx,
1329 struct dc_bios *bios,
1330 enum clock_source_id id,
1331 const struct dce110_clk_src_regs *regs,
1334 struct dce110_clk_src *clk_src =
1335 kzalloc(sizeof(struct dce110_clk_src), GFP_ATOMIC);
1340 if (dcn20_clk_src_construct(clk_src, ctx, bios, id,
1341 regs, &cs_shift, &cs_mask)) {
1342 clk_src->base.dp_clk_src = dp_clk_src;
1343 return &clk_src->base;
1347 BREAK_TO_DEBUGGER();
1351 static void read_dce_straps(
1352 struct dc_context *ctx,
1353 struct resource_straps *straps)
1355 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
1356 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1359 static struct audio *dcn20_create_audio(
1360 struct dc_context *ctx, unsigned int inst)
1362 return dce_audio_create(ctx, inst,
1363 &audio_regs[inst], &audio_shift, &audio_mask);
1366 struct stream_encoder *dcn20_stream_encoder_create(
1367 enum engine_id eng_id,
1368 struct dc_context *ctx)
1370 struct dcn10_stream_encoder *enc1 =
1371 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1376 if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) {
1377 if (eng_id >= ENGINE_ID_DIGD)
1381 dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
1382 &stream_enc_regs[eng_id],
1383 &se_shift, &se_mask);
1388 static const struct dce_hwseq_registers hwseq_reg = {
1389 HWSEQ_DCN2_REG_LIST()
1392 static const struct dce_hwseq_shift hwseq_shift = {
1393 HWSEQ_DCN2_MASK_SH_LIST(__SHIFT)
1396 static const struct dce_hwseq_mask hwseq_mask = {
1397 HWSEQ_DCN2_MASK_SH_LIST(_MASK)
1400 struct dce_hwseq *dcn20_hwseq_create(
1401 struct dc_context *ctx)
1403 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1407 hws->regs = &hwseq_reg;
1408 hws->shifts = &hwseq_shift;
1409 hws->masks = &hwseq_mask;
1414 static const struct resource_create_funcs res_create_funcs = {
1415 .read_dce_straps = read_dce_straps,
1416 .create_audio = dcn20_create_audio,
1417 .create_stream_encoder = dcn20_stream_encoder_create,
1418 .create_hwseq = dcn20_hwseq_create,
1421 static const struct resource_create_funcs res_create_maximus_funcs = {
1422 .read_dce_straps = NULL,
1423 .create_audio = NULL,
1424 .create_stream_encoder = NULL,
1425 .create_hwseq = dcn20_hwseq_create,
1428 static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
1430 void dcn20_clock_source_destroy(struct clock_source **clk_src)
1432 kfree(TO_DCE110_CLK_SRC(*clk_src));
1437 struct display_stream_compressor *dcn20_dsc_create(
1438 struct dc_context *ctx, uint32_t inst)
1440 struct dcn20_dsc *dsc =
1441 kzalloc(sizeof(struct dcn20_dsc), GFP_ATOMIC);
1444 BREAK_TO_DEBUGGER();
1448 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1452 void dcn20_dsc_destroy(struct display_stream_compressor **dsc)
1454 kfree(container_of(*dsc, struct dcn20_dsc, base));
1459 static void dcn20_resource_destruct(struct dcn20_resource_pool *pool)
1463 for (i = 0; i < pool->base.stream_enc_count; i++) {
1464 if (pool->base.stream_enc[i] != NULL) {
1465 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1466 pool->base.stream_enc[i] = NULL;
1470 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1471 if (pool->base.dscs[i] != NULL)
1472 dcn20_dsc_destroy(&pool->base.dscs[i]);
1475 if (pool->base.mpc != NULL) {
1476 kfree(TO_DCN20_MPC(pool->base.mpc));
1477 pool->base.mpc = NULL;
1479 if (pool->base.hubbub != NULL) {
1480 kfree(pool->base.hubbub);
1481 pool->base.hubbub = NULL;
1483 for (i = 0; i < pool->base.pipe_count; i++) {
1484 if (pool->base.dpps[i] != NULL)
1485 dcn20_dpp_destroy(&pool->base.dpps[i]);
1487 if (pool->base.ipps[i] != NULL)
1488 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1490 if (pool->base.hubps[i] != NULL) {
1491 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1492 pool->base.hubps[i] = NULL;
1495 if (pool->base.irqs != NULL) {
1496 dal_irq_service_destroy(&pool->base.irqs);
1500 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1501 if (pool->base.engines[i] != NULL)
1502 dce110_engine_destroy(&pool->base.engines[i]);
1503 if (pool->base.hw_i2cs[i] != NULL) {
1504 kfree(pool->base.hw_i2cs[i]);
1505 pool->base.hw_i2cs[i] = NULL;
1507 if (pool->base.sw_i2cs[i] != NULL) {
1508 kfree(pool->base.sw_i2cs[i]);
1509 pool->base.sw_i2cs[i] = NULL;
1513 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1514 if (pool->base.opps[i] != NULL)
1515 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1518 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1519 if (pool->base.timing_generators[i] != NULL) {
1520 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1521 pool->base.timing_generators[i] = NULL;
1525 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1526 if (pool->base.dwbc[i] != NULL) {
1527 kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
1528 pool->base.dwbc[i] = NULL;
1530 if (pool->base.mcif_wb[i] != NULL) {
1531 kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));
1532 pool->base.mcif_wb[i] = NULL;
1536 for (i = 0; i < pool->base.audio_count; i++) {
1537 if (pool->base.audios[i])
1538 dce_aud_destroy(&pool->base.audios[i]);
1541 for (i = 0; i < pool->base.clk_src_count; i++) {
1542 if (pool->base.clock_sources[i] != NULL) {
1543 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1544 pool->base.clock_sources[i] = NULL;
1548 if (pool->base.dp_clock_source != NULL) {
1549 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1550 pool->base.dp_clock_source = NULL;
1554 if (pool->base.abm != NULL)
1555 dce_abm_destroy(&pool->base.abm);
1557 if (pool->base.dmcu != NULL)
1558 dce_dmcu_destroy(&pool->base.dmcu);
1560 if (pool->base.dccg != NULL)
1561 dcn_dccg_destroy(&pool->base.dccg);
1563 if (pool->base.pp_smu != NULL)
1564 dcn20_pp_smu_destroy(&pool->base.pp_smu);
1566 if (pool->base.oem_device != NULL)
1567 dal_ddc_service_destroy(&pool->base.oem_device);
1570 struct hubp *dcn20_hubp_create(
1571 struct dc_context *ctx,
1574 struct dcn20_hubp *hubp2 =
1575 kzalloc(sizeof(struct dcn20_hubp), GFP_ATOMIC);
1580 if (hubp2_construct(hubp2, ctx, inst,
1581 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1582 return &hubp2->base;
1584 BREAK_TO_DEBUGGER();
1589 static void get_pixel_clock_parameters(
1590 struct pipe_ctx *pipe_ctx,
1591 struct pixel_clk_params *pixel_clk_params)
1593 const struct dc_stream_state *stream = pipe_ctx->stream;
1594 struct pipe_ctx *odm_pipe;
1597 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
1600 pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
1601 pixel_clk_params->encoder_object_id = stream->link->link_enc->id;
1602 pixel_clk_params->signal_type = pipe_ctx->stream->signal;
1603 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
1604 /* TODO: un-hardcode*/
1605 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
1606 LINK_RATE_REF_FREQ_IN_KHZ;
1607 pixel_clk_params->flags.ENABLE_SS = 0;
1608 pixel_clk_params->color_depth =
1609 stream->timing.display_color_depth;
1610 pixel_clk_params->flags.DISPLAY_BLANKED = 1;
1611 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
1613 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
1614 pixel_clk_params->color_depth = COLOR_DEPTH_888;
1617 pixel_clk_params->requested_pix_clk_100hz /= 4;
1618 else if (optc2_is_two_pixels_per_containter(&stream->timing) || opp_cnt == 2)
1619 pixel_clk_params->requested_pix_clk_100hz /= 2;
1621 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1622 pixel_clk_params->requested_pix_clk_100hz *= 2;
1626 static void build_clamping_params(struct dc_stream_state *stream)
1628 stream->clamping.clamping_level = CLAMPING_FULL_RANGE;
1629 stream->clamping.c_depth = stream->timing.display_color_depth;
1630 stream->clamping.pixel_encoding = stream->timing.pixel_encoding;
1633 static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
1636 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
1638 pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
1639 pipe_ctx->clock_source,
1640 &pipe_ctx->stream_res.pix_clk_params,
1641 &pipe_ctx->pll_settings);
1643 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
1645 resource_build_bit_depth_reduction_params(pipe_ctx->stream,
1646 &pipe_ctx->stream->bit_depth_params);
1647 build_clamping_params(pipe_ctx->stream);
1652 enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream)
1654 enum dc_status status = DC_OK;
1655 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
1658 return DC_ERROR_UNEXPECTED;
1661 status = build_pipe_hw_param(pipe_ctx);
1667 void dcn20_acquire_dsc(const struct dc *dc,
1668 struct resource_context *res_ctx,
1669 struct display_stream_compressor **dsc,
1673 const struct resource_pool *pool = dc->res_pool;
1674 struct display_stream_compressor *dsc_old = dc->current_state->res_ctx.pipe_ctx[pipe_idx].stream_res.dsc;
1676 ASSERT(*dsc == NULL); /* If this ASSERT fails, dsc was not released properly */
1679 /* Always do 1-to-1 mapping when number of DSCs is same as number of pipes */
1680 if (pool->res_cap->num_dsc == pool->res_cap->num_opp) {
1681 *dsc = pool->dscs[pipe_idx];
1682 res_ctx->is_dsc_acquired[pipe_idx] = true;
1686 /* Return old DSC to avoid the need for re-programming */
1687 if (dsc_old && !res_ctx->is_dsc_acquired[dsc_old->inst]) {
1689 res_ctx->is_dsc_acquired[dsc_old->inst] = true;
1693 /* Find first free DSC */
1694 for (i = 0; i < pool->res_cap->num_dsc; i++)
1695 if (!res_ctx->is_dsc_acquired[i]) {
1696 *dsc = pool->dscs[i];
1697 res_ctx->is_dsc_acquired[i] = true;
1702 void dcn20_release_dsc(struct resource_context *res_ctx,
1703 const struct resource_pool *pool,
1704 struct display_stream_compressor **dsc)
1708 for (i = 0; i < pool->res_cap->num_dsc; i++)
1709 if (pool->dscs[i] == *dsc) {
1710 res_ctx->is_dsc_acquired[i] = false;
1718 enum dc_status dcn20_add_dsc_to_stream_resource(struct dc *dc,
1719 struct dc_state *dc_ctx,
1720 struct dc_stream_state *dc_stream)
1722 enum dc_status result = DC_OK;
1725 /* Get a DSC if required and available */
1726 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1727 struct pipe_ctx *pipe_ctx = &dc_ctx->res_ctx.pipe_ctx[i];
1729 if (pipe_ctx->stream != dc_stream)
1732 if (pipe_ctx->stream_res.dsc)
1735 dcn20_acquire_dsc(dc, &dc_ctx->res_ctx, &pipe_ctx->stream_res.dsc, i);
1737 /* The number of DSCs can be less than the number of pipes */
1738 if (!pipe_ctx->stream_res.dsc) {
1739 result = DC_NO_DSC_RESOURCE;
1749 static enum dc_status remove_dsc_from_stream_resource(struct dc *dc,
1750 struct dc_state *new_ctx,
1751 struct dc_stream_state *dc_stream)
1753 struct pipe_ctx *pipe_ctx = NULL;
1756 for (i = 0; i < MAX_PIPES; i++) {
1757 if (new_ctx->res_ctx.pipe_ctx[i].stream == dc_stream && !new_ctx->res_ctx.pipe_ctx[i].top_pipe) {
1758 pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];
1760 if (pipe_ctx->stream_res.dsc)
1761 dcn20_release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc);
1766 return DC_ERROR_UNEXPECTED;
1772 enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1774 enum dc_status result = DC_ERROR_UNEXPECTED;
1776 result = resource_map_pool_resources(dc, new_ctx, dc_stream);
1778 if (result == DC_OK)
1779 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
1781 /* Get a DSC if required and available */
1782 if (result == DC_OK && dc_stream->timing.flags.DSC)
1783 result = dcn20_add_dsc_to_stream_resource(dc, new_ctx, dc_stream);
1785 if (result == DC_OK)
1786 result = dcn20_build_mapped_resource(dc, new_ctx, dc_stream);
1792 enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1794 enum dc_status result = DC_OK;
1796 result = remove_dsc_from_stream_resource(dc, new_ctx, dc_stream);
1802 static void swizzle_to_dml_params(
1803 enum swizzle_mode_values swizzle,
1804 unsigned int *sw_mode)
1808 *sw_mode = dm_sw_linear;
1811 *sw_mode = dm_sw_4kb_s;
1814 *sw_mode = dm_sw_4kb_s_x;
1817 *sw_mode = dm_sw_4kb_d;
1820 *sw_mode = dm_sw_4kb_d_x;
1823 *sw_mode = dm_sw_64kb_s;
1825 case DC_SW_64KB_S_X:
1826 *sw_mode = dm_sw_64kb_s_x;
1828 case DC_SW_64KB_S_T:
1829 *sw_mode = dm_sw_64kb_s_t;
1832 *sw_mode = dm_sw_64kb_d;
1834 case DC_SW_64KB_D_X:
1835 *sw_mode = dm_sw_64kb_d_x;
1837 case DC_SW_64KB_D_T:
1838 *sw_mode = dm_sw_64kb_d_t;
1840 case DC_SW_64KB_R_X:
1841 *sw_mode = dm_sw_64kb_r_x;
1844 *sw_mode = dm_sw_var_s;
1847 *sw_mode = dm_sw_var_s_x;
1850 *sw_mode = dm_sw_var_d;
1853 *sw_mode = dm_sw_var_d_x;
1857 ASSERT(0); /* Not supported */
1862 bool dcn20_split_stream_for_odm(
1863 const struct dc *dc,
1864 struct resource_context *res_ctx,
1865 struct pipe_ctx *prev_odm_pipe,
1866 struct pipe_ctx *next_odm_pipe)
1868 int pipe_idx = next_odm_pipe->pipe_idx;
1869 const struct resource_pool *pool = dc->res_pool;
1871 *next_odm_pipe = *prev_odm_pipe;
1873 next_odm_pipe->pipe_idx = pipe_idx;
1874 next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx];
1875 next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx];
1876 next_odm_pipe->plane_res.ipp = pool->ipps[next_odm_pipe->pipe_idx];
1877 next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx];
1878 next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx];
1879 next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst;
1880 next_odm_pipe->stream_res.dsc = NULL;
1881 if (prev_odm_pipe->next_odm_pipe && prev_odm_pipe->next_odm_pipe != next_odm_pipe) {
1882 next_odm_pipe->next_odm_pipe = prev_odm_pipe->next_odm_pipe;
1883 next_odm_pipe->next_odm_pipe->prev_odm_pipe = next_odm_pipe;
1885 if (prev_odm_pipe->top_pipe && prev_odm_pipe->top_pipe->next_odm_pipe) {
1886 prev_odm_pipe->top_pipe->next_odm_pipe->bottom_pipe = next_odm_pipe;
1887 next_odm_pipe->top_pipe = prev_odm_pipe->top_pipe->next_odm_pipe;
1889 if (prev_odm_pipe->bottom_pipe && prev_odm_pipe->bottom_pipe->next_odm_pipe) {
1890 prev_odm_pipe->bottom_pipe->next_odm_pipe->top_pipe = next_odm_pipe;
1891 next_odm_pipe->bottom_pipe = prev_odm_pipe->bottom_pipe->next_odm_pipe;
1893 prev_odm_pipe->next_odm_pipe = next_odm_pipe;
1894 next_odm_pipe->prev_odm_pipe = prev_odm_pipe;
1896 if (prev_odm_pipe->plane_state) {
1897 struct scaler_data *sd = &prev_odm_pipe->plane_res.scl_data;
1900 /* HACTIVE halved for odm combine */
1902 /* Calculate new vp and recout for left pipe */
1903 /* Need at least 16 pixels width per side */
1904 if (sd->recout.x + 16 >= sd->h_active)
1906 new_width = sd->h_active - sd->recout.x;
1907 sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1908 sd->ratios.horz, sd->recout.width - new_width));
1909 sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1910 sd->ratios.horz_c, sd->recout.width - new_width));
1911 sd->recout.width = new_width;
1913 /* Calculate new vp and recout for right pipe */
1914 sd = &next_odm_pipe->plane_res.scl_data;
1915 /* HACTIVE halved for odm combine */
1917 /* Need at least 16 pixels width per side */
1918 if (new_width <= 16)
1920 new_width = sd->recout.width + sd->recout.x - sd->h_active;
1921 sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1922 sd->ratios.horz, sd->recout.width - new_width));
1923 sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1924 sd->ratios.horz_c, sd->recout.width - new_width));
1925 sd->recout.width = new_width;
1926 sd->viewport.x += dc_fixpt_floor(dc_fixpt_mul_int(
1927 sd->ratios.horz, sd->h_active - sd->recout.x));
1928 sd->viewport_c.x += dc_fixpt_floor(dc_fixpt_mul_int(
1929 sd->ratios.horz_c, sd->h_active - sd->recout.x));
1932 if (!next_odm_pipe->top_pipe)
1933 next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx];
1935 next_odm_pipe->stream_res.opp = next_odm_pipe->top_pipe->stream_res.opp;
1936 if (next_odm_pipe->stream->timing.flags.DSC == 1 && !next_odm_pipe->top_pipe) {
1937 dcn20_acquire_dsc(dc, res_ctx, &next_odm_pipe->stream_res.dsc, next_odm_pipe->pipe_idx);
1938 ASSERT(next_odm_pipe->stream_res.dsc);
1939 if (next_odm_pipe->stream_res.dsc == NULL)
1946 void dcn20_split_stream_for_mpc(
1947 struct resource_context *res_ctx,
1948 const struct resource_pool *pool,
1949 struct pipe_ctx *primary_pipe,
1950 struct pipe_ctx *secondary_pipe)
1952 int pipe_idx = secondary_pipe->pipe_idx;
1953 struct pipe_ctx *sec_bot_pipe = secondary_pipe->bottom_pipe;
1955 *secondary_pipe = *primary_pipe;
1956 secondary_pipe->bottom_pipe = sec_bot_pipe;
1958 secondary_pipe->pipe_idx = pipe_idx;
1959 secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx];
1960 secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx];
1961 secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx];
1962 secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx];
1963 secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx];
1964 secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst;
1965 secondary_pipe->stream_res.dsc = NULL;
1966 if (primary_pipe->bottom_pipe && primary_pipe->bottom_pipe != secondary_pipe) {
1967 ASSERT(!secondary_pipe->bottom_pipe);
1968 secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe;
1969 secondary_pipe->bottom_pipe->top_pipe = secondary_pipe;
1971 primary_pipe->bottom_pipe = secondary_pipe;
1972 secondary_pipe->top_pipe = primary_pipe;
1974 ASSERT(primary_pipe->plane_state);
1977 void dcn20_populate_dml_writeback_from_context(
1978 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
1982 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1983 struct dc_writeback_info *wb_info = &res_ctx->pipe_ctx[i].stream->writeback_info[0];
1985 if (!res_ctx->pipe_ctx[i].stream)
1988 /* Set writeback information */
1989 pipes[pipe_cnt].dout.wb_enable = (wb_info->wb_enabled == true) ? 1 : 0;
1990 pipes[pipe_cnt].dout.num_active_wb++;
1991 pipes[pipe_cnt].dout.wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_height;
1992 pipes[pipe_cnt].dout.wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_width;
1993 pipes[pipe_cnt].dout.wb.wb_dst_width = wb_info->dwb_params.dest_width;
1994 pipes[pipe_cnt].dout.wb.wb_dst_height = wb_info->dwb_params.dest_height;
1995 pipes[pipe_cnt].dout.wb.wb_htaps_luma = 1;
1996 pipes[pipe_cnt].dout.wb.wb_vtaps_luma = 1;
1997 pipes[pipe_cnt].dout.wb.wb_htaps_chroma = wb_info->dwb_params.scaler_taps.h_taps_c;
1998 pipes[pipe_cnt].dout.wb.wb_vtaps_chroma = wb_info->dwb_params.scaler_taps.v_taps_c;
1999 pipes[pipe_cnt].dout.wb.wb_hratio = 1.0;
2000 pipes[pipe_cnt].dout.wb.wb_vratio = 1.0;
2001 if (wb_info->dwb_params.out_format == dwb_scaler_mode_yuv420) {
2002 if (wb_info->dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC)
2003 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_8;
2005 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_10;
2007 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_444_32;
2014 int dcn20_populate_dml_pipes_from_context(
2016 struct dc_state *context,
2017 display_e2e_pipe_params_st *pipes,
2021 bool synchronized_vblank = true;
2022 struct resource_context *res_ctx = &context->res_ctx;
2024 for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) {
2025 if (!res_ctx->pipe_ctx[i].stream)
2033 if (res_ctx->pipe_ctx[pipe_cnt].stream == res_ctx->pipe_ctx[i].stream)
2036 if (dc->debug.disable_timing_sync ||
2037 (!resource_are_streams_timing_synchronizable(
2038 res_ctx->pipe_ctx[pipe_cnt].stream,
2039 res_ctx->pipe_ctx[i].stream) &&
2040 !resource_are_vblanks_synchronizable(
2041 res_ctx->pipe_ctx[pipe_cnt].stream,
2042 res_ctx->pipe_ctx[i].stream))) {
2043 synchronized_vblank = false;
2048 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
2049 struct dc_crtc_timing *timing = &res_ctx->pipe_ctx[i].stream->timing;
2050 unsigned int v_total;
2051 unsigned int front_porch;
2053 struct audio_check aud_check = {0};
2055 if (!res_ctx->pipe_ctx[i].stream)
2058 v_total = timing->v_total;
2059 front_porch = timing->v_front_porch;
2062 pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = 0;
2063 pipes[pipe_cnt].pipe.src.dcc = 0;
2064 pipes[pipe_cnt].pipe.src.vm = 0;*/
2066 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
2068 pipes[pipe_cnt].dout.dsc_enable = res_ctx->pipe_ctx[i].stream->timing.flags.DSC;
2069 /* todo: rotation?*/
2070 pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h;
2071 if (res_ctx->pipe_ctx[i].stream->use_dynamic_meta) {
2072 pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = true;
2074 pipes[pipe_cnt].pipe.src.dynamic_metadata_lines_before_active =
2075 (v_total - timing->v_addressable
2076 - timing->v_border_top - timing->v_border_bottom) / 2;
2077 /* 36 bytes dp, 32 hdmi */
2078 pipes[pipe_cnt].pipe.src.dynamic_metadata_xmit_bytes =
2079 dc_is_dp_signal(res_ctx->pipe_ctx[i].stream->signal) ? 36 : 32;
2081 pipes[pipe_cnt].pipe.src.dcc = false;
2082 pipes[pipe_cnt].pipe.src.dcc_rate = 1;
2083 pipes[pipe_cnt].pipe.dest.synchronized_vblank_all_planes = synchronized_vblank;
2084 pipes[pipe_cnt].pipe.dest.hblank_start = timing->h_total - timing->h_front_porch;
2085 pipes[pipe_cnt].pipe.dest.hblank_end = pipes[pipe_cnt].pipe.dest.hblank_start
2086 - timing->h_addressable
2087 - timing->h_border_left
2088 - timing->h_border_right;
2089 pipes[pipe_cnt].pipe.dest.vblank_start = v_total - front_porch;
2090 pipes[pipe_cnt].pipe.dest.vblank_end = pipes[pipe_cnt].pipe.dest.vblank_start
2091 - timing->v_addressable
2092 - timing->v_border_top
2093 - timing->v_border_bottom;
2094 pipes[pipe_cnt].pipe.dest.htotal = timing->h_total;
2095 pipes[pipe_cnt].pipe.dest.vtotal = v_total;
2096 pipes[pipe_cnt].pipe.dest.hactive =
2097 timing->h_addressable + timing->h_border_left + timing->h_border_right;
2098 pipes[pipe_cnt].pipe.dest.vactive =
2099 timing->v_addressable + timing->v_border_top + timing->v_border_bottom;
2100 pipes[pipe_cnt].pipe.dest.interlaced = timing->flags.INTERLACE;
2101 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz = timing->pix_clk_100hz/10000.0;
2102 if (timing->timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
2103 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz *= 2;
2104 pipes[pipe_cnt].pipe.dest.otg_inst = res_ctx->pipe_ctx[i].stream_res.tg->inst;
2105 pipes[pipe_cnt].dout.dp_lanes = 4;
2106 pipes[pipe_cnt].dout.is_virtual = 0;
2107 pipes[pipe_cnt].pipe.dest.vtotal_min = res_ctx->pipe_ctx[i].stream->adjust.v_total_min;
2108 pipes[pipe_cnt].pipe.dest.vtotal_max = res_ctx->pipe_ctx[i].stream->adjust.v_total_max;
2109 switch (get_num_odm_splits(&res_ctx->pipe_ctx[i])) {
2111 pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_2to1;
2114 pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_4to1;
2117 pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_disabled;
2119 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
2120 if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state
2121 == res_ctx->pipe_ctx[i].plane_state) {
2122 struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].top_pipe;
2125 while (first_pipe->top_pipe && first_pipe->top_pipe->plane_state
2126 == res_ctx->pipe_ctx[i].plane_state) {
2127 first_pipe = first_pipe->top_pipe;
2130 /* Treat 4to1 mpc combine as an mpo of 2 2-to-1 combines */
2132 pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx;
2133 else if (split_idx == 1)
2134 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
2135 else if (split_idx == 2)
2136 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].top_pipe->pipe_idx;
2137 } else if (res_ctx->pipe_ctx[i].prev_odm_pipe) {
2138 struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].prev_odm_pipe;
2140 while (first_pipe->prev_odm_pipe)
2141 first_pipe = first_pipe->prev_odm_pipe;
2142 pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx;
2145 switch (res_ctx->pipe_ctx[i].stream->signal) {
2146 case SIGNAL_TYPE_DISPLAY_PORT_MST:
2147 case SIGNAL_TYPE_DISPLAY_PORT:
2148 pipes[pipe_cnt].dout.output_type = dm_dp;
2150 case SIGNAL_TYPE_EDP:
2151 pipes[pipe_cnt].dout.output_type = dm_edp;
2153 case SIGNAL_TYPE_HDMI_TYPE_A:
2154 case SIGNAL_TYPE_DVI_SINGLE_LINK:
2155 case SIGNAL_TYPE_DVI_DUAL_LINK:
2156 pipes[pipe_cnt].dout.output_type = dm_hdmi;
2159 /* In case there is no signal, set dp with 4 lanes to allow max config */
2160 pipes[pipe_cnt].dout.is_virtual = 1;
2161 pipes[pipe_cnt].dout.output_type = dm_dp;
2162 pipes[pipe_cnt].dout.dp_lanes = 4;
2165 switch (res_ctx->pipe_ctx[i].stream->timing.display_color_depth) {
2166 case COLOR_DEPTH_666:
2169 case COLOR_DEPTH_888:
2172 case COLOR_DEPTH_101010:
2175 case COLOR_DEPTH_121212:
2178 case COLOR_DEPTH_141414:
2181 case COLOR_DEPTH_161616:
2184 case COLOR_DEPTH_999:
2187 case COLOR_DEPTH_111111:
2195 switch (res_ctx->pipe_ctx[i].stream->timing.pixel_encoding) {
2196 case PIXEL_ENCODING_RGB:
2197 case PIXEL_ENCODING_YCBCR444:
2198 pipes[pipe_cnt].dout.output_format = dm_444;
2199 pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
2201 case PIXEL_ENCODING_YCBCR420:
2202 pipes[pipe_cnt].dout.output_format = dm_420;
2203 pipes[pipe_cnt].dout.output_bpp = (output_bpc * 3.0) / 2;
2205 case PIXEL_ENCODING_YCBCR422:
2206 if (res_ctx->pipe_ctx[i].stream->timing.flags.DSC &&
2207 !res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.ycbcr422_simple)
2208 pipes[pipe_cnt].dout.output_format = dm_n422;
2210 pipes[pipe_cnt].dout.output_format = dm_s422;
2211 pipes[pipe_cnt].dout.output_bpp = output_bpc * 2;
2214 pipes[pipe_cnt].dout.output_format = dm_444;
2215 pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
2218 if (res_ctx->pipe_ctx[i].stream->timing.flags.DSC)
2219 pipes[pipe_cnt].dout.output_bpp = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.bits_per_pixel / 16.0;
2221 /* todo: default max for now, until there is logic reflecting this in dc*/
2222 pipes[pipe_cnt].dout.dsc_input_bpc = 12;
2223 /*fill up the audio sample rate (unit in kHz)*/
2224 get_audio_check(&res_ctx->pipe_ctx[i].stream->audio_info, &aud_check);
2225 pipes[pipe_cnt].dout.max_audio_sample_rate = aud_check.max_audiosample_rate / 1000;
2227 * For graphic plane, cursor number is 1, nv12 is 0
2228 * bw calculations due to cursor on/off
2230 if (res_ctx->pipe_ctx[i].plane_state &&
2231 res_ctx->pipe_ctx[i].plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
2232 pipes[pipe_cnt].pipe.src.num_cursors = 0;
2234 pipes[pipe_cnt].pipe.src.num_cursors = dc->dml.ip.number_of_cursors;
2236 pipes[pipe_cnt].pipe.src.cur0_src_width = 256;
2237 pipes[pipe_cnt].pipe.src.cur0_bpp = dm_cur_32bit;
2239 if (!res_ctx->pipe_ctx[i].plane_state) {
2240 pipes[pipe_cnt].pipe.src.is_hsplit = pipes[pipe_cnt].pipe.dest.odm_combine != dm_odm_combine_mode_disabled;
2241 pipes[pipe_cnt].pipe.src.source_scan = dm_horz;
2242 pipes[pipe_cnt].pipe.src.sw_mode = dm_sw_4kb_s;
2243 pipes[pipe_cnt].pipe.src.macro_tile_size = dm_64k_tile;
2244 pipes[pipe_cnt].pipe.src.viewport_width = timing->h_addressable;
2245 if (pipes[pipe_cnt].pipe.src.viewport_width > 1920)
2246 pipes[pipe_cnt].pipe.src.viewport_width = 1920;
2247 pipes[pipe_cnt].pipe.src.viewport_height = timing->v_addressable;
2248 if (pipes[pipe_cnt].pipe.src.viewport_height > 1080)
2249 pipes[pipe_cnt].pipe.src.viewport_height = 1080;
2250 pipes[pipe_cnt].pipe.src.surface_height_y = pipes[pipe_cnt].pipe.src.viewport_height;
2251 pipes[pipe_cnt].pipe.src.surface_width_y = pipes[pipe_cnt].pipe.src.viewport_width;
2252 pipes[pipe_cnt].pipe.src.surface_height_c = pipes[pipe_cnt].pipe.src.viewport_height;
2253 pipes[pipe_cnt].pipe.src.surface_width_c = pipes[pipe_cnt].pipe.src.viewport_width;
2254 pipes[pipe_cnt].pipe.src.data_pitch = ((pipes[pipe_cnt].pipe.src.viewport_width + 255) / 256) * 256;
2255 pipes[pipe_cnt].pipe.src.source_format = dm_444_32;
2256 pipes[pipe_cnt].pipe.dest.recout_width = pipes[pipe_cnt].pipe.src.viewport_width; /*vp_width/hratio*/
2257 pipes[pipe_cnt].pipe.dest.recout_height = pipes[pipe_cnt].pipe.src.viewport_height; /*vp_height/vratio*/
2258 pipes[pipe_cnt].pipe.dest.full_recout_width = pipes[pipe_cnt].pipe.dest.recout_width; /*when is_hsplit != 1*/
2259 pipes[pipe_cnt].pipe.dest.full_recout_height = pipes[pipe_cnt].pipe.dest.recout_height; /*when is_hsplit != 1*/
2260 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16;
2261 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = 1.0;
2262 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = 1.0;
2263 pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable = 0; /*Lb only or Full scl*/
2264 pipes[pipe_cnt].pipe.scale_taps.htaps = 1;
2265 pipes[pipe_cnt].pipe.scale_taps.vtaps = 1;
2266 pipes[pipe_cnt].pipe.dest.vtotal_min = v_total;
2267 pipes[pipe_cnt].pipe.dest.vtotal_max = v_total;
2269 if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_2to1) {
2270 pipes[pipe_cnt].pipe.src.viewport_width /= 2;
2271 pipes[pipe_cnt].pipe.dest.recout_width /= 2;
2272 } else if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_4to1) {
2273 pipes[pipe_cnt].pipe.src.viewport_width /= 4;
2274 pipes[pipe_cnt].pipe.dest.recout_width /= 4;
2277 struct dc_plane_state *pln = res_ctx->pipe_ctx[i].plane_state;
2278 struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data;
2280 pipes[pipe_cnt].pipe.src.immediate_flip = pln->flip_immediate;
2281 pipes[pipe_cnt].pipe.src.is_hsplit = (res_ctx->pipe_ctx[i].bottom_pipe && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln)
2282 || (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln)
2283 || pipes[pipe_cnt].pipe.dest.odm_combine != dm_odm_combine_mode_disabled;
2285 /* stereo is not split */
2286 if (pln->stereo_format == PLANE_STEREO_FORMAT_SIDE_BY_SIDE ||
2287 pln->stereo_format == PLANE_STEREO_FORMAT_TOP_AND_BOTTOM) {
2288 pipes[pipe_cnt].pipe.src.is_hsplit = false;
2289 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
2292 pipes[pipe_cnt].pipe.src.source_scan = pln->rotation == ROTATION_ANGLE_90
2293 || pln->rotation == ROTATION_ANGLE_270 ? dm_vert : dm_horz;
2294 pipes[pipe_cnt].pipe.src.viewport_y_y = scl->viewport.y;
2295 pipes[pipe_cnt].pipe.src.viewport_y_c = scl->viewport_c.y;
2296 pipes[pipe_cnt].pipe.src.viewport_width = scl->viewport.width;
2297 pipes[pipe_cnt].pipe.src.viewport_width_c = scl->viewport_c.width;
2298 pipes[pipe_cnt].pipe.src.viewport_height = scl->viewport.height;
2299 pipes[pipe_cnt].pipe.src.viewport_height_c = scl->viewport_c.height;
2300 pipes[pipe_cnt].pipe.src.viewport_width_max = pln->src_rect.width;
2301 pipes[pipe_cnt].pipe.src.viewport_height_max = pln->src_rect.height;
2302 pipes[pipe_cnt].pipe.src.surface_width_y = pln->plane_size.surface_size.width;
2303 pipes[pipe_cnt].pipe.src.surface_height_y = pln->plane_size.surface_size.height;
2304 pipes[pipe_cnt].pipe.src.surface_width_c = pln->plane_size.chroma_size.width;
2305 pipes[pipe_cnt].pipe.src.surface_height_c = pln->plane_size.chroma_size.height;
2306 if (pln->format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA
2307 || pln->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
2308 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;
2309 pipes[pipe_cnt].pipe.src.data_pitch_c = pln->plane_size.chroma_pitch;
2310 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch;
2311 pipes[pipe_cnt].pipe.src.meta_pitch_c = pln->dcc.meta_pitch_c;
2313 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;
2314 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch;
2316 pipes[pipe_cnt].pipe.src.dcc = pln->dcc.enable;
2317 pipes[pipe_cnt].pipe.dest.recout_width = scl->recout.width;
2318 pipes[pipe_cnt].pipe.dest.recout_height = scl->recout.height;
2319 pipes[pipe_cnt].pipe.dest.full_recout_height = scl->recout.height;
2320 pipes[pipe_cnt].pipe.dest.full_recout_width = scl->recout.width;
2321 if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_2to1)
2322 pipes[pipe_cnt].pipe.dest.full_recout_width *= 2;
2323 else if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_4to1)
2324 pipes[pipe_cnt].pipe.dest.full_recout_width *= 4;
2326 struct pipe_ctx *split_pipe = res_ctx->pipe_ctx[i].bottom_pipe;
2328 while (split_pipe && split_pipe->plane_state == pln) {
2329 pipes[pipe_cnt].pipe.dest.full_recout_width += split_pipe->plane_res.scl_data.recout.width;
2330 split_pipe = split_pipe->bottom_pipe;
2332 split_pipe = res_ctx->pipe_ctx[i].top_pipe;
2333 while (split_pipe && split_pipe->plane_state == pln) {
2334 pipes[pipe_cnt].pipe.dest.full_recout_width += split_pipe->plane_res.scl_data.recout.width;
2335 split_pipe = split_pipe->top_pipe;
2339 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16;
2340 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = (double) scl->ratios.horz.value / (1ULL<<32);
2341 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio_c = (double) scl->ratios.horz_c.value / (1ULL<<32);
2342 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = (double) scl->ratios.vert.value / (1ULL<<32);
2343 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio_c = (double) scl->ratios.vert_c.value / (1ULL<<32);
2344 pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable =
2345 scl->ratios.vert.value != dc_fixpt_one.value
2346 || scl->ratios.horz.value != dc_fixpt_one.value
2347 || scl->ratios.vert_c.value != dc_fixpt_one.value
2348 || scl->ratios.horz_c.value != dc_fixpt_one.value /*Lb only or Full scl*/
2349 || dc->debug.always_scale; /*support always scale*/
2350 pipes[pipe_cnt].pipe.scale_taps.htaps = scl->taps.h_taps;
2351 pipes[pipe_cnt].pipe.scale_taps.htaps_c = scl->taps.h_taps_c;
2352 pipes[pipe_cnt].pipe.scale_taps.vtaps = scl->taps.v_taps;
2353 pipes[pipe_cnt].pipe.scale_taps.vtaps_c = scl->taps.v_taps_c;
2355 pipes[pipe_cnt].pipe.src.macro_tile_size =
2356 swizzle_mode_to_macro_tile_size(pln->tiling_info.gfx9.swizzle);
2357 swizzle_to_dml_params(pln->tiling_info.gfx9.swizzle,
2358 &pipes[pipe_cnt].pipe.src.sw_mode);
2360 switch (pln->format) {
2361 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
2362 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
2363 pipes[pipe_cnt].pipe.src.source_format = dm_420_8;
2365 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
2366 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
2367 pipes[pipe_cnt].pipe.src.source_format = dm_420_10;
2369 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
2370 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
2371 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
2372 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
2373 pipes[pipe_cnt].pipe.src.source_format = dm_444_64;
2375 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
2376 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
2377 pipes[pipe_cnt].pipe.src.source_format = dm_444_16;
2379 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
2380 pipes[pipe_cnt].pipe.src.source_format = dm_444_8;
2382 case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
2383 pipes[pipe_cnt].pipe.src.source_format = dm_rgbe_alpha;
2386 pipes[pipe_cnt].pipe.src.source_format = dm_444_32;
2394 /* populate writeback information */
2395 dc->res_pool->funcs->populate_dml_writeback_from_context(dc, res_ctx, pipes);
2400 unsigned int dcn20_calc_max_scaled_time(
2401 unsigned int time_per_pixel,
2402 enum mmhubbub_wbif_mode mode,
2403 unsigned int urgent_watermark)
2405 unsigned int time_per_byte = 0;
2406 unsigned int total_y_free_entry = 0x200; /* two memory piece for luma */
2407 unsigned int total_c_free_entry = 0x140; /* two memory piece for chroma */
2408 unsigned int small_free_entry, max_free_entry;
2409 unsigned int buf_lh_capability;
2410 unsigned int max_scaled_time;
2412 if (mode == PACKED_444) /* packed mode */
2413 time_per_byte = time_per_pixel/4;
2414 else if (mode == PLANAR_420_8BPC)
2415 time_per_byte = time_per_pixel;
2416 else if (mode == PLANAR_420_10BPC) /* p010 */
2417 time_per_byte = time_per_pixel * 819/1024;
2419 if (time_per_byte == 0)
2422 small_free_entry = (total_y_free_entry > total_c_free_entry) ? total_c_free_entry : total_y_free_entry;
2423 max_free_entry = (mode == PACKED_444) ? total_y_free_entry + total_c_free_entry : small_free_entry;
2424 buf_lh_capability = max_free_entry*time_per_byte*32/16; /* there is 4bit fraction */
2425 max_scaled_time = buf_lh_capability - urgent_watermark;
2426 return max_scaled_time;
2429 void dcn20_set_mcif_arb_params(
2431 struct dc_state *context,
2432 display_e2e_pipe_params_st *pipes,
2435 enum mmhubbub_wbif_mode wbif_mode;
2436 struct mcif_arb_params *wb_arb_params;
2437 int i, j, k, dwb_pipe;
2439 /* Writeback MCIF_WB arbitration parameters */
2441 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2443 if (!context->res_ctx.pipe_ctx[i].stream)
2446 for (j = 0; j < MAX_DWB_PIPES; j++) {
2447 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].wb_enabled == false)
2450 //wb_arb_params = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j].mcif_arb_params;
2451 wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe];
2453 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.out_format == dwb_scaler_mode_yuv420) {
2454 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC)
2455 wbif_mode = PLANAR_420_8BPC;
2457 wbif_mode = PLANAR_420_10BPC;
2459 wbif_mode = PACKED_444;
2461 for (k = 0; k < sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]); k++) {
2462 wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2463 wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2465 wb_arb_params->time_per_pixel = 16.0 / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk; /* 4 bit fraction, ms */
2466 wb_arb_params->slice_lines = 32;
2467 wb_arb_params->arbitration_slice = 2;
2468 wb_arb_params->max_scaled_time = dcn20_calc_max_scaled_time(wb_arb_params->time_per_pixel,
2470 wb_arb_params->cli_watermark[0]); /* assume 4 watermark sets have the same value */
2474 if (dwb_pipe >= MAX_DWB_PIPES)
2477 if (dwb_pipe >= MAX_DWB_PIPES)
2482 bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx)
2486 /* Validate DSC config, dsc count validation is already done */
2487 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2488 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];
2489 struct dc_stream_state *stream = pipe_ctx->stream;
2490 struct dsc_config dsc_cfg;
2491 struct pipe_ctx *odm_pipe;
2494 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
2497 /* Only need to validate top pipe */
2498 if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe || !stream || !stream->timing.flags.DSC)
2501 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left
2502 + stream->timing.h_border_right) / opp_cnt;
2503 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top
2504 + stream->timing.v_border_bottom;
2505 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
2506 dsc_cfg.color_depth = stream->timing.display_color_depth;
2507 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;
2508 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
2509 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
2511 if (!pipe_ctx->stream_res.dsc->funcs->dsc_validate_stream(pipe_ctx->stream_res.dsc, &dsc_cfg))
2517 struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc,
2518 struct resource_context *res_ctx,
2519 const struct resource_pool *pool,
2520 const struct pipe_ctx *primary_pipe)
2522 struct pipe_ctx *secondary_pipe = NULL;
2524 if (dc && primary_pipe) {
2526 int preferred_pipe_idx = 0;
2528 /* first check the prev dc state:
2529 * if this primary pipe has a bottom pipe in prev. state
2530 * and if the bottom pipe is still available (which it should be),
2531 * pick that pipe as secondary
2532 * Same logic applies for ODM pipes
2534 if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe) {
2535 preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe->pipe_idx;
2536 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2537 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2538 secondary_pipe->pipe_idx = preferred_pipe_idx;
2541 if (secondary_pipe == NULL &&
2542 dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe) {
2543 preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe->pipe_idx;
2544 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2545 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2546 secondary_pipe->pipe_idx = preferred_pipe_idx;
2551 * if this primary pipe does not have a bottom pipe in prev. state
2552 * start backward and find a pipe that did not used to be a bottom pipe in
2553 * prev. dc state. This way we make sure we keep the same assignment as
2554 * last state and will not have to reprogram every pipe
2556 if (secondary_pipe == NULL) {
2557 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {
2558 if (dc->current_state->res_ctx.pipe_ctx[j].top_pipe == NULL
2559 && dc->current_state->res_ctx.pipe_ctx[j].prev_odm_pipe == NULL) {
2560 preferred_pipe_idx = j;
2562 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2563 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2564 secondary_pipe->pipe_idx = preferred_pipe_idx;
2571 * We should never hit this assert unless assignments are shuffled around
2572 * if this happens we will prob. hit a vsync tdr
2574 ASSERT(secondary_pipe);
2576 * search backwards for the second pipe to keep pipe
2577 * assignment more consistent
2579 if (secondary_pipe == NULL) {
2580 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {
2581 preferred_pipe_idx = j;
2583 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2584 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2585 secondary_pipe->pipe_idx = preferred_pipe_idx;
2592 return secondary_pipe;
2595 void dcn20_merge_pipes_for_validate(
2597 struct dc_state *context)
2601 /* merge previously split odm pipes since mode support needs to make the decision */
2602 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2603 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2604 struct pipe_ctx *odm_pipe = pipe->next_odm_pipe;
2606 if (pipe->prev_odm_pipe)
2609 pipe->next_odm_pipe = NULL;
2611 struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe;
2613 odm_pipe->plane_state = NULL;
2614 odm_pipe->stream = NULL;
2615 odm_pipe->top_pipe = NULL;
2616 odm_pipe->bottom_pipe = NULL;
2617 odm_pipe->prev_odm_pipe = NULL;
2618 odm_pipe->next_odm_pipe = NULL;
2619 if (odm_pipe->stream_res.dsc)
2620 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc);
2621 /* Clear plane_res and stream_res */
2622 memset(&odm_pipe->plane_res, 0, sizeof(odm_pipe->plane_res));
2623 memset(&odm_pipe->stream_res, 0, sizeof(odm_pipe->stream_res));
2624 odm_pipe = next_odm_pipe;
2626 if (pipe->plane_state)
2627 resource_build_scaling_params(pipe);
2630 /* merge previously mpc split pipes since mode support needs to make the decision */
2631 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2632 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2633 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
2635 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state)
2638 pipe->bottom_pipe = hsplit_pipe->bottom_pipe;
2639 if (hsplit_pipe->bottom_pipe)
2640 hsplit_pipe->bottom_pipe->top_pipe = pipe;
2641 hsplit_pipe->plane_state = NULL;
2642 hsplit_pipe->stream = NULL;
2643 hsplit_pipe->top_pipe = NULL;
2644 hsplit_pipe->bottom_pipe = NULL;
2646 /* Clear plane_res and stream_res */
2647 memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res));
2648 memset(&hsplit_pipe->stream_res, 0, sizeof(hsplit_pipe->stream_res));
2649 if (pipe->plane_state)
2650 resource_build_scaling_params(pipe);
2654 int dcn20_validate_apply_pipe_split_flags(
2656 struct dc_state *context,
2661 int i, pipe_idx, vlevel_split;
2662 int plane_count = 0;
2663 bool force_split = false;
2664 bool avoid_split = dc->debug.pipe_split_policy == MPC_SPLIT_AVOID;
2665 struct vba_vars_st *v = &context->bw_ctx.dml.vba;
2666 int max_mpc_comb = v->maxMpcComb;
2668 if (context->stream_count > 1) {
2669 if (dc->debug.pipe_split_policy == MPC_SPLIT_AVOID_MULT_DISP)
2671 } else if (dc->debug.force_single_disp_pipe_split)
2674 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2675 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2678 * Workaround for avoiding pipe-split in cases where we'd split
2679 * planes that are too small, resulting in splits that aren't
2680 * valid for the scaler.
2682 if (pipe->plane_state &&
2683 (pipe->plane_state->dst_rect.width <= 16 ||
2684 pipe->plane_state->dst_rect.height <= 16 ||
2685 pipe->plane_state->src_rect.width <= 16 ||
2686 pipe->plane_state->src_rect.height <= 16))
2689 /* TODO: fix dc bugs and remove this split threshold thing */
2690 if (pipe->stream && !pipe->prev_odm_pipe &&
2691 (!pipe->top_pipe || pipe->top_pipe->plane_state != pipe->plane_state))
2694 if (plane_count > dc->res_pool->pipe_count / 2)
2697 /* W/A: Mode timing with borders may not work well with pipe split, avoid for this corner case */
2698 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2699 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2700 struct dc_crtc_timing timing;
2705 timing = pipe->stream->timing;
2706 if (timing.h_border_left + timing.h_border_right
2707 + timing.v_border_top + timing.v_border_bottom > 0) {
2714 /* Avoid split loop looks for lowest voltage level that allows most unsplit pipes possible */
2716 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2717 if (!context->res_ctx.pipe_ctx[i].stream)
2720 for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++)
2721 if (v->NoOfDPP[vlevel][0][pipe_idx] == 1 &&
2722 v->ModeSupport[vlevel][0])
2724 /* Impossible to not split this pipe */
2725 if (vlevel > context->bw_ctx.dml.soc.num_states)
2726 vlevel = vlevel_split;
2731 v->maxMpcComb = max_mpc_comb;
2734 /* Split loop sets which pipe should be split based on dml outputs and dc flags */
2735 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2736 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2737 int pipe_plane = v->pipe_plane[pipe_idx];
2738 bool split4mpc = context->stream_count == 1 && plane_count == 1
2739 && dc->config.enable_4to1MPC && dc->res_pool->pipe_count >= 4;
2741 if (!context->res_ctx.pipe_ctx[i].stream)
2744 if (split4mpc || v->NoOfDPP[vlevel][max_mpc_comb][pipe_plane] == 4)
2746 else if (force_split || v->NoOfDPP[vlevel][max_mpc_comb][pipe_plane] == 2)
2749 if ((pipe->stream->view_format ==
2750 VIEW_3D_FORMAT_SIDE_BY_SIDE ||
2751 pipe->stream->view_format ==
2752 VIEW_3D_FORMAT_TOP_AND_BOTTOM) &&
2753 (pipe->stream->timing.timing_3d_format ==
2754 TIMING_3D_FORMAT_TOP_AND_BOTTOM ||
2755 pipe->stream->timing.timing_3d_format ==
2756 TIMING_3D_FORMAT_SIDE_BY_SIDE))
2758 if (dc->debug.force_odm_combine & (1 << pipe->stream_res.tg->inst)) {
2760 v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_2to1;
2762 if (dc->debug.force_odm_combine_4to1 & (1 << pipe->stream_res.tg->inst)) {
2764 v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_4to1;
2766 /*420 format workaround*/
2767 if (pipe->stream->timing.h_addressable > 7680 &&
2768 pipe->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
2771 v->ODMCombineEnabled[pipe_plane] =
2772 v->ODMCombineEnablePerState[vlevel][pipe_plane];
2774 if (v->ODMCombineEnabled[pipe_plane] == dm_odm_combine_mode_disabled) {
2775 if (get_num_mpc_splits(pipe) == 1) {
2776 /*If need split for mpc but 2 way split already*/
2778 split[i] = 2; /* 2 -> 4 MPC */
2779 else if (split[i] == 2)
2780 split[i] = 0; /* 2 -> 2 MPC */
2781 else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state)
2782 merge[i] = true; /* 2 -> 1 MPC */
2783 } else if (get_num_mpc_splits(pipe) == 3) {
2784 /*If need split for mpc but 4 way split already*/
2785 if (split[i] == 2 && ((pipe->top_pipe && !pipe->top_pipe->top_pipe)
2786 || !pipe->bottom_pipe)) {
2787 merge[i] = true; /* 4 -> 2 MPC */
2788 } else if (split[i] == 0 && pipe->top_pipe &&
2789 pipe->top_pipe->plane_state == pipe->plane_state)
2790 merge[i] = true; /* 4 -> 1 MPC */
2792 } else if (get_num_odm_splits(pipe)) {
2793 /* ODM -> MPC transition */
2794 if (pipe->prev_odm_pipe) {
2800 if (get_num_odm_splits(pipe) == 1) {
2801 /*If need split for odm but 2 way split already*/
2803 split[i] = 2; /* 2 -> 4 ODM */
2804 else if (split[i] == 2)
2805 split[i] = 0; /* 2 -> 2 ODM */
2806 else if (pipe->prev_odm_pipe) {
2807 ASSERT(0); /* NOT expected yet */
2808 merge[i] = true; /* exit ODM */
2810 } else if (get_num_odm_splits(pipe) == 3) {
2811 /*If need split for odm but 4 way split already*/
2812 if (split[i] == 2 && ((pipe->prev_odm_pipe && !pipe->prev_odm_pipe->prev_odm_pipe)
2813 || !pipe->next_odm_pipe)) {
2814 ASSERT(0); /* NOT expected yet */
2815 merge[i] = true; /* 4 -> 2 ODM */
2816 } else if (split[i] == 0 && pipe->prev_odm_pipe) {
2817 ASSERT(0); /* NOT expected yet */
2818 merge[i] = true; /* exit ODM */
2821 } else if (get_num_mpc_splits(pipe)) {
2822 /* MPC -> ODM transition */
2823 ASSERT(0); /* NOT expected yet */
2824 if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {
2831 /* Adjust dppclk when split is forced, do not bother with dispclk */
2832 if (split[i] != 0 && v->NoOfDPP[vlevel][max_mpc_comb][pipe_idx] == 1)
2833 v->RequiredDPPCLK[vlevel][max_mpc_comb][pipe_idx] /= 2;
2840 bool dcn20_fast_validate_bw(
2842 struct dc_state *context,
2843 display_e2e_pipe_params_st *pipes,
2845 int *pipe_split_from,
2850 int split[MAX_PIPES] = { 0 };
2851 int pipe_cnt, i, pipe_idx, vlevel;
2857 dcn20_merge_pipes_for_validate(dc, context);
2859 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
2861 *pipe_cnt_out = pipe_cnt;
2868 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
2870 if (vlevel > context->bw_ctx.dml.soc.num_states)
2873 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, NULL);
2875 /*initialize pipe_just_split_from to invalid idx*/
2876 for (i = 0; i < MAX_PIPES; i++)
2877 pipe_split_from[i] = -1;
2879 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
2880 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2881 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
2883 if (!pipe->stream || pipe_split_from[i] >= 0)
2888 if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
2889 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
2890 ASSERT(hsplit_pipe);
2891 if (!dcn20_split_stream_for_odm(
2892 dc, &context->res_ctx,
2895 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
2896 dcn20_build_mapped_resource(dc, context, pipe->stream);
2899 if (!pipe->plane_state)
2901 /* Skip 2nd half of already split pipe */
2902 if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state)
2905 /* We do not support mpo + odm at the moment */
2906 if (hsplit_pipe && hsplit_pipe->plane_state != pipe->plane_state
2907 && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx])
2910 if (split[i] == 2) {
2911 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) {
2912 /* pipe not split previously needs split */
2913 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
2914 ASSERT(hsplit_pipe);
2916 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] *= 2;
2919 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
2920 if (!dcn20_split_stream_for_odm(
2921 dc, &context->res_ctx,
2924 dcn20_build_mapped_resource(dc, context, pipe->stream);
2926 dcn20_split_stream_for_mpc(
2927 &context->res_ctx, dc->res_pool,
2929 resource_build_scaling_params(pipe);
2930 resource_build_scaling_params(hsplit_pipe);
2932 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
2934 } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
2935 /* merge should already have been done */
2939 /* Actual dsc count per stream dsc validation*/
2940 if (!dcn20_validate_dsc(dc, context)) {
2941 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] =
2942 DML_FAIL_DSC_VALIDATION_FAILURE;
2946 *vlevel_out = vlevel;
2958 static void dcn20_calculate_wm(
2959 struct dc *dc, struct dc_state *context,
2960 display_e2e_pipe_params_st *pipes,
2962 int *pipe_split_from,
2966 int pipe_cnt, i, pipe_idx;
2968 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
2969 if (!context->res_ctx.pipe_ctx[i].stream)
2972 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
2973 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
2975 if (pipe_split_from[i] < 0) {
2976 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
2977 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
2978 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
2979 pipes[pipe_cnt].pipe.dest.odm_combine =
2980 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx];
2982 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
2985 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
2986 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
2987 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])
2988 pipes[pipe_cnt].pipe.dest.odm_combine =
2989 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_split_from[i]];
2991 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
2994 if (dc->config.forced_clocks) {
2995 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
2996 pipes[pipe_cnt].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
2998 if (dc->debug.min_disp_clk_khz > pipes[pipe_cnt].clks_cfg.dispclk_mhz * 1000)
2999 pipes[pipe_cnt].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
3000 if (dc->debug.min_dpp_clk_khz > pipes[pipe_cnt].clks_cfg.dppclk_mhz * 1000)
3001 pipes[pipe_cnt].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
3006 if (pipe_cnt != pipe_idx) {
3007 if (dc->res_pool->funcs->populate_dml_pipes)
3008 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
3009 context, pipes, fast_validate);
3011 pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
3012 context, pipes, fast_validate);
3015 *out_pipe_cnt = pipe_cnt;
3017 pipes[0].clks_cfg.voltage = vlevel;
3018 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
3019 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
3021 /* only pipe 0 is read for voltage and dcf/soc clocks */
3023 pipes[0].clks_cfg.voltage = 1;
3024 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].dcfclk_mhz;
3025 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].socclk_mhz;
3027 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3028 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3029 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3030 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3031 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3032 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3033 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3034 context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3037 pipes[0].clks_cfg.voltage = 2;
3038 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
3039 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
3041 context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3042 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3043 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3044 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3045 context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3046 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3047 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3050 pipes[0].clks_cfg.voltage = 3;
3051 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
3052 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
3054 context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3055 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3056 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3057 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3058 context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3059 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3060 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3062 pipes[0].clks_cfg.voltage = vlevel;
3063 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
3064 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
3065 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3066 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3067 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3068 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3069 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3070 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3071 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3074 static bool is_dtbclk_required(struct dc *dc, struct dc_state *context)
3077 for (i = 0; i < dc->res_pool->pipe_count; i++) {
3078 if (!context->res_ctx.pipe_ctx[i].stream)
3084 void dcn20_calculate_dlg_params(
3085 struct dc *dc, struct dc_state *context,
3086 display_e2e_pipe_params_st *pipes,
3093 /* Writeback MCIF_WB arbitration parameters */
3094 dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);
3096 context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000;
3097 context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000;
3098 context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000;
3099 context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16;
3100 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000;
3101 context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000;
3102 context->bw_ctx.bw.dcn.clk.p_state_change_support =
3103 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]
3104 != dm_dram_clock_change_unsupported;
3105 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
3107 context->bw_ctx.bw.dcn.clk.z9_support = (context->bw_ctx.dml.vba.StutterPeriod > 5000.0) ?
3108 DCN_Z9_SUPPORT_ALLOW : DCN_Z9_SUPPORT_DISALLOW;
3111 for (i = 0; i < dc->res_pool->pipe_count; i++) {
3112 if (context->res_ctx.pipe_ctx[i].plane_state)
3116 if (plane_count == 0)
3117 context->bw_ctx.bw.dcn.clk.z9_support = DCN_Z9_SUPPORT_ALLOW;
3119 context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context);
3121 if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz)
3122 context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz;
3124 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
3125 if (!context->res_ctx.pipe_ctx[i].stream)
3127 pipes[pipe_idx].pipe.dest.vstartup_start = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
3128 pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
3129 pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
3130 pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
3131 context->res_ctx.pipe_ctx[i].det_buffer_size_kb = context->bw_ctx.dml.ip.det_buffer_size_kbytes;
3132 context->res_ctx.pipe_ctx[i].unbounded_req = pipes[pipe_idx].pipe.src.unbounded_req_mode;
3134 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
3135 context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
3136 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz =
3137 pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
3138 context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;
3141 /*save a original dppclock copy*/
3142 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;
3143 context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz;
3144 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz * 1000;
3145 context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz * 1000;
3147 context->bw_ctx.bw.dcn.compbuf_size_kb = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes
3148 - context->bw_ctx.dml.ip.det_buffer_size_kbytes * pipe_idx;
3150 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
3151 bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != 2;
3153 if (!context->res_ctx.pipe_ctx[i].stream)
3156 context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg(&context->bw_ctx.dml,
3157 &context->res_ctx.pipe_ctx[i].dlg_regs,
3158 &context->res_ctx.pipe_ctx[i].ttu_regs,
3163 context->bw_ctx.bw.dcn.clk.p_state_change_support,
3164 false, false, true);
3166 context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg(&context->bw_ctx.dml,
3167 &context->res_ctx.pipe_ctx[i].rq_regs,
3168 pipes[pipe_idx].pipe);
3173 static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *context,
3178 BW_VAL_TRACE_SETUP();
3181 int pipe_split_from[MAX_PIPES];
3183 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_ATOMIC);
3184 DC_LOGGER_INIT(dc->ctx->logger);
3186 BW_VAL_TRACE_COUNT();
3188 out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel, fast_validate);
3196 BW_VAL_TRACE_END_VOLTAGE_LEVEL();
3198 if (fast_validate) {
3199 BW_VAL_TRACE_SKIP(fast);
3203 dcn20_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, fast_validate);
3204 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
3206 BW_VAL_TRACE_END_WATERMARKS();
3211 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
3212 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
3214 BW_VAL_TRACE_SKIP(fail);
3220 BW_VAL_TRACE_FINISH();
3226 * This must be noinline to ensure anything that deals with FP registers
3227 * is contained within this call; previously our compiling with hard-float
3228 * would result in fp instructions being emitted outside of the boundaries
3229 * of the DC_FP_START/END macros, which makes sense as the compiler has no
3230 * idea about what is wrapped and what is not
3232 * This is largely just a workaround to avoid breakage introduced with 5.6,
3233 * ideally all fp-using code should be moved into its own file, only that
3234 * should be compiled with hard-float, and all code exported from there
3235 * should be strictly wrapped with DC_FP_START/END
3237 static noinline bool dcn20_validate_bandwidth_fp(struct dc *dc,
3238 struct dc_state *context, bool fast_validate)
3240 bool voltage_supported = false;
3241 bool full_pstate_supported = false;
3242 bool dummy_pstate_supported = false;
3243 double p_state_latency_us;
3245 p_state_latency_us = context->bw_ctx.dml.soc.dram_clock_change_latency_us;
3246 context->bw_ctx.dml.soc.disable_dram_clock_change_vactive_support =
3247 dc->debug.disable_dram_clock_change_vactive_support;
3248 context->bw_ctx.dml.soc.allow_dram_clock_one_display_vactive =
3249 dc->debug.enable_dram_clock_change_one_display_vactive;
3251 /*Unsafe due to current pipe merge and split logic*/
3252 ASSERT(context != dc->current_state);
3254 if (fast_validate) {
3255 return dcn20_validate_bandwidth_internal(dc, context, true);
3258 // Best case, we support full UCLK switch latency
3259 voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
3260 full_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;
3262 if (context->bw_ctx.dml.soc.dummy_pstate_latency_us == 0 ||
3263 (voltage_supported && full_pstate_supported)) {
3264 context->bw_ctx.bw.dcn.clk.p_state_change_support = full_pstate_supported;
3265 goto restore_dml_state;
3268 // Fallback: Try to only support G6 temperature read latency
3269 context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latency_us;
3271 voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
3272 dummy_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;
3274 if (voltage_supported && (dummy_pstate_supported || !(context->stream_count))) {
3275 context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
3276 goto restore_dml_state;
3279 // ERROR: fallback is supposed to always work.
3283 context->bw_ctx.dml.soc.dram_clock_change_latency_us = p_state_latency_us;
3284 return voltage_supported;
3287 bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
3290 bool voltage_supported;
3292 voltage_supported = dcn20_validate_bandwidth_fp(dc, context, fast_validate);
3294 return voltage_supported;
3297 struct pipe_ctx *dcn20_acquire_idle_pipe_for_layer(
3298 struct dc_state *state,
3299 const struct resource_pool *pool,
3300 struct dc_stream_state *stream)
3302 struct resource_context *res_ctx = &state->res_ctx;
3303 struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
3304 struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool, head_pipe);
3312 idle_pipe->stream = head_pipe->stream;
3313 idle_pipe->stream_res.tg = head_pipe->stream_res.tg;
3314 idle_pipe->stream_res.opp = head_pipe->stream_res.opp;
3316 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
3317 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
3318 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
3319 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
3324 bool dcn20_get_dcc_compression_cap(const struct dc *dc,
3325 const struct dc_dcc_surface_param *input,
3326 struct dc_surface_dcc_cap *output)
3328 return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(
3329 dc->res_pool->hubbub,
3334 static void dcn20_destroy_resource_pool(struct resource_pool **pool)
3336 struct dcn20_resource_pool *dcn20_pool = TO_DCN20_RES_POOL(*pool);
3338 dcn20_resource_destruct(dcn20_pool);
3344 static struct dc_cap_funcs cap_funcs = {
3345 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
3349 enum dc_status dcn20_patch_unknown_plane_state(struct dc_plane_state *plane_state)
3351 enum surface_pixel_format surf_pix_format = plane_state->format;
3352 unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format);
3354 enum swizzle_mode_values swizzle = DC_SW_LINEAR;
3357 swizzle = DC_SW_64KB_D;
3359 swizzle = DC_SW_64KB_S;
3361 plane_state->tiling_info.gfx9.swizzle = swizzle;
3365 static const struct resource_funcs dcn20_res_pool_funcs = {
3366 .destroy = dcn20_destroy_resource_pool,
3367 .link_enc_create = dcn20_link_encoder_create,
3368 .panel_cntl_create = dcn20_panel_cntl_create,
3369 .validate_bandwidth = dcn20_validate_bandwidth,
3370 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
3371 .add_stream_to_ctx = dcn20_add_stream_to_ctx,
3372 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
3373 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
3374 .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context,
3375 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
3376 .set_mcif_arb_params = dcn20_set_mcif_arb_params,
3377 .populate_dml_pipes = dcn20_populate_dml_pipes_from_context,
3378 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link
3381 bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
3384 uint32_t pipe_count = pool->res_cap->num_dwb;
3386 for (i = 0; i < pipe_count; i++) {
3387 struct dcn20_dwbc *dwbc20 = kzalloc(sizeof(struct dcn20_dwbc),
3391 dm_error("DC: failed to create dwbc20!\n");
3394 dcn20_dwbc_construct(dwbc20, ctx,
3399 pool->dwbc[i] = &dwbc20->base;
3404 bool dcn20_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
3407 uint32_t pipe_count = pool->res_cap->num_dwb;
3409 ASSERT(pipe_count > 0);
3411 for (i = 0; i < pipe_count; i++) {
3412 struct dcn20_mmhubbub *mcif_wb20 = kzalloc(sizeof(struct dcn20_mmhubbub),
3416 dm_error("DC: failed to create mcif_wb20!\n");
3420 dcn20_mmhubbub_construct(mcif_wb20, ctx,
3426 pool->mcif_wb[i] = &mcif_wb20->base;
3431 static struct pp_smu_funcs *dcn20_pp_smu_create(struct dc_context *ctx)
3433 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_ATOMIC);
3438 dm_pp_get_funcs(ctx, pp_smu);
3440 if (pp_smu->ctx.ver != PP_SMU_VER_NV)
3441 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs));
3446 static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
3448 if (pp_smu && *pp_smu) {
3454 void dcn20_cap_soc_clocks(
3455 struct _vcs_dpi_soc_bounding_box_st *bb,
3456 struct pp_smu_nv_clock_table max_clocks)
3460 // First pass - cap all clocks higher than the reported max
3461 for (i = 0; i < bb->num_states; i++) {
3462 if ((bb->clock_limits[i].dcfclk_mhz > (max_clocks.dcfClockInKhz / 1000))
3463 && max_clocks.dcfClockInKhz != 0)
3464 bb->clock_limits[i].dcfclk_mhz = (max_clocks.dcfClockInKhz / 1000);
3466 if ((bb->clock_limits[i].dram_speed_mts > (max_clocks.uClockInKhz / 1000) * 16)
3467 && max_clocks.uClockInKhz != 0)
3468 bb->clock_limits[i].dram_speed_mts = (max_clocks.uClockInKhz / 1000) * 16;
3470 if ((bb->clock_limits[i].fabricclk_mhz > (max_clocks.fabricClockInKhz / 1000))
3471 && max_clocks.fabricClockInKhz != 0)
3472 bb->clock_limits[i].fabricclk_mhz = (max_clocks.fabricClockInKhz / 1000);
3474 if ((bb->clock_limits[i].dispclk_mhz > (max_clocks.displayClockInKhz / 1000))
3475 && max_clocks.displayClockInKhz != 0)
3476 bb->clock_limits[i].dispclk_mhz = (max_clocks.displayClockInKhz / 1000);
3478 if ((bb->clock_limits[i].dppclk_mhz > (max_clocks.dppClockInKhz / 1000))
3479 && max_clocks.dppClockInKhz != 0)
3480 bb->clock_limits[i].dppclk_mhz = (max_clocks.dppClockInKhz / 1000);
3482 if ((bb->clock_limits[i].phyclk_mhz > (max_clocks.phyClockInKhz / 1000))
3483 && max_clocks.phyClockInKhz != 0)
3484 bb->clock_limits[i].phyclk_mhz = (max_clocks.phyClockInKhz / 1000);
3486 if ((bb->clock_limits[i].socclk_mhz > (max_clocks.socClockInKhz / 1000))
3487 && max_clocks.socClockInKhz != 0)
3488 bb->clock_limits[i].socclk_mhz = (max_clocks.socClockInKhz / 1000);
3490 if ((bb->clock_limits[i].dscclk_mhz > (max_clocks.dscClockInKhz / 1000))
3491 && max_clocks.dscClockInKhz != 0)
3492 bb->clock_limits[i].dscclk_mhz = (max_clocks.dscClockInKhz / 1000);
3495 // Second pass - remove all duplicate clock states
3496 for (i = bb->num_states - 1; i > 1; i--) {
3497 bool duplicate = true;
3499 if (bb->clock_limits[i-1].dcfclk_mhz != bb->clock_limits[i].dcfclk_mhz)
3501 if (bb->clock_limits[i-1].dispclk_mhz != bb->clock_limits[i].dispclk_mhz)
3503 if (bb->clock_limits[i-1].dppclk_mhz != bb->clock_limits[i].dppclk_mhz)
3505 if (bb->clock_limits[i-1].dram_speed_mts != bb->clock_limits[i].dram_speed_mts)
3507 if (bb->clock_limits[i-1].dscclk_mhz != bb->clock_limits[i].dscclk_mhz)
3509 if (bb->clock_limits[i-1].fabricclk_mhz != bb->clock_limits[i].fabricclk_mhz)
3511 if (bb->clock_limits[i-1].phyclk_mhz != bb->clock_limits[i].phyclk_mhz)
3513 if (bb->clock_limits[i-1].socclk_mhz != bb->clock_limits[i].socclk_mhz)
3521 void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb,
3522 struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states)
3524 struct _vcs_dpi_voltage_scaling_st calculated_states[DC__VOLTAGE_STATES];
3526 int num_calculated_states = 0;
3529 if (num_states == 0)
3532 memset(calculated_states, 0, sizeof(calculated_states));
3534 if (dc->bb_overrides.min_dcfclk_mhz > 0)
3535 min_dcfclk = dc->bb_overrides.min_dcfclk_mhz;
3537 if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev))
3540 // Accounting for SOC/DCF relationship, we can go as high as
3545 for (i = 0; i < num_states; i++) {
3546 int min_fclk_required_by_uclk;
3547 calculated_states[i].state = i;
3548 calculated_states[i].dram_speed_mts = uclk_states[i] * 16 / 1000;
3550 // FCLK:UCLK ratio is 1.08
3551 min_fclk_required_by_uclk = div_u64(((unsigned long long)uclk_states[i]) * 1080,
3554 calculated_states[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ?
3555 min_dcfclk : min_fclk_required_by_uclk;
3557 calculated_states[i].socclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->socClockInKhz / 1000) ?
3558 max_clocks->socClockInKhz / 1000 : calculated_states[i].fabricclk_mhz;
3560 calculated_states[i].dcfclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->dcfClockInKhz / 1000) ?
3561 max_clocks->dcfClockInKhz / 1000 : calculated_states[i].fabricclk_mhz;
3563 calculated_states[i].dispclk_mhz = max_clocks->displayClockInKhz / 1000;
3564 calculated_states[i].dppclk_mhz = max_clocks->displayClockInKhz / 1000;
3565 calculated_states[i].dscclk_mhz = max_clocks->displayClockInKhz / (1000 * 3);
3567 calculated_states[i].phyclk_mhz = max_clocks->phyClockInKhz / 1000;
3569 num_calculated_states++;
3572 calculated_states[num_calculated_states - 1].socclk_mhz = max_clocks->socClockInKhz / 1000;
3573 calculated_states[num_calculated_states - 1].fabricclk_mhz = max_clocks->socClockInKhz / 1000;
3574 calculated_states[num_calculated_states - 1].dcfclk_mhz = max_clocks->dcfClockInKhz / 1000;
3576 memcpy(bb->clock_limits, calculated_states, sizeof(bb->clock_limits));
3577 bb->num_states = num_calculated_states;
3579 // Duplicate the last state, DML always an extra state identical to max state to work
3580 memcpy(&bb->clock_limits[num_calculated_states], &bb->clock_limits[num_calculated_states - 1], sizeof(struct _vcs_dpi_voltage_scaling_st));
3581 bb->clock_limits[num_calculated_states].state = bb->num_states;
3584 void dcn20_patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
3586 if ((int)(bb->sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns
3587 && dc->bb_overrides.sr_exit_time_ns) {
3588 bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
3591 if ((int)(bb->sr_enter_plus_exit_time_us * 1000)
3592 != dc->bb_overrides.sr_enter_plus_exit_time_ns
3593 && dc->bb_overrides.sr_enter_plus_exit_time_ns) {
3594 bb->sr_enter_plus_exit_time_us =
3595 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
3598 if ((int)(bb->urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns
3599 && dc->bb_overrides.urgent_latency_ns) {
3600 bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
3603 if ((int)(bb->dram_clock_change_latency_us * 1000)
3604 != dc->bb_overrides.dram_clock_change_latency_ns
3605 && dc->bb_overrides.dram_clock_change_latency_ns) {
3606 bb->dram_clock_change_latency_us =
3607 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
3610 if ((int)(bb->dummy_pstate_latency_us * 1000)
3611 != dc->bb_overrides.dummy_clock_change_latency_ns
3612 && dc->bb_overrides.dummy_clock_change_latency_ns) {
3613 bb->dummy_pstate_latency_us =
3614 dc->bb_overrides.dummy_clock_change_latency_ns / 1000.0;
3618 static struct _vcs_dpi_soc_bounding_box_st *get_asic_rev_soc_bb(
3619 uint32_t hw_internal_rev)
3621 if (ASICREV_IS_NAVI14_M(hw_internal_rev))
3622 return &dcn2_0_nv14_soc;
3624 if (ASICREV_IS_NAVI12_P(hw_internal_rev))
3625 return &dcn2_0_nv12_soc;
3630 static struct _vcs_dpi_ip_params_st *get_asic_rev_ip_params(
3631 uint32_t hw_internal_rev)
3634 if (ASICREV_IS_NAVI14_M(hw_internal_rev))
3635 return &dcn2_0_nv14_ip;
3641 static enum dml_project get_dml_project_version(uint32_t hw_internal_rev)
3643 return DML_PROJECT_NAVI10v2;
3646 #define fixed16_to_double(x) (((double) x) / ((double) (1 << 16)))
3647 #define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x))
3649 static bool init_soc_bounding_box(struct dc *dc,
3650 struct dcn20_resource_pool *pool)
3652 struct _vcs_dpi_soc_bounding_box_st *loaded_bb =
3653 get_asic_rev_soc_bb(dc->ctx->asic_id.hw_internal_rev);
3654 struct _vcs_dpi_ip_params_st *loaded_ip =
3655 get_asic_rev_ip_params(dc->ctx->asic_id.hw_internal_rev);
3657 DC_LOGGER_INIT(dc->ctx->logger);
3659 if (pool->base.pp_smu) {
3660 struct pp_smu_nv_clock_table max_clocks = {0};
3661 unsigned int uclk_states[8] = {0};
3662 unsigned int num_states = 0;
3663 enum pp_smu_status status;
3664 bool clock_limits_available = false;
3665 bool uclk_states_available = false;
3667 if (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) {
3668 status = (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states)
3669 (&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states);
3671 uclk_states_available = (status == PP_SMU_RESULT_OK);
3674 if (pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) {
3675 status = (*pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks)
3676 (&pool->base.pp_smu->nv_funcs.pp_smu, &max_clocks);
3677 /* SMU cannot set DCF clock to anything equal to or higher than SOC clock
3679 if (max_clocks.dcfClockInKhz >= max_clocks.socClockInKhz)
3680 max_clocks.dcfClockInKhz = max_clocks.socClockInKhz - 1000;
3681 clock_limits_available = (status == PP_SMU_RESULT_OK);
3684 if (clock_limits_available && uclk_states_available && num_states)
3685 dcn20_update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states);
3686 else if (clock_limits_available)
3687 dcn20_cap_soc_clocks(loaded_bb, max_clocks);
3690 loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;
3691 loaded_ip->max_num_dpp = pool->base.pipe_count;
3692 dcn20_patch_bounding_box(dc, loaded_bb);
3697 static bool dcn20_resource_construct(
3698 uint8_t num_virtual_links,
3700 struct dcn20_resource_pool *pool)
3703 struct dc_context *ctx = dc->ctx;
3704 struct irq_service_init_data init_data;
3705 struct ddc_service_init_data ddc_init_data = {0};
3706 struct _vcs_dpi_soc_bounding_box_st *loaded_bb =
3707 get_asic_rev_soc_bb(ctx->asic_id.hw_internal_rev);
3708 struct _vcs_dpi_ip_params_st *loaded_ip =
3709 get_asic_rev_ip_params(ctx->asic_id.hw_internal_rev);
3710 enum dml_project dml_project_version =
3711 get_dml_project_version(ctx->asic_id.hw_internal_rev);
3715 ctx->dc_bios->regs = &bios_regs;
3716 pool->base.funcs = &dcn20_res_pool_funcs;
3718 if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) {
3719 pool->base.res_cap = &res_cap_nv14;
3720 pool->base.pipe_count = 5;
3721 pool->base.mpcc_count = 5;
3723 pool->base.res_cap = &res_cap_nv10;
3724 pool->base.pipe_count = 6;
3725 pool->base.mpcc_count = 6;
3727 /*************************************************
3728 * Resource + asic cap harcoding *
3729 *************************************************/
3730 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
3732 dc->caps.max_downscale_ratio = 200;
3733 dc->caps.i2c_speed_in_khz = 100;
3734 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/
3735 dc->caps.max_cursor_size = 256;
3736 dc->caps.min_horizontal_blanking_period = 80;
3737 dc->caps.dmdata_alloc_size = 2048;
3739 dc->caps.max_slave_planes = 1;
3740 dc->caps.max_slave_yuv_planes = 1;
3741 dc->caps.max_slave_rgb_planes = 1;
3742 dc->caps.post_blend_color_processing = true;
3743 dc->caps.force_dp_tps4_for_cp2520 = true;
3744 dc->caps.extended_aux_timeout_support = true;
3746 /* Color pipeline capabilities */
3747 dc->caps.color.dpp.dcn_arch = 1;
3748 dc->caps.color.dpp.input_lut_shared = 0;
3749 dc->caps.color.dpp.icsc = 1;
3750 dc->caps.color.dpp.dgam_ram = 1;
3751 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
3752 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
3753 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;
3754 dc->caps.color.dpp.dgam_rom_caps.pq = 0;
3755 dc->caps.color.dpp.dgam_rom_caps.hlg = 0;
3756 dc->caps.color.dpp.post_csc = 0;
3757 dc->caps.color.dpp.gamma_corr = 0;
3758 dc->caps.color.dpp.dgam_rom_for_yuv = 1;
3760 dc->caps.color.dpp.hw_3d_lut = 1;
3761 dc->caps.color.dpp.ogam_ram = 1;
3762 // no OGAM ROM on DCN2, only MPC ROM
3763 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
3764 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
3765 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
3766 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
3767 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
3768 dc->caps.color.dpp.ocsc = 0;
3770 dc->caps.color.mpc.gamut_remap = 0;
3771 dc->caps.color.mpc.num_3dluts = 0;
3772 dc->caps.color.mpc.shared_3d_lut = 0;
3773 dc->caps.color.mpc.ogam_ram = 1;
3774 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
3775 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
3776 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
3777 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
3778 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
3779 dc->caps.color.mpc.ocsc = 1;
3781 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) {
3782 dc->debug = debug_defaults_drv;
3783 } else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
3784 pool->base.pipe_count = 4;
3785 pool->base.mpcc_count = pool->base.pipe_count;
3786 dc->debug = debug_defaults_diags;
3788 dc->debug = debug_defaults_diags;
3791 dc->work_arounds.dedcn20_305_wa = true;
3793 // Init the vm_helper
3795 vm_helper_init(dc->vm_helper, 16);
3797 /*************************************************
3798 * Create resources *
3799 *************************************************/
3801 pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =
3802 dcn20_clock_source_create(ctx, ctx->dc_bios,
3803 CLOCK_SOURCE_COMBO_PHY_PLL0,
3804 &clk_src_regs[0], false);
3805 pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =
3806 dcn20_clock_source_create(ctx, ctx->dc_bios,
3807 CLOCK_SOURCE_COMBO_PHY_PLL1,
3808 &clk_src_regs[1], false);
3809 pool->base.clock_sources[DCN20_CLK_SRC_PLL2] =
3810 dcn20_clock_source_create(ctx, ctx->dc_bios,
3811 CLOCK_SOURCE_COMBO_PHY_PLL2,
3812 &clk_src_regs[2], false);
3813 pool->base.clock_sources[DCN20_CLK_SRC_PLL3] =
3814 dcn20_clock_source_create(ctx, ctx->dc_bios,
3815 CLOCK_SOURCE_COMBO_PHY_PLL3,
3816 &clk_src_regs[3], false);
3817 pool->base.clock_sources[DCN20_CLK_SRC_PLL4] =
3818 dcn20_clock_source_create(ctx, ctx->dc_bios,
3819 CLOCK_SOURCE_COMBO_PHY_PLL4,
3820 &clk_src_regs[4], false);
3821 pool->base.clock_sources[DCN20_CLK_SRC_PLL5] =
3822 dcn20_clock_source_create(ctx, ctx->dc_bios,
3823 CLOCK_SOURCE_COMBO_PHY_PLL5,
3824 &clk_src_regs[5], false);
3825 pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL;
3826 /* todo: not reuse phy_pll registers */
3827 pool->base.dp_clock_source =
3828 dcn20_clock_source_create(ctx, ctx->dc_bios,
3829 CLOCK_SOURCE_ID_DP_DTO,
3830 &clk_src_regs[0], true);
3832 for (i = 0; i < pool->base.clk_src_count; i++) {
3833 if (pool->base.clock_sources[i] == NULL) {
3834 dm_error("DC: failed to create clock sources!\n");
3835 BREAK_TO_DEBUGGER();
3840 pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
3841 if (pool->base.dccg == NULL) {
3842 dm_error("DC: failed to create dccg!\n");
3843 BREAK_TO_DEBUGGER();
3847 pool->base.dmcu = dcn20_dmcu_create(ctx,
3851 if (pool->base.dmcu == NULL) {
3852 dm_error("DC: failed to create dmcu!\n");
3853 BREAK_TO_DEBUGGER();
3857 pool->base.abm = dce_abm_create(ctx,
3861 if (pool->base.abm == NULL) {
3862 dm_error("DC: failed to create abm!\n");
3863 BREAK_TO_DEBUGGER();
3867 pool->base.pp_smu = dcn20_pp_smu_create(ctx);
3870 if (!init_soc_bounding_box(dc, pool)) {
3871 dm_error("DC: failed to initialize soc bounding box!\n");
3872 BREAK_TO_DEBUGGER();
3876 dml_init_instance(&dc->dml, loaded_bb, loaded_ip, dml_project_version);
3878 if (!dc->debug.disable_pplib_wm_range) {
3879 struct pp_smu_wm_range_sets ranges = {0};
3882 ranges.num_reader_wm_sets = 0;
3884 if (loaded_bb->num_states == 1) {
3885 ranges.reader_wm_sets[0].wm_inst = i;
3886 ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3887 ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3888 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3889 ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3891 ranges.num_reader_wm_sets = 1;
3892 } else if (loaded_bb->num_states > 1) {
3893 for (i = 0; i < 4 && i < loaded_bb->num_states; i++) {
3894 ranges.reader_wm_sets[i].wm_inst = i;
3895 ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3896 ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3897 ranges.reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0;
3898 ranges.reader_wm_sets[i].max_fill_clk_mhz = loaded_bb->clock_limits[i].dram_speed_mts / 16;
3900 ranges.num_reader_wm_sets = i + 1;
3903 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3904 ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3907 ranges.num_writer_wm_sets = 1;
3909 ranges.writer_wm_sets[0].wm_inst = 0;
3910 ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3911 ranges.writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3912 ranges.writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3913 ranges.writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3915 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
3916 if (pool->base.pp_smu->nv_funcs.set_wm_ranges)
3917 pool->base.pp_smu->nv_funcs.set_wm_ranges(&pool->base.pp_smu->nv_funcs.pp_smu, &ranges);
3920 init_data.ctx = dc->ctx;
3921 pool->base.irqs = dal_irq_service_dcn20_create(&init_data);
3922 if (!pool->base.irqs)
3925 /* mem input -> ipp -> dpp -> opp -> TG */
3926 for (i = 0; i < pool->base.pipe_count; i++) {
3927 pool->base.hubps[i] = dcn20_hubp_create(ctx, i);
3928 if (pool->base.hubps[i] == NULL) {
3929 BREAK_TO_DEBUGGER();
3931 "DC: failed to create memory input!\n");
3935 pool->base.ipps[i] = dcn20_ipp_create(ctx, i);
3936 if (pool->base.ipps[i] == NULL) {
3937 BREAK_TO_DEBUGGER();
3939 "DC: failed to create input pixel processor!\n");
3943 pool->base.dpps[i] = dcn20_dpp_create(ctx, i);
3944 if (pool->base.dpps[i] == NULL) {
3945 BREAK_TO_DEBUGGER();
3947 "DC: failed to create dpps!\n");
3951 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
3952 pool->base.engines[i] = dcn20_aux_engine_create(ctx, i);
3953 if (pool->base.engines[i] == NULL) {
3954 BREAK_TO_DEBUGGER();
3956 "DC:failed to create aux engine!!\n");
3959 pool->base.hw_i2cs[i] = dcn20_i2c_hw_create(ctx, i);
3960 if (pool->base.hw_i2cs[i] == NULL) {
3961 BREAK_TO_DEBUGGER();
3963 "DC:failed to create hw i2c!!\n");
3966 pool->base.sw_i2cs[i] = NULL;
3969 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
3970 pool->base.opps[i] = dcn20_opp_create(ctx, i);
3971 if (pool->base.opps[i] == NULL) {
3972 BREAK_TO_DEBUGGER();
3974 "DC: failed to create output pixel processor!\n");
3979 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
3980 pool->base.timing_generators[i] = dcn20_timing_generator_create(
3982 if (pool->base.timing_generators[i] == NULL) {
3983 BREAK_TO_DEBUGGER();
3984 dm_error("DC: failed to create tg!\n");
3989 pool->base.timing_generator_count = i;
3991 pool->base.mpc = dcn20_mpc_create(ctx);
3992 if (pool->base.mpc == NULL) {
3993 BREAK_TO_DEBUGGER();
3994 dm_error("DC: failed to create mpc!\n");
3998 pool->base.hubbub = dcn20_hubbub_create(ctx);
3999 if (pool->base.hubbub == NULL) {
4000 BREAK_TO_DEBUGGER();
4001 dm_error("DC: failed to create hubbub!\n");
4005 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
4006 pool->base.dscs[i] = dcn20_dsc_create(ctx, i);
4007 if (pool->base.dscs[i] == NULL) {
4008 BREAK_TO_DEBUGGER();
4009 dm_error("DC: failed to create display stream compressor %d!\n", i);
4014 if (!dcn20_dwbc_create(ctx, &pool->base)) {
4015 BREAK_TO_DEBUGGER();
4016 dm_error("DC: failed to create dwbc!\n");
4019 if (!dcn20_mmhubbub_create(ctx, &pool->base)) {
4020 BREAK_TO_DEBUGGER();
4021 dm_error("DC: failed to create mcif_wb!\n");
4025 if (!resource_construct(num_virtual_links, dc, &pool->base,
4026 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
4027 &res_create_funcs : &res_create_maximus_funcs)))
4030 dcn20_hw_sequencer_construct(dc);
4032 // IF NV12, set PG function pointer to NULL. It's not that
4033 // PG isn't supported for NV12, it's that we don't want to
4034 // program the registers because that will cause more power
4035 // to be consumed. We could have created dcn20_init_hw to get
4036 // the same effect by checking ASIC rev, but there was a
4037 // request at some point to not check ASIC rev on hw sequencer.
4038 if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) {
4039 dc->hwseq->funcs.enable_power_gating_plane = NULL;
4040 dc->debug.disable_dpp_power_gate = true;
4041 dc->debug.disable_hubp_power_gate = true;
4045 dc->caps.max_planes = pool->base.pipe_count;
4047 for (i = 0; i < dc->caps.max_planes; ++i)
4048 dc->caps.planes[i] = plane_cap;
4050 dc->cap_funcs = cap_funcs;
4052 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
4053 ddc_init_data.ctx = dc->ctx;
4054 ddc_init_data.link = NULL;
4055 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
4056 ddc_init_data.id.enum_id = 0;
4057 ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
4058 pool->base.oem_device = dal_ddc_service_create(&ddc_init_data);
4060 pool->base.oem_device = NULL;
4069 dcn20_resource_destruct(pool);
4074 struct resource_pool *dcn20_create_resource_pool(
4075 const struct dc_init_data *init_data,
4078 struct dcn20_resource_pool *pool =
4079 kzalloc(sizeof(struct dcn20_resource_pool), GFP_ATOMIC);
4084 if (dcn20_resource_construct(init_data->num_virtual_links, dc, pool))
4087 BREAK_TO_DEBUGGER();