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26 #include "reg_helper.h"
27 #include "dcn20_optc.h"
37 #define FN(reg_name, field_name) \
38 optc1->tg_shift->field_name, optc1->tg_mask->field_name
42 * Enable CRTC - call ASIC Control Object to enable Timing generator.
44 bool optc2_enable_crtc(struct timing_generator *optc)
46 /* TODO FPGA wait for answer
47 * OTG_MASTER_UPDATE_MODE != CRTC_MASTER_UPDATE_MODE
48 * OTG_MASTER_UPDATE_LOCK != CRTC_MASTER_UPDATE_LOCK
50 struct optc *optc1 = DCN10TG_FROM_TG(optc);
52 /* opp instance for OTG. For DCN1.0, ODM is remoed.
53 * OPP and OPTC should 1:1 mapping
55 REG_UPDATE(OPTC_DATA_SOURCE_SELECT,
56 OPTC_SEG0_SRC_SEL, optc->inst);
58 /* VTG enable first is for HW workaround */
63 REG_UPDATE_2(OTG_CONTROL,
64 OTG_DISABLE_POINT_CNTL, 3,
71 * DRR double buffering control to select buffer point
72 * for V_TOTAL, H_TOTAL, VTOTAL_MIN, VTOTAL_MAX, VTOTAL_MIN_SEL and VTOTAL_MAX_SEL registers
73 * Options: anytime, start of frame, dp start of frame (range timing)
75 void optc2_set_timing_db_mode(struct timing_generator *optc, bool enable)
77 struct optc *optc1 = DCN10TG_FROM_TG(optc);
79 uint32_t blank_data_double_buffer_enable = enable ? 1 : 0;
81 REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL,
82 OTG_RANGE_TIMING_DBUF_UPDATE_MODE, blank_data_double_buffer_enable);
86 *For the below, I'm not sure how your GSL parameters are stored in your env,
87 * so I will assume a gsl_params struct for now
89 void optc2_set_gsl(struct timing_generator *optc,
90 const struct gsl_params *params)
92 struct optc *optc1 = DCN10TG_FROM_TG(optc);
95 * There are (MAX_OPTC+1)/2 gsl groups available for use.
96 * In each group (assign an OTG to a group by setting OTG_GSLX_EN = 1,
97 * set one of the OTGs to be the master (OTG_GSL_MASTER_EN = 1) and the rest are slaves.
99 REG_UPDATE_5(OTG_GSL_CONTROL,
100 OTG_GSL0_EN, params->gsl0_en,
101 OTG_GSL1_EN, params->gsl1_en,
102 OTG_GSL2_EN, params->gsl2_en,
103 OTG_GSL_MASTER_EN, params->gsl_master_en,
104 OTG_GSL_MASTER_MODE, params->gsl_master_mode);
108 /* Use the gsl allow flip as the master update lock */
109 void optc2_use_gsl_as_master_update_lock(struct timing_generator *optc,
110 const struct gsl_params *params)
112 struct optc *optc1 = DCN10TG_FROM_TG(optc);
114 REG_UPDATE(OTG_GSL_CONTROL,
115 OTG_MASTER_UPDATE_LOCK_GSL_EN, params->master_update_lock_gsl_en);
118 /* You can control the GSL timing by limiting GSL to a window (X,Y) */
119 void optc2_set_gsl_window(struct timing_generator *optc,
120 const struct gsl_params *params)
122 struct optc *optc1 = DCN10TG_FROM_TG(optc);
124 REG_SET_2(OTG_GSL_WINDOW_X, 0,
125 OTG_GSL_WINDOW_START_X, params->gsl_window_start_x,
126 OTG_GSL_WINDOW_END_X, params->gsl_window_end_x);
127 REG_SET_2(OTG_GSL_WINDOW_Y, 0,
128 OTG_GSL_WINDOW_START_Y, params->gsl_window_start_y,
129 OTG_GSL_WINDOW_END_Y, params->gsl_window_end_y);
133 * Vupdate keepout can be set to a window to block the update lock for that pipe from changing.
134 * Start offset begins with vstartup and goes for x number of clocks,
135 * end offset starts from end of vupdate to x number of clocks.
137 void optc2_set_vupdate_keepout(struct timing_generator *optc,
138 const struct vupdate_keepout_params *params)
140 struct optc *optc1 = DCN10TG_FROM_TG(optc);
142 REG_SET_3(OTG_VUPDATE_KEEPOUT, 0,
143 MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, params->start_offset,
144 MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, params->end_offset,
145 OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, params->enable);
148 void optc2_set_gsl_source_select(
149 struct timing_generator *optc,
151 uint32_t gsl_ready_signal)
153 struct optc *optc1 = DCN10TG_FROM_TG(optc);
157 REG_UPDATE(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, gsl_ready_signal);
160 REG_UPDATE(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, gsl_ready_signal);
163 REG_UPDATE(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, gsl_ready_signal);
170 /* DSC encoder frame start controls: x = h position, line_num = # of lines from vstartup */
171 void optc2_set_dsc_encoder_frame_start(struct timing_generator *optc,
175 struct optc *optc1 = DCN10TG_FROM_TG(optc);
177 REG_SET_2(OTG_DSC_START_POSITION, 0,
178 OTG_DSC_START_POSITION_X, x_position,
179 OTG_DSC_START_POSITION_LINE_NUM, line_num);
182 /* Set DSC-related configuration.
183 * dsc_mode: 0 disables DSC, other values enable DSC in specified format
184 * sc_bytes_per_pixel: Bytes per pixel in u3.28 format
185 * dsc_slice_width: Slice width in pixels
187 void optc2_set_dsc_config(struct timing_generator *optc,
188 enum optc_dsc_mode dsc_mode,
189 uint32_t dsc_bytes_per_pixel,
190 uint32_t dsc_slice_width)
192 struct optc *optc1 = DCN10TG_FROM_TG(optc);
194 REG_UPDATE(OPTC_DATA_FORMAT_CONTROL,
195 OPTC_DSC_MODE, dsc_mode);
197 REG_SET(OPTC_BYTES_PER_PIXEL, 0,
198 OPTC_DSC_BYTES_PER_PIXEL, dsc_bytes_per_pixel);
200 REG_UPDATE(OPTC_WIDTH_CONTROL,
201 OPTC_DSC_SLICE_WIDTH, dsc_slice_width);
205 * PTI i think is already done somewhere else for 2ka
206 * (opp?, please double check.
207 * OPTC side only has 1 register to set for PTI_ENABLE)
210 void optc2_set_odm_bypass(struct timing_generator *optc,
211 const struct dc_crtc_timing *dc_crtc_timing)
213 struct optc *optc1 = DCN10TG_FROM_TG(optc);
214 uint32_t h_div_2 = 0;
216 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
217 OPTC_NUM_OF_INPUT_SEGMENT, 0,
218 OPTC_SEG0_SRC_SEL, optc->inst,
219 OPTC_SEG1_SRC_SEL, 0xf);
220 REG_WRITE(OTG_H_TIMING_CNTL, 0);
222 h_div_2 = optc1_is_two_pixels_per_containter(dc_crtc_timing);
223 REG_UPDATE(OTG_H_TIMING_CNTL,
224 OTG_H_TIMING_DIV_BY2, h_div_2);
225 REG_SET(OPTC_MEMORY_CONFIG, 0,
227 optc1->opp_count = 1;
230 void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
231 struct dc_crtc_timing *timing)
233 struct optc *optc1 = DCN10TG_FROM_TG(optc);
234 /* 2 pieces of memory required for up to 5120 displays, 4 for up to 8192 */
235 int mpcc_hactive = (timing->h_addressable + timing->h_border_left + timing->h_border_right)
237 int memory_mask = mpcc_hactive <= 2560 ? 0x3 : 0xf;
238 uint32_t data_fmt = 0;
240 /* TODO: In pseudocode but does not affect maximus, delete comment if we dont need on asic
241 * REG_SET(OTG_GLOBAL_CONTROL2, 0, GLOBAL_UPDATE_LOCK_EN, 1);
242 * Program OTG register MASTER_UPDATE_LOCK_DB_X/Y to the position before DP frame start
243 * REG_SET_2(OTG_GLOBAL_CONTROL1, 0,
244 * MASTER_UPDATE_LOCK_DB_X, 160,
245 * MASTER_UPDATE_LOCK_DB_Y, 240);
247 if (REG(OPTC_MEMORY_CONFIG))
248 REG_SET(OPTC_MEMORY_CONFIG, 0,
249 OPTC_MEM_SEL, memory_mask << (optc->inst * 4));
251 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
253 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
256 REG_UPDATE(OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, data_fmt);
258 ASSERT(opp_cnt == 2);
259 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
260 OPTC_NUM_OF_INPUT_SEGMENT, 1,
261 OPTC_SEG0_SRC_SEL, opp_id[0],
262 OPTC_SEG1_SRC_SEL, opp_id[1]);
264 REG_UPDATE(OPTC_WIDTH_CONTROL,
265 OPTC_SEGMENT_WIDTH, mpcc_hactive);
267 REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_BY2, 1);
268 optc1->opp_count = opp_cnt;
271 void optc2_get_optc_source(struct timing_generator *optc,
272 uint32_t *num_of_src_opp,
273 uint32_t *src_opp_id_0,
274 uint32_t *src_opp_id_1)
276 uint32_t num_of_input_segments;
277 struct optc *optc1 = DCN10TG_FROM_TG(optc);
279 REG_GET_3(OPTC_DATA_SOURCE_SELECT,
280 OPTC_NUM_OF_INPUT_SEGMENT, &num_of_input_segments,
281 OPTC_SEG0_SRC_SEL, src_opp_id_0,
282 OPTC_SEG1_SRC_SEL, src_opp_id_1);
284 if (num_of_input_segments == 1)
289 /* Work around VBIOS not updating OPTC_NUM_OF_INPUT_SEGMENT */
290 if (*src_opp_id_1 == 0xf)
294 void optc2_set_dwb_source(struct timing_generator *optc,
295 uint32_t dwb_pipe_inst)
297 struct optc *optc1 = DCN10TG_FROM_TG(optc);
299 if (dwb_pipe_inst == 0)
300 REG_UPDATE(DWB_SOURCE_SELECT,
301 OPTC_DWB0_SOURCE_SELECT, optc->inst);
302 else if (dwb_pipe_inst == 1)
303 REG_UPDATE(DWB_SOURCE_SELECT,
304 OPTC_DWB1_SOURCE_SELECT, optc->inst);
307 void optc2_triplebuffer_lock(struct timing_generator *optc)
309 struct optc *optc1 = DCN10TG_FROM_TG(optc);
311 REG_SET(OTG_GLOBAL_CONTROL0, 0,
312 OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
314 REG_SET(OTG_VUPDATE_KEEPOUT, 0,
315 OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 1);
317 REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
318 OTG_MASTER_UPDATE_LOCK, 1);
320 if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
321 REG_WAIT(OTG_MASTER_UPDATE_LOCK,
322 UPDATE_LOCK_STATUS, 1,
326 void optc2_triplebuffer_unlock(struct timing_generator *optc)
328 struct optc *optc1 = DCN10TG_FROM_TG(optc);
330 REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
331 OTG_MASTER_UPDATE_LOCK, 0);
333 REG_SET(OTG_VUPDATE_KEEPOUT, 0,
334 OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 0);
338 void optc2_lock_doublebuffer_enable(struct timing_generator *optc)
340 struct optc *optc1 = DCN10TG_FROM_TG(optc);
341 uint32_t v_blank_start = 0;
342 uint32_t h_blank_start = 0;
344 REG_UPDATE(OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_EN, 1);
346 REG_UPDATE_2(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 1,
347 DIG_UPDATE_LOCATION, 20);
349 REG_GET(OTG_V_BLANK_START_END, OTG_V_BLANK_START, &v_blank_start);
351 REG_GET(OTG_H_BLANK_START_END, OTG_H_BLANK_START, &h_blank_start);
353 REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
354 MASTER_UPDATE_LOCK_DB_X,
355 h_blank_start - 200 - 1,
356 MASTER_UPDATE_LOCK_DB_Y,
360 void optc2_lock_doublebuffer_disable(struct timing_generator *optc)
362 struct optc *optc1 = DCN10TG_FROM_TG(optc);
364 REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
365 MASTER_UPDATE_LOCK_DB_X,
367 MASTER_UPDATE_LOCK_DB_Y,
370 REG_UPDATE_2(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 0,
371 DIG_UPDATE_LOCATION, 0);
373 REG_UPDATE(OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_EN, 0);
376 void optc2_setup_manual_trigger(struct timing_generator *optc)
378 struct optc *optc1 = DCN10TG_FROM_TG(optc);
380 REG_SET(OTG_MANUAL_FLOW_CONTROL, 0,
381 MANUAL_FLOW_CONTROL, 1);
383 REG_SET(OTG_GLOBAL_CONTROL2, 0,
384 MANUAL_FLOW_CONTROL_SEL, optc->inst);
386 REG_SET_8(OTG_TRIGA_CNTL, 0,
387 OTG_TRIGA_SOURCE_SELECT, 22,
388 OTG_TRIGA_SOURCE_PIPE_SELECT, optc->inst,
389 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1,
390 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 0,
391 OTG_TRIGA_POLARITY_SELECT, 0,
392 OTG_TRIGA_FREQUENCY_SELECT, 0,
397 void optc2_program_manual_trigger(struct timing_generator *optc)
399 struct optc *optc1 = DCN10TG_FROM_TG(optc);
401 REG_SET(OTG_TRIGA_MANUAL_TRIG, 0,
402 OTG_TRIGA_MANUAL_TRIG, 1);
405 static struct timing_generator_funcs dcn20_tg_funcs = {
406 .validate_timing = optc1_validate_timing,
407 .program_timing = optc1_program_timing,
408 .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
409 .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
410 .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
411 .program_global_sync = optc1_program_global_sync,
412 .enable_crtc = optc2_enable_crtc,
413 .disable_crtc = optc1_disable_crtc,
414 /* used by enable_timing_synchronization. Not need for FPGA */
415 .is_counter_moving = optc1_is_counter_moving,
416 .get_position = optc1_get_position,
417 .get_frame_count = optc1_get_vblank_counter,
418 .get_scanoutpos = optc1_get_crtc_scanoutpos,
419 .get_otg_active_size = optc1_get_otg_active_size,
420 .set_early_control = optc1_set_early_control,
421 /* used by enable_timing_synchronization. Not need for FPGA */
422 .wait_for_state = optc1_wait_for_state,
423 .set_blank = optc1_set_blank,
424 .is_blanked = optc1_is_blanked,
425 .set_blank_color = optc1_program_blank_color,
426 .enable_reset_trigger = optc1_enable_reset_trigger,
427 .enable_crtc_reset = optc1_enable_crtc_reset,
428 .did_triggered_reset_occur = optc1_did_triggered_reset_occur,
429 .triplebuffer_lock = optc2_triplebuffer_lock,
430 .triplebuffer_unlock = optc2_triplebuffer_unlock,
431 .disable_reset_trigger = optc1_disable_reset_trigger,
433 .unlock = optc1_unlock,
434 .lock_doublebuffer_enable = optc2_lock_doublebuffer_enable,
435 .lock_doublebuffer_disable = optc2_lock_doublebuffer_disable,
436 .enable_optc_clock = optc1_enable_optc_clock,
437 .set_drr = optc1_set_drr,
438 .set_static_screen_control = optc1_set_static_screen_control,
439 .program_stereo = optc1_program_stereo,
440 .is_stereo_left_eye = optc1_is_stereo_left_eye,
441 .set_blank_data_double_buffer = optc1_set_blank_data_double_buffer,
442 .tg_init = optc1_tg_init,
443 .is_tg_enabled = optc1_is_tg_enabled,
444 .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
445 .clear_optc_underflow = optc1_clear_optc_underflow,
446 .setup_global_swap_lock = NULL,
447 .get_crc = optc1_get_crc,
448 .configure_crc = optc1_configure_crc,
449 .set_dsc_config = optc2_set_dsc_config,
450 .set_dwb_source = optc2_set_dwb_source,
451 .set_odm_bypass = optc2_set_odm_bypass,
452 .set_odm_combine = optc2_set_odm_combine,
453 .get_optc_source = optc2_get_optc_source,
454 .set_gsl = optc2_set_gsl,
455 .set_gsl_source_select = optc2_set_gsl_source_select,
456 .set_vtg_params = optc1_set_vtg_params,
457 .program_manual_trigger = optc2_program_manual_trigger,
458 .setup_manual_trigger = optc2_setup_manual_trigger,
459 .get_hw_timing = optc1_get_hw_timing,
462 void dcn20_timing_generator_init(struct optc *optc1)
464 optc1->base.funcs = &dcn20_tg_funcs;
466 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
467 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
469 optc1->min_h_blank = 32;
470 optc1->min_v_blank = 3;
471 optc1->min_v_blank_interlace = 5;
472 optc1->min_h_sync_width = 4;// Minimum HSYNC = 8 pixels asked By HW in the first place for no actual reason. Oculus Rift S will not light up with 8 as it's hsyncWidth is 6. Changing it to 4 to fix that issue.
473 optc1->min_v_sync_width = 1;