drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h

   1 /*
   2 * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #ifndef __DC_HWSS_DCN20_H__
  27 #define __DC_HWSS_DCN20_H__
  28
  29 bool dcn20_set_blend_lut(
  30         struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);
  31 bool dcn20_set_shaper_3dlut(
  32         struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);
  33 void dcn20_program_front_end_for_ctx(
  34                 struct dc *dc,
  35                 struct dc_state *context);
  36 void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx);
  37 void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);
  38 bool dcn20_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
  39                         const struct dc_plane_state *plane_state);
  40 bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
  41                         const struct dc_stream_state *stream);
  42 void dcn20_program_output_csc(struct dc *dc,
  43                 struct pipe_ctx *pipe_ctx,
  44                 enum dc_color_space colorspace,
  45                 uint16_t *matrix,
  46                 int opp_id);
  47 void dcn20_enable_stream(struct pipe_ctx *pipe_ctx);
  48 void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx,
  49                 struct dc_link_settings *link_settings);
  50 void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx);
  51 void dcn20_blank_pixel_data(
  52                 struct dc *dc,
  53                 struct pipe_ctx *pipe_ctx,
  54                 bool blank);
  55 void dcn20_pipe_control_lock(
  56         struct dc *dc,
  57         struct pipe_ctx *pipe,
  58         bool lock);
  59 void dcn20_pipe_control_lock_global(
  60                 struct dc *dc,
  61                 struct pipe_ctx *pipe,
  62                 bool lock);
  63 void dcn20_prepare_bandwidth(
  64                 struct dc *dc,
  65                 struct dc_state *context);
  66 void dcn20_optimize_bandwidth(
  67                 struct dc *dc,
  68                 struct dc_state *context);
  69 bool dcn20_update_bandwidth(
  70                 struct dc *dc,
  71                 struct dc_state *context);
  72 void dcn20_reset_hw_ctx_wrap(
  73                 struct dc *dc,
  74                 struct dc_state *context);
  75 enum dc_status dcn20_enable_stream_timing(
  76                 struct pipe_ctx *pipe_ctx,
  77                 struct dc_state *context,
  78                 struct dc *dc);
  79 void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx);
  80 void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx);
  81 void dcn20_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx);
  82 void dcn20_init_blank(
  83                 struct dc *dc,
  84                 struct timing_generator *tg);
  85 void dcn20_disable_vga(
  86         struct dce_hwseq *hws);
  87 void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx);
  88 void dcn20_enable_power_gating_plane(
  89         struct dce_hwseq *hws,
  90         bool enable);
  91 void dcn20_dpp_pg_control(
  92                 struct dce_hwseq *hws,
  93                 unsigned int dpp_inst,
  94                 bool power_on);
  95 void dcn20_hubp_pg_control(
  96                 struct dce_hwseq *hws,
  97                 unsigned int hubp_inst,
  98                 bool power_on);
  99 void dcn20_program_triple_buffer(
 100         const struct dc *dc,
 101         struct pipe_ctx *pipe_ctx,
 102         bool enable_triple_buffer);
 103 void dcn20_enable_writeback(
 104                 struct dc *dc,
 105                 const struct dc_stream_status *stream_status,
 106                 struct dc_writeback_info *wb_info,
 107                 struct dc_state *context);
 108 void dcn20_disable_writeback(
 109                 struct dc *dc,
 110                 unsigned int dwb_pipe_inst);
 111 void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);
 112 bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx);
 113 void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx);
 114 void dcn20_init_vm_ctx(
 115                 struct dce_hwseq *hws,
 116                 struct dc *dc,
 117                 struct dc_virtual_addr_space_config *va_config,
 118                 int vmid);
 119 void dcn20_set_flip_control_gsl(
 120                 struct pipe_ctx *pipe_ctx,
 121                 bool flip_immediate);
 122 void dcn20_dsc_pg_control(
 123                 struct dce_hwseq *hws,
 124                 unsigned int dsc_inst,
 125                 bool power_on);
 126 void dcn20_fpga_init_hw(struct dc *dc);
 127 bool dcn20_wait_for_blank_complete(
 128                 struct output_pixel_processor *opp);
 129 void dcn20_dccg_init(struct dce_hwseq *hws);
 130 int dcn20_init_sys_ctx(struct dce_hwseq *hws,
 131                 struct dc *dc,
 132                 struct dc_phy_addr_space_config *pa_config);
 133
 134 #endif /* __DC_HWSS_DCN20_H__ */
 135