drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 #include <linux/delay.h>
  26
  27 #include "dm_services.h"
  28 #include "basics/dc_common.h"
  29 #include "dm_helpers.h"
  30 #include "core_types.h"
  31 #include "resource.h"
  32 #include "dcn20_resource.h"
  33 #include "dcn20_hwseq.h"
  34 #include "dce/dce_hwseq.h"
  35 #include "dcn20_dsc.h"
  36 #include "dcn20_optc.h"
  37 #include "abm.h"
  38 #include "clk_mgr.h"
  39 #include "dmcu.h"
  40 #include "hubp.h"
  41 #include "timing_generator.h"
  42 #include "opp.h"
  43 #include "ipp.h"
  44 #include "mpc.h"
  45 #include "mcif_wb.h"
  46 #include "dchubbub.h"
  47 #include "reg_helper.h"
  48 #include "dcn10/dcn10_cm_common.h"
  49 #include "dc_link_dp.h"
  50 #include "vm_helper.h"
  51 #include "dccg.h"
  52 #include "dc_dmub_srv.h"
  53 #include "dce/dmub_hw_lock_mgr.h"
  54
  55 #define DC_LOGGER_INIT(logger)
  56
  57 #define CTX \
  58         hws->ctx
  59 #define REG(reg)\
  60         hws->regs->reg
  61
  62 #undef FN
  63 #define FN(reg_name, field_name) \
  64         hws->shifts->field_name, hws->masks->field_name
  65
  66 static int find_free_gsl_group(const struct dc *dc)
  67 {
  68         if (dc->res_pool->gsl_groups.gsl_0 == 0)
  69                 return 1;
  70         if (dc->res_pool->gsl_groups.gsl_1 == 0)
  71                 return 2;
  72         if (dc->res_pool->gsl_groups.gsl_2 == 0)
  73                 return 3;
  74
  75         return 0;
  76 }
  77
  78 /* NOTE: This is not a generic setup_gsl function (hence the suffix as_lock)
  79  * This is only used to lock pipes in pipe splitting case with immediate flip
  80  * Ordinary MPC/OTG locks suppress VUPDATE which doesn't help with immediate,
  81  * so we get tearing with freesync since we cannot flip multiple pipes
  82  * atomically.
  83  * We use GSL for this:
  84  * - immediate flip: find first available GSL group if not already assigned
  85  *                   program gsl with that group, set current OTG as master
  86  *                   and always us 0x4 = AND of flip_ready from all pipes
  87  * - vsync flip: disable GSL if used
  88  *
  89  * Groups in stream_res are stored as +1 from HW registers, i.e.
  90  * gsl_0 <=> pipe_ctx->stream_res.gsl_group == 1
  91  * Using a magic value like -1 would require tracking all inits/resets
  92  */
  93 static void dcn20_setup_gsl_group_as_lock(
  94                 const struct dc *dc,
  95                 struct pipe_ctx *pipe_ctx,
  96                 bool enable)
  97 {
  98         struct gsl_params gsl;
  99         int group_idx;
 100
 101         memset(&gsl, 0, sizeof(struct gsl_params));
 102
 103         if (enable) {
 104                 /* return if group already assigned since GSL was set up
 105                  * for vsync flip, we would unassign so it can't be "left over"
 106                  */
 107                 if (pipe_ctx->stream_res.gsl_group > 0)
 108                         return;
 109
 110                 group_idx = find_free_gsl_group(dc);
 111                 ASSERT(group_idx != 0);
 112                 pipe_ctx->stream_res.gsl_group = group_idx;
 113
 114                 /* set gsl group reg field and mark resource used */
 115                 switch (group_idx) {
 116                 case 1:
 117                         gsl.gsl0_en = 1;
 118                         dc->res_pool->gsl_groups.gsl_0 = 1;
 119                         break;
 120                 case 2:
 121                         gsl.gsl1_en = 1;
 122                         dc->res_pool->gsl_groups.gsl_1 = 1;
 123                         break;
 124                 case 3:
 125                         gsl.gsl2_en = 1;
 126                         dc->res_pool->gsl_groups.gsl_2 = 1;
 127                         break;
 128                 default:
 129                         BREAK_TO_DEBUGGER();
 130                         return; // invalid case
 131                 }
 132                 gsl.gsl_master_en = 1;
 133         } else {
 134                 group_idx = pipe_ctx->stream_res.gsl_group;
 135                 if (group_idx == 0)
 136                         return; // if not in use, just return
 137
 138                 pipe_ctx->stream_res.gsl_group = 0;
 139
 140                 /* unset gsl group reg field and mark resource free */
 141                 switch (group_idx) {
 142                 case 1:
 143                         gsl.gsl0_en = 0;
 144                         dc->res_pool->gsl_groups.gsl_0 = 0;
 145                         break;
 146                 case 2:
 147                         gsl.gsl1_en = 0;
 148                         dc->res_pool->gsl_groups.gsl_1 = 0;
 149                         break;
 150                 case 3:
 151                         gsl.gsl2_en = 0;
 152                         dc->res_pool->gsl_groups.gsl_2 = 0;
 153                         break;
 154                 default:
 155                         BREAK_TO_DEBUGGER();
 156                         return;
 157                 }
 158                 gsl.gsl_master_en = 0;
 159         }
 160
 161         /* at this point we want to program whether it's to enable or disable */
 162         if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL &&
 163                 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) {
 164                 pipe_ctx->stream_res.tg->funcs->set_gsl(
 165                         pipe_ctx->stream_res.tg,
 166                         &gsl);
 167
 168                 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select(
 169                         pipe_ctx->stream_res.tg, group_idx,     enable ? 4 : 0);
 170         } else
 171                 BREAK_TO_DEBUGGER();
 172 }
 173
 174 void dcn20_set_flip_control_gsl(
 175                 struct pipe_ctx *pipe_ctx,
 176                 bool flip_immediate)
 177 {
 178         if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl)
 179                 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl(
 180                                 pipe_ctx->plane_res.hubp, flip_immediate);
 181
 182 }
 183
 184 void dcn20_enable_power_gating_plane(
 185         struct dce_hwseq *hws,
 186         bool enable)
 187 {
 188         bool force_on = true; /* disable power gating */
 189
 190         if (enable)
 191                 force_on = false;
 192
 193         /* DCHUBP0/1/2/3/4/5 */
 194         REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on);
 195         REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on);
 196         REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on);
 197         REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on);
 198         if (REG(DOMAIN8_PG_CONFIG))
 199                 REG_UPDATE(DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on);
 200         if (REG(DOMAIN10_PG_CONFIG))
 201                 REG_UPDATE(DOMAIN10_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on);
 202
 203         /* DPP0/1/2/3/4/5 */
 204         REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on);
 205         REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on);
 206         REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on);
 207         REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);
 208         if (REG(DOMAIN9_PG_CONFIG))
 209                 REG_UPDATE(DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on);
 210         if (REG(DOMAIN11_PG_CONFIG))
 211                 REG_UPDATE(DOMAIN11_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on);
 212
 213         /* DCS0/1/2/3/4/5 */
 214         REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, force_on);
 215         REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, force_on);
 216         REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, force_on);
 217         if (REG(DOMAIN19_PG_CONFIG))
 218                 REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, force_on);
 219         if (REG(DOMAIN20_PG_CONFIG))
 220                 REG_UPDATE(DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, force_on);
 221         if (REG(DOMAIN21_PG_CONFIG))
 222                 REG_UPDATE(DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, force_on);
 223 }
 224
 225 void dcn20_dccg_init(struct dce_hwseq *hws)
 226 {
 227         /*
 228          * set MICROSECOND_TIME_BASE_DIV
 229          * 100Mhz refclk -> 0x120264
 230          * 27Mhz refclk -> 0x12021b
 231          * 48Mhz refclk -> 0x120230
 232          *
 233          */
 234         REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x120264);
 235
 236         /*
 237          * set MILLISECOND_TIME_BASE_DIV
 238          * 100Mhz refclk -> 0x1186a0
 239          * 27Mhz refclk -> 0x106978
 240          * 48Mhz refclk -> 0x10bb80
 241          *
 242          */
 243         REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x1186a0);
 244
 245         /* This value is dependent on the hardware pipeline delay so set once per SOC */
 246         REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0x801003c);
 247 }
 248
 249 void dcn20_disable_vga(
 250         struct dce_hwseq *hws)
 251 {
 252         REG_WRITE(D1VGA_CONTROL, 0);
 253         REG_WRITE(D2VGA_CONTROL, 0);
 254         REG_WRITE(D3VGA_CONTROL, 0);
 255         REG_WRITE(D4VGA_CONTROL, 0);
 256         REG_WRITE(D5VGA_CONTROL, 0);
 257         REG_WRITE(D6VGA_CONTROL, 0);
 258 }
 259
 260 void dcn20_program_triple_buffer(
 261         const struct dc *dc,
 262         struct pipe_ctx *pipe_ctx,
 263         bool enable_triple_buffer)
 264 {
 265         if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) {
 266                 pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer(
 267                         pipe_ctx->plane_res.hubp,
 268                         enable_triple_buffer);
 269         }
 270 }
 271
 272 /* Blank pixel data during initialization */
 273 void dcn20_init_blank(
 274                 struct dc *dc,
 275                 struct timing_generator *tg)
 276 {
 277         struct dce_hwseq *hws = dc->hwseq;
 278         enum dc_color_space color_space;
 279         struct tg_color black_color = {0};
 280         struct output_pixel_processor *opp = NULL;
 281         struct output_pixel_processor *bottom_opp = NULL;
 282         uint32_t num_opps, opp_id_src0, opp_id_src1;
 283         uint32_t otg_active_width, otg_active_height;
 284
 285         /* program opp dpg blank color */
 286         color_space = COLOR_SPACE_SRGB;
 287         color_space_to_black_color(dc, color_space, &black_color);
 288
 289         /* get the OTG active size */
 290         tg->funcs->get_otg_active_size(tg,
 291                         &otg_active_width,
 292                         &otg_active_height);
 293
 294         /* get the OPTC source */
 295         tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1);
 296
 297         if (opp_id_src0 >= dc->res_pool->res_cap->num_opp) {
 298                 ASSERT(false);
 299                 return;
 300         }
 301         opp = dc->res_pool->opps[opp_id_src0];
 302
 303         if (num_opps == 2) {
 304                 otg_active_width = otg_active_width / 2;
 305
 306                 if (opp_id_src1 >= dc->res_pool->res_cap->num_opp) {
 307                         ASSERT(false);
 308                         return;
 309                 }
 310                 bottom_opp = dc->res_pool->opps[opp_id_src1];
 311         }
 312
 313         opp->funcs->opp_set_disp_pattern_generator(
 314                         opp,
 315                         CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,
 316                         CONTROLLER_DP_COLOR_SPACE_UDEFINED,
 317                         COLOR_DEPTH_UNDEFINED,
 318                         &black_color,
 319                         otg_active_width,
 320                         otg_active_height,
 321                         0);
 322
 323         if (num_opps == 2) {
 324                 bottom_opp->funcs->opp_set_disp_pattern_generator(
 325                                 bottom_opp,
 326                                 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,
 327                                 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
 328                                 COLOR_DEPTH_UNDEFINED,
 329                                 &black_color,
 330                                 otg_active_width,
 331                                 otg_active_height,
 332                                 0);
 333         }
 334
 335         hws->funcs.wait_for_blank_complete(opp);
 336 }
 337
 338 void dcn20_dsc_pg_control(
 339                 struct dce_hwseq *hws,
 340                 unsigned int dsc_inst,
 341                 bool power_on)
 342 {
 343         uint32_t power_gate = power_on ? 0 : 1;
 344         uint32_t pwr_status = power_on ? 0 : 2;
 345         uint32_t org_ip_request_cntl = 0;
 346
 347         if (hws->ctx->dc->debug.disable_dsc_power_gate)
 348                 return;
 349
 350         if (REG(DOMAIN16_PG_CONFIG) == 0)
 351                 return;
 352
 353         REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
 354         if (org_ip_request_cntl == 0)
 355                 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
 356
 357         switch (dsc_inst) {
 358         case 0: /* DSC0 */
 359                 REG_UPDATE(DOMAIN16_PG_CONFIG,
 360                                 DOMAIN16_POWER_GATE, power_gate);
 361
 362                 REG_WAIT(DOMAIN16_PG_STATUS,
 363                                 DOMAIN16_PGFSM_PWR_STATUS, pwr_status,
 364                                 1, 1000);
 365                 break;
 366         case 1: /* DSC1 */
 367                 REG_UPDATE(DOMAIN17_PG_CONFIG,
 368                                 DOMAIN17_POWER_GATE, power_gate);
 369
 370                 REG_WAIT(DOMAIN17_PG_STATUS,
 371                                 DOMAIN17_PGFSM_PWR_STATUS, pwr_status,
 372                                 1, 1000);
 373                 break;
 374         case 2: /* DSC2 */
 375                 REG_UPDATE(DOMAIN18_PG_CONFIG,
 376                                 DOMAIN18_POWER_GATE, power_gate);
 377
 378                 REG_WAIT(DOMAIN18_PG_STATUS,
 379                                 DOMAIN18_PGFSM_PWR_STATUS, pwr_status,
 380                                 1, 1000);
 381                 break;
 382         case 3: /* DSC3 */
 383                 REG_UPDATE(DOMAIN19_PG_CONFIG,
 384                                 DOMAIN19_POWER_GATE, power_gate);
 385
 386                 REG_WAIT(DOMAIN19_PG_STATUS,
 387                                 DOMAIN19_PGFSM_PWR_STATUS, pwr_status,
 388                                 1, 1000);
 389                 break;
 390         case 4: /* DSC4 */
 391                 REG_UPDATE(DOMAIN20_PG_CONFIG,
 392                                 DOMAIN20_POWER_GATE, power_gate);
 393
 394                 REG_WAIT(DOMAIN20_PG_STATUS,
 395                                 DOMAIN20_PGFSM_PWR_STATUS, pwr_status,
 396                                 1, 1000);
 397                 break;
 398         case 5: /* DSC5 */
 399                 REG_UPDATE(DOMAIN21_PG_CONFIG,
 400                                 DOMAIN21_POWER_GATE, power_gate);
 401
 402                 REG_WAIT(DOMAIN21_PG_STATUS,
 403                                 DOMAIN21_PGFSM_PWR_STATUS, pwr_status,
 404                                 1, 1000);
 405                 break;
 406         default:
 407                 BREAK_TO_DEBUGGER();
 408                 break;
 409         }
 410
 411         if (org_ip_request_cntl == 0)
 412                 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
 413 }
 414
 415 void dcn20_dpp_pg_control(
 416                 struct dce_hwseq *hws,
 417                 unsigned int dpp_inst,
 418                 bool power_on)
 419 {
 420         uint32_t power_gate = power_on ? 0 : 1;
 421         uint32_t pwr_status = power_on ? 0 : 2;
 422
 423         if (hws->ctx->dc->debug.disable_dpp_power_gate)
 424                 return;
 425         if (REG(DOMAIN1_PG_CONFIG) == 0)
 426                 return;
 427
 428         switch (dpp_inst) {
 429         case 0: /* DPP0 */
 430                 REG_UPDATE(DOMAIN1_PG_CONFIG,
 431                                 DOMAIN1_POWER_GATE, power_gate);
 432
 433                 REG_WAIT(DOMAIN1_PG_STATUS,
 434                                 DOMAIN1_PGFSM_PWR_STATUS, pwr_status,
 435                                 1, 1000);
 436                 break;
 437         case 1: /* DPP1 */
 438                 REG_UPDATE(DOMAIN3_PG_CONFIG,
 439                                 DOMAIN3_POWER_GATE, power_gate);
 440
 441                 REG_WAIT(DOMAIN3_PG_STATUS,
 442                                 DOMAIN3_PGFSM_PWR_STATUS, pwr_status,
 443                                 1, 1000);
 444                 break;
 445         case 2: /* DPP2 */
 446                 REG_UPDATE(DOMAIN5_PG_CONFIG,
 447                                 DOMAIN5_POWER_GATE, power_gate);
 448
 449                 REG_WAIT(DOMAIN5_PG_STATUS,
 450                                 DOMAIN5_PGFSM_PWR_STATUS, pwr_status,
 451                                 1, 1000);
 452                 break;
 453         case 3: /* DPP3 */
 454                 REG_UPDATE(DOMAIN7_PG_CONFIG,
 455                                 DOMAIN7_POWER_GATE, power_gate);
 456
 457                 REG_WAIT(DOMAIN7_PG_STATUS,
 458                                 DOMAIN7_PGFSM_PWR_STATUS, pwr_status,
 459                                 1, 1000);
 460                 break;
 461         case 4: /* DPP4 */
 462                 REG_UPDATE(DOMAIN9_PG_CONFIG,
 463                                 DOMAIN9_POWER_GATE, power_gate);
 464
 465                 REG_WAIT(DOMAIN9_PG_STATUS,
 466                                 DOMAIN9_PGFSM_PWR_STATUS, pwr_status,
 467                                 1, 1000);
 468                 break;
 469         case 5: /* DPP5 */
 470                 /*
 471                  * Do not power gate DPP5, should be left at HW default, power on permanently.
 472                  * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard
 473                  * reset.
 474                  * REG_UPDATE(DOMAIN11_PG_CONFIG,
 475                  *              DOMAIN11_POWER_GATE, power_gate);
 476                  *
 477                  * REG_WAIT(DOMAIN11_PG_STATUS,
 478                  *              DOMAIN11_PGFSM_PWR_STATUS, pwr_status,
 479                  *              1, 1000);
 480                  */
 481                 break;
 482         default:
 483                 BREAK_TO_DEBUGGER();
 484                 break;
 485         }
 486 }
 487
 488
 489 void dcn20_hubp_pg_control(
 490                 struct dce_hwseq *hws,
 491                 unsigned int hubp_inst,
 492                 bool power_on)
 493 {
 494         uint32_t power_gate = power_on ? 0 : 1;
 495         uint32_t pwr_status = power_on ? 0 : 2;
 496
 497         if (hws->ctx->dc->debug.disable_hubp_power_gate)
 498                 return;
 499         if (REG(DOMAIN0_PG_CONFIG) == 0)
 500                 return;
 501
 502         switch (hubp_inst) {
 503         case 0: /* DCHUBP0 */
 504                 REG_UPDATE(DOMAIN0_PG_CONFIG,
 505                                 DOMAIN0_POWER_GATE, power_gate);
 506
 507                 REG_WAIT(DOMAIN0_PG_STATUS,
 508                                 DOMAIN0_PGFSM_PWR_STATUS, pwr_status,
 509                                 1, 1000);
 510                 break;
 511         case 1: /* DCHUBP1 */
 512                 REG_UPDATE(DOMAIN2_PG_CONFIG,
 513                                 DOMAIN2_POWER_GATE, power_gate);
 514
 515                 REG_WAIT(DOMAIN2_PG_STATUS,
 516                                 DOMAIN2_PGFSM_PWR_STATUS, pwr_status,
 517                                 1, 1000);
 518                 break;
 519         case 2: /* DCHUBP2 */
 520                 REG_UPDATE(DOMAIN4_PG_CONFIG,
 521                                 DOMAIN4_POWER_GATE, power_gate);
 522
 523                 REG_WAIT(DOMAIN4_PG_STATUS,
 524                                 DOMAIN4_PGFSM_PWR_STATUS, pwr_status,
 525                                 1, 1000);
 526                 break;
 527         case 3: /* DCHUBP3 */
 528                 REG_UPDATE(DOMAIN6_PG_CONFIG,
 529                                 DOMAIN6_POWER_GATE, power_gate);
 530
 531                 REG_WAIT(DOMAIN6_PG_STATUS,
 532                                 DOMAIN6_PGFSM_PWR_STATUS, pwr_status,
 533                                 1, 1000);
 534                 break;
 535         case 4: /* DCHUBP4 */
 536                 REG_UPDATE(DOMAIN8_PG_CONFIG,
 537                                 DOMAIN8_POWER_GATE, power_gate);
 538
 539                 REG_WAIT(DOMAIN8_PG_STATUS,
 540                                 DOMAIN8_PGFSM_PWR_STATUS, pwr_status,
 541                                 1, 1000);
 542                 break;
 543         case 5: /* DCHUBP5 */
 544                 /*
 545                  * Do not power gate DCHUB5, should be left at HW default, power on permanently.
 546                  * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard
 547                  * reset.
 548                  * REG_UPDATE(DOMAIN10_PG_CONFIG,
 549                  *              DOMAIN10_POWER_GATE, power_gate);
 550                  *
 551                  * REG_WAIT(DOMAIN10_PG_STATUS,
 552                  *              DOMAIN10_PGFSM_PWR_STATUS, pwr_status,
 553                  *              1, 1000);
 554                  */
 555                 break;
 556         default:
 557                 BREAK_TO_DEBUGGER();
 558                 break;
 559         }
 560 }
 561
 562
 563 /* disable HW used by plane.
 564  * note:  cannot disable until disconnect is complete
 565  */
 566 void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
 567 {
 568         struct dce_hwseq *hws = dc->hwseq;
 569         struct hubp *hubp = pipe_ctx->plane_res.hubp;
 570         struct dpp *dpp = pipe_ctx->plane_res.dpp;
 571
 572         dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);
 573
 574         /* In flip immediate with pipe splitting case GSL is used for
 575          * synchronization so we must disable it when the plane is disabled.
 576          */
 577         if (pipe_ctx->stream_res.gsl_group != 0)
 578                 dcn20_setup_gsl_group_as_lock(dc, pipe_ctx, false);
 579
 580         dc->hwss.set_flip_control_gsl(pipe_ctx, false);
 581
 582         hubp->funcs->hubp_clk_cntl(hubp, false);
 583
 584         dpp->funcs->dpp_dppclk_control(dpp, false, false);
 585
 586         hubp->power_gated = true;
 587
 588         hws->funcs.plane_atomic_power_down(dc,
 589                         pipe_ctx->plane_res.dpp,
 590                         pipe_ctx->plane_res.hubp);
 591
 592         pipe_ctx->stream = NULL;
 593         memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res));
 594         memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res));
 595         pipe_ctx->top_pipe = NULL;
 596         pipe_ctx->bottom_pipe = NULL;
 597         pipe_ctx->plane_state = NULL;
 598 }
 599
 600
 601 void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
 602 {
 603         DC_LOGGER_INIT(dc->ctx->logger);
 604
 605         if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)
 606                 return;
 607
 608         dcn20_plane_atomic_disable(dc, pipe_ctx);
 609
 610         DC_LOG_DC("Power down front end %d\n",
 611                                         pipe_ctx->pipe_idx);
 612 }
 613
 614 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 615 static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream,
 616                 int opp_cnt)
 617 {
 618         bool hblank_halved = optc2_is_two_pixels_per_containter(&stream->timing);
 619         int flow_ctrl_cnt;
 620
 621         if (opp_cnt >= 2)
 622                 hblank_halved = true;
 623
 624         flow_ctrl_cnt = stream->timing.h_total - stream->timing.h_addressable -
 625                         stream->timing.h_border_left -
 626                         stream->timing.h_border_right;
 627
 628         if (hblank_halved)
 629                 flow_ctrl_cnt /= 2;
 630
 631         /* ODM combine 4:1 case */
 632         if (opp_cnt == 4)
 633                 flow_ctrl_cnt /= 2;
 634
 635         return flow_ctrl_cnt;
 636 }
 637 #endif
 638
 639 enum dc_status dcn20_enable_stream_timing(
 640                 struct pipe_ctx *pipe_ctx,
 641                 struct dc_state *context,
 642                 struct dc *dc)
 643 {
 644         struct dce_hwseq *hws = dc->hwseq;
 645         struct dc_stream_state *stream = pipe_ctx->stream;
 646         struct drr_params params = {0};
 647         unsigned int event_triggers = 0;
 648         struct pipe_ctx *odm_pipe;
 649         int opp_cnt = 1;
 650         int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst };
 651
 652 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 653         bool interlace = stream->timing.flags.INTERLACE;
 654         int i;
 655
 656         struct mpc_dwb_flow_control flow_control;
 657         struct mpc *mpc = dc->res_pool->mpc;
 658         bool rate_control_2x_pclk = (interlace || optc2_is_two_pixels_per_containter(&stream->timing));
 659
 660 #endif
 661         /* by upper caller loop, pipe0 is parent pipe and be called first.
 662          * back end is set up by for pipe0. Other children pipe share back end
 663          * with pipe 0. No program is needed.
 664          */
 665         if (pipe_ctx->top_pipe != NULL)
 666                 return DC_OK;
 667
 668         /* TODO check if timing_changed, disable stream if timing changed */
 669
 670         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
 671                 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;
 672                 opp_cnt++;
 673         }
 674
 675         if (opp_cnt > 1)
 676                 pipe_ctx->stream_res.tg->funcs->set_odm_combine(
 677                                 pipe_ctx->stream_res.tg,
 678                                 opp_inst, opp_cnt,
 679                                 &pipe_ctx->stream->timing);
 680
 681         /* HW program guide assume display already disable
 682          * by unplug sequence. OTG assume stop.
 683          */
 684         pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true);
 685
 686         if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
 687                         pipe_ctx->clock_source,
 688                         &pipe_ctx->stream_res.pix_clk_params,
 689                         &pipe_ctx->pll_settings)) {
 690                 BREAK_TO_DEBUGGER();
 691                 return DC_ERROR_UNEXPECTED;
 692         }
 693
 694         if (dc->hwseq->funcs.PLAT_58856_wa && (!dc_is_dp_signal(stream->signal)))
 695                 dc->hwseq->funcs.PLAT_58856_wa(context, pipe_ctx);
 696
 697         pipe_ctx->stream_res.tg->funcs->program_timing(
 698                         pipe_ctx->stream_res.tg,
 699                         &stream->timing,
 700                         pipe_ctx->pipe_dlg_param.vready_offset,
 701                         pipe_ctx->pipe_dlg_param.vstartup_start,
 702                         pipe_ctx->pipe_dlg_param.vupdate_offset,
 703                         pipe_ctx->pipe_dlg_param.vupdate_width,
 704                         pipe_ctx->stream->signal,
 705                         true);
 706
 707 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 708         rate_control_2x_pclk = rate_control_2x_pclk || opp_cnt > 1;
 709         flow_control.flow_ctrl_mode = 0;
 710         flow_control.flow_ctrl_cnt0 = 0x80;
 711         flow_control.flow_ctrl_cnt1 = calc_mpc_flow_ctrl_cnt(stream, opp_cnt);
 712         if (mpc->funcs->set_out_rate_control) {
 713                 for (i = 0; i < opp_cnt; ++i) {
 714                         mpc->funcs->set_out_rate_control(
 715                                         mpc, opp_inst[i],
 716                                         true,
 717                                         rate_control_2x_pclk,
 718                                         &flow_control);
 719                 }
 720         }
 721 #endif
 722         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
 723                 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control(
 724                                 odm_pipe->stream_res.opp,
 725                                 true);
 726
 727         pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
 728                         pipe_ctx->stream_res.opp,
 729                         true);
 730
 731         hws->funcs.blank_pixel_data(dc, pipe_ctx, true);
 732
 733         /* VTG is  within DCHUB command block. DCFCLK is always on */
 734         if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {
 735                 BREAK_TO_DEBUGGER();
 736                 return DC_ERROR_UNEXPECTED;
 737         }
 738
 739         hws->funcs.wait_for_blank_complete(pipe_ctx->stream_res.opp);
 740
 741         params.vertical_total_min = stream->adjust.v_total_min;
 742         params.vertical_total_max = stream->adjust.v_total_max;
 743         params.vertical_total_mid = stream->adjust.v_total_mid;
 744         params.vertical_total_mid_frame_num = stream->adjust.v_total_mid_frame_num;
 745         if (pipe_ctx->stream_res.tg->funcs->set_drr)
 746                 pipe_ctx->stream_res.tg->funcs->set_drr(
 747                         pipe_ctx->stream_res.tg, &params);
 748
 749         // DRR should set trigger event to monitor surface update event
 750         if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0)
 751                 event_triggers = 0x80;
 752         /* Event triggers and num frames initialized for DRR, but can be
 753          * later updated for PSR use. Note DRR trigger events are generated
 754          * regardless of whether num frames met.
 755          */
 756         if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)
 757                 pipe_ctx->stream_res.tg->funcs->set_static_screen_control(
 758                                 pipe_ctx->stream_res.tg, event_triggers, 2);
 759
 760         /* TODO program crtc source select for non-virtual signal*/
 761         /* TODO program FMT */
 762         /* TODO setup link_enc */
 763         /* TODO set stream attributes */
 764         /* TODO program audio */
 765         /* TODO enable stream if timing changed */
 766         /* TODO unblank stream if DP */
 767
 768         return DC_OK;
 769 }
 770
 771 void dcn20_program_output_csc(struct dc *dc,
 772                 struct pipe_ctx *pipe_ctx,
 773                 enum dc_color_space colorspace,
 774                 uint16_t *matrix,
 775                 int opp_id)
 776 {
 777         struct mpc *mpc = dc->res_pool->mpc;
 778         enum mpc_output_csc_mode ocsc_mode = MPC_OUTPUT_CSC_COEF_A;
 779         int mpcc_id = pipe_ctx->plane_res.hubp->inst;
 780
 781         if (mpc->funcs->power_on_mpc_mem_pwr)
 782                 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true);
 783
 784         if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
 785                 if (mpc->funcs->set_output_csc != NULL)
 786                         mpc->funcs->set_output_csc(mpc,
 787                                         opp_id,
 788                                         matrix,
 789                                         ocsc_mode);
 790         } else {
 791                 if (mpc->funcs->set_ocsc_default != NULL)
 792                         mpc->funcs->set_ocsc_default(mpc,
 793                                         opp_id,
 794                                         colorspace,
 795                                         ocsc_mode);
 796         }
 797 }
 798
 799 bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
 800                                 const struct dc_stream_state *stream)
 801 {
 802         int mpcc_id = pipe_ctx->plane_res.hubp->inst;
 803         struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
 804         struct pwl_params *params = NULL;
 805         /*
 806          * program OGAM only for the top pipe
 807          * if there is a pipe split then fix diagnostic is required:
 808          * how to pass OGAM parameter for stream.
 809          * if programming for all pipes is required then remove condition
 810          * pipe_ctx->top_pipe == NULL ,but then fix the diagnostic.
 811          */
 812         if (mpc->funcs->power_on_mpc_mem_pwr)
 813                 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true);
 814         if (pipe_ctx->top_pipe == NULL
 815                         && mpc->funcs->set_output_gamma && stream->out_transfer_func) {
 816                 if (stream->out_transfer_func->type == TF_TYPE_HWPWL)
 817                         params = &stream->out_transfer_func->pwl;
 818                 else if (pipe_ctx->stream->out_transfer_func->type ==
 819                         TF_TYPE_DISTRIBUTED_POINTS &&
 820                         cm_helper_translate_curve_to_hw_format(
 821                         stream->out_transfer_func,
 822                         &mpc->blender_params, false))
 823                         params = &mpc->blender_params;
 824                 /*
 825                  * there is no ROM
 826                  */
 827                 if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED)
 828                         BREAK_TO_DEBUGGER();
 829         }
 830         /*
 831          * if above if is not executed then 'params' equal to 0 and set in bypass
 832          */
 833         mpc->funcs->set_output_gamma(mpc, mpcc_id, params);
 834
 835         return true;
 836 }
 837
 838 bool dcn20_set_blend_lut(
 839         struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
 840 {
 841         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
 842         bool result = true;
 843         struct pwl_params *blend_lut = NULL;
 844
 845         if (plane_state->blend_tf) {
 846                 if (plane_state->blend_tf->type == TF_TYPE_HWPWL)
 847                         blend_lut = &plane_state->blend_tf->pwl;
 848                 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) {
 849                         cm_helper_translate_curve_to_hw_format(
 850                                         plane_state->blend_tf,
 851                                         &dpp_base->regamma_params, false);
 852                         blend_lut = &dpp_base->regamma_params;
 853                 }
 854         }
 855         result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut);
 856
 857         return result;
 858 }
 859
 860 bool dcn20_set_shaper_3dlut(
 861         struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
 862 {
 863         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
 864         bool result = true;
 865         struct pwl_params *shaper_lut = NULL;
 866
 867         if (plane_state->in_shaper_func) {
 868                 if (plane_state->in_shaper_func->type == TF_TYPE_HWPWL)
 869                         shaper_lut = &plane_state->in_shaper_func->pwl;
 870                 else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) {
 871                         cm_helper_translate_curve_to_hw_format(
 872                                         plane_state->in_shaper_func,
 873                                         &dpp_base->shaper_params, true);
 874                         shaper_lut = &dpp_base->shaper_params;
 875                 }
 876         }
 877
 878         result = dpp_base->funcs->dpp_program_shaper_lut(dpp_base, shaper_lut);
 879         if (plane_state->lut3d_func &&
 880                 plane_state->lut3d_func->state.bits.initialized == 1)
 881                 result = dpp_base->funcs->dpp_program_3dlut(dpp_base,
 882                                                                 &plane_state->lut3d_func->lut_3d);
 883         else
 884                 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, NULL);
 885
 886         return result;
 887 }
 888
 889 bool dcn20_set_input_transfer_func(struct dc *dc,
 890                                 struct pipe_ctx *pipe_ctx,
 891                                 const struct dc_plane_state *plane_state)
 892 {
 893         struct dce_hwseq *hws = dc->hwseq;
 894         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
 895         const struct dc_transfer_func *tf = NULL;
 896         bool result = true;
 897         bool use_degamma_ram = false;
 898
 899         if (dpp_base == NULL || plane_state == NULL)
 900                 return false;
 901
 902         hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state);
 903         hws->funcs.set_blend_lut(pipe_ctx, plane_state);
 904
 905         if (plane_state->in_transfer_func)
 906                 tf = plane_state->in_transfer_func;
 907
 908
 909         if (tf == NULL) {
 910                 dpp_base->funcs->dpp_set_degamma(dpp_base,
 911                                 IPP_DEGAMMA_MODE_BYPASS);
 912                 return true;
 913         }
 914
 915         if (tf->type == TF_TYPE_HWPWL || tf->type == TF_TYPE_DISTRIBUTED_POINTS)
 916                 use_degamma_ram = true;
 917
 918         if (use_degamma_ram == true) {
 919                 if (tf->type == TF_TYPE_HWPWL)
 920                         dpp_base->funcs->dpp_program_degamma_pwl(dpp_base,
 921                                         &tf->pwl);
 922                 else if (tf->type == TF_TYPE_DISTRIBUTED_POINTS) {
 923                         cm_helper_translate_curve_to_degamma_hw_format(tf,
 924                                         &dpp_base->degamma_params);
 925                         dpp_base->funcs->dpp_program_degamma_pwl(dpp_base,
 926                                 &dpp_base->degamma_params);
 927                 }
 928                 return true;
 929         }
 930         /* handle here the optimized cases when de-gamma ROM could be used.
 931          *
 932          */
 933         if (tf->type == TF_TYPE_PREDEFINED) {
 934                 switch (tf->tf) {
 935                 case TRANSFER_FUNCTION_SRGB:
 936                         dpp_base->funcs->dpp_set_degamma(dpp_base,
 937                                         IPP_DEGAMMA_MODE_HW_sRGB);
 938                         break;
 939                 case TRANSFER_FUNCTION_BT709:
 940                         dpp_base->funcs->dpp_set_degamma(dpp_base,
 941                                         IPP_DEGAMMA_MODE_HW_xvYCC);
 942                         break;
 943                 case TRANSFER_FUNCTION_LINEAR:
 944                         dpp_base->funcs->dpp_set_degamma(dpp_base,
 945                                         IPP_DEGAMMA_MODE_BYPASS);
 946                         break;
 947                 case TRANSFER_FUNCTION_PQ:
 948                         dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_USER_PWL);
 949                         cm_helper_translate_curve_to_degamma_hw_format(tf, &dpp_base->degamma_params);
 950                         dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, &dpp_base->degamma_params);
 951                         result = true;
 952                         break;
 953                 default:
 954                         result = false;
 955                         break;
 956                 }
 957         } else if (tf->type == TF_TYPE_BYPASS)
 958                 dpp_base->funcs->dpp_set_degamma(dpp_base,
 959                                 IPP_DEGAMMA_MODE_BYPASS);
 960         else {
 961                 /*
 962                  * if we are here, we did not handle correctly.
 963                  * fix is required for this use case
 964                  */
 965                 BREAK_TO_DEBUGGER();
 966                 dpp_base->funcs->dpp_set_degamma(dpp_base,
 967                                 IPP_DEGAMMA_MODE_BYPASS);
 968         }
 969
 970         return result;
 971 }
 972
 973 void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)
 974 {
 975         struct pipe_ctx *odm_pipe;
 976         int opp_cnt = 1;
 977         int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst };
 978
 979         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
 980                 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;
 981                 opp_cnt++;
 982         }
 983
 984         if (opp_cnt > 1)
 985                 pipe_ctx->stream_res.tg->funcs->set_odm_combine(
 986                                 pipe_ctx->stream_res.tg,
 987                                 opp_inst, opp_cnt,
 988                                 &pipe_ctx->stream->timing);
 989         else
 990                 pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
 991                                 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
 992 }
 993
 994 void dcn20_blank_pixel_data(
 995                 struct dc *dc,
 996                 struct pipe_ctx *pipe_ctx,
 997                 bool blank)
 998 {
 999         struct tg_color black_color = {0};
1000         struct stream_resource *stream_res = &pipe_ctx->stream_res;
1001         struct dc_stream_state *stream = pipe_ctx->stream;
1002         enum dc_color_space color_space = stream->output_color_space;
1003         enum controller_dp_test_pattern test_pattern = CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR;
1004         enum controller_dp_color_space test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED;
1005         struct pipe_ctx *odm_pipe;
1006         int odm_cnt = 1;
1007
1008         int width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;
1009         int height = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top;
1010
1011         if (stream->link->test_pattern_enabled)
1012                 return;
1013
1014         /* get opp dpg blank color */
1015         color_space_to_black_color(dc, color_space, &black_color);
1016
1017         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
1018                 odm_cnt++;
1019
1020         width = width / odm_cnt;
1021
1022         if (blank) {
1023                 dc->hwss.set_abm_immediate_disable(pipe_ctx);
1024
1025                 if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) {
1026                         test_pattern = CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
1027                         test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_RGB;
1028                 }
1029         } else {
1030                 test_pattern = CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
1031         }
1032
1033         stream_res->opp->funcs->opp_set_disp_pattern_generator(
1034                         stream_res->opp,
1035                         test_pattern,
1036                         test_pattern_color_space,
1037                         stream->timing.display_color_depth,
1038                         &black_color,
1039                         width,
1040                         height,
1041                         0);
1042
1043         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
1044                 odm_pipe->stream_res.opp->funcs->opp_set_disp_pattern_generator(
1045                                 odm_pipe->stream_res.opp,
1046                                 dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE && blank ?
1047                                                 CONTROLLER_DP_TEST_PATTERN_COLORRAMP : test_pattern,
1048                                 test_pattern_color_space,
1049                                 stream->timing.display_color_depth,
1050                                 &black_color,
1051                                 width,
1052                                 height,
1053                                 0);
1054         }
1055
1056         if (!blank)
1057                 if (stream_res->abm) {
1058                         dc->hwss.set_pipe(pipe_ctx);
1059                         stream_res->abm->funcs->set_abm_level(stream_res->abm, stream->abm_level);
1060                 }
1061 }
1062
1063
1064 static void dcn20_power_on_plane(
1065         struct dce_hwseq *hws,
1066         struct pipe_ctx *pipe_ctx)
1067 {
1068         DC_LOGGER_INIT(hws->ctx->logger);
1069         if (REG(DC_IP_REQUEST_CNTL)) {
1070                 REG_SET(DC_IP_REQUEST_CNTL, 0,
1071                                 IP_REQUEST_EN, 1);
1072                 dcn20_dpp_pg_control(hws, pipe_ctx->plane_res.dpp->inst, true);
1073                 dcn20_hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, true);
1074                 REG_SET(DC_IP_REQUEST_CNTL, 0,
1075                                 IP_REQUEST_EN, 0);
1076                 DC_LOG_DEBUG(
1077                                 "Un-gated front end for pipe %d\n", pipe_ctx->plane_res.hubp->inst);
1078         }
1079 }
1080
1081 void dcn20_enable_plane(
1082         struct dc *dc,
1083         struct pipe_ctx *pipe_ctx,
1084         struct dc_state *context)
1085 {
1086         //if (dc->debug.sanity_checks) {
1087         //      dcn10_verify_allow_pstate_change_high(dc);
1088         //}
1089         dcn20_power_on_plane(dc->hwseq, pipe_ctx);
1090
1091         /* enable DCFCLK current DCHUB */
1092         pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);
1093
1094         /* initialize HUBP on power up */
1095         pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp);
1096
1097         /* make sure OPP_PIPE_CLOCK_EN = 1 */
1098         pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
1099                         pipe_ctx->stream_res.opp,
1100                         true);
1101
1102 /* TODO: enable/disable in dm as per update type.
1103         if (plane_state) {
1104                 DC_LOG_DC(dc->ctx->logger,
1105                                 "Pipe:%d 0x%x: addr hi:0x%x, "
1106                                 "addr low:0x%x, "
1107                                 "src: %d, %d, %d,"
1108                                 " %d; dst: %d, %d, %d, %d;\n",
1109                                 pipe_ctx->pipe_idx,
1110                                 plane_state,
1111                                 plane_state->address.grph.addr.high_part,
1112                                 plane_state->address.grph.addr.low_part,
1113                                 plane_state->src_rect.x,
1114                                 plane_state->src_rect.y,
1115                                 plane_state->src_rect.width,
1116                                 plane_state->src_rect.height,
1117                                 plane_state->dst_rect.x,
1118                                 plane_state->dst_rect.y,
1119                                 plane_state->dst_rect.width,
1120                                 plane_state->dst_rect.height);
1121
1122                 DC_LOG_DC(dc->ctx->logger,
1123                                 "Pipe %d: width, height, x, y         format:%d\n"
1124                                 "viewport:%d, %d, %d, %d\n"
1125                                 "recout:  %d, %d, %d, %d\n",
1126                                 pipe_ctx->pipe_idx,
1127                                 plane_state->format,
1128                                 pipe_ctx->plane_res.scl_data.viewport.width,
1129                                 pipe_ctx->plane_res.scl_data.viewport.height,
1130                                 pipe_ctx->plane_res.scl_data.viewport.x,
1131                                 pipe_ctx->plane_res.scl_data.viewport.y,
1132                                 pipe_ctx->plane_res.scl_data.recout.width,
1133                                 pipe_ctx->plane_res.scl_data.recout.height,
1134                                 pipe_ctx->plane_res.scl_data.recout.x,
1135                                 pipe_ctx->plane_res.scl_data.recout.y);
1136                 print_rq_dlg_ttu(dc, pipe_ctx);
1137         }
1138 */
1139         if (dc->vm_pa_config.valid) {
1140                 struct vm_system_aperture_param apt;
1141
1142                 apt.sys_default.quad_part = 0;
1143
1144                 apt.sys_low.quad_part = dc->vm_pa_config.system_aperture.start_addr;
1145                 apt.sys_high.quad_part = dc->vm_pa_config.system_aperture.end_addr;
1146
1147                 // Program system aperture settings
1148                 pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt);
1149         }
1150
1151 //      if (dc->debug.sanity_checks) {
1152 //              dcn10_verify_allow_pstate_change_high(dc);
1153 //      }
1154 }
1155
1156 void dcn20_pipe_control_lock(
1157         struct dc *dc,
1158         struct pipe_ctx *pipe,
1159         bool lock)
1160 {
1161         bool flip_immediate = false;
1162
1163         /* use TG master update lock to lock everything on the TG
1164          * therefore only top pipe need to lock
1165          */
1166         if (!pipe || pipe->top_pipe)
1167                 return;
1168
1169         if (pipe->plane_state != NULL)
1170                 flip_immediate = pipe->plane_state->flip_immediate;
1171
1172         if (flip_immediate && lock) {
1173                 const int TIMEOUT_FOR_FLIP_PENDING = 100000;
1174                 int i;
1175
1176                 for (i = 0; i < TIMEOUT_FOR_FLIP_PENDING; ++i) {
1177                         if (!pipe->plane_res.hubp->funcs->hubp_is_flip_pending(pipe->plane_res.hubp))
1178                                 break;
1179                         udelay(1);
1180                 }
1181
1182                 if (pipe->bottom_pipe != NULL) {
1183                         for (i = 0; i < TIMEOUT_FOR_FLIP_PENDING; ++i) {
1184                                 if (!pipe->bottom_pipe->plane_res.hubp->funcs->hubp_is_flip_pending(pipe->bottom_pipe->plane_res.hubp))
1185                                         break;
1186                                 udelay(1);
1187                         }
1188                 }
1189         }
1190
1191         /* In flip immediate and pipe splitting case, we need to use GSL
1192          * for synchronization. Only do setup on locking and on flip type change.
1193          */
1194         if (lock && pipe->bottom_pipe != NULL)
1195                 if ((flip_immediate && pipe->stream_res.gsl_group == 0) ||
1196                     (!flip_immediate && pipe->stream_res.gsl_group > 0))
1197                         dcn20_setup_gsl_group_as_lock(dc, pipe, flip_immediate);
1198
1199         if (pipe->stream && should_use_dmub_lock(pipe->stream->link)) {
1200                 union dmub_hw_lock_flags hw_locks = { 0 };
1201                 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
1202
1203                 hw_locks.bits.lock_pipe = 1;
1204                 inst_flags.otg_inst =  pipe->stream_res.tg->inst;
1205
1206                 if (pipe->plane_state != NULL)
1207                         hw_locks.bits.triple_buffer_lock = pipe->plane_state->triplebuffer_flips;
1208
1209                 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
1210                                         lock,
1211                                         &hw_locks,
1212                                         &inst_flags);
1213         } else if (pipe->plane_state != NULL && pipe->plane_state->triplebuffer_flips) {
1214                 if (lock)
1215                         pipe->stream_res.tg->funcs->triplebuffer_lock(pipe->stream_res.tg);
1216                 else
1217                         pipe->stream_res.tg->funcs->triplebuffer_unlock(pipe->stream_res.tg);
1218         } else {
1219                 if (lock)
1220                         pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);
1221                 else
1222                         pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);
1223         }
1224 }
1225
1226 static void dcn20_detect_pipe_changes(struct pipe_ctx *old_pipe, struct pipe_ctx *new_pipe)
1227 {
1228         new_pipe->update_flags.raw = 0;
1229
1230         /* Exit on unchanged, unused pipe */
1231         if (!old_pipe->plane_state && !new_pipe->plane_state)
1232                 return;
1233         /* Detect pipe enable/disable */
1234         if (!old_pipe->plane_state && new_pipe->plane_state) {
1235                 new_pipe->update_flags.bits.enable = 1;
1236                 new_pipe->update_flags.bits.mpcc = 1;
1237                 new_pipe->update_flags.bits.dppclk = 1;
1238                 new_pipe->update_flags.bits.hubp_interdependent = 1;
1239                 new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1;
1240                 new_pipe->update_flags.bits.gamut_remap = 1;
1241                 new_pipe->update_flags.bits.scaler = 1;
1242                 new_pipe->update_flags.bits.viewport = 1;
1243                 if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) {
1244                         new_pipe->update_flags.bits.odm = 1;
1245                         new_pipe->update_flags.bits.global_sync = 1;
1246                 }
1247                 return;
1248         }
1249         if (old_pipe->plane_state && !new_pipe->plane_state) {
1250                 new_pipe->update_flags.bits.disable = 1;
1251                 return;
1252         }
1253
1254         /* Detect top pipe only changes */
1255         if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) {
1256                 /* Detect odm changes */
1257                 if ((old_pipe->next_odm_pipe && new_pipe->next_odm_pipe
1258                         && old_pipe->next_odm_pipe->pipe_idx != new_pipe->next_odm_pipe->pipe_idx)
1259                                 || (!old_pipe->next_odm_pipe && new_pipe->next_odm_pipe)
1260                                 || (old_pipe->next_odm_pipe && !new_pipe->next_odm_pipe)
1261                                 || old_pipe->stream_res.opp != new_pipe->stream_res.opp)
1262                         new_pipe->update_flags.bits.odm = 1;
1263
1264                 /* Detect global sync changes */
1265                 if (old_pipe->pipe_dlg_param.vready_offset != new_pipe->pipe_dlg_param.vready_offset
1266                                 || old_pipe->pipe_dlg_param.vstartup_start != new_pipe->pipe_dlg_param.vstartup_start
1267                                 || old_pipe->pipe_dlg_param.vupdate_offset != new_pipe->pipe_dlg_param.vupdate_offset
1268                                 || old_pipe->pipe_dlg_param.vupdate_width != new_pipe->pipe_dlg_param.vupdate_width)
1269                         new_pipe->update_flags.bits.global_sync = 1;
1270         }
1271
1272         /*
1273          * Detect opp / tg change, only set on change, not on enable
1274          * Assume mpcc inst = pipe index, if not this code needs to be updated
1275          * since mpcc is what is affected by these. In fact all of our sequence
1276          * makes this assumption at the moment with how hubp reset is matched to
1277          * same index mpcc reset.
1278          */
1279         if (old_pipe->stream_res.opp != new_pipe->stream_res.opp)
1280                 new_pipe->update_flags.bits.opp_changed = 1;
1281         if (old_pipe->stream_res.tg != new_pipe->stream_res.tg)
1282                 new_pipe->update_flags.bits.tg_changed = 1;
1283
1284         /*
1285          * Detect mpcc blending changes, only dpp inst and opp matter here,
1286          * mpccs getting removed/inserted update connected ones during their own
1287          * programming
1288          */
1289         if (old_pipe->plane_res.dpp != new_pipe->plane_res.dpp
1290                         || old_pipe->stream_res.opp != new_pipe->stream_res.opp)
1291                 new_pipe->update_flags.bits.mpcc = 1;
1292
1293         /* Detect dppclk change */
1294         if (old_pipe->plane_res.bw.dppclk_khz != new_pipe->plane_res.bw.dppclk_khz)
1295                 new_pipe->update_flags.bits.dppclk = 1;
1296
1297         /* Check for scl update */
1298         if (memcmp(&old_pipe->plane_res.scl_data, &new_pipe->plane_res.scl_data, sizeof(struct scaler_data)))
1299                         new_pipe->update_flags.bits.scaler = 1;
1300         /* Check for vp update */
1301         if (memcmp(&old_pipe->plane_res.scl_data.viewport, &new_pipe->plane_res.scl_data.viewport, sizeof(struct rect))
1302                         || memcmp(&old_pipe->plane_res.scl_data.viewport_c,
1303                                 &new_pipe->plane_res.scl_data.viewport_c, sizeof(struct rect)))
1304                 new_pipe->update_flags.bits.viewport = 1;
1305
1306         /* Detect dlg/ttu/rq updates */
1307         {
1308                 struct _vcs_dpi_display_dlg_regs_st old_dlg_attr = old_pipe->dlg_regs;
1309                 struct _vcs_dpi_display_ttu_regs_st old_ttu_attr = old_pipe->ttu_regs;
1310                 struct _vcs_dpi_display_dlg_regs_st *new_dlg_attr = &new_pipe->dlg_regs;
1311                 struct _vcs_dpi_display_ttu_regs_st *new_ttu_attr = &new_pipe->ttu_regs;
1312
1313                 /* Detect pipe interdependent updates */
1314                 if (old_dlg_attr.dst_y_prefetch != new_dlg_attr->dst_y_prefetch ||
1315                                 old_dlg_attr.vratio_prefetch != new_dlg_attr->vratio_prefetch ||
1316                                 old_dlg_attr.vratio_prefetch_c != new_dlg_attr->vratio_prefetch_c ||
1317                                 old_dlg_attr.dst_y_per_vm_vblank != new_dlg_attr->dst_y_per_vm_vblank ||
1318                                 old_dlg_attr.dst_y_per_row_vblank != new_dlg_attr->dst_y_per_row_vblank ||
1319                                 old_dlg_attr.dst_y_per_vm_flip != new_dlg_attr->dst_y_per_vm_flip ||
1320                                 old_dlg_attr.dst_y_per_row_flip != new_dlg_attr->dst_y_per_row_flip ||
1321                                 old_dlg_attr.refcyc_per_meta_chunk_vblank_l != new_dlg_attr->refcyc_per_meta_chunk_vblank_l ||
1322                                 old_dlg_attr.refcyc_per_meta_chunk_vblank_c != new_dlg_attr->refcyc_per_meta_chunk_vblank_c ||
1323                                 old_dlg_attr.refcyc_per_meta_chunk_flip_l != new_dlg_attr->refcyc_per_meta_chunk_flip_l ||
1324                                 old_dlg_attr.refcyc_per_line_delivery_pre_l != new_dlg_attr->refcyc_per_line_delivery_pre_l ||
1325                                 old_dlg_attr.refcyc_per_line_delivery_pre_c != new_dlg_attr->refcyc_per_line_delivery_pre_c ||
1326                                 old_ttu_attr.refcyc_per_req_delivery_pre_l != new_ttu_attr->refcyc_per_req_delivery_pre_l ||
1327                                 old_ttu_attr.refcyc_per_req_delivery_pre_c != new_ttu_attr->refcyc_per_req_delivery_pre_c ||
1328                                 old_ttu_attr.refcyc_per_req_delivery_pre_cur0 != new_ttu_attr->refcyc_per_req_delivery_pre_cur0 ||
1329                                 old_ttu_attr.refcyc_per_req_delivery_pre_cur1 != new_ttu_attr->refcyc_per_req_delivery_pre_cur1 ||
1330                                 old_ttu_attr.min_ttu_vblank != new_ttu_attr->min_ttu_vblank ||
1331                                 old_ttu_attr.qos_level_flip != new_ttu_attr->qos_level_flip) {
1332                         old_dlg_attr.dst_y_prefetch = new_dlg_attr->dst_y_prefetch;
1333                         old_dlg_attr.vratio_prefetch = new_dlg_attr->vratio_prefetch;
1334                         old_dlg_attr.vratio_prefetch_c = new_dlg_attr->vratio_prefetch_c;
1335                         old_dlg_attr.dst_y_per_vm_vblank = new_dlg_attr->dst_y_per_vm_vblank;
1336                         old_dlg_attr.dst_y_per_row_vblank = new_dlg_attr->dst_y_per_row_vblank;
1337                         old_dlg_attr.dst_y_per_vm_flip = new_dlg_attr->dst_y_per_vm_flip;
1338                         old_dlg_attr.dst_y_per_row_flip = new_dlg_attr->dst_y_per_row_flip;
1339                         old_dlg_attr.refcyc_per_meta_chunk_vblank_l = new_dlg_attr->refcyc_per_meta_chunk_vblank_l;
1340                         old_dlg_attr.refcyc_per_meta_chunk_vblank_c = new_dlg_attr->refcyc_per_meta_chunk_vblank_c;
1341                         old_dlg_attr.refcyc_per_meta_chunk_flip_l = new_dlg_attr->refcyc_per_meta_chunk_flip_l;
1342                         old_dlg_attr.refcyc_per_line_delivery_pre_l = new_dlg_attr->refcyc_per_line_delivery_pre_l;
1343                         old_dlg_attr.refcyc_per_line_delivery_pre_c = new_dlg_attr->refcyc_per_line_delivery_pre_c;
1344                         old_ttu_attr.refcyc_per_req_delivery_pre_l = new_ttu_attr->refcyc_per_req_delivery_pre_l;
1345                         old_ttu_attr.refcyc_per_req_delivery_pre_c = new_ttu_attr->refcyc_per_req_delivery_pre_c;
1346                         old_ttu_attr.refcyc_per_req_delivery_pre_cur0 = new_ttu_attr->refcyc_per_req_delivery_pre_cur0;
1347                         old_ttu_attr.refcyc_per_req_delivery_pre_cur1 = new_ttu_attr->refcyc_per_req_delivery_pre_cur1;
1348                         old_ttu_attr.min_ttu_vblank = new_ttu_attr->min_ttu_vblank;
1349                         old_ttu_attr.qos_level_flip = new_ttu_attr->qos_level_flip;
1350                         new_pipe->update_flags.bits.hubp_interdependent = 1;
1351                 }
1352                 /* Detect any other updates to ttu/rq/dlg */
1353                 if (memcmp(&old_dlg_attr, &new_pipe->dlg_regs, sizeof(old_dlg_attr)) ||
1354                                 memcmp(&old_ttu_attr, &new_pipe->ttu_regs, sizeof(old_ttu_attr)) ||
1355                                 memcmp(&old_pipe->rq_regs, &new_pipe->rq_regs, sizeof(old_pipe->rq_regs)))
1356                         new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1;
1357         }
1358 }
1359
1360 static void dcn20_update_dchubp_dpp(
1361         struct dc *dc,
1362         struct pipe_ctx *pipe_ctx,
1363         struct dc_state *context)
1364 {
1365         struct dce_hwseq *hws = dc->hwseq;
1366         struct hubp *hubp = pipe_ctx->plane_res.hubp;
1367         struct dpp *dpp = pipe_ctx->plane_res.dpp;
1368         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1369         bool viewport_changed = false;
1370
1371         if (pipe_ctx->update_flags.bits.dppclk)
1372                 dpp->funcs->dpp_dppclk_control(dpp, false, true);
1373
1374         /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG
1375          * VTG is within DCHUBBUB which is commond block share by each pipe HUBP.
1376          * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG
1377          */
1378         if (pipe_ctx->update_flags.bits.hubp_rq_dlg_ttu) {
1379                 hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst);
1380
1381                 hubp->funcs->hubp_setup(
1382                         hubp,
1383                         &pipe_ctx->dlg_regs,
1384                         &pipe_ctx->ttu_regs,
1385                         &pipe_ctx->rq_regs,
1386                         &pipe_ctx->pipe_dlg_param);
1387         }
1388         if (pipe_ctx->update_flags.bits.hubp_interdependent)
1389                 hubp->funcs->hubp_setup_interdependent(
1390                         hubp,
1391                         &pipe_ctx->dlg_regs,
1392                         &pipe_ctx->ttu_regs);
1393
1394         if (pipe_ctx->update_flags.bits.enable ||
1395                         plane_state->update_flags.bits.bpp_change ||
1396                         plane_state->update_flags.bits.input_csc_change ||
1397                         plane_state->update_flags.bits.color_space_change ||
1398                         plane_state->update_flags.bits.coeff_reduction_change) {
1399                 struct dc_bias_and_scale bns_params = {0};
1400
1401                 // program the input csc
1402                 dpp->funcs->dpp_setup(dpp,
1403                                 plane_state->format,
1404                                 EXPANSION_MODE_ZERO,
1405                                 plane_state->input_csc_color_matrix,
1406                                 plane_state->color_space,
1407                                 NULL);
1408
1409                 if (dpp->funcs->dpp_program_bias_and_scale) {
1410                         //TODO :for CNVC set scale and bias registers if necessary
1411                         build_prescale_params(&bns_params, plane_state);
1412                         dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
1413                 }
1414         }
1415
1416         if (pipe_ctx->update_flags.bits.mpcc
1417                         || plane_state->update_flags.bits.global_alpha_change
1418                         || plane_state->update_flags.bits.per_pixel_alpha_change) {
1419                 // MPCC inst is equal to pipe index in practice
1420                 int mpcc_inst = hubp->inst;
1421                 int opp_inst;
1422                 int opp_count = dc->res_pool->pipe_count;
1423
1424                 for (opp_inst = 0; opp_inst < opp_count; opp_inst++) {
1425                         if (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst]) {
1426                                 dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst);
1427                                 dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false;
1428                                 break;
1429                         }
1430                 }
1431                 hws->funcs.update_mpcc(dc, pipe_ctx);
1432         }
1433
1434         if (pipe_ctx->update_flags.bits.scaler ||
1435                         plane_state->update_flags.bits.scaling_change ||
1436                         plane_state->update_flags.bits.position_change ||
1437                         plane_state->update_flags.bits.per_pixel_alpha_change ||
1438                         pipe_ctx->stream->update_flags.bits.scaling) {
1439                 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->plane_state->per_pixel_alpha;
1440                 ASSERT(pipe_ctx->plane_res.scl_data.lb_params.depth == LB_PIXEL_DEPTH_30BPP);
1441                 /* scaler configuration */
1442                 pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(
1443                                 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);
1444         }
1445
1446         if (pipe_ctx->update_flags.bits.viewport ||
1447                         (context == dc->current_state && plane_state->update_flags.bits.position_change) ||
1448                         (context == dc->current_state && plane_state->update_flags.bits.scaling_change) ||
1449                         (context == dc->current_state && pipe_ctx->stream->update_flags.bits.scaling)) {
1450
1451                 hubp->funcs->mem_program_viewport(
1452                         hubp,
1453                         &pipe_ctx->plane_res.scl_data.viewport,
1454                         &pipe_ctx->plane_res.scl_data.viewport_c);
1455                 viewport_changed = true;
1456         }
1457
1458         /* Any updates are handled in dc interface, just need to apply existing for plane enable */
1459         if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed ||
1460                         pipe_ctx->update_flags.bits.scaler || viewport_changed == true) &&
1461                         pipe_ctx->stream->cursor_attributes.address.quad_part != 0) {
1462                 dc->hwss.set_cursor_position(pipe_ctx);
1463                 dc->hwss.set_cursor_attribute(pipe_ctx);
1464
1465                 if (dc->hwss.set_cursor_sdr_white_level)
1466                         dc->hwss.set_cursor_sdr_white_level(pipe_ctx);
1467         }
1468
1469         /* Any updates are handled in dc interface, just need
1470          * to apply existing for plane enable / opp change */
1471         if (pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed
1472                         || pipe_ctx->stream->update_flags.bits.gamut_remap
1473                         || pipe_ctx->stream->update_flags.bits.out_csc) {
1474 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
1475                 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
1476
1477                 if (mpc->funcs->set_gamut_remap) {
1478                         int i;
1479                         int mpcc_id = hubp->inst;
1480                         struct mpc_grph_gamut_adjustment adjust;
1481                         bool enable_remap_dpp = false;
1482
1483                         memset(&adjust, 0, sizeof(adjust));
1484                         adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
1485
1486                         /* save the enablement of gamut remap for dpp */
1487                         enable_remap_dpp = pipe_ctx->stream->gamut_remap_matrix.enable_remap;
1488
1489                         /* force bypass gamut remap for dpp/cm */
1490                         pipe_ctx->stream->gamut_remap_matrix.enable_remap = false;
1491                         dc->hwss.program_gamut_remap(pipe_ctx);
1492
1493                         /* restore gamut remap flag and use this remap into mpc */
1494                         pipe_ctx->stream->gamut_remap_matrix.enable_remap = enable_remap_dpp;
1495
1496                         /* build remap matrix for top plane if enabled */
1497                         if (enable_remap_dpp && pipe_ctx->top_pipe == NULL) {
1498                                         adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
1499                                         for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
1500                                                 adjust.temperature_matrix[i] =
1501                                                                 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
1502                         }
1503                         mpc->funcs->set_gamut_remap(mpc, mpcc_id, &adjust);
1504                 } else
1505 #endif
1506                         /* dpp/cm gamut remap*/
1507                         dc->hwss.program_gamut_remap(pipe_ctx);
1508
1509                 /*call the dcn2 method which uses mpc csc*/
1510                 dc->hwss.program_output_csc(dc,
1511                                 pipe_ctx,
1512                                 pipe_ctx->stream->output_color_space,
1513                                 pipe_ctx->stream->csc_color_matrix.matrix,
1514                                 hubp->opp_id);
1515         }
1516
1517         if (pipe_ctx->update_flags.bits.enable ||
1518                         pipe_ctx->update_flags.bits.opp_changed ||
1519                         plane_state->update_flags.bits.pixel_format_change ||
1520                         plane_state->update_flags.bits.horizontal_mirror_change ||
1521                         plane_state->update_flags.bits.rotation_change ||
1522                         plane_state->update_flags.bits.swizzle_change ||
1523                         plane_state->update_flags.bits.dcc_change ||
1524                         plane_state->update_flags.bits.bpp_change ||
1525                         plane_state->update_flags.bits.scaling_change ||
1526                         plane_state->update_flags.bits.plane_size_change) {
1527                 struct plane_size size = plane_state->plane_size;
1528
1529                 size.surface_size = pipe_ctx->plane_res.scl_data.viewport;
1530                 hubp->funcs->hubp_program_surface_config(
1531                         hubp,
1532                         plane_state->format,
1533                         &plane_state->tiling_info,
1534                         &size,
1535                         plane_state->rotation,
1536                         &plane_state->dcc,
1537                         plane_state->horizontal_mirror,
1538                         0);
1539                 hubp->power_gated = false;
1540         }
1541
1542         if (pipe_ctx->update_flags.bits.enable || plane_state->update_flags.bits.addr_update)
1543                 hws->funcs.update_plane_addr(dc, pipe_ctx);
1544
1545
1546
1547         if (pipe_ctx->update_flags.bits.enable)
1548                 hubp->funcs->set_blank(hubp, false);
1549 }
1550
1551
1552 static void dcn20_program_pipe(
1553                 struct dc *dc,
1554                 struct pipe_ctx *pipe_ctx,
1555                 struct dc_state *context)
1556 {
1557         struct dce_hwseq *hws = dc->hwseq;
1558         /* Only need to unblank on top pipe */
1559         if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.abm_level)
1560                         && !pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe)
1561                 hws->funcs.blank_pixel_data(dc, pipe_ctx, !pipe_ctx->plane_state->visible);
1562
1563         if (pipe_ctx->update_flags.bits.global_sync) {
1564                 pipe_ctx->stream_res.tg->funcs->program_global_sync(
1565                                 pipe_ctx->stream_res.tg,
1566                                 pipe_ctx->pipe_dlg_param.vready_offset,
1567                                 pipe_ctx->pipe_dlg_param.vstartup_start,
1568                                 pipe_ctx->pipe_dlg_param.vupdate_offset,
1569                                 pipe_ctx->pipe_dlg_param.vupdate_width);
1570
1571                 pipe_ctx->stream_res.tg->funcs->set_vtg_params(
1572                                 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
1573
1574                 if (hws->funcs.setup_vupdate_interrupt)
1575                         hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
1576         }
1577
1578         if (pipe_ctx->update_flags.bits.odm)
1579                 hws->funcs.update_odm(dc, context, pipe_ctx);
1580
1581         if (pipe_ctx->update_flags.bits.enable) {
1582                 dcn20_enable_plane(dc, pipe_ctx, context);
1583                 if (dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes)
1584                         dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes(dc->res_pool->hubbub);
1585         }
1586
1587         if (pipe_ctx->update_flags.raw || pipe_ctx->plane_state->update_flags.raw || pipe_ctx->stream->update_flags.raw)
1588                 dcn20_update_dchubp_dpp(dc, pipe_ctx, context);
1589
1590         if (pipe_ctx->update_flags.bits.enable
1591                         || pipe_ctx->plane_state->update_flags.bits.hdr_mult)
1592                 hws->funcs.set_hdr_multiplier(pipe_ctx);
1593
1594         if (pipe_ctx->update_flags.bits.enable ||
1595                         pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
1596                         pipe_ctx->plane_state->update_flags.bits.gamma_change)
1597                 hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);
1598
1599         /* dcn10_translate_regamma_to_hw_format takes 750us to finish
1600          * only do gamma programming for powering on, internal memcmp to avoid
1601          * updating on slave planes
1602          */
1603         if (pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.out_tf)
1604                 hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
1605
1606         /* If the pipe has been enabled or has a different opp, we
1607          * should reprogram the fmt. This deals with cases where
1608          * interation between mpc and odm combine on different streams
1609          * causes a different pipe to be chosen to odm combine with.
1610          */
1611         if (pipe_ctx->update_flags.bits.enable
1612             || pipe_ctx->update_flags.bits.opp_changed) {
1613
1614                 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
1615                         pipe_ctx->stream_res.opp,
1616                         COLOR_SPACE_YCBCR601,
1617                         pipe_ctx->stream->timing.display_color_depth,
1618                         pipe_ctx->stream->signal);
1619
1620                 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
1621                         pipe_ctx->stream_res.opp,
1622                         &pipe_ctx->stream->bit_depth_params,
1623                         &pipe_ctx->stream->clamping);
1624         }
1625 }
1626
1627 void dcn20_program_front_end_for_ctx(
1628                 struct dc *dc,
1629                 struct dc_state *context)
1630 {
1631         int i;
1632         struct dce_hwseq *hws = dc->hwseq;
1633         DC_LOGGER_INIT(dc->ctx->logger);
1634
1635         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1636                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1637
1638                 if (!pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe && pipe_ctx->plane_state) {
1639                         ASSERT(!pipe_ctx->plane_state->triplebuffer_flips);
1640                         if (dc->hwss.program_triplebuffer != NULL &&
1641                                 !dc->debug.disable_tri_buf) {
1642                                 /*turn off triple buffer for full update*/
1643                                 dc->hwss.program_triplebuffer(
1644                                         dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);
1645                         }
1646                 }
1647         }
1648
1649         /* Set pipe update flags and lock pipes */
1650         for (i = 0; i < dc->res_pool->pipe_count; i++)
1651                 dcn20_detect_pipe_changes(&dc->current_state->res_ctx.pipe_ctx[i],
1652                                 &context->res_ctx.pipe_ctx[i]);
1653
1654         /* OTG blank before disabling all front ends */
1655         for (i = 0; i < dc->res_pool->pipe_count; i++)
1656                 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable
1657                                 && !context->res_ctx.pipe_ctx[i].top_pipe
1658                                 && !context->res_ctx.pipe_ctx[i].prev_odm_pipe
1659                                 && context->res_ctx.pipe_ctx[i].stream)
1660                         hws->funcs.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true);
1661
1662         /* Disconnect mpcc */
1663         for (i = 0; i < dc->res_pool->pipe_count; i++)
1664                 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable
1665                                 || context->res_ctx.pipe_ctx[i].update_flags.bits.opp_changed) {
1666                         hws->funcs.plane_atomic_disconnect(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
1667                         DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx);
1668                 }
1669
1670         /*
1671          * Program all updated pipes, order matters for mpcc setup. Start with
1672          * top pipe and program all pipes that follow in order
1673          */
1674         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1675                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1676
1677                 if (pipe->plane_state && !pipe->top_pipe) {
1678                         while (pipe) {
1679                                 dcn20_program_pipe(dc, pipe, context);
1680                                 pipe = pipe->bottom_pipe;
1681                         }
1682                         /* Program secondary blending tree and writeback pipes */
1683                         pipe = &context->res_ctx.pipe_ctx[i];
1684                         if (!pipe->prev_odm_pipe && pipe->stream->num_wb_info > 0
1685                                         && (pipe->update_flags.raw || pipe->plane_state->update_flags.raw || pipe->stream->update_flags.raw)
1686                                         && hws->funcs.program_all_writeback_pipes_in_tree)
1687                                 hws->funcs.program_all_writeback_pipes_in_tree(dc, pipe->stream, context);
1688                 }
1689         }
1690 }
1691
1692 void dcn20_post_unlock_program_front_end(
1693                 struct dc *dc,
1694                 struct dc_state *context)
1695 {
1696         int i;
1697         const unsigned int TIMEOUT_FOR_PIPE_ENABLE_MS = 100;
1698         struct dce_hwseq *hwseq = dc->hwseq;
1699
1700         DC_LOGGER_INIT(dc->ctx->logger);
1701
1702         for (i = 0; i < dc->res_pool->pipe_count; i++)
1703                 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable)
1704                         dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
1705
1706         /*
1707          * If we are enabling a pipe, we need to wait for pending clear as this is a critical
1708          * part of the enable operation otherwise, DM may request an immediate flip which
1709          * will cause HW to perform an "immediate enable" (as opposed to "vsync enable") which
1710          * is unsupported on DCN.
1711          */
1712         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1713                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1714
1715                 if (pipe->plane_state && !pipe->top_pipe && pipe->update_flags.bits.enable) {
1716                         struct hubp *hubp = pipe->plane_res.hubp;
1717                         int j = 0;
1718
1719                         for (j = 0; j < TIMEOUT_FOR_PIPE_ENABLE_MS*1000
1720                                         && hubp->funcs->hubp_is_flip_pending(hubp); j++)
1721                                 mdelay(1);
1722                 }
1723         }
1724
1725         /* WA to apply WM setting*/
1726         if (hwseq->wa.DEGVIDCN21)
1727                 dc->res_pool->hubbub->funcs->apply_DEDCN21_147_wa(dc->res_pool->hubbub);
1728
1729
1730         /* WA for stutter underflow during MPO transitions when adding 2nd plane */
1731         if (hwseq->wa.disallow_self_refresh_during_multi_plane_transition) {
1732
1733                 if (dc->current_state->stream_status[0].plane_count == 1 &&
1734                                 context->stream_status[0].plane_count > 1) {
1735
1736                         struct timing_generator *tg = dc->res_pool->timing_generators[0];
1737
1738                         dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, false);
1739
1740                         hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied = true;
1741                         hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied_on_frame = tg->funcs->get_frame_count(tg);
1742                 }
1743         }
1744 }
1745
1746 void dcn20_prepare_bandwidth(
1747                 struct dc *dc,
1748                 struct dc_state *context)
1749 {
1750         struct hubbub *hubbub = dc->res_pool->hubbub;
1751
1752         dc->clk_mgr->funcs->update_clocks(
1753                         dc->clk_mgr,
1754                         context,
1755                         false);
1756
1757         /* program dchubbub watermarks */
1758         dc->wm_optimized_required = hubbub->funcs->program_watermarks(hubbub,
1759                                         &context->bw_ctx.bw.dcn.watermarks,
1760                                         dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
1761                                         false);
1762 }
1763
1764 void dcn20_optimize_bandwidth(
1765                 struct dc *dc,
1766                 struct dc_state *context)
1767 {
1768         struct hubbub *hubbub = dc->res_pool->hubbub;
1769
1770         /* program dchubbub watermarks */
1771         hubbub->funcs->program_watermarks(hubbub,
1772                                         &context->bw_ctx.bw.dcn.watermarks,
1773                                         dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
1774                                         true);
1775
1776         dc->clk_mgr->funcs->update_clocks(
1777                         dc->clk_mgr,
1778                         context,
1779                         true);
1780 }
1781
1782 bool dcn20_update_bandwidth(
1783                 struct dc *dc,
1784                 struct dc_state *context)
1785 {
1786         int i;
1787         struct dce_hwseq *hws = dc->hwseq;
1788
1789         /* recalculate DML parameters */
1790         if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false))
1791                 return false;
1792
1793         /* apply updated bandwidth parameters */
1794         dc->hwss.prepare_bandwidth(dc, context);
1795
1796         /* update hubp configs for all pipes */
1797         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1798                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1799
1800                 if (pipe_ctx->plane_state == NULL)
1801                         continue;
1802
1803                 if (pipe_ctx->top_pipe == NULL) {
1804                         bool blank = !is_pipe_tree_visible(pipe_ctx);
1805
1806                         pipe_ctx->stream_res.tg->funcs->program_global_sync(
1807                                         pipe_ctx->stream_res.tg,
1808                                         pipe_ctx->pipe_dlg_param.vready_offset,
1809                                         pipe_ctx->pipe_dlg_param.vstartup_start,
1810                                         pipe_ctx->pipe_dlg_param.vupdate_offset,
1811                                         pipe_ctx->pipe_dlg_param.vupdate_width);
1812
1813                         pipe_ctx->stream_res.tg->funcs->set_vtg_params(
1814                                         pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
1815
1816                         if (pipe_ctx->prev_odm_pipe == NULL)
1817                                 hws->funcs.blank_pixel_data(dc, pipe_ctx, blank);
1818
1819                         if (hws->funcs.setup_vupdate_interrupt)
1820                                 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
1821                 }
1822
1823                 pipe_ctx->plane_res.hubp->funcs->hubp_setup(
1824                                 pipe_ctx->plane_res.hubp,
1825                                         &pipe_ctx->dlg_regs,
1826                                         &pipe_ctx->ttu_regs,
1827                                         &pipe_ctx->rq_regs,
1828                                         &pipe_ctx->pipe_dlg_param);
1829         }
1830
1831         return true;
1832 }
1833
1834 void dcn20_enable_writeback(
1835                 struct dc *dc,
1836                 struct dc_writeback_info *wb_info,
1837                 struct dc_state *context)
1838 {
1839         struct dwbc *dwb;
1840         struct mcif_wb *mcif_wb;
1841         struct timing_generator *optc;
1842
1843         ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES);
1844         ASSERT(wb_info->wb_enabled);
1845         dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
1846         mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];
1847
1848         /* set the OPTC source mux */
1849         optc = dc->res_pool->timing_generators[dwb->otg_inst];
1850         optc->funcs->set_dwb_source(optc, wb_info->dwb_pipe_inst);
1851         /* set MCIF_WB buffer and arbitration configuration */
1852         mcif_wb->funcs->config_mcif_buf(mcif_wb, &wb_info->mcif_buf_params, wb_info->dwb_params.dest_height);
1853         mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]);
1854         /* Enable MCIF_WB */
1855         mcif_wb->funcs->enable_mcif(mcif_wb);
1856         /* Enable DWB */
1857         dwb->funcs->enable(dwb, &wb_info->dwb_params);
1858         /* TODO: add sequence to enable/disable warmup */
1859 }
1860
1861 void dcn20_disable_writeback(
1862                 struct dc *dc,
1863                 unsigned int dwb_pipe_inst)
1864 {
1865         struct dwbc *dwb;
1866         struct mcif_wb *mcif_wb;
1867
1868         ASSERT(dwb_pipe_inst < MAX_DWB_PIPES);
1869         dwb = dc->res_pool->dwbc[dwb_pipe_inst];
1870         mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst];
1871
1872         dwb->funcs->disable(dwb);
1873         mcif_wb->funcs->disable_mcif(mcif_wb);
1874 }
1875
1876 bool dcn20_wait_for_blank_complete(
1877                 struct output_pixel_processor *opp)
1878 {
1879         int counter;
1880
1881         for (counter = 0; counter < 1000; counter++) {
1882                 if (opp->funcs->dpg_is_blanked(opp))
1883                         break;
1884
1885                 udelay(100);
1886         }
1887
1888         if (counter == 1000) {
1889                 dm_error("DC: failed to blank crtc!\n");
1890                 return false;
1891         }
1892
1893         return true;
1894 }
1895
1896 bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx)
1897 {
1898         struct hubp *hubp = pipe_ctx->plane_res.hubp;
1899
1900         if (!hubp)
1901                 return false;
1902         return hubp->funcs->dmdata_status_done(hubp);
1903 }
1904
1905 void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)
1906 {
1907         struct dce_hwseq *hws = dc->hwseq;
1908
1909         if (pipe_ctx->stream_res.dsc) {
1910                 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
1911
1912                 dcn20_dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, true);
1913                 while (odm_pipe) {
1914                         dcn20_dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, true);
1915                         odm_pipe = odm_pipe->next_odm_pipe;
1916                 }
1917         }
1918 }
1919
1920 void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)
1921 {
1922         struct dce_hwseq *hws = dc->hwseq;
1923
1924         if (pipe_ctx->stream_res.dsc) {
1925                 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
1926
1927                 dcn20_dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, false);
1928                 while (odm_pipe) {
1929                         dcn20_dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, false);
1930                         odm_pipe = odm_pipe->next_odm_pipe;
1931                 }
1932         }
1933 }
1934
1935 void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx)
1936 {
1937         struct dc_dmdata_attributes attr = { 0 };
1938         struct hubp *hubp = pipe_ctx->plane_res.hubp;
1939
1940         attr.dmdata_mode = DMDATA_HW_MODE;
1941         attr.dmdata_size =
1942                 dc_is_hdmi_signal(pipe_ctx->stream->signal) ? 32 : 36;
1943         attr.address.quad_part =
1944                         pipe_ctx->stream->dmdata_address.quad_part;
1945         attr.dmdata_dl_delta = 0;
1946         attr.dmdata_qos_mode = 0;
1947         attr.dmdata_qos_level = 0;
1948         attr.dmdata_repeat = 1; /* always repeat */
1949         attr.dmdata_updated = 1;
1950         attr.dmdata_sw_data = NULL;
1951
1952         hubp->funcs->dmdata_set_attributes(hubp, &attr);
1953 }
1954
1955 void dcn20_init_vm_ctx(
1956                 struct dce_hwseq *hws,
1957                 struct dc *dc,
1958                 struct dc_virtual_addr_space_config *va_config,
1959                 int vmid)
1960 {
1961         struct dcn_hubbub_virt_addr_config config;
1962
1963         if (vmid == 0) {
1964                 ASSERT(0); /* VMID cannot be 0 for vm context */
1965                 return;
1966         }
1967
1968         config.page_table_start_addr = va_config->page_table_start_addr;
1969         config.page_table_end_addr = va_config->page_table_end_addr;
1970         config.page_table_block_size = va_config->page_table_block_size_in_bytes;
1971         config.page_table_depth = va_config->page_table_depth;
1972         config.page_table_base_addr = va_config->page_table_base_addr;
1973
1974         dc->res_pool->hubbub->funcs->init_vm_ctx(dc->res_pool->hubbub, &config, vmid);
1975 }
1976
1977 int dcn20_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)
1978 {
1979         struct dcn_hubbub_phys_addr_config config;
1980
1981         config.system_aperture.fb_top = pa_config->system_aperture.fb_top;
1982         config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset;
1983         config.system_aperture.fb_base = pa_config->system_aperture.fb_base;
1984         config.system_aperture.agp_top = pa_config->system_aperture.agp_top;
1985         config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot;
1986         config.system_aperture.agp_base = pa_config->system_aperture.agp_base;
1987         config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr;
1988         config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr;
1989         config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr;
1990         config.page_table_default_page_addr = pa_config->page_table_default_page_addr;
1991
1992         return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config);
1993 }
1994
1995 static bool patch_address_for_sbs_tb_stereo(
1996                 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr)
1997 {
1998         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1999         bool sec_split = pipe_ctx->top_pipe &&
2000                         pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
2001         if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2002                         (pipe_ctx->stream->timing.timing_3d_format ==
2003                         TIMING_3D_FORMAT_SIDE_BY_SIDE ||
2004                         pipe_ctx->stream->timing.timing_3d_format ==
2005                         TIMING_3D_FORMAT_TOP_AND_BOTTOM)) {
2006                 *addr = plane_state->address.grph_stereo.left_addr;
2007                 plane_state->address.grph_stereo.left_addr =
2008                                 plane_state->address.grph_stereo.right_addr;
2009                 return true;
2010         }
2011
2012         if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE &&
2013                         plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) {
2014                 plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO;
2015                 plane_state->address.grph_stereo.right_addr =
2016                                 plane_state->address.grph_stereo.left_addr;
2017         }
2018         return false;
2019 }
2020
2021 void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)
2022 {
2023         bool addr_patched = false;
2024         PHYSICAL_ADDRESS_LOC addr;
2025         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2026
2027         if (plane_state == NULL)
2028                 return;
2029
2030         addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);
2031
2032         // Call Helper to track VMID use
2033         vm_helper_mark_vmid_used(dc->vm_helper, plane_state->address.vmid, pipe_ctx->plane_res.hubp->inst);
2034
2035         pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(
2036                         pipe_ctx->plane_res.hubp,
2037                         &plane_state->address,
2038                         plane_state->flip_immediate);
2039
2040         plane_state->status.requested_address = plane_state->address;
2041
2042         if (plane_state->flip_immediate)
2043                 plane_state->status.current_address = plane_state->address;
2044
2045         if (addr_patched)
2046                 pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;
2047 }
2048
2049 void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx,
2050                 struct dc_link_settings *link_settings)
2051 {
2052         struct encoder_unblank_param params = { { 0 } };
2053         struct dc_stream_state *stream = pipe_ctx->stream;
2054         struct dc_link *link = stream->link;
2055         struct dce_hwseq *hws = link->dc->hwseq;
2056         struct pipe_ctx *odm_pipe;
2057
2058         params.opp_cnt = 1;
2059         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
2060                 params.opp_cnt++;
2061         }
2062         /* only 3 items below are used by unblank */
2063         params.timing = pipe_ctx->stream->timing;
2064
2065         params.link_settings.link_rate = link_settings->link_rate;
2066
2067         if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
2068                 if (optc2_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1)
2069                         params.timing.pix_clk_100hz /= 2;
2070                 pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine(
2071                                 pipe_ctx->stream_res.stream_enc, params.opp_cnt > 1);
2072                 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, &params);
2073         }
2074
2075         if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
2076                 hws->funcs.edp_backlight_control(link, true);
2077         }
2078 }
2079
2080 void dcn20_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx)
2081 {
2082         struct timing_generator *tg = pipe_ctx->stream_res.tg;
2083         int start_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);
2084
2085         if (start_line < 0)
2086                 start_line = 0;
2087
2088         if (tg->funcs->setup_vertical_interrupt2)
2089                 tg->funcs->setup_vertical_interrupt2(tg, start_line);
2090 }
2091
2092 static void dcn20_reset_back_end_for_pipe(
2093                 struct dc *dc,
2094                 struct pipe_ctx *pipe_ctx,
2095                 struct dc_state *context)
2096 {
2097         int i;
2098         struct dc_link *link;
2099         DC_LOGGER_INIT(dc->ctx->logger);
2100         if (pipe_ctx->stream_res.stream_enc == NULL) {
2101                 pipe_ctx->stream = NULL;
2102                 return;
2103         }
2104
2105         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
2106                 link = pipe_ctx->stream->link;
2107                 /* DPMS may already disable or */
2108                 /* dpms_off status is incorrect due to fastboot
2109                  * feature. When system resume from S4 with second
2110                  * screen only, the dpms_off would be true but
2111                  * VBIOS lit up eDP, so check link status too.
2112                  */
2113                 if (!pipe_ctx->stream->dpms_off || link->link_status.link_active)
2114                         core_link_disable_stream(pipe_ctx);
2115                 else if (pipe_ctx->stream_res.audio)
2116                         dc->hwss.disable_audio_stream(pipe_ctx);
2117
2118                 /* free acquired resources */
2119                 if (pipe_ctx->stream_res.audio) {
2120                         /*disable az_endpoint*/
2121                         pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
2122
2123                         /*free audio*/
2124                         if (dc->caps.dynamic_audio == true) {
2125                                 /*we have to dynamic arbitrate the audio endpoints*/
2126                                 /*we free the resource, need reset is_audio_acquired*/
2127                                 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
2128                                                 pipe_ctx->stream_res.audio, false);
2129                                 pipe_ctx->stream_res.audio = NULL;
2130                         }
2131                 }
2132         }
2133         else if (pipe_ctx->stream_res.dsc) {
2134                 dp_set_dsc_enable(pipe_ctx, false);
2135         }
2136
2137         /* by upper caller loop, parent pipe: pipe0, will be reset last.
2138          * back end share by all pipes and will be disable only when disable
2139          * parent pipe.
2140          */
2141         if (pipe_ctx->top_pipe == NULL) {
2142
2143                 dc->hwss.set_abm_immediate_disable(pipe_ctx);
2144
2145                 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
2146
2147                 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
2148                 if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass)
2149                         pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
2150                                         pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
2151
2152                 if (pipe_ctx->stream_res.tg->funcs->set_drr)
2153                         pipe_ctx->stream_res.tg->funcs->set_drr(
2154                                         pipe_ctx->stream_res.tg, NULL);
2155         }
2156
2157         for (i = 0; i < dc->res_pool->pipe_count; i++)
2158                 if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx)
2159                         break;
2160
2161         if (i == dc->res_pool->pipe_count)
2162                 return;
2163
2164         pipe_ctx->stream = NULL;
2165         DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n",
2166                                         pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
2167 }
2168
2169 void dcn20_reset_hw_ctx_wrap(
2170                 struct dc *dc,
2171                 struct dc_state *context)
2172 {
2173         int i;
2174         struct dce_hwseq *hws = dc->hwseq;
2175
2176         /* Reset Back End*/
2177         for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
2178                 struct pipe_ctx *pipe_ctx_old =
2179                         &dc->current_state->res_ctx.pipe_ctx[i];
2180                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2181
2182                 if (!pipe_ctx_old->stream)
2183                         continue;
2184
2185                 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe)
2186                         continue;
2187
2188                 if (!pipe_ctx->stream ||
2189                                 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
2190                         struct clock_source *old_clk = pipe_ctx_old->clock_source;
2191
2192                         dcn20_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
2193                         if (hws->funcs.enable_stream_gating)
2194                                 hws->funcs.enable_stream_gating(dc, pipe_ctx);
2195                         if (old_clk)
2196                                 old_clk->funcs->cs_power_down(old_clk);
2197                 }
2198         }
2199 }
2200
2201 void dcn20_get_mpctree_visual_confirm_color(
2202                 struct pipe_ctx *pipe_ctx,
2203                 struct tg_color *color)
2204 {
2205         const struct tg_color pipe_colors[6] = {
2206                         {MAX_TG_COLOR_VALUE, 0, 0}, // red
2207                         {MAX_TG_COLOR_VALUE, 0, MAX_TG_COLOR_VALUE}, // yellow
2208                         {0, MAX_TG_COLOR_VALUE, 0}, // blue
2209                         {MAX_TG_COLOR_VALUE / 2, 0, MAX_TG_COLOR_VALUE / 2}, // purple
2210                         {0, 0, MAX_TG_COLOR_VALUE}, // green
2211                         {MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE * 2 / 3, 0}, // orange
2212         };
2213
2214         struct pipe_ctx *top_pipe = pipe_ctx;
2215
2216         while (top_pipe->top_pipe) {
2217                 top_pipe = top_pipe->top_pipe;
2218         }
2219
2220         *color = pipe_colors[top_pipe->pipe_idx];
2221 }
2222
2223 void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
2224 {
2225         struct dce_hwseq *hws = dc->hwseq;
2226         struct hubp *hubp = pipe_ctx->plane_res.hubp;
2227         struct mpcc_blnd_cfg blnd_cfg = { {0} };
2228         bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha;
2229         int mpcc_id;
2230         struct mpcc *new_mpcc;
2231         struct mpc *mpc = dc->res_pool->mpc;
2232         struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);
2233
2234         // input to MPCC is always RGB, by default leave black_color at 0
2235         if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) {
2236                 hws->funcs.get_hdr_visual_confirm_color(
2237                                 pipe_ctx, &blnd_cfg.black_color);
2238         } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) {
2239                 hws->funcs.get_surface_visual_confirm_color(
2240                                 pipe_ctx, &blnd_cfg.black_color);
2241         } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE) {
2242                 dcn20_get_mpctree_visual_confirm_color(
2243                                 pipe_ctx, &blnd_cfg.black_color);
2244         }
2245
2246         if (per_pixel_alpha)
2247                 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;
2248         else
2249                 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA;
2250
2251         blnd_cfg.overlap_only = false;
2252         blnd_cfg.global_gain = 0xff;
2253
2254         if (pipe_ctx->plane_state->global_alpha)
2255                 blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value;
2256         else
2257                 blnd_cfg.global_alpha = 0xff;
2258
2259         blnd_cfg.background_color_bpc = 4;
2260         blnd_cfg.bottom_gain_mode = 0;
2261         blnd_cfg.top_gain = 0x1f000;
2262         blnd_cfg.bottom_inside_gain = 0x1f000;
2263         blnd_cfg.bottom_outside_gain = 0x1f000;
2264         blnd_cfg.pre_multiplied_alpha = per_pixel_alpha;
2265 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
2266         if (pipe_ctx->plane_state->format
2267                         == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA)
2268                 blnd_cfg.pre_multiplied_alpha = false;
2269 #endif
2270
2271         /*
2272          * TODO: remove hack
2273          * Note: currently there is a bug in init_hw such that
2274          * on resume from hibernate, BIOS sets up MPCC0, and
2275          * we do mpcc_remove but the mpcc cannot go to idle
2276          * after remove. This cause us to pick mpcc1 here,
2277          * which causes a pstate hang for yet unknown reason.
2278          */
2279         mpcc_id = hubp->inst;
2280
2281         /* If there is no full update, don't need to touch MPC tree*/
2282         if (!pipe_ctx->plane_state->update_flags.bits.full_update &&
2283                 !pipe_ctx->update_flags.bits.mpcc) {
2284                 mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id);
2285                 return;
2286         }
2287
2288         /* check if this MPCC is already being used */
2289         new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id);
2290         /* remove MPCC if being used */
2291         if (new_mpcc != NULL)
2292                 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc);
2293         else
2294                 if (dc->debug.sanity_checks)
2295                         mpc->funcs->assert_mpcc_idle_before_connect(
2296                                         dc->res_pool->mpc, mpcc_id);
2297
2298         /* Call MPC to insert new plane */
2299         new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,
2300                         mpc_tree_params,
2301                         &blnd_cfg,
2302                         NULL,
2303                         NULL,
2304                         hubp->inst,
2305                         mpcc_id);
2306
2307         ASSERT(new_mpcc != NULL);
2308         hubp->opp_id = pipe_ctx->stream_res.opp->inst;
2309         hubp->mpcc_id = mpcc_id;
2310 }
2311
2312 void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)
2313 {
2314         enum dc_lane_count lane_count =
2315                 pipe_ctx->stream->link->cur_link_settings.lane_count;
2316
2317         struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
2318         struct dc_link *link = pipe_ctx->stream->link;
2319
2320         uint32_t active_total_with_borders;
2321         uint32_t early_control = 0;
2322         struct timing_generator *tg = pipe_ctx->stream_res.tg;
2323
2324         /* For MST, there are multiply stream go to only one link.
2325          * connect DIG back_end to front_end while enable_stream and
2326          * disconnect them during disable_stream
2327          * BY this, it is logic clean to separate stream and link
2328          */
2329         link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
2330                                                     pipe_ctx->stream_res.stream_enc->id, true);
2331
2332         if (pipe_ctx->plane_state && pipe_ctx->plane_state->flip_immediate != 1) {
2333                 if (link->dc->hwss.program_dmdata_engine)
2334                         link->dc->hwss.program_dmdata_engine(pipe_ctx);
2335         }
2336
2337         link->dc->hwss.update_info_frame(pipe_ctx);
2338
2339         /* enable early control to avoid corruption on DP monitor*/
2340         active_total_with_borders =
2341                         timing->h_addressable
2342                                 + timing->h_border_left
2343                                 + timing->h_border_right;
2344
2345         if (lane_count != 0)
2346                 early_control = active_total_with_borders % lane_count;
2347
2348         if (early_control == 0)
2349                 early_control = lane_count;
2350
2351         tg->funcs->set_early_control(tg, early_control);
2352
2353         /* enable audio only within mode set */
2354         if (pipe_ctx->stream_res.audio != NULL) {
2355                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
2356                         pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
2357         }
2358 }
2359
2360 void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx)
2361 {
2362         struct dc_stream_state    *stream     = pipe_ctx->stream;
2363         struct hubp               *hubp       = pipe_ctx->plane_res.hubp;
2364         bool                       enable     = false;
2365         struct stream_encoder     *stream_enc = pipe_ctx->stream_res.stream_enc;
2366         enum dynamic_metadata_mode mode       = dc_is_dp_signal(stream->signal)
2367                                                         ? dmdata_dp
2368                                                         : dmdata_hdmi;
2369
2370         /* if using dynamic meta, don't set up generic infopackets */
2371         if (pipe_ctx->stream->dmdata_address.quad_part != 0) {
2372                 pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false;
2373                 enable = true;
2374         }
2375
2376         if (!hubp)
2377                 return;
2378
2379         if (!stream_enc || !stream_enc->funcs->set_dynamic_metadata)
2380                 return;
2381
2382         stream_enc->funcs->set_dynamic_metadata(stream_enc, enable,
2383                                                 hubp->inst, mode);
2384 }
2385
2386 void dcn20_fpga_init_hw(struct dc *dc)
2387 {
2388         int i, j;
2389         struct dce_hwseq *hws = dc->hwseq;
2390         struct resource_pool *res_pool = dc->res_pool;
2391         struct dc_state  *context = dc->current_state;
2392
2393         if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
2394                 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
2395
2396         // Initialize the dccg
2397         if (res_pool->dccg->funcs->dccg_init)
2398                 res_pool->dccg->funcs->dccg_init(res_pool->dccg);
2399
2400         //Enable ability to power gate / don't force power on permanently
2401         hws->funcs.enable_power_gating_plane(hws, true);
2402
2403         // Specific to FPGA dccg and registers
2404         REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF);
2405         REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF);
2406
2407         hws->funcs.dccg_init(hws);
2408
2409         REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2);
2410         REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
2411         if (REG(REFCLK_CNTL))
2412                 REG_WRITE(REFCLK_CNTL, 0);
2413         //
2414
2415
2416         /* Blank pixel data with OPP DPG */
2417         for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
2418                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2419
2420                 if (tg->funcs->is_tg_enabled(tg))
2421                         dcn20_init_blank(dc, tg);
2422         }
2423
2424         for (i = 0; i < res_pool->timing_generator_count; i++) {
2425                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2426
2427                 if (tg->funcs->is_tg_enabled(tg))
2428                         tg->funcs->lock(tg);
2429         }
2430
2431         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2432                 struct dpp *dpp = res_pool->dpps[i];
2433
2434                 dpp->funcs->dpp_reset(dpp);
2435         }
2436
2437         /* Reset all MPCC muxes */
2438         res_pool->mpc->funcs->mpc_init(res_pool->mpc);
2439
2440         /* initialize OPP mpc_tree parameter */
2441         for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {
2442                 res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst;
2443                 res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
2444                 for (j = 0; j < MAX_PIPES; j++)
2445                         res_pool->opps[i]->mpcc_disconnect_pending[j] = false;
2446         }
2447
2448         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2449                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2450                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2451                 struct hubp *hubp = dc->res_pool->hubps[i];
2452                 struct dpp *dpp = dc->res_pool->dpps[i];
2453
2454                 pipe_ctx->stream_res.tg = tg;
2455                 pipe_ctx->pipe_idx = i;
2456
2457                 pipe_ctx->plane_res.hubp = hubp;
2458                 pipe_ctx->plane_res.dpp = dpp;
2459                 pipe_ctx->plane_res.mpcc_inst = dpp->inst;
2460                 hubp->mpcc_id = dpp->inst;
2461                 hubp->opp_id = OPP_ID_INVALID;
2462                 hubp->power_gated = false;
2463                 pipe_ctx->stream_res.opp = NULL;
2464
2465                 hubp->funcs->hubp_init(hubp);
2466
2467                 //dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
2468                 //dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
2469                 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
2470                 pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
2471                 /*to do*/
2472                 hws->funcs.plane_atomic_disconnect(dc, pipe_ctx);
2473         }
2474
2475         /* initialize DWB pointer to MCIF_WB */
2476         for (i = 0; i < res_pool->res_cap->num_dwb; i++)
2477                 res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i];
2478
2479         for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
2480                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2481
2482                 if (tg->funcs->is_tg_enabled(tg))
2483                         tg->funcs->unlock(tg);
2484         }
2485
2486         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2487                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2488
2489                 dc->hwss.disable_plane(dc, pipe_ctx);
2490
2491                 pipe_ctx->stream_res.tg = NULL;
2492                 pipe_ctx->plane_res.hubp = NULL;
2493         }
2494
2495         for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
2496                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2497
2498                 tg->funcs->tg_init(tg);
2499         }
2500 }
2501 #ifndef TRIM_FSFT
2502 bool dcn20_optimize_timing_for_fsft(struct dc *dc,
2503                 struct dc_crtc_timing *timing,
2504                 unsigned int max_input_rate_in_khz)
2505 {
2506         unsigned int old_v_front_porch;
2507         unsigned int old_v_total;
2508         unsigned int max_input_rate_in_100hz;
2509         unsigned long long new_v_total;
2510
2511         max_input_rate_in_100hz = max_input_rate_in_khz * 10;
2512         if (max_input_rate_in_100hz < timing->pix_clk_100hz)
2513                 return false;
2514
2515         old_v_total = timing->v_total;
2516         old_v_front_porch = timing->v_front_porch;
2517
2518         timing->fast_transport_output_rate_100hz = timing->pix_clk_100hz;
2519         timing->pix_clk_100hz = max_input_rate_in_100hz;
2520
2521         new_v_total = div_u64((unsigned long long)old_v_total * max_input_rate_in_100hz, timing->pix_clk_100hz);
2522
2523         timing->v_total = new_v_total;
2524         timing->v_front_porch = old_v_front_porch + (timing->v_total - old_v_total);
2525         return true;
2526 }
2527 #endif