drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 #include <linux/delay.h>
  26
  27 #include "dm_services.h"
  28 #include "basics/dc_common.h"
  29 #include "dm_helpers.h"
  30 #include "core_types.h"
  31 #include "resource.h"
  32 #include "dcn20_resource.h"
  33 #include "dcn20_hwseq.h"
  34 #include "dce/dce_hwseq.h"
  35 #include "dcn20_dsc.h"
  36 #include "dcn20_optc.h"
  37 #include "abm.h"
  38 #include "clk_mgr.h"
  39 #include "dmcu.h"
  40 #include "hubp.h"
  41 #include "timing_generator.h"
  42 #include "opp.h"
  43 #include "ipp.h"
  44 #include "mpc.h"
  45 #include "mcif_wb.h"
  46 #include "dchubbub.h"
  47 #include "reg_helper.h"
  48 #include "dcn10/dcn10_cm_common.h"
  49 #include "dc_link_dp.h"
  50 #include "vm_helper.h"
  51 #include "dccg.h"
  52
  53 #define DC_LOGGER_INIT(logger)
  54
  55 #define CTX \
  56         hws->ctx
  57 #define REG(reg)\
  58         hws->regs->reg
  59
  60 #undef FN
  61 #define FN(reg_name, field_name) \
  62         hws->shifts->field_name, hws->masks->field_name
  63
  64 static int find_free_gsl_group(const struct dc *dc)
  65 {
  66         if (dc->res_pool->gsl_groups.gsl_0 == 0)
  67                 return 1;
  68         if (dc->res_pool->gsl_groups.gsl_1 == 0)
  69                 return 2;
  70         if (dc->res_pool->gsl_groups.gsl_2 == 0)
  71                 return 3;
  72
  73         return 0;
  74 }
  75
  76 /* NOTE: This is not a generic setup_gsl function (hence the suffix as_lock)
  77  * This is only used to lock pipes in pipe splitting case with immediate flip
  78  * Ordinary MPC/OTG locks suppress VUPDATE which doesn't help with immediate,
  79  * so we get tearing with freesync since we cannot flip multiple pipes
  80  * atomically.
  81  * We use GSL for this:
  82  * - immediate flip: find first available GSL group if not already assigned
  83  *                   program gsl with that group, set current OTG as master
  84  *                   and always us 0x4 = AND of flip_ready from all pipes
  85  * - vsync flip: disable GSL if used
  86  *
  87  * Groups in stream_res are stored as +1 from HW registers, i.e.
  88  * gsl_0 <=> pipe_ctx->stream_res.gsl_group == 1
  89  * Using a magic value like -1 would require tracking all inits/resets
  90  */
  91 static void dcn20_setup_gsl_group_as_lock(
  92                 const struct dc *dc,
  93                 struct pipe_ctx *pipe_ctx,
  94                 bool enable)
  95 {
  96         struct gsl_params gsl;
  97         int group_idx;
  98
  99         memset(&gsl, 0, sizeof(struct gsl_params));
 100
 101         if (enable) {
 102                 /* return if group already assigned since GSL was set up
 103                  * for vsync flip, we would unassign so it can't be "left over"
 104                  */
 105                 if (pipe_ctx->stream_res.gsl_group > 0)
 106                         return;
 107
 108                 group_idx = find_free_gsl_group(dc);
 109                 ASSERT(group_idx != 0);
 110                 pipe_ctx->stream_res.gsl_group = group_idx;
 111
 112                 /* set gsl group reg field and mark resource used */
 113                 switch (group_idx) {
 114                 case 1:
 115                         gsl.gsl0_en = 1;
 116                         dc->res_pool->gsl_groups.gsl_0 = 1;
 117                         break;
 118                 case 2:
 119                         gsl.gsl1_en = 1;
 120                         dc->res_pool->gsl_groups.gsl_1 = 1;
 121                         break;
 122                 case 3:
 123                         gsl.gsl2_en = 1;
 124                         dc->res_pool->gsl_groups.gsl_2 = 1;
 125                         break;
 126                 default:
 127                         BREAK_TO_DEBUGGER();
 128                         return; // invalid case
 129                 }
 130                 gsl.gsl_master_en = 1;
 131         } else {
 132                 group_idx = pipe_ctx->stream_res.gsl_group;
 133                 if (group_idx == 0)
 134                         return; // if not in use, just return
 135
 136                 pipe_ctx->stream_res.gsl_group = 0;
 137
 138                 /* unset gsl group reg field and mark resource free */
 139                 switch (group_idx) {
 140                 case 1:
 141                         gsl.gsl0_en = 0;
 142                         dc->res_pool->gsl_groups.gsl_0 = 0;
 143                         break;
 144                 case 2:
 145                         gsl.gsl1_en = 0;
 146                         dc->res_pool->gsl_groups.gsl_1 = 0;
 147                         break;
 148                 case 3:
 149                         gsl.gsl2_en = 0;
 150                         dc->res_pool->gsl_groups.gsl_2 = 0;
 151                         break;
 152                 default:
 153                         BREAK_TO_DEBUGGER();
 154                         return;
 155                 }
 156                 gsl.gsl_master_en = 0;
 157         }
 158
 159         /* at this point we want to program whether it's to enable or disable */
 160         if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL &&
 161                 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) {
 162                 pipe_ctx->stream_res.tg->funcs->set_gsl(
 163                         pipe_ctx->stream_res.tg,
 164                         &gsl);
 165
 166                 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select(
 167                         pipe_ctx->stream_res.tg, group_idx,     enable ? 4 : 0);
 168         } else
 169                 BREAK_TO_DEBUGGER();
 170 }
 171
 172 void dcn20_set_flip_control_gsl(
 173                 struct pipe_ctx *pipe_ctx,
 174                 bool flip_immediate)
 175 {
 176         if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl)
 177                 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl(
 178                                 pipe_ctx->plane_res.hubp, flip_immediate);
 179
 180 }
 181
 182 void dcn20_enable_power_gating_plane(
 183         struct dce_hwseq *hws,
 184         bool enable)
 185 {
 186         bool force_on = true; /* disable power gating */
 187
 188         if (enable)
 189                 force_on = false;
 190
 191         /* DCHUBP0/1/2/3/4/5 */
 192         REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on);
 193         REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on);
 194         REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on);
 195         REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on);
 196         if (REG(DOMAIN8_PG_CONFIG))
 197                 REG_UPDATE(DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on);
 198         if (REG(DOMAIN10_PG_CONFIG))
 199                 REG_UPDATE(DOMAIN10_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on);
 200
 201         /* DPP0/1/2/3/4/5 */
 202         REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on);
 203         REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on);
 204         REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on);
 205         REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);
 206         if (REG(DOMAIN9_PG_CONFIG))
 207                 REG_UPDATE(DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on);
 208         if (REG(DOMAIN11_PG_CONFIG))
 209                 REG_UPDATE(DOMAIN11_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on);
 210
 211         /* DCS0/1/2/3/4/5 */
 212         REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, force_on);
 213         REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, force_on);
 214         REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, force_on);
 215         if (REG(DOMAIN19_PG_CONFIG))
 216                 REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, force_on);
 217         if (REG(DOMAIN20_PG_CONFIG))
 218                 REG_UPDATE(DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, force_on);
 219         if (REG(DOMAIN21_PG_CONFIG))
 220                 REG_UPDATE(DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, force_on);
 221 }
 222
 223 void dcn20_dccg_init(struct dce_hwseq *hws)
 224 {
 225         /*
 226          * set MICROSECOND_TIME_BASE_DIV
 227          * 100Mhz refclk -> 0x120264
 228          * 27Mhz refclk -> 0x12021b
 229          * 48Mhz refclk -> 0x120230
 230          *
 231          */
 232         REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x120264);
 233
 234         /*
 235          * set MILLISECOND_TIME_BASE_DIV
 236          * 100Mhz refclk -> 0x1186a0
 237          * 27Mhz refclk -> 0x106978
 238          * 48Mhz refclk -> 0x10bb80
 239          *
 240          */
 241         REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x1186a0);
 242
 243         /* This value is dependent on the hardware pipeline delay so set once per SOC */
 244         REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0x801003c);
 245 }
 246
 247 void dcn20_disable_vga(
 248         struct dce_hwseq *hws)
 249 {
 250         REG_WRITE(D1VGA_CONTROL, 0);
 251         REG_WRITE(D2VGA_CONTROL, 0);
 252         REG_WRITE(D3VGA_CONTROL, 0);
 253         REG_WRITE(D4VGA_CONTROL, 0);
 254         REG_WRITE(D5VGA_CONTROL, 0);
 255         REG_WRITE(D6VGA_CONTROL, 0);
 256 }
 257
 258 void dcn20_program_triple_buffer(
 259         const struct dc *dc,
 260         struct pipe_ctx *pipe_ctx,
 261         bool enable_triple_buffer)
 262 {
 263         if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) {
 264                 pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer(
 265                         pipe_ctx->plane_res.hubp,
 266                         enable_triple_buffer);
 267         }
 268 }
 269
 270 /* Blank pixel data during initialization */
 271 void dcn20_init_blank(
 272                 struct dc *dc,
 273                 struct timing_generator *tg)
 274 {
 275         struct dce_hwseq *hws = dc->hwseq;
 276         enum dc_color_space color_space;
 277         struct tg_color black_color = {0};
 278         struct output_pixel_processor *opp = NULL;
 279         struct output_pixel_processor *bottom_opp = NULL;
 280         uint32_t num_opps, opp_id_src0, opp_id_src1;
 281         uint32_t otg_active_width, otg_active_height;
 282
 283         /* program opp dpg blank color */
 284         color_space = COLOR_SPACE_SRGB;
 285         color_space_to_black_color(dc, color_space, &black_color);
 286
 287         /* get the OTG active size */
 288         tg->funcs->get_otg_active_size(tg,
 289                         &otg_active_width,
 290                         &otg_active_height);
 291
 292         /* get the OPTC source */
 293         tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1);
 294         ASSERT(opp_id_src0 < dc->res_pool->res_cap->num_opp);
 295         opp = dc->res_pool->opps[opp_id_src0];
 296
 297         if (num_opps == 2) {
 298                 otg_active_width = otg_active_width / 2;
 299                 ASSERT(opp_id_src1 < dc->res_pool->res_cap->num_opp);
 300                 bottom_opp = dc->res_pool->opps[opp_id_src1];
 301         }
 302
 303         opp->funcs->opp_set_disp_pattern_generator(
 304                         opp,
 305                         CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,
 306                         CONTROLLER_DP_COLOR_SPACE_UDEFINED,
 307                         COLOR_DEPTH_UNDEFINED,
 308                         &black_color,
 309                         otg_active_width,
 310                         otg_active_height);
 311
 312         if (num_opps == 2) {
 313                 bottom_opp->funcs->opp_set_disp_pattern_generator(
 314                                 bottom_opp,
 315                                 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,
 316                                 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
 317                                 COLOR_DEPTH_UNDEFINED,
 318                                 &black_color,
 319                                 otg_active_width,
 320                                 otg_active_height);
 321         }
 322
 323         hws->funcs.wait_for_blank_complete(opp);
 324 }
 325
 326 void dcn20_dsc_pg_control(
 327                 struct dce_hwseq *hws,
 328                 unsigned int dsc_inst,
 329                 bool power_on)
 330 {
 331         uint32_t power_gate = power_on ? 0 : 1;
 332         uint32_t pwr_status = power_on ? 0 : 2;
 333         uint32_t org_ip_request_cntl = 0;
 334
 335         if (hws->ctx->dc->debug.disable_dsc_power_gate)
 336                 return;
 337
 338         if (REG(DOMAIN16_PG_CONFIG) == 0)
 339                 return;
 340
 341         REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
 342         if (org_ip_request_cntl == 0)
 343                 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
 344
 345         switch (dsc_inst) {
 346         case 0: /* DSC0 */
 347                 REG_UPDATE(DOMAIN16_PG_CONFIG,
 348                                 DOMAIN16_POWER_GATE, power_gate);
 349
 350                 REG_WAIT(DOMAIN16_PG_STATUS,
 351                                 DOMAIN16_PGFSM_PWR_STATUS, pwr_status,
 352                                 1, 1000);
 353                 break;
 354         case 1: /* DSC1 */
 355                 REG_UPDATE(DOMAIN17_PG_CONFIG,
 356                                 DOMAIN17_POWER_GATE, power_gate);
 357
 358                 REG_WAIT(DOMAIN17_PG_STATUS,
 359                                 DOMAIN17_PGFSM_PWR_STATUS, pwr_status,
 360                                 1, 1000);
 361                 break;
 362         case 2: /* DSC2 */
 363                 REG_UPDATE(DOMAIN18_PG_CONFIG,
 364                                 DOMAIN18_POWER_GATE, power_gate);
 365
 366                 REG_WAIT(DOMAIN18_PG_STATUS,
 367                                 DOMAIN18_PGFSM_PWR_STATUS, pwr_status,
 368                                 1, 1000);
 369                 break;
 370         case 3: /* DSC3 */
 371                 REG_UPDATE(DOMAIN19_PG_CONFIG,
 372                                 DOMAIN19_POWER_GATE, power_gate);
 373
 374                 REG_WAIT(DOMAIN19_PG_STATUS,
 375                                 DOMAIN19_PGFSM_PWR_STATUS, pwr_status,
 376                                 1, 1000);
 377                 break;
 378         case 4: /* DSC4 */
 379                 REG_UPDATE(DOMAIN20_PG_CONFIG,
 380                                 DOMAIN20_POWER_GATE, power_gate);
 381
 382                 REG_WAIT(DOMAIN20_PG_STATUS,
 383                                 DOMAIN20_PGFSM_PWR_STATUS, pwr_status,
 384                                 1, 1000);
 385                 break;
 386         case 5: /* DSC5 */
 387                 REG_UPDATE(DOMAIN21_PG_CONFIG,
 388                                 DOMAIN21_POWER_GATE, power_gate);
 389
 390                 REG_WAIT(DOMAIN21_PG_STATUS,
 391                                 DOMAIN21_PGFSM_PWR_STATUS, pwr_status,
 392                                 1, 1000);
 393                 break;
 394         default:
 395                 BREAK_TO_DEBUGGER();
 396                 break;
 397         }
 398
 399         if (org_ip_request_cntl == 0)
 400                 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
 401 }
 402
 403 void dcn20_dpp_pg_control(
 404                 struct dce_hwseq *hws,
 405                 unsigned int dpp_inst,
 406                 bool power_on)
 407 {
 408         uint32_t power_gate = power_on ? 0 : 1;
 409         uint32_t pwr_status = power_on ? 0 : 2;
 410
 411         if (hws->ctx->dc->debug.disable_dpp_power_gate)
 412                 return;
 413         if (REG(DOMAIN1_PG_CONFIG) == 0)
 414                 return;
 415
 416         switch (dpp_inst) {
 417         case 0: /* DPP0 */
 418                 REG_UPDATE(DOMAIN1_PG_CONFIG,
 419                                 DOMAIN1_POWER_GATE, power_gate);
 420
 421                 REG_WAIT(DOMAIN1_PG_STATUS,
 422                                 DOMAIN1_PGFSM_PWR_STATUS, pwr_status,
 423                                 1, 1000);
 424                 break;
 425         case 1: /* DPP1 */
 426                 REG_UPDATE(DOMAIN3_PG_CONFIG,
 427                                 DOMAIN3_POWER_GATE, power_gate);
 428
 429                 REG_WAIT(DOMAIN3_PG_STATUS,
 430                                 DOMAIN3_PGFSM_PWR_STATUS, pwr_status,
 431                                 1, 1000);
 432                 break;
 433         case 2: /* DPP2 */
 434                 REG_UPDATE(DOMAIN5_PG_CONFIG,
 435                                 DOMAIN5_POWER_GATE, power_gate);
 436
 437                 REG_WAIT(DOMAIN5_PG_STATUS,
 438                                 DOMAIN5_PGFSM_PWR_STATUS, pwr_status,
 439                                 1, 1000);
 440                 break;
 441         case 3: /* DPP3 */
 442                 REG_UPDATE(DOMAIN7_PG_CONFIG,
 443                                 DOMAIN7_POWER_GATE, power_gate);
 444
 445                 REG_WAIT(DOMAIN7_PG_STATUS,
 446                                 DOMAIN7_PGFSM_PWR_STATUS, pwr_status,
 447                                 1, 1000);
 448                 break;
 449         case 4: /* DPP4 */
 450                 REG_UPDATE(DOMAIN9_PG_CONFIG,
 451                                 DOMAIN9_POWER_GATE, power_gate);
 452
 453                 REG_WAIT(DOMAIN9_PG_STATUS,
 454                                 DOMAIN9_PGFSM_PWR_STATUS, pwr_status,
 455                                 1, 1000);
 456                 break;
 457         case 5: /* DPP5 */
 458                 /*
 459                  * Do not power gate DPP5, should be left at HW default, power on permanently.
 460                  * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard
 461                  * reset.
 462                  * REG_UPDATE(DOMAIN11_PG_CONFIG,
 463                  *              DOMAIN11_POWER_GATE, power_gate);
 464                  *
 465                  * REG_WAIT(DOMAIN11_PG_STATUS,
 466                  *              DOMAIN11_PGFSM_PWR_STATUS, pwr_status,
 467                  *              1, 1000);
 468                  */
 469                 break;
 470         default:
 471                 BREAK_TO_DEBUGGER();
 472                 break;
 473         }
 474 }
 475
 476
 477 void dcn20_hubp_pg_control(
 478                 struct dce_hwseq *hws,
 479                 unsigned int hubp_inst,
 480                 bool power_on)
 481 {
 482         uint32_t power_gate = power_on ? 0 : 1;
 483         uint32_t pwr_status = power_on ? 0 : 2;
 484
 485         if (hws->ctx->dc->debug.disable_hubp_power_gate)
 486                 return;
 487         if (REG(DOMAIN0_PG_CONFIG) == 0)
 488                 return;
 489
 490         switch (hubp_inst) {
 491         case 0: /* DCHUBP0 */
 492                 REG_UPDATE(DOMAIN0_PG_CONFIG,
 493                                 DOMAIN0_POWER_GATE, power_gate);
 494
 495                 REG_WAIT(DOMAIN0_PG_STATUS,
 496                                 DOMAIN0_PGFSM_PWR_STATUS, pwr_status,
 497                                 1, 1000);
 498                 break;
 499         case 1: /* DCHUBP1 */
 500                 REG_UPDATE(DOMAIN2_PG_CONFIG,
 501                                 DOMAIN2_POWER_GATE, power_gate);
 502
 503                 REG_WAIT(DOMAIN2_PG_STATUS,
 504                                 DOMAIN2_PGFSM_PWR_STATUS, pwr_status,
 505                                 1, 1000);
 506                 break;
 507         case 2: /* DCHUBP2 */
 508                 REG_UPDATE(DOMAIN4_PG_CONFIG,
 509                                 DOMAIN4_POWER_GATE, power_gate);
 510
 511                 REG_WAIT(DOMAIN4_PG_STATUS,
 512                                 DOMAIN4_PGFSM_PWR_STATUS, pwr_status,
 513                                 1, 1000);
 514                 break;
 515         case 3: /* DCHUBP3 */
 516                 REG_UPDATE(DOMAIN6_PG_CONFIG,
 517                                 DOMAIN6_POWER_GATE, power_gate);
 518
 519                 REG_WAIT(DOMAIN6_PG_STATUS,
 520                                 DOMAIN6_PGFSM_PWR_STATUS, pwr_status,
 521                                 1, 1000);
 522                 break;
 523         case 4: /* DCHUBP4 */
 524                 REG_UPDATE(DOMAIN8_PG_CONFIG,
 525                                 DOMAIN8_POWER_GATE, power_gate);
 526
 527                 REG_WAIT(DOMAIN8_PG_STATUS,
 528                                 DOMAIN8_PGFSM_PWR_STATUS, pwr_status,
 529                                 1, 1000);
 530                 break;
 531         case 5: /* DCHUBP5 */
 532                 /*
 533                  * Do not power gate DCHUB5, should be left at HW default, power on permanently.
 534                  * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard
 535                  * reset.
 536                  * REG_UPDATE(DOMAIN10_PG_CONFIG,
 537                  *              DOMAIN10_POWER_GATE, power_gate);
 538                  *
 539                  * REG_WAIT(DOMAIN10_PG_STATUS,
 540                  *              DOMAIN10_PGFSM_PWR_STATUS, pwr_status,
 541                  *              1, 1000);
 542                  */
 543                 break;
 544         default:
 545                 BREAK_TO_DEBUGGER();
 546                 break;
 547         }
 548 }
 549
 550
 551 /* disable HW used by plane.
 552  * note:  cannot disable until disconnect is complete
 553  */
 554 void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
 555 {
 556         struct dce_hwseq *hws = dc->hwseq;
 557         struct hubp *hubp = pipe_ctx->plane_res.hubp;
 558         struct dpp *dpp = pipe_ctx->plane_res.dpp;
 559
 560         dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);
 561
 562         /* In flip immediate with pipe splitting case GSL is used for
 563          * synchronization so we must disable it when the plane is disabled.
 564          */
 565         if (pipe_ctx->stream_res.gsl_group != 0)
 566                 dcn20_setup_gsl_group_as_lock(dc, pipe_ctx, false);
 567
 568         dc->hwss.set_flip_control_gsl(pipe_ctx, false);
 569
 570         hubp->funcs->hubp_clk_cntl(hubp, false);
 571
 572         dpp->funcs->dpp_dppclk_control(dpp, false, false);
 573
 574         hubp->power_gated = true;
 575         dc->optimized_required = false; /* We're powering off, no need to optimize */
 576
 577         hws->funcs.plane_atomic_power_down(dc,
 578                         pipe_ctx->plane_res.dpp,
 579                         pipe_ctx->plane_res.hubp);
 580
 581         pipe_ctx->stream = NULL;
 582         memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res));
 583         memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res));
 584         pipe_ctx->top_pipe = NULL;
 585         pipe_ctx->bottom_pipe = NULL;
 586         pipe_ctx->plane_state = NULL;
 587 }
 588
 589
 590 void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
 591 {
 592         DC_LOGGER_INIT(dc->ctx->logger);
 593
 594         if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)
 595                 return;
 596
 597         dcn20_plane_atomic_disable(dc, pipe_ctx);
 598
 599         DC_LOG_DC("Power down front end %d\n",
 600                                         pipe_ctx->pipe_idx);
 601 }
 602
 603 enum dc_status dcn20_enable_stream_timing(
 604                 struct pipe_ctx *pipe_ctx,
 605                 struct dc_state *context,
 606                 struct dc *dc)
 607 {
 608         struct dce_hwseq *hws = dc->hwseq;
 609         struct dc_stream_state *stream = pipe_ctx->stream;
 610         struct drr_params params = {0};
 611         unsigned int event_triggers = 0;
 612         struct pipe_ctx *odm_pipe;
 613         int opp_cnt = 1;
 614         int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst };
 615
 616         /* by upper caller loop, pipe0 is parent pipe and be called first.
 617          * back end is set up by for pipe0. Other children pipe share back end
 618          * with pipe 0. No program is needed.
 619          */
 620         if (pipe_ctx->top_pipe != NULL)
 621                 return DC_OK;
 622
 623         /* TODO check if timing_changed, disable stream if timing changed */
 624
 625         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
 626                 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;
 627                 opp_cnt++;
 628         }
 629
 630         if (opp_cnt > 1)
 631                 pipe_ctx->stream_res.tg->funcs->set_odm_combine(
 632                                 pipe_ctx->stream_res.tg,
 633                                 opp_inst, opp_cnt,
 634                                 &pipe_ctx->stream->timing);
 635
 636         /* HW program guide assume display already disable
 637          * by unplug sequence. OTG assume stop.
 638          */
 639         pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true);
 640
 641         if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
 642                         pipe_ctx->clock_source,
 643                         &pipe_ctx->stream_res.pix_clk_params,
 644                         &pipe_ctx->pll_settings)) {
 645                 BREAK_TO_DEBUGGER();
 646                 return DC_ERROR_UNEXPECTED;
 647         }
 648
 649         pipe_ctx->stream_res.tg->funcs->program_timing(
 650                         pipe_ctx->stream_res.tg,
 651                         &stream->timing,
 652                         pipe_ctx->pipe_dlg_param.vready_offset,
 653                         pipe_ctx->pipe_dlg_param.vstartup_start,
 654                         pipe_ctx->pipe_dlg_param.vupdate_offset,
 655                         pipe_ctx->pipe_dlg_param.vupdate_width,
 656                         pipe_ctx->stream->signal,
 657                         true);
 658
 659         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
 660                 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control(
 661                                 odm_pipe->stream_res.opp,
 662                                 true);
 663
 664         pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
 665                         pipe_ctx->stream_res.opp,
 666                         true);
 667
 668         hws->funcs.blank_pixel_data(dc, pipe_ctx, true);
 669
 670         /* VTG is  within DCHUB command block. DCFCLK is always on */
 671         if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {
 672                 BREAK_TO_DEBUGGER();
 673                 return DC_ERROR_UNEXPECTED;
 674         }
 675
 676         hws->funcs.wait_for_blank_complete(pipe_ctx->stream_res.opp);
 677
 678         params.vertical_total_min = stream->adjust.v_total_min;
 679         params.vertical_total_max = stream->adjust.v_total_max;
 680         params.vertical_total_mid = stream->adjust.v_total_mid;
 681         params.vertical_total_mid_frame_num = stream->adjust.v_total_mid_frame_num;
 682         if (pipe_ctx->stream_res.tg->funcs->set_drr)
 683                 pipe_ctx->stream_res.tg->funcs->set_drr(
 684                         pipe_ctx->stream_res.tg, &params);
 685
 686         // DRR should set trigger event to monitor surface update event
 687         if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0)
 688                 event_triggers = 0x80;
 689         if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)
 690                 pipe_ctx->stream_res.tg->funcs->set_static_screen_control(
 691                                 pipe_ctx->stream_res.tg, event_triggers);
 692
 693         /* TODO program crtc source select for non-virtual signal*/
 694         /* TODO program FMT */
 695         /* TODO setup link_enc */
 696         /* TODO set stream attributes */
 697         /* TODO program audio */
 698         /* TODO enable stream if timing changed */
 699         /* TODO unblank stream if DP */
 700
 701         return DC_OK;
 702 }
 703
 704 void dcn20_program_output_csc(struct dc *dc,
 705                 struct pipe_ctx *pipe_ctx,
 706                 enum dc_color_space colorspace,
 707                 uint16_t *matrix,
 708                 int opp_id)
 709 {
 710         struct mpc *mpc = dc->res_pool->mpc;
 711         enum mpc_output_csc_mode ocsc_mode = MPC_OUTPUT_CSC_COEF_A;
 712         int mpcc_id = pipe_ctx->plane_res.hubp->inst;
 713
 714         if (mpc->funcs->power_on_mpc_mem_pwr)
 715                 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true);
 716
 717         if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
 718                 if (mpc->funcs->set_output_csc != NULL)
 719                         mpc->funcs->set_output_csc(mpc,
 720                                         opp_id,
 721                                         matrix,
 722                                         ocsc_mode);
 723         } else {
 724                 if (mpc->funcs->set_ocsc_default != NULL)
 725                         mpc->funcs->set_ocsc_default(mpc,
 726                                         opp_id,
 727                                         colorspace,
 728                                         ocsc_mode);
 729         }
 730 }
 731
 732 bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
 733                                 const struct dc_stream_state *stream)
 734 {
 735         int mpcc_id = pipe_ctx->plane_res.hubp->inst;
 736         struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
 737         struct pwl_params *params = NULL;
 738         /*
 739          * program OGAM only for the top pipe
 740          * if there is a pipe split then fix diagnostic is required:
 741          * how to pass OGAM parameter for stream.
 742          * if programming for all pipes is required then remove condition
 743          * pipe_ctx->top_pipe == NULL ,but then fix the diagnostic.
 744          */
 745         if (mpc->funcs->power_on_mpc_mem_pwr)
 746                 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true);
 747         if (pipe_ctx->top_pipe == NULL
 748                         && mpc->funcs->set_output_gamma && stream->out_transfer_func) {
 749                 if (stream->out_transfer_func->type == TF_TYPE_HWPWL)
 750                         params = &stream->out_transfer_func->pwl;
 751                 else if (pipe_ctx->stream->out_transfer_func->type ==
 752                         TF_TYPE_DISTRIBUTED_POINTS &&
 753                         cm_helper_translate_curve_to_hw_format(
 754                         stream->out_transfer_func,
 755                         &mpc->blender_params, false))
 756                         params = &mpc->blender_params;
 757                 /*
 758                  * there is no ROM
 759                  */
 760                 if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED)
 761                         BREAK_TO_DEBUGGER();
 762         }
 763         /*
 764          * if above if is not executed then 'params' equal to 0 and set in bypass
 765          */
 766         mpc->funcs->set_output_gamma(mpc, mpcc_id, params);
 767
 768         return true;
 769 }
 770
 771 bool dcn20_set_blend_lut(
 772         struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
 773 {
 774         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
 775         bool result = true;
 776         struct pwl_params *blend_lut = NULL;
 777
 778         if (plane_state->blend_tf) {
 779                 if (plane_state->blend_tf->type == TF_TYPE_HWPWL)
 780                         blend_lut = &plane_state->blend_tf->pwl;
 781                 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) {
 782                         cm_helper_translate_curve_to_hw_format(
 783                                         plane_state->blend_tf,
 784                                         &dpp_base->regamma_params, false);
 785                         blend_lut = &dpp_base->regamma_params;
 786                 }
 787         }
 788         result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut);
 789
 790         return result;
 791 }
 792
 793 bool dcn20_set_shaper_3dlut(
 794         struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
 795 {
 796         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
 797         bool result = true;
 798         struct pwl_params *shaper_lut = NULL;
 799
 800         if (plane_state->in_shaper_func) {
 801                 if (plane_state->in_shaper_func->type == TF_TYPE_HWPWL)
 802                         shaper_lut = &plane_state->in_shaper_func->pwl;
 803                 else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) {
 804                         cm_helper_translate_curve_to_hw_format(
 805                                         plane_state->in_shaper_func,
 806                                         &dpp_base->shaper_params, true);
 807                         shaper_lut = &dpp_base->shaper_params;
 808                 }
 809         }
 810
 811         result = dpp_base->funcs->dpp_program_shaper_lut(dpp_base, shaper_lut);
 812         if (plane_state->lut3d_func &&
 813                 plane_state->lut3d_func->state.bits.initialized == 1)
 814                 result = dpp_base->funcs->dpp_program_3dlut(dpp_base,
 815                                                                 &plane_state->lut3d_func->lut_3d);
 816         else
 817                 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, NULL);
 818
 819         return result;
 820 }
 821
 822 bool dcn20_set_input_transfer_func(struct dc *dc,
 823                                 struct pipe_ctx *pipe_ctx,
 824                                 const struct dc_plane_state *plane_state)
 825 {
 826         struct dce_hwseq *hws = dc->hwseq;
 827         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
 828         const struct dc_transfer_func *tf = NULL;
 829         bool result = true;
 830         bool use_degamma_ram = false;
 831
 832         if (dpp_base == NULL || plane_state == NULL)
 833                 return false;
 834
 835         hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state);
 836         hws->funcs.set_blend_lut(pipe_ctx, plane_state);
 837
 838         if (plane_state->in_transfer_func)
 839                 tf = plane_state->in_transfer_func;
 840
 841
 842         if (tf == NULL) {
 843                 dpp_base->funcs->dpp_set_degamma(dpp_base,
 844                                 IPP_DEGAMMA_MODE_BYPASS);
 845                 return true;
 846         }
 847
 848         if (tf->type == TF_TYPE_HWPWL || tf->type == TF_TYPE_DISTRIBUTED_POINTS)
 849                 use_degamma_ram = true;
 850
 851         if (use_degamma_ram == true) {
 852                 if (tf->type == TF_TYPE_HWPWL)
 853                         dpp_base->funcs->dpp_program_degamma_pwl(dpp_base,
 854                                         &tf->pwl);
 855                 else if (tf->type == TF_TYPE_DISTRIBUTED_POINTS) {
 856                         cm_helper_translate_curve_to_degamma_hw_format(tf,
 857                                         &dpp_base->degamma_params);
 858                         dpp_base->funcs->dpp_program_degamma_pwl(dpp_base,
 859                                 &dpp_base->degamma_params);
 860                 }
 861                 return true;
 862         }
 863         /* handle here the optimized cases when de-gamma ROM could be used.
 864          *
 865          */
 866         if (tf->type == TF_TYPE_PREDEFINED) {
 867                 switch (tf->tf) {
 868                 case TRANSFER_FUNCTION_SRGB:
 869                         dpp_base->funcs->dpp_set_degamma(dpp_base,
 870                                         IPP_DEGAMMA_MODE_HW_sRGB);
 871                         break;
 872                 case TRANSFER_FUNCTION_BT709:
 873                         dpp_base->funcs->dpp_set_degamma(dpp_base,
 874                                         IPP_DEGAMMA_MODE_HW_xvYCC);
 875                         break;
 876                 case TRANSFER_FUNCTION_LINEAR:
 877                         dpp_base->funcs->dpp_set_degamma(dpp_base,
 878                                         IPP_DEGAMMA_MODE_BYPASS);
 879                         break;
 880                 case TRANSFER_FUNCTION_PQ:
 881                         dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_USER_PWL);
 882                         cm_helper_translate_curve_to_degamma_hw_format(tf, &dpp_base->degamma_params);
 883                         dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, &dpp_base->degamma_params);
 884                         result = true;
 885                         break;
 886                 default:
 887                         result = false;
 888                         break;
 889                 }
 890         } else if (tf->type == TF_TYPE_BYPASS)
 891                 dpp_base->funcs->dpp_set_degamma(dpp_base,
 892                                 IPP_DEGAMMA_MODE_BYPASS);
 893         else {
 894                 /*
 895                  * if we are here, we did not handle correctly.
 896                  * fix is required for this use case
 897                  */
 898                 BREAK_TO_DEBUGGER();
 899                 dpp_base->funcs->dpp_set_degamma(dpp_base,
 900                                 IPP_DEGAMMA_MODE_BYPASS);
 901         }
 902
 903         return result;
 904 }
 905
 906 void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)
 907 {
 908         struct pipe_ctx *odm_pipe;
 909         int opp_cnt = 1;
 910         int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst };
 911
 912         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
 913                 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;
 914                 opp_cnt++;
 915         }
 916
 917         if (opp_cnt > 1)
 918                 pipe_ctx->stream_res.tg->funcs->set_odm_combine(
 919                                 pipe_ctx->stream_res.tg,
 920                                 opp_inst, opp_cnt,
 921                                 &pipe_ctx->stream->timing);
 922         else
 923                 pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
 924                                 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
 925 }
 926
 927 void dcn20_blank_pixel_data(
 928                 struct dc *dc,
 929                 struct pipe_ctx *pipe_ctx,
 930                 bool blank)
 931 {
 932         struct tg_color black_color = {0};
 933         struct stream_resource *stream_res = &pipe_ctx->stream_res;
 934         struct dc_stream_state *stream = pipe_ctx->stream;
 935         enum dc_color_space color_space = stream->output_color_space;
 936         enum controller_dp_test_pattern test_pattern = CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR;
 937         enum controller_dp_color_space test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED;
 938         struct pipe_ctx *odm_pipe;
 939         int odm_cnt = 1;
 940
 941         int width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;
 942         int height = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top;
 943
 944         /* get opp dpg blank color */
 945         color_space_to_black_color(dc, color_space, &black_color);
 946
 947         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
 948                 odm_cnt++;
 949
 950         width = width / odm_cnt;
 951
 952         if (blank) {
 953                 if (stream_res->abm)
 954                         stream_res->abm->funcs->set_abm_immediate_disable(stream_res->abm);
 955
 956                 if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) {
 957                         test_pattern = CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
 958                         test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_RGB;
 959                 }
 960         } else {
 961                 test_pattern = CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
 962         }
 963
 964         stream_res->opp->funcs->opp_set_disp_pattern_generator(
 965                         stream_res->opp,
 966                         test_pattern,
 967                         test_pattern_color_space,
 968                         stream->timing.display_color_depth,
 969                         &black_color,
 970                         width,
 971                         height);
 972
 973         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
 974                 odm_pipe->stream_res.opp->funcs->opp_set_disp_pattern_generator(
 975                                 odm_pipe->stream_res.opp,
 976                                 dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE && blank ?
 977                                                 CONTROLLER_DP_TEST_PATTERN_COLORRAMP : test_pattern,
 978                                 test_pattern_color_space,
 979                                 stream->timing.display_color_depth,
 980                                 &black_color,
 981                                 width,
 982                                 height);
 983         }
 984
 985         if (!blank)
 986                 if (stream_res->abm) {
 987                         stream_res->abm->funcs->set_pipe(stream_res->abm, stream_res->tg->inst + 1);
 988                         stream_res->abm->funcs->set_abm_level(stream_res->abm, stream->abm_level);
 989                 }
 990 }
 991
 992
 993 static void dcn20_power_on_plane(
 994         struct dce_hwseq *hws,
 995         struct pipe_ctx *pipe_ctx)
 996 {
 997         DC_LOGGER_INIT(hws->ctx->logger);
 998         if (REG(DC_IP_REQUEST_CNTL)) {
 999                 REG_SET(DC_IP_REQUEST_CNTL, 0,
1000                                 IP_REQUEST_EN, 1);
1001                 dcn20_dpp_pg_control(hws, pipe_ctx->plane_res.dpp->inst, true);
1002                 dcn20_hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, true);
1003                 REG_SET(DC_IP_REQUEST_CNTL, 0,
1004                                 IP_REQUEST_EN, 0);
1005                 DC_LOG_DEBUG(
1006                                 "Un-gated front end for pipe %d\n", pipe_ctx->plane_res.hubp->inst);
1007         }
1008 }
1009
1010 void dcn20_enable_plane(
1011         struct dc *dc,
1012         struct pipe_ctx *pipe_ctx,
1013         struct dc_state *context)
1014 {
1015         //if (dc->debug.sanity_checks) {
1016         //      dcn10_verify_allow_pstate_change_high(dc);
1017         //}
1018         dcn20_power_on_plane(dc->hwseq, pipe_ctx);
1019
1020         /* enable DCFCLK current DCHUB */
1021         pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);
1022
1023         /* initialize HUBP on power up */
1024         pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp);
1025
1026         /* make sure OPP_PIPE_CLOCK_EN = 1 */
1027         pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
1028                         pipe_ctx->stream_res.opp,
1029                         true);
1030
1031 /* TODO: enable/disable in dm as per update type.
1032         if (plane_state) {
1033                 DC_LOG_DC(dc->ctx->logger,
1034                                 "Pipe:%d 0x%x: addr hi:0x%x, "
1035                                 "addr low:0x%x, "
1036                                 "src: %d, %d, %d,"
1037                                 " %d; dst: %d, %d, %d, %d;\n",
1038                                 pipe_ctx->pipe_idx,
1039                                 plane_state,
1040                                 plane_state->address.grph.addr.high_part,
1041                                 plane_state->address.grph.addr.low_part,
1042                                 plane_state->src_rect.x,
1043                                 plane_state->src_rect.y,
1044                                 plane_state->src_rect.width,
1045                                 plane_state->src_rect.height,
1046                                 plane_state->dst_rect.x,
1047                                 plane_state->dst_rect.y,
1048                                 plane_state->dst_rect.width,
1049                                 plane_state->dst_rect.height);
1050
1051                 DC_LOG_DC(dc->ctx->logger,
1052                                 "Pipe %d: width, height, x, y         format:%d\n"
1053                                 "viewport:%d, %d, %d, %d\n"
1054                                 "recout:  %d, %d, %d, %d\n",
1055                                 pipe_ctx->pipe_idx,
1056                                 plane_state->format,
1057                                 pipe_ctx->plane_res.scl_data.viewport.width,
1058                                 pipe_ctx->plane_res.scl_data.viewport.height,
1059                                 pipe_ctx->plane_res.scl_data.viewport.x,
1060                                 pipe_ctx->plane_res.scl_data.viewport.y,
1061                                 pipe_ctx->plane_res.scl_data.recout.width,
1062                                 pipe_ctx->plane_res.scl_data.recout.height,
1063                                 pipe_ctx->plane_res.scl_data.recout.x,
1064                                 pipe_ctx->plane_res.scl_data.recout.y);
1065                 print_rq_dlg_ttu(dc, pipe_ctx);
1066         }
1067 */
1068         if (dc->vm_pa_config.valid) {
1069                 struct vm_system_aperture_param apt;
1070
1071                 apt.sys_default.quad_part = 0;
1072
1073                 apt.sys_low.quad_part = dc->vm_pa_config.system_aperture.start_addr;
1074                 apt.sys_high.quad_part = dc->vm_pa_config.system_aperture.end_addr;
1075
1076                 // Program system aperture settings
1077                 pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt);
1078         }
1079
1080 //      if (dc->debug.sanity_checks) {
1081 //              dcn10_verify_allow_pstate_change_high(dc);
1082 //      }
1083 }
1084
1085
1086 void dcn20_pipe_control_lock_global(
1087                 struct dc *dc,
1088                 struct pipe_ctx *pipe,
1089                 bool lock)
1090 {
1091         if (lock) {
1092                 pipe->stream_res.tg->funcs->lock_doublebuffer_enable(
1093                                 pipe->stream_res.tg);
1094                 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);
1095         } else {
1096                 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);
1097                 pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg,
1098                                 CRTC_STATE_VACTIVE);
1099                 pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg,
1100                                 CRTC_STATE_VBLANK);
1101                 pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg,
1102                                 CRTC_STATE_VACTIVE);
1103                 pipe->stream_res.tg->funcs->lock_doublebuffer_disable(
1104                                 pipe->stream_res.tg);
1105         }
1106 }
1107
1108 void dcn20_pipe_control_lock(
1109         struct dc *dc,
1110         struct pipe_ctx *pipe,
1111         bool lock)
1112 {
1113         bool flip_immediate = false;
1114
1115         /* use TG master update lock to lock everything on the TG
1116          * therefore only top pipe need to lock
1117          */
1118         if (pipe->top_pipe)
1119                 return;
1120
1121         if (pipe->plane_state != NULL)
1122                 flip_immediate = pipe->plane_state->flip_immediate;
1123
1124         if (flip_immediate && lock) {
1125                 const int TIMEOUT_FOR_FLIP_PENDING = 100000;
1126                 int i;
1127
1128                 for (i = 0; i < TIMEOUT_FOR_FLIP_PENDING; ++i) {
1129                         if (!pipe->plane_res.hubp->funcs->hubp_is_flip_pending(pipe->plane_res.hubp))
1130                                 break;
1131                         udelay(1);
1132                 }
1133
1134                 if (pipe->bottom_pipe != NULL) {
1135                         for (i = 0; i < TIMEOUT_FOR_FLIP_PENDING; ++i) {
1136                                 if (!pipe->bottom_pipe->plane_res.hubp->funcs->hubp_is_flip_pending(pipe->bottom_pipe->plane_res.hubp))
1137                                         break;
1138                                 udelay(1);
1139                         }
1140                 }
1141         }
1142
1143         /* In flip immediate and pipe splitting case, we need to use GSL
1144          * for synchronization. Only do setup on locking and on flip type change.
1145          */
1146         if (lock && pipe->bottom_pipe != NULL)
1147                 if ((flip_immediate && pipe->stream_res.gsl_group == 0) ||
1148                     (!flip_immediate && pipe->stream_res.gsl_group > 0))
1149                         dcn20_setup_gsl_group_as_lock(dc, pipe, flip_immediate);
1150
1151         if (pipe->plane_state != NULL && pipe->plane_state->triplebuffer_flips) {
1152                 if (lock)
1153                         pipe->stream_res.tg->funcs->triplebuffer_lock(pipe->stream_res.tg);
1154                 else
1155                         pipe->stream_res.tg->funcs->triplebuffer_unlock(pipe->stream_res.tg);
1156         } else {
1157                 if (lock)
1158                         pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);
1159                 else
1160                         pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);
1161         }
1162 }
1163
1164 static void dcn20_detect_pipe_changes(struct pipe_ctx *old_pipe, struct pipe_ctx *new_pipe)
1165 {
1166         new_pipe->update_flags.raw = 0;
1167
1168         /* Exit on unchanged, unused pipe */
1169         if (!old_pipe->plane_state && !new_pipe->plane_state)
1170                 return;
1171         /* Detect pipe enable/disable */
1172         if (!old_pipe->plane_state && new_pipe->plane_state) {
1173                 new_pipe->update_flags.bits.enable = 1;
1174                 new_pipe->update_flags.bits.mpcc = 1;
1175                 new_pipe->update_flags.bits.dppclk = 1;
1176                 new_pipe->update_flags.bits.hubp_interdependent = 1;
1177                 new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1;
1178                 new_pipe->update_flags.bits.gamut_remap = 1;
1179                 new_pipe->update_flags.bits.scaler = 1;
1180                 new_pipe->update_flags.bits.viewport = 1;
1181                 if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) {
1182                         new_pipe->update_flags.bits.odm = 1;
1183                         new_pipe->update_flags.bits.global_sync = 1;
1184                 }
1185                 return;
1186         }
1187         if (old_pipe->plane_state && !new_pipe->plane_state) {
1188                 new_pipe->update_flags.bits.disable = 1;
1189                 return;
1190         }
1191
1192         /* Detect top pipe only changes */
1193         if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) {
1194                 /* Detect odm changes */
1195                 if ((old_pipe->next_odm_pipe && new_pipe->next_odm_pipe
1196                         && old_pipe->next_odm_pipe->pipe_idx != new_pipe->next_odm_pipe->pipe_idx)
1197                                 || (!old_pipe->next_odm_pipe && new_pipe->next_odm_pipe)
1198                                 || (old_pipe->next_odm_pipe && !new_pipe->next_odm_pipe)
1199                                 || old_pipe->stream_res.opp != new_pipe->stream_res.opp)
1200                         new_pipe->update_flags.bits.odm = 1;
1201
1202                 /* Detect global sync changes */
1203                 if (old_pipe->pipe_dlg_param.vready_offset != new_pipe->pipe_dlg_param.vready_offset
1204                                 || old_pipe->pipe_dlg_param.vstartup_start != new_pipe->pipe_dlg_param.vstartup_start
1205                                 || old_pipe->pipe_dlg_param.vupdate_offset != new_pipe->pipe_dlg_param.vupdate_offset
1206                                 || old_pipe->pipe_dlg_param.vupdate_width != new_pipe->pipe_dlg_param.vupdate_width)
1207                         new_pipe->update_flags.bits.global_sync = 1;
1208         }
1209
1210         /*
1211          * Detect opp / tg change, only set on change, not on enable
1212          * Assume mpcc inst = pipe index, if not this code needs to be updated
1213          * since mpcc is what is affected by these. In fact all of our sequence
1214          * makes this assumption at the moment with how hubp reset is matched to
1215          * same index mpcc reset.
1216          */
1217         if (old_pipe->stream_res.opp != new_pipe->stream_res.opp)
1218                 new_pipe->update_flags.bits.opp_changed = 1;
1219         if (old_pipe->stream_res.tg != new_pipe->stream_res.tg)
1220                 new_pipe->update_flags.bits.tg_changed = 1;
1221
1222         /* Detect mpcc blending changes, only dpp inst and bot matter here */
1223         if (old_pipe->plane_res.dpp != new_pipe->plane_res.dpp
1224                         || old_pipe->stream_res.opp != new_pipe->stream_res.opp
1225                         || (!old_pipe->bottom_pipe && new_pipe->bottom_pipe)
1226                         || (old_pipe->bottom_pipe && !new_pipe->bottom_pipe)
1227                         || (old_pipe->bottom_pipe && new_pipe->bottom_pipe
1228                                 && old_pipe->bottom_pipe->plane_res.mpcc_inst
1229                                         != new_pipe->bottom_pipe->plane_res.mpcc_inst))
1230                 new_pipe->update_flags.bits.mpcc = 1;
1231
1232         /* Detect dppclk change */
1233         if (old_pipe->plane_res.bw.dppclk_khz != new_pipe->plane_res.bw.dppclk_khz)
1234                 new_pipe->update_flags.bits.dppclk = 1;
1235
1236         /* Check for scl update */
1237         if (memcmp(&old_pipe->plane_res.scl_data, &new_pipe->plane_res.scl_data, sizeof(struct scaler_data)))
1238                         new_pipe->update_flags.bits.scaler = 1;
1239         /* Check for vp update */
1240         if (memcmp(&old_pipe->plane_res.scl_data.viewport, &new_pipe->plane_res.scl_data.viewport, sizeof(struct rect))
1241                         || memcmp(&old_pipe->plane_res.scl_data.viewport_c,
1242                                 &new_pipe->plane_res.scl_data.viewport_c, sizeof(struct rect)))
1243                 new_pipe->update_flags.bits.viewport = 1;
1244
1245         /* Detect dlg/ttu/rq updates */
1246         {
1247                 struct _vcs_dpi_display_dlg_regs_st old_dlg_attr = old_pipe->dlg_regs;
1248                 struct _vcs_dpi_display_ttu_regs_st old_ttu_attr = old_pipe->ttu_regs;
1249                 struct _vcs_dpi_display_dlg_regs_st *new_dlg_attr = &new_pipe->dlg_regs;
1250                 struct _vcs_dpi_display_ttu_regs_st *new_ttu_attr = &new_pipe->ttu_regs;
1251
1252                 /* Detect pipe interdependent updates */
1253                 if (old_dlg_attr.dst_y_prefetch != new_dlg_attr->dst_y_prefetch ||
1254                                 old_dlg_attr.vratio_prefetch != new_dlg_attr->vratio_prefetch ||
1255                                 old_dlg_attr.vratio_prefetch_c != new_dlg_attr->vratio_prefetch_c ||
1256                                 old_dlg_attr.dst_y_per_vm_vblank != new_dlg_attr->dst_y_per_vm_vblank ||
1257                                 old_dlg_attr.dst_y_per_row_vblank != new_dlg_attr->dst_y_per_row_vblank ||
1258                                 old_dlg_attr.dst_y_per_vm_flip != new_dlg_attr->dst_y_per_vm_flip ||
1259                                 old_dlg_attr.dst_y_per_row_flip != new_dlg_attr->dst_y_per_row_flip ||
1260                                 old_dlg_attr.refcyc_per_meta_chunk_vblank_l != new_dlg_attr->refcyc_per_meta_chunk_vblank_l ||
1261                                 old_dlg_attr.refcyc_per_meta_chunk_vblank_c != new_dlg_attr->refcyc_per_meta_chunk_vblank_c ||
1262                                 old_dlg_attr.refcyc_per_meta_chunk_flip_l != new_dlg_attr->refcyc_per_meta_chunk_flip_l ||
1263                                 old_dlg_attr.refcyc_per_line_delivery_pre_l != new_dlg_attr->refcyc_per_line_delivery_pre_l ||
1264                                 old_dlg_attr.refcyc_per_line_delivery_pre_c != new_dlg_attr->refcyc_per_line_delivery_pre_c ||
1265                                 old_ttu_attr.refcyc_per_req_delivery_pre_l != new_ttu_attr->refcyc_per_req_delivery_pre_l ||
1266                                 old_ttu_attr.refcyc_per_req_delivery_pre_c != new_ttu_attr->refcyc_per_req_delivery_pre_c ||
1267                                 old_ttu_attr.refcyc_per_req_delivery_pre_cur0 != new_ttu_attr->refcyc_per_req_delivery_pre_cur0 ||
1268                                 old_ttu_attr.refcyc_per_req_delivery_pre_cur1 != new_ttu_attr->refcyc_per_req_delivery_pre_cur1 ||
1269                                 old_ttu_attr.min_ttu_vblank != new_ttu_attr->min_ttu_vblank ||
1270                                 old_ttu_attr.qos_level_flip != new_ttu_attr->qos_level_flip) {
1271                         old_dlg_attr.dst_y_prefetch = new_dlg_attr->dst_y_prefetch;
1272                         old_dlg_attr.vratio_prefetch = new_dlg_attr->vratio_prefetch;
1273                         old_dlg_attr.vratio_prefetch_c = new_dlg_attr->vratio_prefetch_c;
1274                         old_dlg_attr.dst_y_per_vm_vblank = new_dlg_attr->dst_y_per_vm_vblank;
1275                         old_dlg_attr.dst_y_per_row_vblank = new_dlg_attr->dst_y_per_row_vblank;
1276                         old_dlg_attr.dst_y_per_vm_flip = new_dlg_attr->dst_y_per_vm_flip;
1277                         old_dlg_attr.dst_y_per_row_flip = new_dlg_attr->dst_y_per_row_flip;
1278                         old_dlg_attr.refcyc_per_meta_chunk_vblank_l = new_dlg_attr->refcyc_per_meta_chunk_vblank_l;
1279                         old_dlg_attr.refcyc_per_meta_chunk_vblank_c = new_dlg_attr->refcyc_per_meta_chunk_vblank_c;
1280                         old_dlg_attr.refcyc_per_meta_chunk_flip_l = new_dlg_attr->refcyc_per_meta_chunk_flip_l;
1281                         old_dlg_attr.refcyc_per_line_delivery_pre_l = new_dlg_attr->refcyc_per_line_delivery_pre_l;
1282                         old_dlg_attr.refcyc_per_line_delivery_pre_c = new_dlg_attr->refcyc_per_line_delivery_pre_c;
1283                         old_ttu_attr.refcyc_per_req_delivery_pre_l = new_ttu_attr->refcyc_per_req_delivery_pre_l;
1284                         old_ttu_attr.refcyc_per_req_delivery_pre_c = new_ttu_attr->refcyc_per_req_delivery_pre_c;
1285                         old_ttu_attr.refcyc_per_req_delivery_pre_cur0 = new_ttu_attr->refcyc_per_req_delivery_pre_cur0;
1286                         old_ttu_attr.refcyc_per_req_delivery_pre_cur1 = new_ttu_attr->refcyc_per_req_delivery_pre_cur1;
1287                         old_ttu_attr.min_ttu_vblank = new_ttu_attr->min_ttu_vblank;
1288                         old_ttu_attr.qos_level_flip = new_ttu_attr->qos_level_flip;
1289                         new_pipe->update_flags.bits.hubp_interdependent = 1;
1290                 }
1291                 /* Detect any other updates to ttu/rq/dlg */
1292                 if (memcmp(&old_dlg_attr, &new_pipe->dlg_regs, sizeof(old_dlg_attr)) ||
1293                                 memcmp(&old_ttu_attr, &new_pipe->ttu_regs, sizeof(old_ttu_attr)) ||
1294                                 memcmp(&old_pipe->rq_regs, &new_pipe->rq_regs, sizeof(old_pipe->rq_regs)))
1295                         new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1;
1296         }
1297 }
1298
1299 static void dcn20_update_dchubp_dpp(
1300         struct dc *dc,
1301         struct pipe_ctx *pipe_ctx,
1302         struct dc_state *context)
1303 {
1304         struct dce_hwseq *hws = dc->hwseq;
1305         struct hubp *hubp = pipe_ctx->plane_res.hubp;
1306         struct dpp *dpp = pipe_ctx->plane_res.dpp;
1307         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1308         bool viewport_changed = false;
1309
1310         if (pipe_ctx->update_flags.bits.dppclk)
1311                 dpp->funcs->dpp_dppclk_control(dpp, false, true);
1312
1313         /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG
1314          * VTG is within DCHUBBUB which is commond block share by each pipe HUBP.
1315          * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG
1316          */
1317         if (pipe_ctx->update_flags.bits.hubp_rq_dlg_ttu) {
1318                 hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst);
1319
1320                 hubp->funcs->hubp_setup(
1321                         hubp,
1322                         &pipe_ctx->dlg_regs,
1323                         &pipe_ctx->ttu_regs,
1324                         &pipe_ctx->rq_regs,
1325                         &pipe_ctx->pipe_dlg_param);
1326         }
1327         if (pipe_ctx->update_flags.bits.hubp_interdependent)
1328                 hubp->funcs->hubp_setup_interdependent(
1329                         hubp,
1330                         &pipe_ctx->dlg_regs,
1331                         &pipe_ctx->ttu_regs);
1332
1333         if (pipe_ctx->update_flags.bits.enable ||
1334                         plane_state->update_flags.bits.bpp_change ||
1335                         plane_state->update_flags.bits.input_csc_change ||
1336                         plane_state->update_flags.bits.color_space_change ||
1337                         plane_state->update_flags.bits.coeff_reduction_change) {
1338                 struct dc_bias_and_scale bns_params = {0};
1339
1340                 // program the input csc
1341                 dpp->funcs->dpp_setup(dpp,
1342                                 plane_state->format,
1343                                 EXPANSION_MODE_ZERO,
1344                                 plane_state->input_csc_color_matrix,
1345                                 plane_state->color_space,
1346                                 NULL);
1347
1348                 if (dpp->funcs->dpp_program_bias_and_scale) {
1349                         //TODO :for CNVC set scale and bias registers if necessary
1350                         build_prescale_params(&bns_params, plane_state);
1351                         dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
1352                 }
1353         }
1354
1355         if (pipe_ctx->update_flags.bits.mpcc
1356                         || plane_state->update_flags.bits.global_alpha_change
1357                         || plane_state->update_flags.bits.per_pixel_alpha_change) {
1358                 // MPCC inst is equal to pipe index in practice
1359                 int mpcc_inst = hubp->inst;
1360                 int opp_inst;
1361                 int opp_count = dc->res_pool->pipe_count;
1362
1363                 for (opp_inst = 0; opp_inst < opp_count; opp_inst++) {
1364                         if (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst]) {
1365                                 dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst);
1366                                 dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false;
1367                                 break;
1368                         }
1369                 }
1370                 hws->funcs.update_mpcc(dc, pipe_ctx);
1371         }
1372
1373         if (pipe_ctx->update_flags.bits.scaler ||
1374                         plane_state->update_flags.bits.scaling_change ||
1375                         plane_state->update_flags.bits.position_change ||
1376                         plane_state->update_flags.bits.per_pixel_alpha_change ||
1377                         pipe_ctx->stream->update_flags.bits.scaling) {
1378                 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->plane_state->per_pixel_alpha;
1379                 ASSERT(pipe_ctx->plane_res.scl_data.lb_params.depth == LB_PIXEL_DEPTH_30BPP);
1380                 /* scaler configuration */
1381                 pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(
1382                                 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);
1383         }
1384
1385         if (pipe_ctx->update_flags.bits.viewport ||
1386                         (context == dc->current_state && plane_state->update_flags.bits.scaling_change) ||
1387                         (context == dc->current_state && pipe_ctx->stream->update_flags.bits.scaling)) {
1388
1389                 hubp->funcs->mem_program_viewport(
1390                         hubp,
1391                         &pipe_ctx->plane_res.scl_data.viewport,
1392                         &pipe_ctx->plane_res.scl_data.viewport_c);
1393                 viewport_changed = true;
1394         }
1395
1396         /* Any updates are handled in dc interface, just need to apply existing for plane enable */
1397         if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed ||
1398                         pipe_ctx->update_flags.bits.scaler || pipe_ctx->update_flags.bits.viewport)
1399                         && pipe_ctx->stream->cursor_attributes.address.quad_part != 0) {
1400                 dc->hwss.set_cursor_position(pipe_ctx);
1401                 dc->hwss.set_cursor_attribute(pipe_ctx);
1402
1403                 if (dc->hwss.set_cursor_sdr_white_level)
1404                         dc->hwss.set_cursor_sdr_white_level(pipe_ctx);
1405         }
1406
1407         /* Any updates are handled in dc interface, just need
1408          * to apply existing for plane enable / opp change */
1409         if (pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed
1410                         || pipe_ctx->stream->update_flags.bits.gamut_remap
1411                         || pipe_ctx->stream->update_flags.bits.out_csc) {
1412                         /* dpp/cm gamut remap*/
1413                         dc->hwss.program_gamut_remap(pipe_ctx);
1414
1415                 /*call the dcn2 method which uses mpc csc*/
1416                 dc->hwss.program_output_csc(dc,
1417                                 pipe_ctx,
1418                                 pipe_ctx->stream->output_color_space,
1419                                 pipe_ctx->stream->csc_color_matrix.matrix,
1420                                 hubp->opp_id);
1421         }
1422
1423         if (pipe_ctx->update_flags.bits.enable ||
1424                         pipe_ctx->update_flags.bits.opp_changed ||
1425                         plane_state->update_flags.bits.pixel_format_change ||
1426                         plane_state->update_flags.bits.horizontal_mirror_change ||
1427                         plane_state->update_flags.bits.rotation_change ||
1428                         plane_state->update_flags.bits.swizzle_change ||
1429                         plane_state->update_flags.bits.dcc_change ||
1430                         plane_state->update_flags.bits.bpp_change ||
1431                         plane_state->update_flags.bits.scaling_change ||
1432                         plane_state->update_flags.bits.plane_size_change) {
1433                 struct plane_size size = plane_state->plane_size;
1434
1435                 size.surface_size = pipe_ctx->plane_res.scl_data.viewport;
1436                 hubp->funcs->hubp_program_surface_config(
1437                         hubp,
1438                         plane_state->format,
1439                         &plane_state->tiling_info,
1440                         &size,
1441                         plane_state->rotation,
1442                         &plane_state->dcc,
1443                         plane_state->horizontal_mirror,
1444                         0);
1445                 hubp->power_gated = false;
1446         }
1447
1448         if (hubp->funcs->apply_PLAT_54186_wa && viewport_changed)
1449                 hubp->funcs->apply_PLAT_54186_wa(hubp, &plane_state->address);
1450
1451         if (pipe_ctx->update_flags.bits.enable || plane_state->update_flags.bits.addr_update)
1452                 hws->funcs.update_plane_addr(dc, pipe_ctx);
1453
1454
1455
1456         if (pipe_ctx->update_flags.bits.enable)
1457                 hubp->funcs->set_blank(hubp, false);
1458 }
1459
1460
1461 static void dcn20_program_pipe(
1462                 struct dc *dc,
1463                 struct pipe_ctx *pipe_ctx,
1464                 struct dc_state *context)
1465 {
1466         struct dce_hwseq *hws = dc->hwseq;
1467         /* Only need to unblank on top pipe */
1468         if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.abm_level)
1469                         && !pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe)
1470                 hws->funcs.blank_pixel_data(dc, pipe_ctx, !pipe_ctx->plane_state->visible);
1471
1472         if (pipe_ctx->update_flags.bits.global_sync) {
1473                 pipe_ctx->stream_res.tg->funcs->program_global_sync(
1474                                 pipe_ctx->stream_res.tg,
1475                                 pipe_ctx->pipe_dlg_param.vready_offset,
1476                                 pipe_ctx->pipe_dlg_param.vstartup_start,
1477                                 pipe_ctx->pipe_dlg_param.vupdate_offset,
1478                                 pipe_ctx->pipe_dlg_param.vupdate_width);
1479
1480                 pipe_ctx->stream_res.tg->funcs->set_vtg_params(
1481                                 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
1482
1483                 if (hws->funcs.setup_vupdate_interrupt)
1484                         hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
1485         }
1486
1487         if (pipe_ctx->update_flags.bits.odm)
1488                 hws->funcs.update_odm(dc, context, pipe_ctx);
1489
1490         if (pipe_ctx->update_flags.bits.enable)
1491                 dcn20_enable_plane(dc, pipe_ctx, context);
1492
1493         if (pipe_ctx->update_flags.raw || pipe_ctx->plane_state->update_flags.raw || pipe_ctx->stream->update_flags.raw)
1494                 dcn20_update_dchubp_dpp(dc, pipe_ctx, context);
1495
1496         if (pipe_ctx->update_flags.bits.enable
1497                         || pipe_ctx->plane_state->update_flags.bits.hdr_mult)
1498                 hws->funcs.set_hdr_multiplier(pipe_ctx);
1499
1500         if (pipe_ctx->update_flags.bits.enable ||
1501                         pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
1502                         pipe_ctx->plane_state->update_flags.bits.gamma_change)
1503                 hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);
1504
1505         /* dcn10_translate_regamma_to_hw_format takes 750us to finish
1506          * only do gamma programming for powering on, internal memcmp to avoid
1507          * updating on slave planes
1508          */
1509         if (pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.out_tf)
1510                 hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
1511
1512         /* If the pipe has been enabled or has a different opp, we
1513          * should reprogram the fmt. This deals with cases where
1514          * interation between mpc and odm combine on different streams
1515          * causes a different pipe to be chosen to odm combine with.
1516          */
1517         if (pipe_ctx->update_flags.bits.enable
1518             || pipe_ctx->update_flags.bits.opp_changed) {
1519
1520                 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
1521                         pipe_ctx->stream_res.opp,
1522                         COLOR_SPACE_YCBCR601,
1523                         pipe_ctx->stream->timing.display_color_depth,
1524                         pipe_ctx->stream->signal);
1525
1526                 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
1527                         pipe_ctx->stream_res.opp,
1528                         &pipe_ctx->stream->bit_depth_params,
1529                         &pipe_ctx->stream->clamping);
1530         }
1531 }
1532
1533 static bool does_pipe_need_lock(struct pipe_ctx *pipe)
1534 {
1535         if ((pipe->plane_state && pipe->plane_state->update_flags.raw)
1536                         || pipe->update_flags.raw)
1537                 return true;
1538         if (pipe->bottom_pipe)
1539                 return does_pipe_need_lock(pipe->bottom_pipe);
1540
1541         return false;
1542 }
1543
1544 void dcn20_program_front_end_for_ctx(
1545                 struct dc *dc,
1546                 struct dc_state *context)
1547 {
1548         const unsigned int TIMEOUT_FOR_PIPE_ENABLE_MS = 100;
1549         int i;
1550         struct dce_hwseq *hws = dc->hwseq;
1551         bool pipe_locked[MAX_PIPES] = {false};
1552         DC_LOGGER_INIT(dc->ctx->logger);
1553
1554         /* Carry over GSL groups in case the context is changing. */
1555         for (i = 0; i < dc->res_pool->pipe_count; i++)
1556                 if (context->res_ctx.pipe_ctx[i].stream == dc->current_state->res_ctx.pipe_ctx[i].stream)
1557                         context->res_ctx.pipe_ctx[i].stream_res.gsl_group =
1558                                 dc->current_state->res_ctx.pipe_ctx[i].stream_res.gsl_group;
1559
1560         /* Set pipe update flags and lock pipes */
1561         for (i = 0; i < dc->res_pool->pipe_count; i++)
1562                 dcn20_detect_pipe_changes(&dc->current_state->res_ctx.pipe_ctx[i],
1563                                 &context->res_ctx.pipe_ctx[i]);
1564         for (i = 0; i < dc->res_pool->pipe_count; i++)
1565                 if (!context->res_ctx.pipe_ctx[i].top_pipe &&
1566                                 does_pipe_need_lock(&context->res_ctx.pipe_ctx[i])) {
1567                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1568
1569                         if (pipe_ctx->update_flags.bits.tg_changed || pipe_ctx->update_flags.bits.enable)
1570                                 dc->hwss.pipe_control_lock(dc, pipe_ctx, true);
1571                         if (!pipe_ctx->update_flags.bits.enable)
1572                                 dc->hwss.pipe_control_lock(dc, &dc->current_state->res_ctx.pipe_ctx[i], true);
1573                         pipe_locked[i] = true;
1574                 }
1575
1576         /* OTG blank before disabling all front ends */
1577         for (i = 0; i < dc->res_pool->pipe_count; i++)
1578                 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable
1579                                 && !context->res_ctx.pipe_ctx[i].top_pipe
1580                                 && !context->res_ctx.pipe_ctx[i].prev_odm_pipe
1581                                 && context->res_ctx.pipe_ctx[i].stream)
1582                         hws->funcs.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true);
1583
1584         /* Disconnect mpcc */
1585         for (i = 0; i < dc->res_pool->pipe_count; i++)
1586                 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable
1587                                 || context->res_ctx.pipe_ctx[i].update_flags.bits.opp_changed) {
1588                         hws->funcs.plane_atomic_disconnect(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
1589                         DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx);
1590                 }
1591
1592         /*
1593          * Program all updated pipes, order matters for mpcc setup. Start with
1594          * top pipe and program all pipes that follow in order
1595          */
1596         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1597                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1598
1599                 if (pipe->plane_state && !pipe->top_pipe) {
1600                         while (pipe) {
1601                                 dcn20_program_pipe(dc, pipe, context);
1602                                 pipe = pipe->bottom_pipe;
1603                         }
1604                         /* Program secondary blending tree and writeback pipes */
1605                         pipe = &context->res_ctx.pipe_ctx[i];
1606                         if (!pipe->prev_odm_pipe && pipe->stream->num_wb_info > 0
1607                                         && (pipe->update_flags.raw || pipe->plane_state->update_flags.raw || pipe->stream->update_flags.raw)
1608                                         && hws->funcs.program_all_writeback_pipes_in_tree)
1609                                 hws->funcs.program_all_writeback_pipes_in_tree(dc, pipe->stream, context);
1610                 }
1611         }
1612
1613         /* Unlock all locked pipes */
1614         for (i = 0; i < dc->res_pool->pipe_count; i++)
1615                 if (pipe_locked[i]) {
1616                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1617
1618                         if (pipe_ctx->update_flags.bits.tg_changed || pipe_ctx->update_flags.bits.enable)
1619                                 dc->hwss.pipe_control_lock(dc, pipe_ctx, false);
1620                         if (!pipe_ctx->update_flags.bits.enable)
1621                                 dc->hwss.pipe_control_lock(dc, &dc->current_state->res_ctx.pipe_ctx[i], false);
1622                 }
1623
1624         for (i = 0; i < dc->res_pool->pipe_count; i++)
1625                 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable)
1626                         dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
1627
1628         /*
1629          * If we are enabling a pipe, we need to wait for pending clear as this is a critical
1630          * part of the enable operation otherwise, DM may request an immediate flip which
1631          * will cause HW to perform an "immediate enable" (as opposed to "vsync enable") which
1632          * is unsupported on DCN.
1633          */
1634         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1635                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1636
1637                 if (pipe->plane_state && !pipe->top_pipe && pipe->update_flags.bits.enable) {
1638                         struct hubp *hubp = pipe->plane_res.hubp;
1639                         int j = 0;
1640
1641                         for (j = 0; j < TIMEOUT_FOR_PIPE_ENABLE_MS
1642                                         && hubp->funcs->hubp_is_flip_pending(hubp); j++)
1643                                 msleep(1);
1644                 }
1645         }
1646
1647         /* WA to apply WM setting*/
1648         if (dc->hwseq->wa.DEGVIDCN21)
1649                 dc->res_pool->hubbub->funcs->apply_DEDCN21_147_wa(dc->res_pool->hubbub);
1650 }
1651
1652
1653 void dcn20_prepare_bandwidth(
1654                 struct dc *dc,
1655                 struct dc_state *context)
1656 {
1657         struct hubbub *hubbub = dc->res_pool->hubbub;
1658
1659         dc->clk_mgr->funcs->update_clocks(
1660                         dc->clk_mgr,
1661                         context,
1662                         false);
1663
1664         /* program dchubbub watermarks */
1665         hubbub->funcs->program_watermarks(hubbub,
1666                                         &context->bw_ctx.bw.dcn.watermarks,
1667                                         dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
1668                                         false);
1669 }
1670
1671 void dcn20_optimize_bandwidth(
1672                 struct dc *dc,
1673                 struct dc_state *context)
1674 {
1675         struct hubbub *hubbub = dc->res_pool->hubbub;
1676
1677         /* program dchubbub watermarks */
1678         hubbub->funcs->program_watermarks(hubbub,
1679                                         &context->bw_ctx.bw.dcn.watermarks,
1680                                         dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
1681                                         true);
1682
1683         dc->clk_mgr->funcs->update_clocks(
1684                         dc->clk_mgr,
1685                         context,
1686                         true);
1687 }
1688
1689 bool dcn20_update_bandwidth(
1690                 struct dc *dc,
1691                 struct dc_state *context)
1692 {
1693         int i;
1694         struct dce_hwseq *hws = dc->hwseq;
1695
1696         /* recalculate DML parameters */
1697         if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false))
1698                 return false;
1699
1700         /* apply updated bandwidth parameters */
1701         dc->hwss.prepare_bandwidth(dc, context);
1702
1703         /* update hubp configs for all pipes */
1704         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1705                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1706
1707                 if (pipe_ctx->plane_state == NULL)
1708                         continue;
1709
1710                 if (pipe_ctx->top_pipe == NULL) {
1711                         bool blank = !is_pipe_tree_visible(pipe_ctx);
1712
1713                         pipe_ctx->stream_res.tg->funcs->program_global_sync(
1714                                         pipe_ctx->stream_res.tg,
1715                                         pipe_ctx->pipe_dlg_param.vready_offset,
1716                                         pipe_ctx->pipe_dlg_param.vstartup_start,
1717                                         pipe_ctx->pipe_dlg_param.vupdate_offset,
1718                                         pipe_ctx->pipe_dlg_param.vupdate_width);
1719
1720                         pipe_ctx->stream_res.tg->funcs->set_vtg_params(
1721                                         pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
1722
1723                         if (pipe_ctx->prev_odm_pipe == NULL)
1724                                 hws->funcs.blank_pixel_data(dc, pipe_ctx, blank);
1725
1726                         if (hws->funcs.setup_vupdate_interrupt)
1727                                 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
1728                 }
1729
1730                 pipe_ctx->plane_res.hubp->funcs->hubp_setup(
1731                                 pipe_ctx->plane_res.hubp,
1732                                         &pipe_ctx->dlg_regs,
1733                                         &pipe_ctx->ttu_regs,
1734                                         &pipe_ctx->rq_regs,
1735                                         &pipe_ctx->pipe_dlg_param);
1736         }
1737
1738         return true;
1739 }
1740
1741 void dcn20_enable_writeback(
1742                 struct dc *dc,
1743                 struct dc_writeback_info *wb_info,
1744                 struct dc_state *context)
1745 {
1746         struct dwbc *dwb;
1747         struct mcif_wb *mcif_wb;
1748         struct timing_generator *optc;
1749
1750         ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES);
1751         ASSERT(wb_info->wb_enabled);
1752         dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
1753         mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];
1754
1755         /* set the OPTC source mux */
1756         optc = dc->res_pool->timing_generators[dwb->otg_inst];
1757         optc->funcs->set_dwb_source(optc, wb_info->dwb_pipe_inst);
1758         /* set MCIF_WB buffer and arbitration configuration */
1759         mcif_wb->funcs->config_mcif_buf(mcif_wb, &wb_info->mcif_buf_params, wb_info->dwb_params.dest_height);
1760         mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]);
1761         /* Enable MCIF_WB */
1762         mcif_wb->funcs->enable_mcif(mcif_wb);
1763         /* Enable DWB */
1764         dwb->funcs->enable(dwb, &wb_info->dwb_params);
1765         /* TODO: add sequence to enable/disable warmup */
1766 }
1767
1768 void dcn20_disable_writeback(
1769                 struct dc *dc,
1770                 unsigned int dwb_pipe_inst)
1771 {
1772         struct dwbc *dwb;
1773         struct mcif_wb *mcif_wb;
1774
1775         ASSERT(dwb_pipe_inst < MAX_DWB_PIPES);
1776         dwb = dc->res_pool->dwbc[dwb_pipe_inst];
1777         mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst];
1778
1779         dwb->funcs->disable(dwb);
1780         mcif_wb->funcs->disable_mcif(mcif_wb);
1781 }
1782
1783 bool dcn20_wait_for_blank_complete(
1784                 struct output_pixel_processor *opp)
1785 {
1786         int counter;
1787
1788         for (counter = 0; counter < 1000; counter++) {
1789                 if (opp->funcs->dpg_is_blanked(opp))
1790                         break;
1791
1792                 udelay(100);
1793         }
1794
1795         if (counter == 1000) {
1796                 dm_error("DC: failed to blank crtc!\n");
1797                 return false;
1798         }
1799
1800         return true;
1801 }
1802
1803 bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx)
1804 {
1805         struct hubp *hubp = pipe_ctx->plane_res.hubp;
1806
1807         if (!hubp)
1808                 return false;
1809         return hubp->funcs->dmdata_status_done(hubp);
1810 }
1811
1812 void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)
1813 {
1814         struct dce_hwseq *hws = dc->hwseq;
1815
1816         if (pipe_ctx->stream_res.dsc) {
1817                 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
1818
1819                 dcn20_dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, true);
1820                 while (odm_pipe) {
1821                         dcn20_dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, true);
1822                         odm_pipe = odm_pipe->next_odm_pipe;
1823                 }
1824         }
1825 }
1826
1827 void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)
1828 {
1829         struct dce_hwseq *hws = dc->hwseq;
1830
1831         if (pipe_ctx->stream_res.dsc) {
1832                 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
1833
1834                 dcn20_dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, false);
1835                 while (odm_pipe) {
1836                         dcn20_dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, false);
1837                         odm_pipe = odm_pipe->next_odm_pipe;
1838                 }
1839         }
1840 }
1841
1842 void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx)
1843 {
1844         struct dc_dmdata_attributes attr = { 0 };
1845         struct hubp *hubp = pipe_ctx->plane_res.hubp;
1846
1847         attr.dmdata_mode = DMDATA_HW_MODE;
1848         attr.dmdata_size =
1849                 dc_is_hdmi_signal(pipe_ctx->stream->signal) ? 32 : 36;
1850         attr.address.quad_part =
1851                         pipe_ctx->stream->dmdata_address.quad_part;
1852         attr.dmdata_dl_delta = 0;
1853         attr.dmdata_qos_mode = 0;
1854         attr.dmdata_qos_level = 0;
1855         attr.dmdata_repeat = 1; /* always repeat */
1856         attr.dmdata_updated = 1;
1857         attr.dmdata_sw_data = NULL;
1858
1859         hubp->funcs->dmdata_set_attributes(hubp, &attr);
1860 }
1861
1862 void dcn20_init_vm_ctx(
1863                 struct dce_hwseq *hws,
1864                 struct dc *dc,
1865                 struct dc_virtual_addr_space_config *va_config,
1866                 int vmid)
1867 {
1868         struct dcn_hubbub_virt_addr_config config;
1869
1870         if (vmid == 0) {
1871                 ASSERT(0); /* VMID cannot be 0 for vm context */
1872                 return;
1873         }
1874
1875         config.page_table_start_addr = va_config->page_table_start_addr;
1876         config.page_table_end_addr = va_config->page_table_end_addr;
1877         config.page_table_block_size = va_config->page_table_block_size_in_bytes;
1878         config.page_table_depth = va_config->page_table_depth;
1879         config.page_table_base_addr = va_config->page_table_base_addr;
1880
1881         dc->res_pool->hubbub->funcs->init_vm_ctx(dc->res_pool->hubbub, &config, vmid);
1882 }
1883
1884 int dcn20_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)
1885 {
1886         struct dcn_hubbub_phys_addr_config config;
1887
1888         config.system_aperture.fb_top = pa_config->system_aperture.fb_top;
1889         config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset;
1890         config.system_aperture.fb_base = pa_config->system_aperture.fb_base;
1891         config.system_aperture.agp_top = pa_config->system_aperture.agp_top;
1892         config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot;
1893         config.system_aperture.agp_base = pa_config->system_aperture.agp_base;
1894         config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr;
1895         config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr;
1896         config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr;
1897         config.page_table_default_page_addr = pa_config->page_table_default_page_addr;
1898
1899         return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config);
1900 }
1901
1902 static bool patch_address_for_sbs_tb_stereo(
1903                 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr)
1904 {
1905         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1906         bool sec_split = pipe_ctx->top_pipe &&
1907                         pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
1908         if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
1909                         (pipe_ctx->stream->timing.timing_3d_format ==
1910                         TIMING_3D_FORMAT_SIDE_BY_SIDE ||
1911                         pipe_ctx->stream->timing.timing_3d_format ==
1912                         TIMING_3D_FORMAT_TOP_AND_BOTTOM)) {
1913                 *addr = plane_state->address.grph_stereo.left_addr;
1914                 plane_state->address.grph_stereo.left_addr =
1915                                 plane_state->address.grph_stereo.right_addr;
1916                 return true;
1917         }
1918
1919         if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE &&
1920                         plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) {
1921                 plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO;
1922                 plane_state->address.grph_stereo.right_addr =
1923                                 plane_state->address.grph_stereo.left_addr;
1924         }
1925         return false;
1926 }
1927
1928 void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)
1929 {
1930         bool addr_patched = false;
1931         PHYSICAL_ADDRESS_LOC addr;
1932         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1933
1934         if (plane_state == NULL)
1935                 return;
1936
1937         addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);
1938
1939         // Call Helper to track VMID use
1940         vm_helper_mark_vmid_used(dc->vm_helper, plane_state->address.vmid, pipe_ctx->plane_res.hubp->inst);
1941
1942         pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(
1943                         pipe_ctx->plane_res.hubp,
1944                         &plane_state->address,
1945                         plane_state->flip_immediate);
1946
1947         plane_state->status.requested_address = plane_state->address;
1948
1949         if (plane_state->flip_immediate)
1950                 plane_state->status.current_address = plane_state->address;
1951
1952         if (addr_patched)
1953                 pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;
1954 }
1955
1956 void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx,
1957                 struct dc_link_settings *link_settings)
1958 {
1959         struct encoder_unblank_param params = { { 0 } };
1960         struct dc_stream_state *stream = pipe_ctx->stream;
1961         struct dc_link *link = stream->link;
1962         struct dce_hwseq *hws = link->dc->hwseq;
1963         struct pipe_ctx *odm_pipe;
1964
1965         params.opp_cnt = 1;
1966         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
1967                 params.opp_cnt++;
1968         }
1969         /* only 3 items below are used by unblank */
1970         params.timing = pipe_ctx->stream->timing;
1971
1972         params.link_settings.link_rate = link_settings->link_rate;
1973
1974         if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
1975                 if (optc2_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1)
1976                         params.timing.pix_clk_100hz /= 2;
1977                 pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine(
1978                                 pipe_ctx->stream_res.stream_enc, params.opp_cnt > 1);
1979                 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, &params);
1980         }
1981
1982         if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1983                 hws->funcs.edp_backlight_control(link, true);
1984         }
1985 }
1986
1987 void dcn20_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx)
1988 {
1989         struct timing_generator *tg = pipe_ctx->stream_res.tg;
1990         int start_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);
1991
1992         if (start_line < 0)
1993                 start_line = 0;
1994
1995         if (tg->funcs->setup_vertical_interrupt2)
1996                 tg->funcs->setup_vertical_interrupt2(tg, start_line);
1997 }
1998
1999 static void dcn20_reset_back_end_for_pipe(
2000                 struct dc *dc,
2001                 struct pipe_ctx *pipe_ctx,
2002                 struct dc_state *context)
2003 {
2004         int i;
2005         struct dc_link *link;
2006         DC_LOGGER_INIT(dc->ctx->logger);
2007         if (pipe_ctx->stream_res.stream_enc == NULL) {
2008                 pipe_ctx->stream = NULL;
2009                 return;
2010         }
2011
2012         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
2013                 link = pipe_ctx->stream->link;
2014                 /* DPMS may already disable or */
2015                 /* dpms_off status is incorrect due to fastboot
2016                  * feature. When system resume from S4 with second
2017                  * screen only, the dpms_off would be true but
2018                  * VBIOS lit up eDP, so check link status too.
2019                  */
2020                 if (!pipe_ctx->stream->dpms_off || link->link_status.link_active)
2021                         core_link_disable_stream(pipe_ctx);
2022                 else if (pipe_ctx->stream_res.audio)
2023                         dc->hwss.disable_audio_stream(pipe_ctx);
2024
2025                 /* free acquired resources */
2026                 if (pipe_ctx->stream_res.audio) {
2027                         /*disable az_endpoint*/
2028                         pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
2029
2030                         /*free audio*/
2031                         if (dc->caps.dynamic_audio == true) {
2032                                 /*we have to dynamic arbitrate the audio endpoints*/
2033                                 /*we free the resource, need reset is_audio_acquired*/
2034                                 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
2035                                                 pipe_ctx->stream_res.audio, false);
2036                                 pipe_ctx->stream_res.audio = NULL;
2037                         }
2038                 }
2039         }
2040         else if (pipe_ctx->stream_res.dsc) {
2041                 dp_set_dsc_enable(pipe_ctx, false);
2042         }
2043
2044         /* by upper caller loop, parent pipe: pipe0, will be reset last.
2045          * back end share by all pipes and will be disable only when disable
2046          * parent pipe.
2047          */
2048         if (pipe_ctx->top_pipe == NULL) {
2049                 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
2050
2051                 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
2052                 if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass)
2053                         pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
2054                                         pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
2055
2056                 if (pipe_ctx->stream_res.tg->funcs->set_drr)
2057                         pipe_ctx->stream_res.tg->funcs->set_drr(
2058                                         pipe_ctx->stream_res.tg, NULL);
2059         }
2060
2061         for (i = 0; i < dc->res_pool->pipe_count; i++)
2062                 if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx)
2063                         break;
2064
2065         if (i == dc->res_pool->pipe_count)
2066                 return;
2067
2068         pipe_ctx->stream = NULL;
2069         DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n",
2070                                         pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
2071 }
2072
2073 void dcn20_reset_hw_ctx_wrap(
2074                 struct dc *dc,
2075                 struct dc_state *context)
2076 {
2077         int i;
2078         struct dce_hwseq *hws = dc->hwseq;
2079
2080         /* Reset Back End*/
2081         for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
2082                 struct pipe_ctx *pipe_ctx_old =
2083                         &dc->current_state->res_ctx.pipe_ctx[i];
2084                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2085
2086                 if (!pipe_ctx_old->stream)
2087                         continue;
2088
2089                 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe)
2090                         continue;
2091
2092                 if (!pipe_ctx->stream ||
2093                                 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
2094                         struct clock_source *old_clk = pipe_ctx_old->clock_source;
2095
2096                         dcn20_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
2097                         if (hws->funcs.enable_stream_gating)
2098                                 hws->funcs.enable_stream_gating(dc, pipe_ctx);
2099                         if (old_clk)
2100                                 old_clk->funcs->cs_power_down(old_clk);
2101                 }
2102         }
2103 }
2104
2105 void dcn20_get_mpctree_visual_confirm_color(
2106                 struct pipe_ctx *pipe_ctx,
2107                 struct tg_color *color)
2108 {
2109         const struct tg_color pipe_colors[6] = {
2110                         {MAX_TG_COLOR_VALUE, 0, 0}, // red
2111                         {MAX_TG_COLOR_VALUE, 0, MAX_TG_COLOR_VALUE}, // yellow
2112                         {0, MAX_TG_COLOR_VALUE, 0}, // blue
2113                         {MAX_TG_COLOR_VALUE / 2, 0, MAX_TG_COLOR_VALUE / 2}, // purple
2114                         {0, 0, MAX_TG_COLOR_VALUE}, // green
2115                         {MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE * 2 / 3, 0}, // orange
2116         };
2117
2118         struct pipe_ctx *top_pipe = pipe_ctx;
2119
2120         while (top_pipe->top_pipe) {
2121                 top_pipe = top_pipe->top_pipe;
2122         }
2123
2124         *color = pipe_colors[top_pipe->pipe_idx];
2125 }
2126
2127 void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
2128 {
2129         struct dce_hwseq *hws = dc->hwseq;
2130         struct hubp *hubp = pipe_ctx->plane_res.hubp;
2131         struct mpcc_blnd_cfg blnd_cfg = { {0} };
2132         bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha;
2133         int mpcc_id;
2134         struct mpcc *new_mpcc;
2135         struct mpc *mpc = dc->res_pool->mpc;
2136         struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);
2137
2138         // input to MPCC is always RGB, by default leave black_color at 0
2139         if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) {
2140                 hws->funcs.get_hdr_visual_confirm_color(
2141                                 pipe_ctx, &blnd_cfg.black_color);
2142         } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) {
2143                 hws->funcs.get_surface_visual_confirm_color(
2144                                 pipe_ctx, &blnd_cfg.black_color);
2145         } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE) {
2146                 dcn20_get_mpctree_visual_confirm_color(
2147                                 pipe_ctx, &blnd_cfg.black_color);
2148         }
2149
2150         if (per_pixel_alpha)
2151                 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;
2152         else
2153                 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA;
2154
2155         blnd_cfg.overlap_only = false;
2156         blnd_cfg.global_gain = 0xff;
2157
2158         if (pipe_ctx->plane_state->global_alpha)
2159                 blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value;
2160         else
2161                 blnd_cfg.global_alpha = 0xff;
2162
2163         blnd_cfg.background_color_bpc = 4;
2164         blnd_cfg.bottom_gain_mode = 0;
2165         blnd_cfg.top_gain = 0x1f000;
2166         blnd_cfg.bottom_inside_gain = 0x1f000;
2167         blnd_cfg.bottom_outside_gain = 0x1f000;
2168         blnd_cfg.pre_multiplied_alpha = per_pixel_alpha;
2169
2170         /*
2171          * TODO: remove hack
2172          * Note: currently there is a bug in init_hw such that
2173          * on resume from hibernate, BIOS sets up MPCC0, and
2174          * we do mpcc_remove but the mpcc cannot go to idle
2175          * after remove. This cause us to pick mpcc1 here,
2176          * which causes a pstate hang for yet unknown reason.
2177          */
2178         mpcc_id = hubp->inst;
2179
2180         /* check if this MPCC is already being used */
2181         new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id);
2182         /* remove MPCC if being used */
2183         if (new_mpcc != NULL)
2184                 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc);
2185         else
2186                 if (dc->debug.sanity_checks)
2187                         mpc->funcs->assert_mpcc_idle_before_connect(
2188                                         dc->res_pool->mpc, mpcc_id);
2189
2190         /* Call MPC to insert new plane */
2191         new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,
2192                         mpc_tree_params,
2193                         &blnd_cfg,
2194                         NULL,
2195                         NULL,
2196                         hubp->inst,
2197                         mpcc_id);
2198
2199         ASSERT(new_mpcc != NULL);
2200         hubp->opp_id = pipe_ctx->stream_res.opp->inst;
2201         hubp->mpcc_id = mpcc_id;
2202 }
2203
2204 void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)
2205 {
2206         enum dc_lane_count lane_count =
2207                 pipe_ctx->stream->link->cur_link_settings.lane_count;
2208
2209         struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
2210         struct dc_link *link = pipe_ctx->stream->link;
2211
2212         uint32_t active_total_with_borders;
2213         uint32_t early_control = 0;
2214         struct timing_generator *tg = pipe_ctx->stream_res.tg;
2215
2216         /* For MST, there are multiply stream go to only one link.
2217          * connect DIG back_end to front_end while enable_stream and
2218          * disconnect them during disable_stream
2219          * BY this, it is logic clean to separate stream and link
2220          */
2221         link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
2222                                                     pipe_ctx->stream_res.stream_enc->id, true);
2223
2224         if (pipe_ctx->plane_state && pipe_ctx->plane_state->flip_immediate != 1) {
2225                 if (link->dc->hwss.program_dmdata_engine)
2226                         link->dc->hwss.program_dmdata_engine(pipe_ctx);
2227         }
2228
2229         link->dc->hwss.update_info_frame(pipe_ctx);
2230
2231         /* enable early control to avoid corruption on DP monitor*/
2232         active_total_with_borders =
2233                         timing->h_addressable
2234                                 + timing->h_border_left
2235                                 + timing->h_border_right;
2236
2237         if (lane_count != 0)
2238                 early_control = active_total_with_borders % lane_count;
2239
2240         if (early_control == 0)
2241                 early_control = lane_count;
2242
2243         tg->funcs->set_early_control(tg, early_control);
2244
2245         /* enable audio only within mode set */
2246         if (pipe_ctx->stream_res.audio != NULL) {
2247                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
2248                         pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
2249         }
2250 }
2251
2252 void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx)
2253 {
2254         struct dc_stream_state    *stream     = pipe_ctx->stream;
2255         struct hubp               *hubp       = pipe_ctx->plane_res.hubp;
2256         bool                       enable     = false;
2257         struct stream_encoder     *stream_enc = pipe_ctx->stream_res.stream_enc;
2258         enum dynamic_metadata_mode mode       = dc_is_dp_signal(stream->signal)
2259                                                         ? dmdata_dp
2260                                                         : dmdata_hdmi;
2261
2262         /* if using dynamic meta, don't set up generic infopackets */
2263         if (pipe_ctx->stream->dmdata_address.quad_part != 0) {
2264                 pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false;
2265                 enable = true;
2266         }
2267
2268         if (!hubp)
2269                 return;
2270
2271         if (!stream_enc || !stream_enc->funcs->set_dynamic_metadata)
2272                 return;
2273
2274         stream_enc->funcs->set_dynamic_metadata(stream_enc, enable,
2275                                                 hubp->inst, mode);
2276 }
2277
2278 void dcn20_fpga_init_hw(struct dc *dc)
2279 {
2280         int i, j;
2281         struct dce_hwseq *hws = dc->hwseq;
2282         struct resource_pool *res_pool = dc->res_pool;
2283         struct dc_state  *context = dc->current_state;
2284
2285         if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
2286                 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
2287
2288         // Initialize the dccg
2289         if (res_pool->dccg->funcs->dccg_init)
2290                 res_pool->dccg->funcs->dccg_init(res_pool->dccg);
2291
2292         //Enable ability to power gate / don't force power on permanently
2293         hws->funcs.enable_power_gating_plane(hws, true);
2294
2295         // Specific to FPGA dccg and registers
2296         REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF);
2297         REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF);
2298
2299         hws->funcs.dccg_init(hws);
2300
2301         REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2);
2302         REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
2303         REG_WRITE(REFCLK_CNTL, 0);
2304         //
2305
2306
2307         /* Blank pixel data with OPP DPG */
2308         for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
2309                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2310
2311                 if (tg->funcs->is_tg_enabled(tg))
2312                         dcn20_init_blank(dc, tg);
2313         }
2314
2315         for (i = 0; i < res_pool->timing_generator_count; i++) {
2316                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2317
2318                 if (tg->funcs->is_tg_enabled(tg))
2319                         tg->funcs->lock(tg);
2320         }
2321
2322         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2323                 struct dpp *dpp = res_pool->dpps[i];
2324
2325                 dpp->funcs->dpp_reset(dpp);
2326         }
2327
2328         /* Reset all MPCC muxes */
2329         res_pool->mpc->funcs->mpc_init(res_pool->mpc);
2330
2331         /* initialize OPP mpc_tree parameter */
2332         for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {
2333                 res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst;
2334                 res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
2335                 for (j = 0; j < MAX_PIPES; j++)
2336                         res_pool->opps[i]->mpcc_disconnect_pending[j] = false;
2337         }
2338
2339         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2340                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2341                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2342                 struct hubp *hubp = dc->res_pool->hubps[i];
2343                 struct dpp *dpp = dc->res_pool->dpps[i];
2344
2345                 pipe_ctx->stream_res.tg = tg;
2346                 pipe_ctx->pipe_idx = i;
2347
2348                 pipe_ctx->plane_res.hubp = hubp;
2349                 pipe_ctx->plane_res.dpp = dpp;
2350                 pipe_ctx->plane_res.mpcc_inst = dpp->inst;
2351                 hubp->mpcc_id = dpp->inst;
2352                 hubp->opp_id = OPP_ID_INVALID;
2353                 hubp->power_gated = false;
2354                 pipe_ctx->stream_res.opp = NULL;
2355
2356                 hubp->funcs->hubp_init(hubp);
2357
2358                 //dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
2359                 //dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
2360                 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
2361                 pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
2362                 /*to do*/
2363                 hws->funcs.plane_atomic_disconnect(dc, pipe_ctx);
2364         }
2365
2366         /* initialize DWB pointer to MCIF_WB */
2367         for (i = 0; i < res_pool->res_cap->num_dwb; i++)
2368                 res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i];
2369
2370         for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
2371                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2372
2373                 if (tg->funcs->is_tg_enabled(tg))
2374                         tg->funcs->unlock(tg);
2375         }
2376
2377         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2378                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2379
2380                 dc->hwss.disable_plane(dc, pipe_ctx);
2381
2382                 pipe_ctx->stream_res.tg = NULL;
2383                 pipe_ctx->plane_res.hubp = NULL;
2384         }
2385
2386         for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
2387                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2388
2389                 tg->funcs->tg_init(tg);
2390         }
2391 }