2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <linux/delay.h>
27 #include "dm_services.h"
28 #include "basics/dc_common.h"
29 #include "dm_helpers.h"
30 #include "core_types.h"
32 #include "dcn20_resource.h"
33 #include "dcn20_hwseq.h"
34 #include "dce/dce_hwseq.h"
35 #include "dcn20_dsc.h"
36 #include "dcn20_optc.h"
41 #include "timing_generator.h"
47 #include "reg_helper.h"
48 #include "dcn10/dcn10_cm_common.h"
49 #include "dc_link_dp.h"
50 #include "vm_helper.h"
53 #define DC_LOGGER_INIT(logger)
61 #define FN(reg_name, field_name) \
62 hws->shifts->field_name, hws->masks->field_name
64 static int find_free_gsl_group(const struct dc *dc)
66 if (dc->res_pool->gsl_groups.gsl_0 == 0)
68 if (dc->res_pool->gsl_groups.gsl_1 == 0)
70 if (dc->res_pool->gsl_groups.gsl_2 == 0)
76 /* NOTE: This is not a generic setup_gsl function (hence the suffix as_lock)
77 * This is only used to lock pipes in pipe splitting case with immediate flip
78 * Ordinary MPC/OTG locks suppress VUPDATE which doesn't help with immediate,
79 * so we get tearing with freesync since we cannot flip multiple pipes
81 * We use GSL for this:
82 * - immediate flip: find first available GSL group if not already assigned
83 * program gsl with that group, set current OTG as master
84 * and always us 0x4 = AND of flip_ready from all pipes
85 * - vsync flip: disable GSL if used
87 * Groups in stream_res are stored as +1 from HW registers, i.e.
88 * gsl_0 <=> pipe_ctx->stream_res.gsl_group == 1
89 * Using a magic value like -1 would require tracking all inits/resets
91 static void dcn20_setup_gsl_group_as_lock(
93 struct pipe_ctx *pipe_ctx,
96 struct gsl_params gsl;
99 memset(&gsl, 0, sizeof(struct gsl_params));
102 /* return if group already assigned since GSL was set up
103 * for vsync flip, we would unassign so it can't be "left over"
105 if (pipe_ctx->stream_res.gsl_group > 0)
108 group_idx = find_free_gsl_group(dc);
109 ASSERT(group_idx != 0);
110 pipe_ctx->stream_res.gsl_group = group_idx;
112 /* set gsl group reg field and mark resource used */
116 dc->res_pool->gsl_groups.gsl_0 = 1;
120 dc->res_pool->gsl_groups.gsl_1 = 1;
124 dc->res_pool->gsl_groups.gsl_2 = 1;
128 return; // invalid case
130 gsl.gsl_master_en = 1;
132 group_idx = pipe_ctx->stream_res.gsl_group;
134 return; // if not in use, just return
136 pipe_ctx->stream_res.gsl_group = 0;
138 /* unset gsl group reg field and mark resource free */
142 dc->res_pool->gsl_groups.gsl_0 = 0;
146 dc->res_pool->gsl_groups.gsl_1 = 0;
150 dc->res_pool->gsl_groups.gsl_2 = 0;
156 gsl.gsl_master_en = 0;
159 /* at this point we want to program whether it's to enable or disable */
160 if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL &&
161 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) {
162 pipe_ctx->stream_res.tg->funcs->set_gsl(
163 pipe_ctx->stream_res.tg,
166 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select(
167 pipe_ctx->stream_res.tg, group_idx, enable ? 4 : 0);
172 void dcn20_set_flip_control_gsl(
173 struct pipe_ctx *pipe_ctx,
176 if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl)
177 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl(
178 pipe_ctx->plane_res.hubp, flip_immediate);
182 void dcn20_enable_power_gating_plane(
183 struct dce_hwseq *hws,
186 bool force_on = 1; /* disable power gating */
191 /* DCHUBP0/1/2/3/4/5 */
192 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on);
193 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on);
194 REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on);
195 REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on);
196 if (REG(DOMAIN8_PG_CONFIG))
197 REG_UPDATE(DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on);
198 if (REG(DOMAIN10_PG_CONFIG))
199 REG_UPDATE(DOMAIN10_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on);
202 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on);
203 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on);
204 REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on);
205 REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);
206 if (REG(DOMAIN9_PG_CONFIG))
207 REG_UPDATE(DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on);
208 if (REG(DOMAIN11_PG_CONFIG))
209 REG_UPDATE(DOMAIN11_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on);
212 REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, force_on);
213 REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, force_on);
214 REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, force_on);
215 if (REG(DOMAIN19_PG_CONFIG))
216 REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, force_on);
217 if (REG(DOMAIN20_PG_CONFIG))
218 REG_UPDATE(DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, force_on);
219 if (REG(DOMAIN21_PG_CONFIG))
220 REG_UPDATE(DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, force_on);
223 void dcn20_dccg_init(struct dce_hwseq *hws)
226 * set MICROSECOND_TIME_BASE_DIV
227 * 100Mhz refclk -> 0x120264
228 * 27Mhz refclk -> 0x12021b
229 * 48Mhz refclk -> 0x120230
232 REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x120264);
235 * set MILLISECOND_TIME_BASE_DIV
236 * 100Mhz refclk -> 0x1186a0
237 * 27Mhz refclk -> 0x106978
238 * 48Mhz refclk -> 0x10bb80
241 REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x1186a0);
243 /* This value is dependent on the hardware pipeline delay so set once per SOC */
244 REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0x801003c);
247 void dcn20_disable_vga(
248 struct dce_hwseq *hws)
250 REG_WRITE(D1VGA_CONTROL, 0);
251 REG_WRITE(D2VGA_CONTROL, 0);
252 REG_WRITE(D3VGA_CONTROL, 0);
253 REG_WRITE(D4VGA_CONTROL, 0);
254 REG_WRITE(D5VGA_CONTROL, 0);
255 REG_WRITE(D6VGA_CONTROL, 0);
258 void dcn20_program_triple_buffer(
260 struct pipe_ctx *pipe_ctx,
261 bool enable_triple_buffer)
263 if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) {
264 pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer(
265 pipe_ctx->plane_res.hubp,
266 enable_triple_buffer);
270 /* Blank pixel data during initialization */
271 void dcn20_init_blank(
273 struct timing_generator *tg)
275 struct dce_hwseq *hws = dc->hwseq;
276 enum dc_color_space color_space;
277 struct tg_color black_color = {0};
278 struct output_pixel_processor *opp = NULL;
279 struct output_pixel_processor *bottom_opp = NULL;
280 uint32_t num_opps, opp_id_src0, opp_id_src1;
281 uint32_t otg_active_width, otg_active_height;
283 /* program opp dpg blank color */
284 color_space = COLOR_SPACE_SRGB;
285 color_space_to_black_color(dc, color_space, &black_color);
287 /* get the OTG active size */
288 tg->funcs->get_otg_active_size(tg,
292 /* get the OPTC source */
293 tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1);
294 ASSERT(opp_id_src0 < dc->res_pool->res_cap->num_opp);
295 opp = dc->res_pool->opps[opp_id_src0];
298 otg_active_width = otg_active_width / 2;
299 ASSERT(opp_id_src1 < dc->res_pool->res_cap->num_opp);
300 bottom_opp = dc->res_pool->opps[opp_id_src1];
303 opp->funcs->opp_set_disp_pattern_generator(
305 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,
306 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
307 COLOR_DEPTH_UNDEFINED,
313 bottom_opp->funcs->opp_set_disp_pattern_generator(
315 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,
316 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
317 COLOR_DEPTH_UNDEFINED,
323 hws->funcs.wait_for_blank_complete(opp);
326 void dcn20_dsc_pg_control(
327 struct dce_hwseq *hws,
328 unsigned int dsc_inst,
331 uint32_t power_gate = power_on ? 0 : 1;
332 uint32_t pwr_status = power_on ? 0 : 2;
333 uint32_t org_ip_request_cntl = 0;
335 if (hws->ctx->dc->debug.disable_dsc_power_gate)
338 if (REG(DOMAIN16_PG_CONFIG) == 0)
341 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
342 if (org_ip_request_cntl == 0)
343 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
347 REG_UPDATE(DOMAIN16_PG_CONFIG,
348 DOMAIN16_POWER_GATE, power_gate);
350 REG_WAIT(DOMAIN16_PG_STATUS,
351 DOMAIN16_PGFSM_PWR_STATUS, pwr_status,
355 REG_UPDATE(DOMAIN17_PG_CONFIG,
356 DOMAIN17_POWER_GATE, power_gate);
358 REG_WAIT(DOMAIN17_PG_STATUS,
359 DOMAIN17_PGFSM_PWR_STATUS, pwr_status,
363 REG_UPDATE(DOMAIN18_PG_CONFIG,
364 DOMAIN18_POWER_GATE, power_gate);
366 REG_WAIT(DOMAIN18_PG_STATUS,
367 DOMAIN18_PGFSM_PWR_STATUS, pwr_status,
371 REG_UPDATE(DOMAIN19_PG_CONFIG,
372 DOMAIN19_POWER_GATE, power_gate);
374 REG_WAIT(DOMAIN19_PG_STATUS,
375 DOMAIN19_PGFSM_PWR_STATUS, pwr_status,
379 REG_UPDATE(DOMAIN20_PG_CONFIG,
380 DOMAIN20_POWER_GATE, power_gate);
382 REG_WAIT(DOMAIN20_PG_STATUS,
383 DOMAIN20_PGFSM_PWR_STATUS, pwr_status,
387 REG_UPDATE(DOMAIN21_PG_CONFIG,
388 DOMAIN21_POWER_GATE, power_gate);
390 REG_WAIT(DOMAIN21_PG_STATUS,
391 DOMAIN21_PGFSM_PWR_STATUS, pwr_status,
399 if (org_ip_request_cntl == 0)
400 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
403 void dcn20_dpp_pg_control(
404 struct dce_hwseq *hws,
405 unsigned int dpp_inst,
408 uint32_t power_gate = power_on ? 0 : 1;
409 uint32_t pwr_status = power_on ? 0 : 2;
411 if (hws->ctx->dc->debug.disable_dpp_power_gate)
413 if (REG(DOMAIN1_PG_CONFIG) == 0)
418 REG_UPDATE(DOMAIN1_PG_CONFIG,
419 DOMAIN1_POWER_GATE, power_gate);
421 REG_WAIT(DOMAIN1_PG_STATUS,
422 DOMAIN1_PGFSM_PWR_STATUS, pwr_status,
426 REG_UPDATE(DOMAIN3_PG_CONFIG,
427 DOMAIN3_POWER_GATE, power_gate);
429 REG_WAIT(DOMAIN3_PG_STATUS,
430 DOMAIN3_PGFSM_PWR_STATUS, pwr_status,
434 REG_UPDATE(DOMAIN5_PG_CONFIG,
435 DOMAIN5_POWER_GATE, power_gate);
437 REG_WAIT(DOMAIN5_PG_STATUS,
438 DOMAIN5_PGFSM_PWR_STATUS, pwr_status,
442 REG_UPDATE(DOMAIN7_PG_CONFIG,
443 DOMAIN7_POWER_GATE, power_gate);
445 REG_WAIT(DOMAIN7_PG_STATUS,
446 DOMAIN7_PGFSM_PWR_STATUS, pwr_status,
450 REG_UPDATE(DOMAIN9_PG_CONFIG,
451 DOMAIN9_POWER_GATE, power_gate);
453 REG_WAIT(DOMAIN9_PG_STATUS,
454 DOMAIN9_PGFSM_PWR_STATUS, pwr_status,
459 * Do not power gate DPP5, should be left at HW default, power on permanently.
460 * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard
462 * REG_UPDATE(DOMAIN11_PG_CONFIG,
463 * DOMAIN11_POWER_GATE, power_gate);
465 * REG_WAIT(DOMAIN11_PG_STATUS,
466 * DOMAIN11_PGFSM_PWR_STATUS, pwr_status,
477 void dcn20_hubp_pg_control(
478 struct dce_hwseq *hws,
479 unsigned int hubp_inst,
482 uint32_t power_gate = power_on ? 0 : 1;
483 uint32_t pwr_status = power_on ? 0 : 2;
485 if (hws->ctx->dc->debug.disable_hubp_power_gate)
487 if (REG(DOMAIN0_PG_CONFIG) == 0)
491 case 0: /* DCHUBP0 */
492 REG_UPDATE(DOMAIN0_PG_CONFIG,
493 DOMAIN0_POWER_GATE, power_gate);
495 REG_WAIT(DOMAIN0_PG_STATUS,
496 DOMAIN0_PGFSM_PWR_STATUS, pwr_status,
499 case 1: /* DCHUBP1 */
500 REG_UPDATE(DOMAIN2_PG_CONFIG,
501 DOMAIN2_POWER_GATE, power_gate);
503 REG_WAIT(DOMAIN2_PG_STATUS,
504 DOMAIN2_PGFSM_PWR_STATUS, pwr_status,
507 case 2: /* DCHUBP2 */
508 REG_UPDATE(DOMAIN4_PG_CONFIG,
509 DOMAIN4_POWER_GATE, power_gate);
511 REG_WAIT(DOMAIN4_PG_STATUS,
512 DOMAIN4_PGFSM_PWR_STATUS, pwr_status,
515 case 3: /* DCHUBP3 */
516 REG_UPDATE(DOMAIN6_PG_CONFIG,
517 DOMAIN6_POWER_GATE, power_gate);
519 REG_WAIT(DOMAIN6_PG_STATUS,
520 DOMAIN6_PGFSM_PWR_STATUS, pwr_status,
523 case 4: /* DCHUBP4 */
524 REG_UPDATE(DOMAIN8_PG_CONFIG,
525 DOMAIN8_POWER_GATE, power_gate);
527 REG_WAIT(DOMAIN8_PG_STATUS,
528 DOMAIN8_PGFSM_PWR_STATUS, pwr_status,
531 case 5: /* DCHUBP5 */
533 * Do not power gate DCHUB5, should be left at HW default, power on permanently.
534 * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard
536 * REG_UPDATE(DOMAIN10_PG_CONFIG,
537 * DOMAIN10_POWER_GATE, power_gate);
539 * REG_WAIT(DOMAIN10_PG_STATUS,
540 * DOMAIN10_PGFSM_PWR_STATUS, pwr_status,
551 /* disable HW used by plane.
552 * note: cannot disable until disconnect is complete
554 void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
556 struct dce_hwseq *hws = dc->hwseq;
557 struct hubp *hubp = pipe_ctx->plane_res.hubp;
558 struct dpp *dpp = pipe_ctx->plane_res.dpp;
560 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);
562 /* In flip immediate with pipe splitting case GSL is used for
563 * synchronization so we must disable it when the plane is disabled.
565 if (pipe_ctx->stream_res.gsl_group != 0)
566 dcn20_setup_gsl_group_as_lock(dc, pipe_ctx, false);
568 dc->hwss.set_flip_control_gsl(pipe_ctx, false);
570 hubp->funcs->hubp_clk_cntl(hubp, false);
572 dpp->funcs->dpp_dppclk_control(dpp, false, false);
574 hubp->power_gated = true;
575 dc->optimized_required = false; /* We're powering off, no need to optimize */
577 hws->funcs.plane_atomic_power_down(dc,
578 pipe_ctx->plane_res.dpp,
579 pipe_ctx->plane_res.hubp);
581 pipe_ctx->stream = NULL;
582 memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res));
583 memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res));
584 pipe_ctx->top_pipe = NULL;
585 pipe_ctx->bottom_pipe = NULL;
586 pipe_ctx->plane_state = NULL;
590 void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
592 DC_LOGGER_INIT(dc->ctx->logger);
594 if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)
597 dcn20_plane_atomic_disable(dc, pipe_ctx);
599 DC_LOG_DC("Power down front end %d\n",
603 enum dc_status dcn20_enable_stream_timing(
604 struct pipe_ctx *pipe_ctx,
605 struct dc_state *context,
608 struct dce_hwseq *hws = dc->hwseq;
609 struct dc_stream_state *stream = pipe_ctx->stream;
610 struct drr_params params = {0};
611 unsigned int event_triggers = 0;
612 struct pipe_ctx *odm_pipe;
614 int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst };
616 /* by upper caller loop, pipe0 is parent pipe and be called first.
617 * back end is set up by for pipe0. Other children pipe share back end
618 * with pipe 0. No program is needed.
620 if (pipe_ctx->top_pipe != NULL)
623 /* TODO check if timing_changed, disable stream if timing changed */
625 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
626 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;
631 pipe_ctx->stream_res.tg->funcs->set_odm_combine(
632 pipe_ctx->stream_res.tg,
634 &pipe_ctx->stream->timing);
636 /* HW program guide assume display already disable
637 * by unplug sequence. OTG assume stop.
639 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true);
641 if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
642 pipe_ctx->clock_source,
643 &pipe_ctx->stream_res.pix_clk_params,
644 &pipe_ctx->pll_settings)) {
646 return DC_ERROR_UNEXPECTED;
649 pipe_ctx->stream_res.tg->funcs->program_timing(
650 pipe_ctx->stream_res.tg,
652 pipe_ctx->pipe_dlg_param.vready_offset,
653 pipe_ctx->pipe_dlg_param.vstartup_start,
654 pipe_ctx->pipe_dlg_param.vupdate_offset,
655 pipe_ctx->pipe_dlg_param.vupdate_width,
656 pipe_ctx->stream->signal,
659 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
660 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control(
661 odm_pipe->stream_res.opp,
664 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
665 pipe_ctx->stream_res.opp,
668 hws->funcs.blank_pixel_data(dc, pipe_ctx, true);
670 /* VTG is within DCHUB command block. DCFCLK is always on */
671 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {
673 return DC_ERROR_UNEXPECTED;
676 hws->funcs.wait_for_blank_complete(pipe_ctx->stream_res.opp);
678 params.vertical_total_min = stream->adjust.v_total_min;
679 params.vertical_total_max = stream->adjust.v_total_max;
680 params.vertical_total_mid = stream->adjust.v_total_mid;
681 params.vertical_total_mid_frame_num = stream->adjust.v_total_mid_frame_num;
682 if (pipe_ctx->stream_res.tg->funcs->set_drr)
683 pipe_ctx->stream_res.tg->funcs->set_drr(
684 pipe_ctx->stream_res.tg, ¶ms);
686 // DRR should set trigger event to monitor surface update event
687 if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0)
688 event_triggers = 0x80;
689 if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)
690 pipe_ctx->stream_res.tg->funcs->set_static_screen_control(
691 pipe_ctx->stream_res.tg, event_triggers);
693 /* TODO program crtc source select for non-virtual signal*/
694 /* TODO program FMT */
695 /* TODO setup link_enc */
696 /* TODO set stream attributes */
697 /* TODO program audio */
698 /* TODO enable stream if timing changed */
699 /* TODO unblank stream if DP */
704 void dcn20_program_output_csc(struct dc *dc,
705 struct pipe_ctx *pipe_ctx,
706 enum dc_color_space colorspace,
710 struct mpc *mpc = dc->res_pool->mpc;
711 enum mpc_output_csc_mode ocsc_mode = MPC_OUTPUT_CSC_COEF_A;
712 int mpcc_id = pipe_ctx->plane_res.hubp->inst;
714 if (mpc->funcs->power_on_mpc_mem_pwr)
715 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true);
717 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
718 if (mpc->funcs->set_output_csc != NULL)
719 mpc->funcs->set_output_csc(mpc,
724 if (mpc->funcs->set_ocsc_default != NULL)
725 mpc->funcs->set_ocsc_default(mpc,
732 bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
733 const struct dc_stream_state *stream)
735 int mpcc_id = pipe_ctx->plane_res.hubp->inst;
736 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
737 struct pwl_params *params = NULL;
739 * program OGAM only for the top pipe
740 * if there is a pipe split then fix diagnostic is required:
741 * how to pass OGAM parameter for stream.
742 * if programming for all pipes is required then remove condition
743 * pipe_ctx->top_pipe == NULL ,but then fix the diagnostic.
745 if (mpc->funcs->power_on_mpc_mem_pwr)
746 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true);
747 if (pipe_ctx->top_pipe == NULL
748 && mpc->funcs->set_output_gamma && stream->out_transfer_func) {
749 if (stream->out_transfer_func->type == TF_TYPE_HWPWL)
750 params = &stream->out_transfer_func->pwl;
751 else if (pipe_ctx->stream->out_transfer_func->type ==
752 TF_TYPE_DISTRIBUTED_POINTS &&
753 cm_helper_translate_curve_to_hw_format(
754 stream->out_transfer_func,
755 &mpc->blender_params, false))
756 params = &mpc->blender_params;
760 if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED)
764 * if above if is not executed then 'params' equal to 0 and set in bypass
766 mpc->funcs->set_output_gamma(mpc, mpcc_id, params);
771 bool dcn20_set_blend_lut(
772 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
774 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
776 struct pwl_params *blend_lut = NULL;
778 if (plane_state->blend_tf) {
779 if (plane_state->blend_tf->type == TF_TYPE_HWPWL)
780 blend_lut = &plane_state->blend_tf->pwl;
781 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) {
782 cm_helper_translate_curve_to_hw_format(
783 plane_state->blend_tf,
784 &dpp_base->regamma_params, false);
785 blend_lut = &dpp_base->regamma_params;
788 result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut);
793 bool dcn20_set_shaper_3dlut(
794 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
796 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
798 struct pwl_params *shaper_lut = NULL;
800 if (plane_state->in_shaper_func) {
801 if (plane_state->in_shaper_func->type == TF_TYPE_HWPWL)
802 shaper_lut = &plane_state->in_shaper_func->pwl;
803 else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) {
804 cm_helper_translate_curve_to_hw_format(
805 plane_state->in_shaper_func,
806 &dpp_base->shaper_params, true);
807 shaper_lut = &dpp_base->shaper_params;
811 result = dpp_base->funcs->dpp_program_shaper_lut(dpp_base, shaper_lut);
812 if (plane_state->lut3d_func &&
813 plane_state->lut3d_func->state.bits.initialized == 1)
814 result = dpp_base->funcs->dpp_program_3dlut(dpp_base,
815 &plane_state->lut3d_func->lut_3d);
817 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, NULL);
822 bool dcn20_set_input_transfer_func(struct dc *dc,
823 struct pipe_ctx *pipe_ctx,
824 const struct dc_plane_state *plane_state)
826 struct dce_hwseq *hws = dc->hwseq;
827 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
828 const struct dc_transfer_func *tf = NULL;
830 bool use_degamma_ram = false;
832 if (dpp_base == NULL || plane_state == NULL)
835 hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state);
836 hws->funcs.set_blend_lut(pipe_ctx, plane_state);
838 if (plane_state->in_transfer_func)
839 tf = plane_state->in_transfer_func;
843 dpp_base->funcs->dpp_set_degamma(dpp_base,
844 IPP_DEGAMMA_MODE_BYPASS);
848 if (tf->type == TF_TYPE_HWPWL || tf->type == TF_TYPE_DISTRIBUTED_POINTS)
849 use_degamma_ram = true;
851 if (use_degamma_ram == true) {
852 if (tf->type == TF_TYPE_HWPWL)
853 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base,
855 else if (tf->type == TF_TYPE_DISTRIBUTED_POINTS) {
856 cm_helper_translate_curve_to_degamma_hw_format(tf,
857 &dpp_base->degamma_params);
858 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base,
859 &dpp_base->degamma_params);
863 /* handle here the optimized cases when de-gamma ROM could be used.
866 if (tf->type == TF_TYPE_PREDEFINED) {
868 case TRANSFER_FUNCTION_SRGB:
869 dpp_base->funcs->dpp_set_degamma(dpp_base,
870 IPP_DEGAMMA_MODE_HW_sRGB);
872 case TRANSFER_FUNCTION_BT709:
873 dpp_base->funcs->dpp_set_degamma(dpp_base,
874 IPP_DEGAMMA_MODE_HW_xvYCC);
876 case TRANSFER_FUNCTION_LINEAR:
877 dpp_base->funcs->dpp_set_degamma(dpp_base,
878 IPP_DEGAMMA_MODE_BYPASS);
880 case TRANSFER_FUNCTION_PQ:
881 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_USER_PWL);
882 cm_helper_translate_curve_to_degamma_hw_format(tf, &dpp_base->degamma_params);
883 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, &dpp_base->degamma_params);
890 } else if (tf->type == TF_TYPE_BYPASS)
891 dpp_base->funcs->dpp_set_degamma(dpp_base,
892 IPP_DEGAMMA_MODE_BYPASS);
895 * if we are here, we did not handle correctly.
896 * fix is required for this use case
899 dpp_base->funcs->dpp_set_degamma(dpp_base,
900 IPP_DEGAMMA_MODE_BYPASS);
906 void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)
908 struct pipe_ctx *odm_pipe;
910 int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst };
912 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
913 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;
918 pipe_ctx->stream_res.tg->funcs->set_odm_combine(
919 pipe_ctx->stream_res.tg,
921 &pipe_ctx->stream->timing);
923 pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
924 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
927 void dcn20_blank_pixel_data(
929 struct pipe_ctx *pipe_ctx,
932 struct tg_color black_color = {0};
933 struct stream_resource *stream_res = &pipe_ctx->stream_res;
934 struct dc_stream_state *stream = pipe_ctx->stream;
935 enum dc_color_space color_space = stream->output_color_space;
936 enum controller_dp_test_pattern test_pattern = CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR;
937 enum controller_dp_color_space test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED;
938 struct pipe_ctx *odm_pipe;
941 int width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;
942 int height = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top;
944 /* get opp dpg blank color */
945 color_space_to_black_color(dc, color_space, &black_color);
947 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
950 width = width / odm_cnt;
954 stream_res->abm->funcs->set_abm_immediate_disable(stream_res->abm);
956 if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) {
957 test_pattern = CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
958 test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_RGB;
961 test_pattern = CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
964 stream_res->opp->funcs->opp_set_disp_pattern_generator(
967 test_pattern_color_space,
968 stream->timing.display_color_depth,
973 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
974 odm_pipe->stream_res.opp->funcs->opp_set_disp_pattern_generator(
975 odm_pipe->stream_res.opp,
976 dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE && blank ?
977 CONTROLLER_DP_TEST_PATTERN_COLORRAMP : test_pattern,
978 test_pattern_color_space,
979 stream->timing.display_color_depth,
986 if (stream_res->abm) {
987 stream_res->abm->funcs->set_pipe(stream_res->abm, stream_res->tg->inst + 1);
988 stream_res->abm->funcs->set_abm_level(stream_res->abm, stream->abm_level);
993 static void dcn20_power_on_plane(
994 struct dce_hwseq *hws,
995 struct pipe_ctx *pipe_ctx)
997 DC_LOGGER_INIT(hws->ctx->logger);
998 if (REG(DC_IP_REQUEST_CNTL)) {
999 REG_SET(DC_IP_REQUEST_CNTL, 0,
1001 dcn20_dpp_pg_control(hws, pipe_ctx->plane_res.dpp->inst, true);
1002 dcn20_hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, true);
1003 REG_SET(DC_IP_REQUEST_CNTL, 0,
1006 "Un-gated front end for pipe %d\n", pipe_ctx->plane_res.hubp->inst);
1010 void dcn20_enable_plane(
1012 struct pipe_ctx *pipe_ctx,
1013 struct dc_state *context)
1015 //if (dc->debug.sanity_checks) {
1016 // dcn10_verify_allow_pstate_change_high(dc);
1018 dcn20_power_on_plane(dc->hwseq, pipe_ctx);
1020 /* enable DCFCLK current DCHUB */
1021 pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);
1023 /* initialize HUBP on power up */
1024 pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp);
1026 /* make sure OPP_PIPE_CLOCK_EN = 1 */
1027 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
1028 pipe_ctx->stream_res.opp,
1031 /* TODO: enable/disable in dm as per update type.
1033 DC_LOG_DC(dc->ctx->logger,
1034 "Pipe:%d 0x%x: addr hi:0x%x, "
1037 " %d; dst: %d, %d, %d, %d;\n",
1040 plane_state->address.grph.addr.high_part,
1041 plane_state->address.grph.addr.low_part,
1042 plane_state->src_rect.x,
1043 plane_state->src_rect.y,
1044 plane_state->src_rect.width,
1045 plane_state->src_rect.height,
1046 plane_state->dst_rect.x,
1047 plane_state->dst_rect.y,
1048 plane_state->dst_rect.width,
1049 plane_state->dst_rect.height);
1051 DC_LOG_DC(dc->ctx->logger,
1052 "Pipe %d: width, height, x, y format:%d\n"
1053 "viewport:%d, %d, %d, %d\n"
1054 "recout: %d, %d, %d, %d\n",
1056 plane_state->format,
1057 pipe_ctx->plane_res.scl_data.viewport.width,
1058 pipe_ctx->plane_res.scl_data.viewport.height,
1059 pipe_ctx->plane_res.scl_data.viewport.x,
1060 pipe_ctx->plane_res.scl_data.viewport.y,
1061 pipe_ctx->plane_res.scl_data.recout.width,
1062 pipe_ctx->plane_res.scl_data.recout.height,
1063 pipe_ctx->plane_res.scl_data.recout.x,
1064 pipe_ctx->plane_res.scl_data.recout.y);
1065 print_rq_dlg_ttu(dc, pipe_ctx);
1068 if (dc->vm_pa_config.valid) {
1069 struct vm_system_aperture_param apt;
1071 apt.sys_default.quad_part = 0;
1073 apt.sys_low.quad_part = dc->vm_pa_config.system_aperture.start_addr;
1074 apt.sys_high.quad_part = dc->vm_pa_config.system_aperture.end_addr;
1076 // Program system aperture settings
1077 pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt);
1080 // if (dc->debug.sanity_checks) {
1081 // dcn10_verify_allow_pstate_change_high(dc);
1086 void dcn20_pipe_control_lock_global(
1088 struct pipe_ctx *pipe,
1092 pipe->stream_res.tg->funcs->lock_doublebuffer_enable(
1093 pipe->stream_res.tg);
1094 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);
1096 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);
1097 pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg,
1098 CRTC_STATE_VACTIVE);
1099 pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg,
1101 pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg,
1102 CRTC_STATE_VACTIVE);
1103 pipe->stream_res.tg->funcs->lock_doublebuffer_disable(
1104 pipe->stream_res.tg);
1108 void dcn20_pipe_control_lock(
1110 struct pipe_ctx *pipe,
1113 bool flip_immediate = false;
1115 /* use TG master update lock to lock everything on the TG
1116 * therefore only top pipe need to lock
1121 if (pipe->plane_state != NULL)
1122 flip_immediate = pipe->plane_state->flip_immediate;
1124 if (flip_immediate && lock) {
1125 const int TIMEOUT_FOR_FLIP_PENDING = 100000;
1128 for (i = 0; i < TIMEOUT_FOR_FLIP_PENDING; ++i) {
1129 if (!pipe->plane_res.hubp->funcs->hubp_is_flip_pending(pipe->plane_res.hubp))
1134 if (pipe->bottom_pipe != NULL) {
1135 for (i = 0; i < TIMEOUT_FOR_FLIP_PENDING; ++i) {
1136 if (!pipe->bottom_pipe->plane_res.hubp->funcs->hubp_is_flip_pending(pipe->bottom_pipe->plane_res.hubp))
1143 /* In flip immediate and pipe splitting case, we need to use GSL
1144 * for synchronization. Only do setup on locking and on flip type change.
1146 if (lock && pipe->bottom_pipe != NULL)
1147 if ((flip_immediate && pipe->stream_res.gsl_group == 0) ||
1148 (!flip_immediate && pipe->stream_res.gsl_group > 0))
1149 dcn20_setup_gsl_group_as_lock(dc, pipe, flip_immediate);
1151 if (pipe->plane_state != NULL && pipe->plane_state->triplebuffer_flips) {
1153 pipe->stream_res.tg->funcs->triplebuffer_lock(pipe->stream_res.tg);
1155 pipe->stream_res.tg->funcs->triplebuffer_unlock(pipe->stream_res.tg);
1158 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);
1160 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);
1164 static void dcn20_detect_pipe_changes(struct pipe_ctx *old_pipe, struct pipe_ctx *new_pipe)
1166 new_pipe->update_flags.raw = 0;
1168 /* Exit on unchanged, unused pipe */
1169 if (!old_pipe->plane_state && !new_pipe->plane_state)
1171 /* Detect pipe enable/disable */
1172 if (!old_pipe->plane_state && new_pipe->plane_state) {
1173 new_pipe->update_flags.bits.enable = 1;
1174 new_pipe->update_flags.bits.mpcc = 1;
1175 new_pipe->update_flags.bits.dppclk = 1;
1176 new_pipe->update_flags.bits.hubp_interdependent = 1;
1177 new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1;
1178 new_pipe->update_flags.bits.gamut_remap = 1;
1179 new_pipe->update_flags.bits.scaler = 1;
1180 new_pipe->update_flags.bits.viewport = 1;
1181 if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) {
1182 new_pipe->update_flags.bits.odm = 1;
1183 new_pipe->update_flags.bits.global_sync = 1;
1187 if (old_pipe->plane_state && !new_pipe->plane_state) {
1188 new_pipe->update_flags.bits.disable = 1;
1192 /* Detect top pipe only changes */
1193 if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) {
1194 /* Detect odm changes */
1195 if ((old_pipe->next_odm_pipe && new_pipe->next_odm_pipe
1196 && old_pipe->next_odm_pipe->pipe_idx != new_pipe->next_odm_pipe->pipe_idx)
1197 || (!old_pipe->next_odm_pipe && new_pipe->next_odm_pipe)
1198 || (old_pipe->next_odm_pipe && !new_pipe->next_odm_pipe)
1199 || old_pipe->stream_res.opp != new_pipe->stream_res.opp)
1200 new_pipe->update_flags.bits.odm = 1;
1202 /* Detect global sync changes */
1203 if (old_pipe->pipe_dlg_param.vready_offset != new_pipe->pipe_dlg_param.vready_offset
1204 || old_pipe->pipe_dlg_param.vstartup_start != new_pipe->pipe_dlg_param.vstartup_start
1205 || old_pipe->pipe_dlg_param.vupdate_offset != new_pipe->pipe_dlg_param.vupdate_offset
1206 || old_pipe->pipe_dlg_param.vupdate_width != new_pipe->pipe_dlg_param.vupdate_width)
1207 new_pipe->update_flags.bits.global_sync = 1;
1211 * Detect opp / tg change, only set on change, not on enable
1212 * Assume mpcc inst = pipe index, if not this code needs to be updated
1213 * since mpcc is what is affected by these. In fact all of our sequence
1214 * makes this assumption at the moment with how hubp reset is matched to
1215 * same index mpcc reset.
1217 if (old_pipe->stream_res.opp != new_pipe->stream_res.opp)
1218 new_pipe->update_flags.bits.opp_changed = 1;
1219 if (old_pipe->stream_res.tg != new_pipe->stream_res.tg)
1220 new_pipe->update_flags.bits.tg_changed = 1;
1222 /* Detect mpcc blending changes, only dpp inst and bot matter here */
1223 if (old_pipe->plane_res.dpp != new_pipe->plane_res.dpp
1224 || old_pipe->stream_res.opp != new_pipe->stream_res.opp
1225 || (!old_pipe->bottom_pipe && new_pipe->bottom_pipe)
1226 || (old_pipe->bottom_pipe && !new_pipe->bottom_pipe)
1227 || (old_pipe->bottom_pipe && new_pipe->bottom_pipe
1228 && old_pipe->bottom_pipe->plane_res.mpcc_inst
1229 != new_pipe->bottom_pipe->plane_res.mpcc_inst))
1230 new_pipe->update_flags.bits.mpcc = 1;
1232 /* Detect dppclk change */
1233 if (old_pipe->plane_res.bw.dppclk_khz != new_pipe->plane_res.bw.dppclk_khz)
1234 new_pipe->update_flags.bits.dppclk = 1;
1236 /* Check for scl update */
1237 if (memcmp(&old_pipe->plane_res.scl_data, &new_pipe->plane_res.scl_data, sizeof(struct scaler_data)))
1238 new_pipe->update_flags.bits.scaler = 1;
1239 /* Check for vp update */
1240 if (memcmp(&old_pipe->plane_res.scl_data.viewport, &new_pipe->plane_res.scl_data.viewport, sizeof(struct rect))
1241 || memcmp(&old_pipe->plane_res.scl_data.viewport_c,
1242 &new_pipe->plane_res.scl_data.viewport_c, sizeof(struct rect)))
1243 new_pipe->update_flags.bits.viewport = 1;
1245 /* Detect dlg/ttu/rq updates */
1247 struct _vcs_dpi_display_dlg_regs_st old_dlg_attr = old_pipe->dlg_regs;
1248 struct _vcs_dpi_display_ttu_regs_st old_ttu_attr = old_pipe->ttu_regs;
1249 struct _vcs_dpi_display_dlg_regs_st *new_dlg_attr = &new_pipe->dlg_regs;
1250 struct _vcs_dpi_display_ttu_regs_st *new_ttu_attr = &new_pipe->ttu_regs;
1252 /* Detect pipe interdependent updates */
1253 if (old_dlg_attr.dst_y_prefetch != new_dlg_attr->dst_y_prefetch ||
1254 old_dlg_attr.vratio_prefetch != new_dlg_attr->vratio_prefetch ||
1255 old_dlg_attr.vratio_prefetch_c != new_dlg_attr->vratio_prefetch_c ||
1256 old_dlg_attr.dst_y_per_vm_vblank != new_dlg_attr->dst_y_per_vm_vblank ||
1257 old_dlg_attr.dst_y_per_row_vblank != new_dlg_attr->dst_y_per_row_vblank ||
1258 old_dlg_attr.dst_y_per_vm_flip != new_dlg_attr->dst_y_per_vm_flip ||
1259 old_dlg_attr.dst_y_per_row_flip != new_dlg_attr->dst_y_per_row_flip ||
1260 old_dlg_attr.refcyc_per_meta_chunk_vblank_l != new_dlg_attr->refcyc_per_meta_chunk_vblank_l ||
1261 old_dlg_attr.refcyc_per_meta_chunk_vblank_c != new_dlg_attr->refcyc_per_meta_chunk_vblank_c ||
1262 old_dlg_attr.refcyc_per_meta_chunk_flip_l != new_dlg_attr->refcyc_per_meta_chunk_flip_l ||
1263 old_dlg_attr.refcyc_per_line_delivery_pre_l != new_dlg_attr->refcyc_per_line_delivery_pre_l ||
1264 old_dlg_attr.refcyc_per_line_delivery_pre_c != new_dlg_attr->refcyc_per_line_delivery_pre_c ||
1265 old_ttu_attr.refcyc_per_req_delivery_pre_l != new_ttu_attr->refcyc_per_req_delivery_pre_l ||
1266 old_ttu_attr.refcyc_per_req_delivery_pre_c != new_ttu_attr->refcyc_per_req_delivery_pre_c ||
1267 old_ttu_attr.refcyc_per_req_delivery_pre_cur0 != new_ttu_attr->refcyc_per_req_delivery_pre_cur0 ||
1268 old_ttu_attr.refcyc_per_req_delivery_pre_cur1 != new_ttu_attr->refcyc_per_req_delivery_pre_cur1 ||
1269 old_ttu_attr.min_ttu_vblank != new_ttu_attr->min_ttu_vblank ||
1270 old_ttu_attr.qos_level_flip != new_ttu_attr->qos_level_flip) {
1271 old_dlg_attr.dst_y_prefetch = new_dlg_attr->dst_y_prefetch;
1272 old_dlg_attr.vratio_prefetch = new_dlg_attr->vratio_prefetch;
1273 old_dlg_attr.vratio_prefetch_c = new_dlg_attr->vratio_prefetch_c;
1274 old_dlg_attr.dst_y_per_vm_vblank = new_dlg_attr->dst_y_per_vm_vblank;
1275 old_dlg_attr.dst_y_per_row_vblank = new_dlg_attr->dst_y_per_row_vblank;
1276 old_dlg_attr.dst_y_per_vm_flip = new_dlg_attr->dst_y_per_vm_flip;
1277 old_dlg_attr.dst_y_per_row_flip = new_dlg_attr->dst_y_per_row_flip;
1278 old_dlg_attr.refcyc_per_meta_chunk_vblank_l = new_dlg_attr->refcyc_per_meta_chunk_vblank_l;
1279 old_dlg_attr.refcyc_per_meta_chunk_vblank_c = new_dlg_attr->refcyc_per_meta_chunk_vblank_c;
1280 old_dlg_attr.refcyc_per_meta_chunk_flip_l = new_dlg_attr->refcyc_per_meta_chunk_flip_l;
1281 old_dlg_attr.refcyc_per_line_delivery_pre_l = new_dlg_attr->refcyc_per_line_delivery_pre_l;
1282 old_dlg_attr.refcyc_per_line_delivery_pre_c = new_dlg_attr->refcyc_per_line_delivery_pre_c;
1283 old_ttu_attr.refcyc_per_req_delivery_pre_l = new_ttu_attr->refcyc_per_req_delivery_pre_l;
1284 old_ttu_attr.refcyc_per_req_delivery_pre_c = new_ttu_attr->refcyc_per_req_delivery_pre_c;
1285 old_ttu_attr.refcyc_per_req_delivery_pre_cur0 = new_ttu_attr->refcyc_per_req_delivery_pre_cur0;
1286 old_ttu_attr.refcyc_per_req_delivery_pre_cur1 = new_ttu_attr->refcyc_per_req_delivery_pre_cur1;
1287 old_ttu_attr.min_ttu_vblank = new_ttu_attr->min_ttu_vblank;
1288 old_ttu_attr.qos_level_flip = new_ttu_attr->qos_level_flip;
1289 new_pipe->update_flags.bits.hubp_interdependent = 1;
1291 /* Detect any other updates to ttu/rq/dlg */
1292 if (memcmp(&old_dlg_attr, &new_pipe->dlg_regs, sizeof(old_dlg_attr)) ||
1293 memcmp(&old_ttu_attr, &new_pipe->ttu_regs, sizeof(old_ttu_attr)) ||
1294 memcmp(&old_pipe->rq_regs, &new_pipe->rq_regs, sizeof(old_pipe->rq_regs)))
1295 new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1;
1299 static void dcn20_update_dchubp_dpp(
1301 struct pipe_ctx *pipe_ctx,
1302 struct dc_state *context)
1304 struct dce_hwseq *hws = dc->hwseq;
1305 struct hubp *hubp = pipe_ctx->plane_res.hubp;
1306 struct dpp *dpp = pipe_ctx->plane_res.dpp;
1307 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1308 bool viewport_changed = false;
1310 if (pipe_ctx->update_flags.bits.dppclk)
1311 dpp->funcs->dpp_dppclk_control(dpp, false, true);
1313 /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG
1314 * VTG is within DCHUBBUB which is commond block share by each pipe HUBP.
1315 * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG
1317 if (pipe_ctx->update_flags.bits.hubp_rq_dlg_ttu) {
1318 hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst);
1320 hubp->funcs->hubp_setup(
1322 &pipe_ctx->dlg_regs,
1323 &pipe_ctx->ttu_regs,
1325 &pipe_ctx->pipe_dlg_param);
1327 if (pipe_ctx->update_flags.bits.hubp_interdependent)
1328 hubp->funcs->hubp_setup_interdependent(
1330 &pipe_ctx->dlg_regs,
1331 &pipe_ctx->ttu_regs);
1333 if (pipe_ctx->update_flags.bits.enable ||
1334 plane_state->update_flags.bits.bpp_change ||
1335 plane_state->update_flags.bits.input_csc_change ||
1336 plane_state->update_flags.bits.color_space_change ||
1337 plane_state->update_flags.bits.coeff_reduction_change) {
1338 struct dc_bias_and_scale bns_params = {0};
1340 // program the input csc
1341 dpp->funcs->dpp_setup(dpp,
1342 plane_state->format,
1343 EXPANSION_MODE_ZERO,
1344 plane_state->input_csc_color_matrix,
1345 plane_state->color_space,
1348 if (dpp->funcs->dpp_program_bias_and_scale) {
1349 //TODO :for CNVC set scale and bias registers if necessary
1350 build_prescale_params(&bns_params, plane_state);
1351 dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
1355 if (pipe_ctx->update_flags.bits.mpcc
1356 || plane_state->update_flags.bits.global_alpha_change
1357 || plane_state->update_flags.bits.per_pixel_alpha_change) {
1358 // MPCC inst is equal to pipe index in practice
1359 int mpcc_inst = pipe_ctx->pipe_idx;
1361 int opp_count = dc->res_pool->pipe_count;
1363 for (opp_inst = 0; opp_inst < opp_count; opp_inst++) {
1364 if (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst]) {
1365 dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst);
1366 dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false;
1370 hws->funcs.update_mpcc(dc, pipe_ctx);
1373 if (pipe_ctx->update_flags.bits.scaler ||
1374 plane_state->update_flags.bits.scaling_change ||
1375 plane_state->update_flags.bits.position_change ||
1376 plane_state->update_flags.bits.per_pixel_alpha_change ||
1377 pipe_ctx->stream->update_flags.bits.scaling) {
1378 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->plane_state->per_pixel_alpha;
1379 ASSERT(pipe_ctx->plane_res.scl_data.lb_params.depth == LB_PIXEL_DEPTH_30BPP);
1380 /* scaler configuration */
1381 pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(
1382 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);
1385 if (pipe_ctx->update_flags.bits.viewport ||
1386 (context == dc->current_state && plane_state->update_flags.bits.scaling_change) ||
1387 (context == dc->current_state && pipe_ctx->stream->update_flags.bits.scaling)) {
1389 hubp->funcs->mem_program_viewport(
1391 &pipe_ctx->plane_res.scl_data.viewport,
1392 &pipe_ctx->plane_res.scl_data.viewport_c);
1393 viewport_changed = true;
1396 /* Any updates are handled in dc interface, just need to apply existing for plane enable */
1397 if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed ||
1398 pipe_ctx->update_flags.bits.scaler || pipe_ctx->update_flags.bits.viewport)
1399 && pipe_ctx->stream->cursor_attributes.address.quad_part != 0) {
1400 dc->hwss.set_cursor_position(pipe_ctx);
1401 dc->hwss.set_cursor_attribute(pipe_ctx);
1403 if (dc->hwss.set_cursor_sdr_white_level)
1404 dc->hwss.set_cursor_sdr_white_level(pipe_ctx);
1407 /* Any updates are handled in dc interface, just need
1408 * to apply existing for plane enable / opp change */
1409 if (pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed
1410 || pipe_ctx->stream->update_flags.bits.gamut_remap
1411 || pipe_ctx->stream->update_flags.bits.out_csc) {
1412 /* dpp/cm gamut remap*/
1413 dc->hwss.program_gamut_remap(pipe_ctx);
1415 /*call the dcn2 method which uses mpc csc*/
1416 dc->hwss.program_output_csc(dc,
1418 pipe_ctx->stream->output_color_space,
1419 pipe_ctx->stream->csc_color_matrix.matrix,
1423 if (pipe_ctx->update_flags.bits.enable ||
1424 pipe_ctx->update_flags.bits.opp_changed ||
1425 plane_state->update_flags.bits.pixel_format_change ||
1426 plane_state->update_flags.bits.horizontal_mirror_change ||
1427 plane_state->update_flags.bits.rotation_change ||
1428 plane_state->update_flags.bits.swizzle_change ||
1429 plane_state->update_flags.bits.dcc_change ||
1430 plane_state->update_flags.bits.bpp_change ||
1431 plane_state->update_flags.bits.scaling_change ||
1432 plane_state->update_flags.bits.plane_size_change) {
1433 struct plane_size size = plane_state->plane_size;
1435 size.surface_size = pipe_ctx->plane_res.scl_data.viewport;
1436 hubp->funcs->hubp_program_surface_config(
1438 plane_state->format,
1439 &plane_state->tiling_info,
1441 plane_state->rotation,
1443 plane_state->horizontal_mirror,
1445 hubp->power_gated = false;
1448 if (hubp->funcs->apply_PLAT_54186_wa && viewport_changed)
1449 hubp->funcs->apply_PLAT_54186_wa(hubp, &plane_state->address);
1451 if (pipe_ctx->update_flags.bits.enable || plane_state->update_flags.bits.addr_update)
1452 hws->funcs.update_plane_addr(dc, pipe_ctx);
1456 if (pipe_ctx->update_flags.bits.enable)
1457 hubp->funcs->set_blank(hubp, false);
1461 static void dcn20_program_pipe(
1463 struct pipe_ctx *pipe_ctx,
1464 struct dc_state *context)
1466 struct dce_hwseq *hws = dc->hwseq;
1467 /* Only need to unblank on top pipe */
1468 if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.abm_level)
1469 && !pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe)
1470 hws->funcs.blank_pixel_data(dc, pipe_ctx, !pipe_ctx->plane_state->visible);
1472 if (pipe_ctx->update_flags.bits.global_sync) {
1473 pipe_ctx->stream_res.tg->funcs->program_global_sync(
1474 pipe_ctx->stream_res.tg,
1475 pipe_ctx->pipe_dlg_param.vready_offset,
1476 pipe_ctx->pipe_dlg_param.vstartup_start,
1477 pipe_ctx->pipe_dlg_param.vupdate_offset,
1478 pipe_ctx->pipe_dlg_param.vupdate_width);
1480 pipe_ctx->stream_res.tg->funcs->set_vtg_params(
1481 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
1483 if (hws->funcs.setup_vupdate_interrupt)
1484 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
1487 if (pipe_ctx->update_flags.bits.odm)
1488 hws->funcs.update_odm(dc, context, pipe_ctx);
1490 if (pipe_ctx->update_flags.bits.enable)
1491 dcn20_enable_plane(dc, pipe_ctx, context);
1493 if (pipe_ctx->update_flags.raw || pipe_ctx->plane_state->update_flags.raw || pipe_ctx->stream->update_flags.raw)
1494 dcn20_update_dchubp_dpp(dc, pipe_ctx, context);
1496 if (pipe_ctx->update_flags.bits.enable
1497 || pipe_ctx->plane_state->update_flags.bits.hdr_mult)
1498 hws->funcs.set_hdr_multiplier(pipe_ctx);
1500 if (pipe_ctx->update_flags.bits.enable ||
1501 pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
1502 pipe_ctx->plane_state->update_flags.bits.gamma_change)
1503 hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);
1505 /* dcn10_translate_regamma_to_hw_format takes 750us to finish
1506 * only do gamma programming for powering on, internal memcmp to avoid
1507 * updating on slave planes
1509 if (pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.out_tf)
1510 hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
1512 /* If the pipe has been enabled or has a different opp, we
1513 * should reprogram the fmt. This deals with cases where
1514 * interation between mpc and odm combine on different streams
1515 * causes a different pipe to be chosen to odm combine with.
1517 if (pipe_ctx->update_flags.bits.enable
1518 || pipe_ctx->update_flags.bits.opp_changed) {
1520 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
1521 pipe_ctx->stream_res.opp,
1522 COLOR_SPACE_YCBCR601,
1523 pipe_ctx->stream->timing.display_color_depth,
1524 pipe_ctx->stream->signal);
1526 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
1527 pipe_ctx->stream_res.opp,
1528 &pipe_ctx->stream->bit_depth_params,
1529 &pipe_ctx->stream->clamping);
1533 static bool does_pipe_need_lock(struct pipe_ctx *pipe)
1535 if ((pipe->plane_state && pipe->plane_state->update_flags.raw)
1536 || pipe->update_flags.raw)
1538 if (pipe->bottom_pipe)
1539 return does_pipe_need_lock(pipe->bottom_pipe);
1544 void dcn20_program_front_end_for_ctx(
1546 struct dc_state *context)
1548 const unsigned int TIMEOUT_FOR_PIPE_ENABLE_MS = 100;
1550 struct dce_hwseq *hws = dc->hwseq;
1551 bool pipe_locked[MAX_PIPES] = {false};
1552 DC_LOGGER_INIT(dc->ctx->logger);
1554 /* Carry over GSL groups in case the context is changing. */
1555 for (i = 0; i < dc->res_pool->pipe_count; i++)
1556 if (context->res_ctx.pipe_ctx[i].stream == dc->current_state->res_ctx.pipe_ctx[i].stream)
1557 context->res_ctx.pipe_ctx[i].stream_res.gsl_group =
1558 dc->current_state->res_ctx.pipe_ctx[i].stream_res.gsl_group;
1560 /* Set pipe update flags and lock pipes */
1561 for (i = 0; i < dc->res_pool->pipe_count; i++)
1562 dcn20_detect_pipe_changes(&dc->current_state->res_ctx.pipe_ctx[i],
1563 &context->res_ctx.pipe_ctx[i]);
1564 for (i = 0; i < dc->res_pool->pipe_count; i++)
1565 if (!context->res_ctx.pipe_ctx[i].top_pipe &&
1566 does_pipe_need_lock(&context->res_ctx.pipe_ctx[i])) {
1567 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1569 if (pipe_ctx->update_flags.bits.tg_changed || pipe_ctx->update_flags.bits.enable)
1570 dc->hwss.pipe_control_lock(dc, pipe_ctx, true);
1571 if (!pipe_ctx->update_flags.bits.enable)
1572 dc->hwss.pipe_control_lock(dc, &dc->current_state->res_ctx.pipe_ctx[i], true);
1573 pipe_locked[i] = true;
1576 /* OTG blank before disabling all front ends */
1577 for (i = 0; i < dc->res_pool->pipe_count; i++)
1578 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable
1579 && !context->res_ctx.pipe_ctx[i].top_pipe
1580 && !context->res_ctx.pipe_ctx[i].prev_odm_pipe
1581 && context->res_ctx.pipe_ctx[i].stream)
1582 hws->funcs.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true);
1584 /* Disconnect mpcc */
1585 for (i = 0; i < dc->res_pool->pipe_count; i++)
1586 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable
1587 || context->res_ctx.pipe_ctx[i].update_flags.bits.opp_changed) {
1588 hws->funcs.plane_atomic_disconnect(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
1589 DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx);
1593 * Program all updated pipes, order matters for mpcc setup. Start with
1594 * top pipe and program all pipes that follow in order
1596 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1597 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1599 if (pipe->plane_state && !pipe->top_pipe) {
1601 dcn20_program_pipe(dc, pipe, context);
1602 pipe = pipe->bottom_pipe;
1604 /* Program secondary blending tree and writeback pipes */
1605 pipe = &context->res_ctx.pipe_ctx[i];
1606 if (!pipe->prev_odm_pipe && pipe->stream->num_wb_info > 0
1607 && (pipe->update_flags.raw || pipe->plane_state->update_flags.raw || pipe->stream->update_flags.raw)
1608 && hws->funcs.program_all_writeback_pipes_in_tree)
1609 hws->funcs.program_all_writeback_pipes_in_tree(dc, pipe->stream, context);
1613 /* Unlock all locked pipes */
1614 for (i = 0; i < dc->res_pool->pipe_count; i++)
1615 if (pipe_locked[i]) {
1616 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1618 if (pipe_ctx->update_flags.bits.tg_changed || pipe_ctx->update_flags.bits.enable)
1619 dc->hwss.pipe_control_lock(dc, pipe_ctx, false);
1620 if (!pipe_ctx->update_flags.bits.enable)
1621 dc->hwss.pipe_control_lock(dc, &dc->current_state->res_ctx.pipe_ctx[i], false);
1624 for (i = 0; i < dc->res_pool->pipe_count; i++)
1625 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable)
1626 dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
1629 * If we are enabling a pipe, we need to wait for pending clear as this is a critical
1630 * part of the enable operation otherwise, DM may request an immediate flip which
1631 * will cause HW to perform an "immediate enable" (as opposed to "vsync enable") which
1632 * is unsupported on DCN.
1634 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1635 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1637 if (pipe->plane_state && !pipe->top_pipe && pipe->update_flags.bits.enable) {
1638 struct hubp *hubp = pipe->plane_res.hubp;
1641 for (j = 0; j < TIMEOUT_FOR_PIPE_ENABLE_MS
1642 && hubp->funcs->hubp_is_flip_pending(hubp); j++)
1647 /* WA to apply WM setting*/
1648 if (dc->hwseq->wa.DEGVIDCN21)
1649 dc->res_pool->hubbub->funcs->apply_DEDCN21_147_wa(dc->res_pool->hubbub);
1653 void dcn20_prepare_bandwidth(
1655 struct dc_state *context)
1657 struct hubbub *hubbub = dc->res_pool->hubbub;
1659 dc->clk_mgr->funcs->update_clocks(
1664 /* program dchubbub watermarks */
1665 hubbub->funcs->program_watermarks(hubbub,
1666 &context->bw_ctx.bw.dcn.watermarks,
1667 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
1671 void dcn20_optimize_bandwidth(
1673 struct dc_state *context)
1675 struct hubbub *hubbub = dc->res_pool->hubbub;
1677 /* program dchubbub watermarks */
1678 hubbub->funcs->program_watermarks(hubbub,
1679 &context->bw_ctx.bw.dcn.watermarks,
1680 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
1683 dc->clk_mgr->funcs->update_clocks(
1689 bool dcn20_update_bandwidth(
1691 struct dc_state *context)
1694 struct dce_hwseq *hws = dc->hwseq;
1696 /* recalculate DML parameters */
1697 if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false))
1700 /* apply updated bandwidth parameters */
1701 dc->hwss.prepare_bandwidth(dc, context);
1703 /* update hubp configs for all pipes */
1704 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1705 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1707 if (pipe_ctx->plane_state == NULL)
1710 if (pipe_ctx->top_pipe == NULL) {
1711 bool blank = !is_pipe_tree_visible(pipe_ctx);
1713 pipe_ctx->stream_res.tg->funcs->program_global_sync(
1714 pipe_ctx->stream_res.tg,
1715 pipe_ctx->pipe_dlg_param.vready_offset,
1716 pipe_ctx->pipe_dlg_param.vstartup_start,
1717 pipe_ctx->pipe_dlg_param.vupdate_offset,
1718 pipe_ctx->pipe_dlg_param.vupdate_width);
1720 pipe_ctx->stream_res.tg->funcs->set_vtg_params(
1721 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
1723 if (pipe_ctx->prev_odm_pipe == NULL)
1724 hws->funcs.blank_pixel_data(dc, pipe_ctx, blank);
1726 if (hws->funcs.setup_vupdate_interrupt)
1727 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
1730 pipe_ctx->plane_res.hubp->funcs->hubp_setup(
1731 pipe_ctx->plane_res.hubp,
1732 &pipe_ctx->dlg_regs,
1733 &pipe_ctx->ttu_regs,
1735 &pipe_ctx->pipe_dlg_param);
1741 void dcn20_enable_writeback(
1743 struct dc_writeback_info *wb_info,
1744 struct dc_state *context)
1747 struct mcif_wb *mcif_wb;
1748 struct timing_generator *optc;
1750 ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES);
1751 ASSERT(wb_info->wb_enabled);
1752 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
1753 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];
1755 /* set the OPTC source mux */
1756 optc = dc->res_pool->timing_generators[dwb->otg_inst];
1757 optc->funcs->set_dwb_source(optc, wb_info->dwb_pipe_inst);
1758 /* set MCIF_WB buffer and arbitration configuration */
1759 mcif_wb->funcs->config_mcif_buf(mcif_wb, &wb_info->mcif_buf_params, wb_info->dwb_params.dest_height);
1760 mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]);
1761 /* Enable MCIF_WB */
1762 mcif_wb->funcs->enable_mcif(mcif_wb);
1764 dwb->funcs->enable(dwb, &wb_info->dwb_params);
1765 /* TODO: add sequence to enable/disable warmup */
1768 void dcn20_disable_writeback(
1770 unsigned int dwb_pipe_inst)
1773 struct mcif_wb *mcif_wb;
1775 ASSERT(dwb_pipe_inst < MAX_DWB_PIPES);
1776 dwb = dc->res_pool->dwbc[dwb_pipe_inst];
1777 mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst];
1779 dwb->funcs->disable(dwb);
1780 mcif_wb->funcs->disable_mcif(mcif_wb);
1783 bool dcn20_wait_for_blank_complete(
1784 struct output_pixel_processor *opp)
1788 for (counter = 0; counter < 1000; counter++) {
1789 if (opp->funcs->dpg_is_blanked(opp))
1795 if (counter == 1000) {
1796 dm_error("DC: failed to blank crtc!\n");
1803 bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx)
1805 struct hubp *hubp = pipe_ctx->plane_res.hubp;
1809 return hubp->funcs->dmdata_status_done(hubp);
1812 void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)
1814 struct dce_hwseq *hws = dc->hwseq;
1816 if (pipe_ctx->stream_res.dsc) {
1817 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
1819 dcn20_dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, true);
1821 dcn20_dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, true);
1822 odm_pipe = odm_pipe->next_odm_pipe;
1827 void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)
1829 struct dce_hwseq *hws = dc->hwseq;
1831 if (pipe_ctx->stream_res.dsc) {
1832 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
1834 dcn20_dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, false);
1836 dcn20_dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, false);
1837 odm_pipe = odm_pipe->next_odm_pipe;
1842 void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx)
1844 struct dc_dmdata_attributes attr = { 0 };
1845 struct hubp *hubp = pipe_ctx->plane_res.hubp;
1847 attr.dmdata_mode = DMDATA_HW_MODE;
1849 dc_is_hdmi_signal(pipe_ctx->stream->signal) ? 32 : 36;
1850 attr.address.quad_part =
1851 pipe_ctx->stream->dmdata_address.quad_part;
1852 attr.dmdata_dl_delta = 0;
1853 attr.dmdata_qos_mode = 0;
1854 attr.dmdata_qos_level = 0;
1855 attr.dmdata_repeat = 1; /* always repeat */
1856 attr.dmdata_updated = 1;
1857 attr.dmdata_sw_data = NULL;
1859 hubp->funcs->dmdata_set_attributes(hubp, &attr);
1862 void dcn20_init_vm_ctx(
1863 struct dce_hwseq *hws,
1865 struct dc_virtual_addr_space_config *va_config,
1868 struct dcn_hubbub_virt_addr_config config;
1871 ASSERT(0); /* VMID cannot be 0 for vm context */
1875 config.page_table_start_addr = va_config->page_table_start_addr;
1876 config.page_table_end_addr = va_config->page_table_end_addr;
1877 config.page_table_block_size = va_config->page_table_block_size_in_bytes;
1878 config.page_table_depth = va_config->page_table_depth;
1879 config.page_table_base_addr = va_config->page_table_base_addr;
1881 dc->res_pool->hubbub->funcs->init_vm_ctx(dc->res_pool->hubbub, &config, vmid);
1884 int dcn20_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)
1886 struct dcn_hubbub_phys_addr_config config;
1888 config.system_aperture.fb_top = pa_config->system_aperture.fb_top;
1889 config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset;
1890 config.system_aperture.fb_base = pa_config->system_aperture.fb_base;
1891 config.system_aperture.agp_top = pa_config->system_aperture.agp_top;
1892 config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot;
1893 config.system_aperture.agp_base = pa_config->system_aperture.agp_base;
1894 config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr;
1895 config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr;
1896 config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr;
1897 config.page_table_default_page_addr = pa_config->page_table_default_page_addr;
1899 return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config);
1902 static bool patch_address_for_sbs_tb_stereo(
1903 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr)
1905 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1906 bool sec_split = pipe_ctx->top_pipe &&
1907 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
1908 if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
1909 (pipe_ctx->stream->timing.timing_3d_format ==
1910 TIMING_3D_FORMAT_SIDE_BY_SIDE ||
1911 pipe_ctx->stream->timing.timing_3d_format ==
1912 TIMING_3D_FORMAT_TOP_AND_BOTTOM)) {
1913 *addr = plane_state->address.grph_stereo.left_addr;
1914 plane_state->address.grph_stereo.left_addr =
1915 plane_state->address.grph_stereo.right_addr;
1919 if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE &&
1920 plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) {
1921 plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO;
1922 plane_state->address.grph_stereo.right_addr =
1923 plane_state->address.grph_stereo.left_addr;
1928 void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)
1930 bool addr_patched = false;
1931 PHYSICAL_ADDRESS_LOC addr;
1932 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1934 if (plane_state == NULL)
1937 addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);
1939 // Call Helper to track VMID use
1940 vm_helper_mark_vmid_used(dc->vm_helper, plane_state->address.vmid, pipe_ctx->plane_res.hubp->inst);
1942 pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(
1943 pipe_ctx->plane_res.hubp,
1944 &plane_state->address,
1945 plane_state->flip_immediate);
1947 plane_state->status.requested_address = plane_state->address;
1949 if (plane_state->flip_immediate)
1950 plane_state->status.current_address = plane_state->address;
1953 pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;
1956 void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx,
1957 struct dc_link_settings *link_settings)
1959 struct encoder_unblank_param params = { { 0 } };
1960 struct dc_stream_state *stream = pipe_ctx->stream;
1961 struct dc_link *link = stream->link;
1962 struct dce_hwseq *hws = link->dc->hwseq;
1963 struct pipe_ctx *odm_pipe;
1966 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
1969 /* only 3 items below are used by unblank */
1970 params.timing = pipe_ctx->stream->timing;
1972 params.link_settings.link_rate = link_settings->link_rate;
1974 if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
1975 if (optc2_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1)
1976 params.timing.pix_clk_100hz /= 2;
1977 pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine(
1978 pipe_ctx->stream_res.stream_enc, params.opp_cnt > 1);
1979 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, ¶ms);
1982 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1983 hws->funcs.edp_backlight_control(link, true);
1987 void dcn20_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx)
1989 struct timing_generator *tg = pipe_ctx->stream_res.tg;
1990 int start_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);
1995 if (tg->funcs->setup_vertical_interrupt2)
1996 tg->funcs->setup_vertical_interrupt2(tg, start_line);
1999 static void dcn20_reset_back_end_for_pipe(
2001 struct pipe_ctx *pipe_ctx,
2002 struct dc_state *context)
2005 DC_LOGGER_INIT(dc->ctx->logger);
2006 if (pipe_ctx->stream_res.stream_enc == NULL) {
2007 pipe_ctx->stream = NULL;
2011 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
2012 /* DPMS may already disable */
2013 if (!pipe_ctx->stream->dpms_off)
2014 core_link_disable_stream(pipe_ctx);
2015 else if (pipe_ctx->stream_res.audio)
2016 dc->hwss.disable_audio_stream(pipe_ctx);
2018 /* free acquired resources */
2019 if (pipe_ctx->stream_res.audio) {
2020 /*disable az_endpoint*/
2021 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
2024 if (dc->caps.dynamic_audio == true) {
2025 /*we have to dynamic arbitrate the audio endpoints*/
2026 /*we free the resource, need reset is_audio_acquired*/
2027 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
2028 pipe_ctx->stream_res.audio, false);
2029 pipe_ctx->stream_res.audio = NULL;
2033 else if (pipe_ctx->stream_res.dsc) {
2034 dp_set_dsc_enable(pipe_ctx, false);
2037 /* by upper caller loop, parent pipe: pipe0, will be reset last.
2038 * back end share by all pipes and will be disable only when disable
2041 if (pipe_ctx->top_pipe == NULL) {
2042 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
2044 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
2045 if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass)
2046 pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
2047 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
2049 if (pipe_ctx->stream_res.tg->funcs->set_drr)
2050 pipe_ctx->stream_res.tg->funcs->set_drr(
2051 pipe_ctx->stream_res.tg, NULL);
2054 for (i = 0; i < dc->res_pool->pipe_count; i++)
2055 if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx)
2058 if (i == dc->res_pool->pipe_count)
2061 pipe_ctx->stream = NULL;
2062 DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n",
2063 pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
2066 void dcn20_reset_hw_ctx_wrap(
2068 struct dc_state *context)
2071 struct dce_hwseq *hws = dc->hwseq;
2074 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
2075 struct pipe_ctx *pipe_ctx_old =
2076 &dc->current_state->res_ctx.pipe_ctx[i];
2077 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2079 if (!pipe_ctx_old->stream)
2082 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe)
2085 if (!pipe_ctx->stream ||
2086 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
2087 struct clock_source *old_clk = pipe_ctx_old->clock_source;
2089 dcn20_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
2090 if (hws->funcs.enable_stream_gating)
2091 hws->funcs.enable_stream_gating(dc, pipe_ctx);
2093 old_clk->funcs->cs_power_down(old_clk);
2098 void dcn20_get_mpctree_visual_confirm_color(
2099 struct pipe_ctx *pipe_ctx,
2100 struct tg_color *color)
2102 const struct tg_color pipe_colors[6] = {
2103 {MAX_TG_COLOR_VALUE, 0, 0}, // red
2104 {MAX_TG_COLOR_VALUE, 0, MAX_TG_COLOR_VALUE}, // yellow
2105 {0, MAX_TG_COLOR_VALUE, 0}, // blue
2106 {MAX_TG_COLOR_VALUE / 2, 0, MAX_TG_COLOR_VALUE / 2}, // purple
2107 {0, 0, MAX_TG_COLOR_VALUE}, // green
2108 {MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE * 2 / 3, 0}, // orange
2111 struct pipe_ctx *top_pipe = pipe_ctx;
2113 while (top_pipe->top_pipe) {
2114 top_pipe = top_pipe->top_pipe;
2117 *color = pipe_colors[top_pipe->pipe_idx];
2120 void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
2122 struct dce_hwseq *hws = dc->hwseq;
2123 struct hubp *hubp = pipe_ctx->plane_res.hubp;
2124 struct mpcc_blnd_cfg blnd_cfg = { {0} };
2125 bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha;
2127 struct mpcc *new_mpcc;
2128 struct mpc *mpc = dc->res_pool->mpc;
2129 struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);
2131 // input to MPCC is always RGB, by default leave black_color at 0
2132 if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) {
2133 hws->funcs.get_hdr_visual_confirm_color(
2134 pipe_ctx, &blnd_cfg.black_color);
2135 } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) {
2136 hws->funcs.get_surface_visual_confirm_color(
2137 pipe_ctx, &blnd_cfg.black_color);
2138 } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE) {
2139 dcn20_get_mpctree_visual_confirm_color(
2140 pipe_ctx, &blnd_cfg.black_color);
2143 if (per_pixel_alpha)
2144 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;
2146 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA;
2148 blnd_cfg.overlap_only = false;
2149 blnd_cfg.global_gain = 0xff;
2151 if (pipe_ctx->plane_state->global_alpha)
2152 blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value;
2154 blnd_cfg.global_alpha = 0xff;
2156 blnd_cfg.background_color_bpc = 4;
2157 blnd_cfg.bottom_gain_mode = 0;
2158 blnd_cfg.top_gain = 0x1f000;
2159 blnd_cfg.bottom_inside_gain = 0x1f000;
2160 blnd_cfg.bottom_outside_gain = 0x1f000;
2161 blnd_cfg.pre_multiplied_alpha = per_pixel_alpha;
2165 * Note: currently there is a bug in init_hw such that
2166 * on resume from hibernate, BIOS sets up MPCC0, and
2167 * we do mpcc_remove but the mpcc cannot go to idle
2168 * after remove. This cause us to pick mpcc1 here,
2169 * which causes a pstate hang for yet unknown reason.
2171 mpcc_id = hubp->inst;
2173 /* check if this MPCC is already being used */
2174 new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id);
2175 /* remove MPCC if being used */
2176 if (new_mpcc != NULL)
2177 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc);
2179 if (dc->debug.sanity_checks)
2180 mpc->funcs->assert_mpcc_idle_before_connect(
2181 dc->res_pool->mpc, mpcc_id);
2183 /* Call MPC to insert new plane */
2184 new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,
2192 ASSERT(new_mpcc != NULL);
2193 hubp->opp_id = pipe_ctx->stream_res.opp->inst;
2194 hubp->mpcc_id = mpcc_id;
2197 void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)
2199 enum dc_lane_count lane_count =
2200 pipe_ctx->stream->link->cur_link_settings.lane_count;
2202 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
2203 struct dc_link *link = pipe_ctx->stream->link;
2205 uint32_t active_total_with_borders;
2206 uint32_t early_control = 0;
2207 struct timing_generator *tg = pipe_ctx->stream_res.tg;
2209 /* For MST, there are multiply stream go to only one link.
2210 * connect DIG back_end to front_end while enable_stream and
2211 * disconnect them during disable_stream
2212 * BY this, it is logic clean to separate stream and link
2214 link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
2215 pipe_ctx->stream_res.stream_enc->id, true);
2217 if (pipe_ctx->plane_state && pipe_ctx->plane_state->flip_immediate != 1) {
2218 if (link->dc->hwss.program_dmdata_engine)
2219 link->dc->hwss.program_dmdata_engine(pipe_ctx);
2222 link->dc->hwss.update_info_frame(pipe_ctx);
2224 /* enable early control to avoid corruption on DP monitor*/
2225 active_total_with_borders =
2226 timing->h_addressable
2227 + timing->h_border_left
2228 + timing->h_border_right;
2230 if (lane_count != 0)
2231 early_control = active_total_with_borders % lane_count;
2233 if (early_control == 0)
2234 early_control = lane_count;
2236 tg->funcs->set_early_control(tg, early_control);
2238 /* enable audio only within mode set */
2239 if (pipe_ctx->stream_res.audio != NULL) {
2240 if (dc_is_dp_signal(pipe_ctx->stream->signal))
2241 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
2245 void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx)
2247 struct dc_stream_state *stream = pipe_ctx->stream;
2248 struct hubp *hubp = pipe_ctx->plane_res.hubp;
2249 bool enable = false;
2250 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;
2251 enum dynamic_metadata_mode mode = dc_is_dp_signal(stream->signal)
2255 /* if using dynamic meta, don't set up generic infopackets */
2256 if (pipe_ctx->stream->dmdata_address.quad_part != 0) {
2257 pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false;
2264 if (!stream_enc || !stream_enc->funcs->set_dynamic_metadata)
2267 stream_enc->funcs->set_dynamic_metadata(stream_enc, enable,
2271 void dcn20_fpga_init_hw(struct dc *dc)
2274 struct dce_hwseq *hws = dc->hwseq;
2275 struct resource_pool *res_pool = dc->res_pool;
2276 struct dc_state *context = dc->current_state;
2278 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
2279 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
2281 // Initialize the dccg
2282 if (res_pool->dccg->funcs->dccg_init)
2283 res_pool->dccg->funcs->dccg_init(res_pool->dccg);
2285 //Enable ability to power gate / don't force power on permanently
2286 hws->funcs.enable_power_gating_plane(hws, true);
2288 // Specific to FPGA dccg and registers
2289 REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF);
2290 REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF);
2292 hws->funcs.dccg_init(hws);
2294 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2);
2295 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
2296 REG_WRITE(REFCLK_CNTL, 0);
2300 /* Blank pixel data with OPP DPG */
2301 for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
2302 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2304 if (tg->funcs->is_tg_enabled(tg))
2305 dcn20_init_blank(dc, tg);
2308 for (i = 0; i < res_pool->timing_generator_count; i++) {
2309 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2311 if (tg->funcs->is_tg_enabled(tg))
2312 tg->funcs->lock(tg);
2315 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2316 struct dpp *dpp = res_pool->dpps[i];
2318 dpp->funcs->dpp_reset(dpp);
2321 /* Reset all MPCC muxes */
2322 res_pool->mpc->funcs->mpc_init(res_pool->mpc);
2324 /* initialize OPP mpc_tree parameter */
2325 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {
2326 res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst;
2327 res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
2328 for (j = 0; j < MAX_PIPES; j++)
2329 res_pool->opps[i]->mpcc_disconnect_pending[j] = false;
2332 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2333 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2334 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2335 struct hubp *hubp = dc->res_pool->hubps[i];
2336 struct dpp *dpp = dc->res_pool->dpps[i];
2338 pipe_ctx->stream_res.tg = tg;
2339 pipe_ctx->pipe_idx = i;
2341 pipe_ctx->plane_res.hubp = hubp;
2342 pipe_ctx->plane_res.dpp = dpp;
2343 pipe_ctx->plane_res.mpcc_inst = dpp->inst;
2344 hubp->mpcc_id = dpp->inst;
2345 hubp->opp_id = OPP_ID_INVALID;
2346 hubp->power_gated = false;
2347 pipe_ctx->stream_res.opp = NULL;
2349 hubp->funcs->hubp_init(hubp);
2351 //dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
2352 //dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
2353 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
2354 pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
2356 hws->funcs.plane_atomic_disconnect(dc, pipe_ctx);
2359 /* initialize DWB pointer to MCIF_WB */
2360 for (i = 0; i < res_pool->res_cap->num_dwb; i++)
2361 res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i];
2363 for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
2364 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2366 if (tg->funcs->is_tg_enabled(tg))
2367 tg->funcs->unlock(tg);
2370 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2371 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2373 dc->hwss.disable_plane(dc, pipe_ctx);
2375 pipe_ctx->stream_res.tg = NULL;
2376 pipe_ctx->plane_res.hubp = NULL;
2379 for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
2380 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2382 tg->funcs->tg_init(tg);