drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 #include <linux/delay.h>
  26
  27 #include "dm_services.h"
  28 #include "basics/dc_common.h"
  29 #include "dm_helpers.h"
  30 #include "core_types.h"
  31 #include "resource.h"
  32 #include "dcn20_resource.h"
  33 #include "dcn20_hwseq.h"
  34 #include "dce/dce_hwseq.h"
  35 #include "dcn20_dsc.h"
  36 #include "dcn20_optc.h"
  37 #include "abm.h"
  38 #include "clk_mgr.h"
  39 #include "dmcu.h"
  40 #include "hubp.h"
  41 #include "timing_generator.h"
  42 #include "opp.h"
  43 #include "ipp.h"
  44 #include "mpc.h"
  45 #include "mcif_wb.h"
  46 #include "dchubbub.h"
  47 #include "reg_helper.h"
  48 #include "dcn10/dcn10_cm_common.h"
  49 #include "dc_link_dp.h"
  50 #include "vm_helper.h"
  51 #include "dccg.h"
  52 #include "dc_dmub_srv.h"
  53 #include "dce/dmub_hw_lock_mgr.h"
  54 #include "hw_sequencer.h"
  55 #include "inc/link_dpcd.h"
  56 #include "dpcd_defs.h"
  57 #include "inc/link_enc_cfg.h"
  58 #include "link_hwss.h"
  59
  60 #define DC_LOGGER_INIT(logger)
  61
  62 #define CTX \
  63         hws->ctx
  64 #define REG(reg)\
  65         hws->regs->reg
  66
  67 #undef FN
  68 #define FN(reg_name, field_name) \
  69         hws->shifts->field_name, hws->masks->field_name
  70
  71 static int find_free_gsl_group(const struct dc *dc)
  72 {
  73         if (dc->res_pool->gsl_groups.gsl_0 == 0)
  74                 return 1;
  75         if (dc->res_pool->gsl_groups.gsl_1 == 0)
  76                 return 2;
  77         if (dc->res_pool->gsl_groups.gsl_2 == 0)
  78                 return 3;
  79
  80         return 0;
  81 }
  82
  83 /* NOTE: This is not a generic setup_gsl function (hence the suffix as_lock)
  84  * This is only used to lock pipes in pipe splitting case with immediate flip
  85  * Ordinary MPC/OTG locks suppress VUPDATE which doesn't help with immediate,
  86  * so we get tearing with freesync since we cannot flip multiple pipes
  87  * atomically.
  88  * We use GSL for this:
  89  * - immediate flip: find first available GSL group if not already assigned
  90  *                   program gsl with that group, set current OTG as master
  91  *                   and always us 0x4 = AND of flip_ready from all pipes
  92  * - vsync flip: disable GSL if used
  93  *
  94  * Groups in stream_res are stored as +1 from HW registers, i.e.
  95  * gsl_0 <=> pipe_ctx->stream_res.gsl_group == 1
  96  * Using a magic value like -1 would require tracking all inits/resets
  97  */
  98 static void dcn20_setup_gsl_group_as_lock(
  99                 const struct dc *dc,
 100                 struct pipe_ctx *pipe_ctx,
 101                 bool enable)
 102 {
 103         struct gsl_params gsl;
 104         int group_idx;
 105
 106         memset(&gsl, 0, sizeof(struct gsl_params));
 107
 108         if (enable) {
 109                 /* return if group already assigned since GSL was set up
 110                  * for vsync flip, we would unassign so it can't be "left over"
 111                  */
 112                 if (pipe_ctx->stream_res.gsl_group > 0)
 113                         return;
 114
 115                 group_idx = find_free_gsl_group(dc);
 116                 ASSERT(group_idx != 0);
 117                 pipe_ctx->stream_res.gsl_group = group_idx;
 118
 119                 /* set gsl group reg field and mark resource used */
 120                 switch (group_idx) {
 121                 case 1:
 122                         gsl.gsl0_en = 1;
 123                         dc->res_pool->gsl_groups.gsl_0 = 1;
 124                         break;
 125                 case 2:
 126                         gsl.gsl1_en = 1;
 127                         dc->res_pool->gsl_groups.gsl_1 = 1;
 128                         break;
 129                 case 3:
 130                         gsl.gsl2_en = 1;
 131                         dc->res_pool->gsl_groups.gsl_2 = 1;
 132                         break;
 133                 default:
 134                         BREAK_TO_DEBUGGER();
 135                         return; // invalid case
 136                 }
 137                 gsl.gsl_master_en = 1;
 138         } else {
 139                 group_idx = pipe_ctx->stream_res.gsl_group;
 140                 if (group_idx == 0)
 141                         return; // if not in use, just return
 142
 143                 pipe_ctx->stream_res.gsl_group = 0;
 144
 145                 /* unset gsl group reg field and mark resource free */
 146                 switch (group_idx) {
 147                 case 1:
 148                         gsl.gsl0_en = 0;
 149                         dc->res_pool->gsl_groups.gsl_0 = 0;
 150                         break;
 151                 case 2:
 152                         gsl.gsl1_en = 0;
 153                         dc->res_pool->gsl_groups.gsl_1 = 0;
 154                         break;
 155                 case 3:
 156                         gsl.gsl2_en = 0;
 157                         dc->res_pool->gsl_groups.gsl_2 = 0;
 158                         break;
 159                 default:
 160                         BREAK_TO_DEBUGGER();
 161                         return;
 162                 }
 163                 gsl.gsl_master_en = 0;
 164         }
 165
 166         /* at this point we want to program whether it's to enable or disable */
 167         if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL &&
 168                 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) {
 169                 pipe_ctx->stream_res.tg->funcs->set_gsl(
 170                         pipe_ctx->stream_res.tg,
 171                         &gsl);
 172
 173                 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select(
 174                         pipe_ctx->stream_res.tg, group_idx,     enable ? 4 : 0);
 175         } else
 176                 BREAK_TO_DEBUGGER();
 177 }
 178
 179 void dcn20_set_flip_control_gsl(
 180                 struct pipe_ctx *pipe_ctx,
 181                 bool flip_immediate)
 182 {
 183         if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl)
 184                 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl(
 185                                 pipe_ctx->plane_res.hubp, flip_immediate);
 186
 187 }
 188
 189 void dcn20_enable_power_gating_plane(
 190         struct dce_hwseq *hws,
 191         bool enable)
 192 {
 193         bool force_on = true; /* disable power gating */
 194
 195         if (enable)
 196                 force_on = false;
 197
 198         /* DCHUBP0/1/2/3/4/5 */
 199         REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on);
 200         REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on);
 201         REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on);
 202         REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on);
 203         if (REG(DOMAIN8_PG_CONFIG))
 204                 REG_UPDATE(DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on);
 205         if (REG(DOMAIN10_PG_CONFIG))
 206                 REG_UPDATE(DOMAIN10_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on);
 207
 208         /* DPP0/1/2/3/4/5 */
 209         REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on);
 210         REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on);
 211         REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on);
 212         REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);
 213         if (REG(DOMAIN9_PG_CONFIG))
 214                 REG_UPDATE(DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on);
 215         if (REG(DOMAIN11_PG_CONFIG))
 216                 REG_UPDATE(DOMAIN11_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on);
 217
 218         /* DCS0/1/2/3/4/5 */
 219         REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, force_on);
 220         REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, force_on);
 221         REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, force_on);
 222         if (REG(DOMAIN19_PG_CONFIG))
 223                 REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, force_on);
 224         if (REG(DOMAIN20_PG_CONFIG))
 225                 REG_UPDATE(DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, force_on);
 226         if (REG(DOMAIN21_PG_CONFIG))
 227                 REG_UPDATE(DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, force_on);
 228 }
 229
 230 void dcn20_dccg_init(struct dce_hwseq *hws)
 231 {
 232         /*
 233          * set MICROSECOND_TIME_BASE_DIV
 234          * 100Mhz refclk -> 0x120264
 235          * 27Mhz refclk -> 0x12021b
 236          * 48Mhz refclk -> 0x120230
 237          *
 238          */
 239         REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x120264);
 240
 241         /*
 242          * set MILLISECOND_TIME_BASE_DIV
 243          * 100Mhz refclk -> 0x1186a0
 244          * 27Mhz refclk -> 0x106978
 245          * 48Mhz refclk -> 0x10bb80
 246          *
 247          */
 248         REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x1186a0);
 249
 250         /* This value is dependent on the hardware pipeline delay so set once per SOC */
 251         REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0xe01003c);
 252 }
 253
 254 void dcn20_disable_vga(
 255         struct dce_hwseq *hws)
 256 {
 257         REG_WRITE(D1VGA_CONTROL, 0);
 258         REG_WRITE(D2VGA_CONTROL, 0);
 259         REG_WRITE(D3VGA_CONTROL, 0);
 260         REG_WRITE(D4VGA_CONTROL, 0);
 261         REG_WRITE(D5VGA_CONTROL, 0);
 262         REG_WRITE(D6VGA_CONTROL, 0);
 263 }
 264
 265 void dcn20_program_triple_buffer(
 266         const struct dc *dc,
 267         struct pipe_ctx *pipe_ctx,
 268         bool enable_triple_buffer)
 269 {
 270         if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) {
 271                 pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer(
 272                         pipe_ctx->plane_res.hubp,
 273                         enable_triple_buffer);
 274         }
 275 }
 276
 277 /* Blank pixel data during initialization */
 278 void dcn20_init_blank(
 279                 struct dc *dc,
 280                 struct timing_generator *tg)
 281 {
 282         struct dce_hwseq *hws = dc->hwseq;
 283         enum dc_color_space color_space;
 284         struct tg_color black_color = {0};
 285         struct output_pixel_processor *opp = NULL;
 286         struct output_pixel_processor *bottom_opp = NULL;
 287         uint32_t num_opps, opp_id_src0, opp_id_src1;
 288         uint32_t otg_active_width, otg_active_height;
 289
 290         /* program opp dpg blank color */
 291         color_space = COLOR_SPACE_SRGB;
 292         color_space_to_black_color(dc, color_space, &black_color);
 293
 294         /* get the OTG active size */
 295         tg->funcs->get_otg_active_size(tg,
 296                         &otg_active_width,
 297                         &otg_active_height);
 298
 299         /* get the OPTC source */
 300         tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1);
 301
 302         if (opp_id_src0 >= dc->res_pool->res_cap->num_opp) {
 303                 ASSERT(false);
 304                 return;
 305         }
 306         opp = dc->res_pool->opps[opp_id_src0];
 307
 308         if (num_opps == 2) {
 309                 otg_active_width = otg_active_width / 2;
 310
 311                 if (opp_id_src1 >= dc->res_pool->res_cap->num_opp) {
 312                         ASSERT(false);
 313                         return;
 314                 }
 315                 bottom_opp = dc->res_pool->opps[opp_id_src1];
 316         }
 317
 318         opp->funcs->opp_set_disp_pattern_generator(
 319                         opp,
 320                         CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,
 321                         CONTROLLER_DP_COLOR_SPACE_UDEFINED,
 322                         COLOR_DEPTH_UNDEFINED,
 323                         &black_color,
 324                         otg_active_width,
 325                         otg_active_height,
 326                         0);
 327
 328         if (num_opps == 2) {
 329                 bottom_opp->funcs->opp_set_disp_pattern_generator(
 330                                 bottom_opp,
 331                                 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,
 332                                 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
 333                                 COLOR_DEPTH_UNDEFINED,
 334                                 &black_color,
 335                                 otg_active_width,
 336                                 otg_active_height,
 337                                 0);
 338         }
 339
 340         hws->funcs.wait_for_blank_complete(opp);
 341 }
 342
 343 void dcn20_dsc_pg_control(
 344                 struct dce_hwseq *hws,
 345                 unsigned int dsc_inst,
 346                 bool power_on)
 347 {
 348         uint32_t power_gate = power_on ? 0 : 1;
 349         uint32_t pwr_status = power_on ? 0 : 2;
 350         uint32_t org_ip_request_cntl = 0;
 351
 352         if (hws->ctx->dc->debug.disable_dsc_power_gate)
 353                 return;
 354
 355         if (REG(DOMAIN16_PG_CONFIG) == 0)
 356                 return;
 357
 358         REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
 359         if (org_ip_request_cntl == 0)
 360                 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
 361
 362         switch (dsc_inst) {
 363         case 0: /* DSC0 */
 364                 REG_UPDATE(DOMAIN16_PG_CONFIG,
 365                                 DOMAIN16_POWER_GATE, power_gate);
 366
 367                 REG_WAIT(DOMAIN16_PG_STATUS,
 368                                 DOMAIN16_PGFSM_PWR_STATUS, pwr_status,
 369                                 1, 1000);
 370                 break;
 371         case 1: /* DSC1 */
 372                 REG_UPDATE(DOMAIN17_PG_CONFIG,
 373                                 DOMAIN17_POWER_GATE, power_gate);
 374
 375                 REG_WAIT(DOMAIN17_PG_STATUS,
 376                                 DOMAIN17_PGFSM_PWR_STATUS, pwr_status,
 377                                 1, 1000);
 378                 break;
 379         case 2: /* DSC2 */
 380                 REG_UPDATE(DOMAIN18_PG_CONFIG,
 381                                 DOMAIN18_POWER_GATE, power_gate);
 382
 383                 REG_WAIT(DOMAIN18_PG_STATUS,
 384                                 DOMAIN18_PGFSM_PWR_STATUS, pwr_status,
 385                                 1, 1000);
 386                 break;
 387         case 3: /* DSC3 */
 388                 REG_UPDATE(DOMAIN19_PG_CONFIG,
 389                                 DOMAIN19_POWER_GATE, power_gate);
 390
 391                 REG_WAIT(DOMAIN19_PG_STATUS,
 392                                 DOMAIN19_PGFSM_PWR_STATUS, pwr_status,
 393                                 1, 1000);
 394                 break;
 395         case 4: /* DSC4 */
 396                 REG_UPDATE(DOMAIN20_PG_CONFIG,
 397                                 DOMAIN20_POWER_GATE, power_gate);
 398
 399                 REG_WAIT(DOMAIN20_PG_STATUS,
 400                                 DOMAIN20_PGFSM_PWR_STATUS, pwr_status,
 401                                 1, 1000);
 402                 break;
 403         case 5: /* DSC5 */
 404                 REG_UPDATE(DOMAIN21_PG_CONFIG,
 405                                 DOMAIN21_POWER_GATE, power_gate);
 406
 407                 REG_WAIT(DOMAIN21_PG_STATUS,
 408                                 DOMAIN21_PGFSM_PWR_STATUS, pwr_status,
 409                                 1, 1000);
 410                 break;
 411         default:
 412                 BREAK_TO_DEBUGGER();
 413                 break;
 414         }
 415
 416         if (org_ip_request_cntl == 0)
 417                 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
 418 }
 419
 420 void dcn20_dpp_pg_control(
 421                 struct dce_hwseq *hws,
 422                 unsigned int dpp_inst,
 423                 bool power_on)
 424 {
 425         uint32_t power_gate = power_on ? 0 : 1;
 426         uint32_t pwr_status = power_on ? 0 : 2;
 427
 428         if (hws->ctx->dc->debug.disable_dpp_power_gate)
 429                 return;
 430         if (REG(DOMAIN1_PG_CONFIG) == 0)
 431                 return;
 432
 433         switch (dpp_inst) {
 434         case 0: /* DPP0 */
 435                 REG_UPDATE(DOMAIN1_PG_CONFIG,
 436                                 DOMAIN1_POWER_GATE, power_gate);
 437
 438                 REG_WAIT(DOMAIN1_PG_STATUS,
 439                                 DOMAIN1_PGFSM_PWR_STATUS, pwr_status,
 440                                 1, 1000);
 441                 break;
 442         case 1: /* DPP1 */
 443                 REG_UPDATE(DOMAIN3_PG_CONFIG,
 444                                 DOMAIN3_POWER_GATE, power_gate);
 445
 446                 REG_WAIT(DOMAIN3_PG_STATUS,
 447                                 DOMAIN3_PGFSM_PWR_STATUS, pwr_status,
 448                                 1, 1000);
 449                 break;
 450         case 2: /* DPP2 */
 451                 REG_UPDATE(DOMAIN5_PG_CONFIG,
 452                                 DOMAIN5_POWER_GATE, power_gate);
 453
 454                 REG_WAIT(DOMAIN5_PG_STATUS,
 455                                 DOMAIN5_PGFSM_PWR_STATUS, pwr_status,
 456                                 1, 1000);
 457                 break;
 458         case 3: /* DPP3 */
 459                 REG_UPDATE(DOMAIN7_PG_CONFIG,
 460                                 DOMAIN7_POWER_GATE, power_gate);
 461
 462                 REG_WAIT(DOMAIN7_PG_STATUS,
 463                                 DOMAIN7_PGFSM_PWR_STATUS, pwr_status,
 464                                 1, 1000);
 465                 break;
 466         case 4: /* DPP4 */
 467                 REG_UPDATE(DOMAIN9_PG_CONFIG,
 468                                 DOMAIN9_POWER_GATE, power_gate);
 469
 470                 REG_WAIT(DOMAIN9_PG_STATUS,
 471                                 DOMAIN9_PGFSM_PWR_STATUS, pwr_status,
 472                                 1, 1000);
 473                 break;
 474         case 5: /* DPP5 */
 475                 /*
 476                  * Do not power gate DPP5, should be left at HW default, power on permanently.
 477                  * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard
 478                  * reset.
 479                  * REG_UPDATE(DOMAIN11_PG_CONFIG,
 480                  *              DOMAIN11_POWER_GATE, power_gate);
 481                  *
 482                  * REG_WAIT(DOMAIN11_PG_STATUS,
 483                  *              DOMAIN11_PGFSM_PWR_STATUS, pwr_status,
 484                  *              1, 1000);
 485                  */
 486                 break;
 487         default:
 488                 BREAK_TO_DEBUGGER();
 489                 break;
 490         }
 491 }
 492
 493
 494 void dcn20_hubp_pg_control(
 495                 struct dce_hwseq *hws,
 496                 unsigned int hubp_inst,
 497                 bool power_on)
 498 {
 499         uint32_t power_gate = power_on ? 0 : 1;
 500         uint32_t pwr_status = power_on ? 0 : 2;
 501
 502         if (hws->ctx->dc->debug.disable_hubp_power_gate)
 503                 return;
 504         if (REG(DOMAIN0_PG_CONFIG) == 0)
 505                 return;
 506
 507         switch (hubp_inst) {
 508         case 0: /* DCHUBP0 */
 509                 REG_UPDATE(DOMAIN0_PG_CONFIG,
 510                                 DOMAIN0_POWER_GATE, power_gate);
 511
 512                 REG_WAIT(DOMAIN0_PG_STATUS,
 513                                 DOMAIN0_PGFSM_PWR_STATUS, pwr_status,
 514                                 1, 1000);
 515                 break;
 516         case 1: /* DCHUBP1 */
 517                 REG_UPDATE(DOMAIN2_PG_CONFIG,
 518                                 DOMAIN2_POWER_GATE, power_gate);
 519
 520                 REG_WAIT(DOMAIN2_PG_STATUS,
 521                                 DOMAIN2_PGFSM_PWR_STATUS, pwr_status,
 522                                 1, 1000);
 523                 break;
 524         case 2: /* DCHUBP2 */
 525                 REG_UPDATE(DOMAIN4_PG_CONFIG,
 526                                 DOMAIN4_POWER_GATE, power_gate);
 527
 528                 REG_WAIT(DOMAIN4_PG_STATUS,
 529                                 DOMAIN4_PGFSM_PWR_STATUS, pwr_status,
 530                                 1, 1000);
 531                 break;
 532         case 3: /* DCHUBP3 */
 533                 REG_UPDATE(DOMAIN6_PG_CONFIG,
 534                                 DOMAIN6_POWER_GATE, power_gate);
 535
 536                 REG_WAIT(DOMAIN6_PG_STATUS,
 537                                 DOMAIN6_PGFSM_PWR_STATUS, pwr_status,
 538                                 1, 1000);
 539                 break;
 540         case 4: /* DCHUBP4 */
 541                 REG_UPDATE(DOMAIN8_PG_CONFIG,
 542                                 DOMAIN8_POWER_GATE, power_gate);
 543
 544                 REG_WAIT(DOMAIN8_PG_STATUS,
 545                                 DOMAIN8_PGFSM_PWR_STATUS, pwr_status,
 546                                 1, 1000);
 547                 break;
 548         case 5: /* DCHUBP5 */
 549                 /*
 550                  * Do not power gate DCHUB5, should be left at HW default, power on permanently.
 551                  * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard
 552                  * reset.
 553                  * REG_UPDATE(DOMAIN10_PG_CONFIG,
 554                  *              DOMAIN10_POWER_GATE, power_gate);
 555                  *
 556                  * REG_WAIT(DOMAIN10_PG_STATUS,
 557                  *              DOMAIN10_PGFSM_PWR_STATUS, pwr_status,
 558                  *              1, 1000);
 559                  */
 560                 break;
 561         default:
 562                 BREAK_TO_DEBUGGER();
 563                 break;
 564         }
 565 }
 566
 567
 568 /* disable HW used by plane.
 569  * note:  cannot disable until disconnect is complete
 570  */
 571 void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
 572 {
 573         struct dce_hwseq *hws = dc->hwseq;
 574         struct hubp *hubp = pipe_ctx->plane_res.hubp;
 575         struct dpp *dpp = pipe_ctx->plane_res.dpp;
 576
 577         dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);
 578
 579         /* In flip immediate with pipe splitting case GSL is used for
 580          * synchronization so we must disable it when the plane is disabled.
 581          */
 582         if (pipe_ctx->stream_res.gsl_group != 0)
 583                 dcn20_setup_gsl_group_as_lock(dc, pipe_ctx, false);
 584
 585         dc->hwss.set_flip_control_gsl(pipe_ctx, false);
 586
 587         hubp->funcs->hubp_clk_cntl(hubp, false);
 588
 589         dpp->funcs->dpp_dppclk_control(dpp, false, false);
 590
 591         hubp->power_gated = true;
 592
 593         hws->funcs.plane_atomic_power_down(dc,
 594                         pipe_ctx->plane_res.dpp,
 595                         pipe_ctx->plane_res.hubp);
 596
 597         pipe_ctx->stream = NULL;
 598         memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res));
 599         memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res));
 600         pipe_ctx->top_pipe = NULL;
 601         pipe_ctx->bottom_pipe = NULL;
 602         pipe_ctx->plane_state = NULL;
 603 }
 604
 605
 606 void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
 607 {
 608         DC_LOGGER_INIT(dc->ctx->logger);
 609
 610         if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)
 611                 return;
 612
 613         dcn20_plane_atomic_disable(dc, pipe_ctx);
 614
 615         DC_LOG_DC("Power down front end %d\n",
 616                                         pipe_ctx->pipe_idx);
 617 }
 618
 619 void dcn20_disable_pixel_data(struct dc *dc, struct pipe_ctx *pipe_ctx, bool blank)
 620 {
 621         dcn20_blank_pixel_data(dc, pipe_ctx, blank);
 622 }
 623
 624 static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream,
 625                 int opp_cnt)
 626 {
 627         bool hblank_halved = optc2_is_two_pixels_per_containter(&stream->timing);
 628         int flow_ctrl_cnt;
 629
 630         if (opp_cnt >= 2)
 631                 hblank_halved = true;
 632
 633         flow_ctrl_cnt = stream->timing.h_total - stream->timing.h_addressable -
 634                         stream->timing.h_border_left -
 635                         stream->timing.h_border_right;
 636
 637         if (hblank_halved)
 638                 flow_ctrl_cnt /= 2;
 639
 640         /* ODM combine 4:1 case */
 641         if (opp_cnt == 4)
 642                 flow_ctrl_cnt /= 2;
 643
 644         return flow_ctrl_cnt;
 645 }
 646
 647 enum dc_status dcn20_enable_stream_timing(
 648                 struct pipe_ctx *pipe_ctx,
 649                 struct dc_state *context,
 650                 struct dc *dc)
 651 {
 652         struct dce_hwseq *hws = dc->hwseq;
 653         struct dc_stream_state *stream = pipe_ctx->stream;
 654         struct drr_params params = {0};
 655         unsigned int event_triggers = 0;
 656         struct pipe_ctx *odm_pipe;
 657         int opp_cnt = 1;
 658         int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst };
 659         bool interlace = stream->timing.flags.INTERLACE;
 660         int i;
 661         struct mpc_dwb_flow_control flow_control;
 662         struct mpc *mpc = dc->res_pool->mpc;
 663         bool rate_control_2x_pclk = (interlace || optc2_is_two_pixels_per_containter(&stream->timing));
 664         unsigned int k1_div = PIXEL_RATE_DIV_NA;
 665         unsigned int k2_div = PIXEL_RATE_DIV_NA;
 666
 667         if (hws->funcs.calculate_dccg_k1_k2_values && dc->res_pool->dccg->funcs->set_pixel_rate_div) {
 668                 hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div);
 669
 670                 dc->res_pool->dccg->funcs->set_pixel_rate_div(
 671                         dc->res_pool->dccg,
 672                         pipe_ctx->stream_res.tg->inst,
 673                         k1_div, k2_div);
 674         }
 675         /* by upper caller loop, pipe0 is parent pipe and be called first.
 676          * back end is set up by for pipe0. Other children pipe share back end
 677          * with pipe 0. No program is needed.
 678          */
 679         if (pipe_ctx->top_pipe != NULL)
 680                 return DC_OK;
 681
 682         /* TODO check if timing_changed, disable stream if timing changed */
 683
 684         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
 685                 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;
 686                 opp_cnt++;
 687         }
 688
 689         if (opp_cnt > 1)
 690                 pipe_ctx->stream_res.tg->funcs->set_odm_combine(
 691                                 pipe_ctx->stream_res.tg,
 692                                 opp_inst, opp_cnt,
 693                                 &pipe_ctx->stream->timing);
 694
 695         /* HW program guide assume display already disable
 696          * by unplug sequence. OTG assume stop.
 697          */
 698         pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true);
 699
 700         if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
 701                         pipe_ctx->clock_source,
 702                         &pipe_ctx->stream_res.pix_clk_params,
 703                         &pipe_ctx->pll_settings)) {
 704                 BREAK_TO_DEBUGGER();
 705                 return DC_ERROR_UNEXPECTED;
 706         }
 707
 708         if (dc->hwseq->funcs.PLAT_58856_wa && (!dc_is_dp_signal(stream->signal)))
 709                 dc->hwseq->funcs.PLAT_58856_wa(context, pipe_ctx);
 710
 711         pipe_ctx->stream_res.tg->funcs->program_timing(
 712                         pipe_ctx->stream_res.tg,
 713                         &stream->timing,
 714                         pipe_ctx->pipe_dlg_param.vready_offset,
 715                         pipe_ctx->pipe_dlg_param.vstartup_start,
 716                         pipe_ctx->pipe_dlg_param.vupdate_offset,
 717                         pipe_ctx->pipe_dlg_param.vupdate_width,
 718                         pipe_ctx->stream->signal,
 719                         true);
 720
 721         rate_control_2x_pclk = rate_control_2x_pclk || opp_cnt > 1;
 722         flow_control.flow_ctrl_mode = 0;
 723         flow_control.flow_ctrl_cnt0 = 0x80;
 724         flow_control.flow_ctrl_cnt1 = calc_mpc_flow_ctrl_cnt(stream, opp_cnt);
 725         if (mpc->funcs->set_out_rate_control) {
 726                 for (i = 0; i < opp_cnt; ++i) {
 727                         mpc->funcs->set_out_rate_control(
 728                                         mpc, opp_inst[i],
 729                                         true,
 730                                         rate_control_2x_pclk,
 731                                         &flow_control);
 732                 }
 733         }
 734
 735         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
 736                 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control(
 737                                 odm_pipe->stream_res.opp,
 738                                 true);
 739
 740         pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
 741                         pipe_ctx->stream_res.opp,
 742                         true);
 743
 744         hws->funcs.blank_pixel_data(dc, pipe_ctx, true);
 745
 746         /* VTG is  within DCHUB command block. DCFCLK is always on */
 747         if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {
 748                 BREAK_TO_DEBUGGER();
 749                 return DC_ERROR_UNEXPECTED;
 750         }
 751
 752         hws->funcs.wait_for_blank_complete(pipe_ctx->stream_res.opp);
 753
 754         params.vertical_total_min = stream->adjust.v_total_min;
 755         params.vertical_total_max = stream->adjust.v_total_max;
 756         params.vertical_total_mid = stream->adjust.v_total_mid;
 757         params.vertical_total_mid_frame_num = stream->adjust.v_total_mid_frame_num;
 758         if (pipe_ctx->stream_res.tg->funcs->set_drr)
 759                 pipe_ctx->stream_res.tg->funcs->set_drr(
 760                         pipe_ctx->stream_res.tg, &params);
 761
 762         // DRR should set trigger event to monitor surface update event
 763         if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0)
 764                 event_triggers = 0x80;
 765         /* Event triggers and num frames initialized for DRR, but can be
 766          * later updated for PSR use. Note DRR trigger events are generated
 767          * regardless of whether num frames met.
 768          */
 769         if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)
 770                 pipe_ctx->stream_res.tg->funcs->set_static_screen_control(
 771                                 pipe_ctx->stream_res.tg, event_triggers, 2);
 772
 773         /* TODO program crtc source select for non-virtual signal*/
 774         /* TODO program FMT */
 775         /* TODO setup link_enc */
 776         /* TODO set stream attributes */
 777         /* TODO program audio */
 778         /* TODO enable stream if timing changed */
 779         /* TODO unblank stream if DP */
 780
 781         if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.type == SUBVP_PHANTOM) {
 782                 if (pipe_ctx->stream_res.tg && pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable)
 783                         pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable(pipe_ctx->stream_res.tg);
 784         }
 785         return DC_OK;
 786 }
 787
 788 void dcn20_program_output_csc(struct dc *dc,
 789                 struct pipe_ctx *pipe_ctx,
 790                 enum dc_color_space colorspace,
 791                 uint16_t *matrix,
 792                 int opp_id)
 793 {
 794         struct mpc *mpc = dc->res_pool->mpc;
 795         enum mpc_output_csc_mode ocsc_mode = MPC_OUTPUT_CSC_COEF_A;
 796         int mpcc_id = pipe_ctx->plane_res.hubp->inst;
 797
 798         if (mpc->funcs->power_on_mpc_mem_pwr)
 799                 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true);
 800
 801         if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
 802                 if (mpc->funcs->set_output_csc != NULL)
 803                         mpc->funcs->set_output_csc(mpc,
 804                                         opp_id,
 805                                         matrix,
 806                                         ocsc_mode);
 807         } else {
 808                 if (mpc->funcs->set_ocsc_default != NULL)
 809                         mpc->funcs->set_ocsc_default(mpc,
 810                                         opp_id,
 811                                         colorspace,
 812                                         ocsc_mode);
 813         }
 814 }
 815
 816 bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
 817                                 const struct dc_stream_state *stream)
 818 {
 819         int mpcc_id = pipe_ctx->plane_res.hubp->inst;
 820         struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
 821         struct pwl_params *params = NULL;
 822         /*
 823          * program OGAM only for the top pipe
 824          * if there is a pipe split then fix diagnostic is required:
 825          * how to pass OGAM parameter for stream.
 826          * if programming for all pipes is required then remove condition
 827          * pipe_ctx->top_pipe == NULL ,but then fix the diagnostic.
 828          */
 829         if (mpc->funcs->power_on_mpc_mem_pwr)
 830                 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true);
 831         if (pipe_ctx->top_pipe == NULL
 832                         && mpc->funcs->set_output_gamma && stream->out_transfer_func) {
 833                 if (stream->out_transfer_func->type == TF_TYPE_HWPWL)
 834                         params = &stream->out_transfer_func->pwl;
 835                 else if (pipe_ctx->stream->out_transfer_func->type ==
 836                         TF_TYPE_DISTRIBUTED_POINTS &&
 837                         cm_helper_translate_curve_to_hw_format(
 838                         stream->out_transfer_func,
 839                         &mpc->blender_params, false))
 840                         params = &mpc->blender_params;
 841                 /*
 842                  * there is no ROM
 843                  */
 844                 if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED)
 845                         BREAK_TO_DEBUGGER();
 846         }
 847         /*
 848          * if above if is not executed then 'params' equal to 0 and set in bypass
 849          */
 850         mpc->funcs->set_output_gamma(mpc, mpcc_id, params);
 851
 852         return true;
 853 }
 854
 855 bool dcn20_set_blend_lut(
 856         struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
 857 {
 858         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
 859         bool result = true;
 860         struct pwl_params *blend_lut = NULL;
 861
 862         if (plane_state->blend_tf) {
 863                 if (plane_state->blend_tf->type == TF_TYPE_HWPWL)
 864                         blend_lut = &plane_state->blend_tf->pwl;
 865                 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) {
 866                         cm_helper_translate_curve_to_hw_format(
 867                                         plane_state->blend_tf,
 868                                         &dpp_base->regamma_params, false);
 869                         blend_lut = &dpp_base->regamma_params;
 870                 }
 871         }
 872         result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut);
 873
 874         return result;
 875 }
 876
 877 bool dcn20_set_shaper_3dlut(
 878         struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
 879 {
 880         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
 881         bool result = true;
 882         struct pwl_params *shaper_lut = NULL;
 883
 884         if (plane_state->in_shaper_func) {
 885                 if (plane_state->in_shaper_func->type == TF_TYPE_HWPWL)
 886                         shaper_lut = &plane_state->in_shaper_func->pwl;
 887                 else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) {
 888                         cm_helper_translate_curve_to_hw_format(
 889                                         plane_state->in_shaper_func,
 890                                         &dpp_base->shaper_params, true);
 891                         shaper_lut = &dpp_base->shaper_params;
 892                 }
 893         }
 894
 895         result = dpp_base->funcs->dpp_program_shaper_lut(dpp_base, shaper_lut);
 896         if (plane_state->lut3d_func &&
 897                 plane_state->lut3d_func->state.bits.initialized == 1)
 898                 result = dpp_base->funcs->dpp_program_3dlut(dpp_base,
 899                                                                 &plane_state->lut3d_func->lut_3d);
 900         else
 901                 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, NULL);
 902
 903         return result;
 904 }
 905
 906 bool dcn20_set_input_transfer_func(struct dc *dc,
 907                                 struct pipe_ctx *pipe_ctx,
 908                                 const struct dc_plane_state *plane_state)
 909 {
 910         struct dce_hwseq *hws = dc->hwseq;
 911         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
 912         const struct dc_transfer_func *tf = NULL;
 913         bool result = true;
 914         bool use_degamma_ram = false;
 915
 916         if (dpp_base == NULL || plane_state == NULL)
 917                 return false;
 918
 919         hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state);
 920         hws->funcs.set_blend_lut(pipe_ctx, plane_state);
 921
 922         if (plane_state->in_transfer_func)
 923                 tf = plane_state->in_transfer_func;
 924
 925
 926         if (tf == NULL) {
 927                 dpp_base->funcs->dpp_set_degamma(dpp_base,
 928                                 IPP_DEGAMMA_MODE_BYPASS);
 929                 return true;
 930         }
 931
 932         if (tf->type == TF_TYPE_HWPWL || tf->type == TF_TYPE_DISTRIBUTED_POINTS)
 933                 use_degamma_ram = true;
 934
 935         if (use_degamma_ram == true) {
 936                 if (tf->type == TF_TYPE_HWPWL)
 937                         dpp_base->funcs->dpp_program_degamma_pwl(dpp_base,
 938                                         &tf->pwl);
 939                 else if (tf->type == TF_TYPE_DISTRIBUTED_POINTS) {
 940                         cm_helper_translate_curve_to_degamma_hw_format(tf,
 941                                         &dpp_base->degamma_params);
 942                         dpp_base->funcs->dpp_program_degamma_pwl(dpp_base,
 943                                 &dpp_base->degamma_params);
 944                 }
 945                 return true;
 946         }
 947         /* handle here the optimized cases when de-gamma ROM could be used.
 948          *
 949          */
 950         if (tf->type == TF_TYPE_PREDEFINED) {
 951                 switch (tf->tf) {
 952                 case TRANSFER_FUNCTION_SRGB:
 953                         dpp_base->funcs->dpp_set_degamma(dpp_base,
 954                                         IPP_DEGAMMA_MODE_HW_sRGB);
 955                         break;
 956                 case TRANSFER_FUNCTION_BT709:
 957                         dpp_base->funcs->dpp_set_degamma(dpp_base,
 958                                         IPP_DEGAMMA_MODE_HW_xvYCC);
 959                         break;
 960                 case TRANSFER_FUNCTION_LINEAR:
 961                         dpp_base->funcs->dpp_set_degamma(dpp_base,
 962                                         IPP_DEGAMMA_MODE_BYPASS);
 963                         break;
 964                 case TRANSFER_FUNCTION_PQ:
 965                         dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_USER_PWL);
 966                         cm_helper_translate_curve_to_degamma_hw_format(tf, &dpp_base->degamma_params);
 967                         dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, &dpp_base->degamma_params);
 968                         result = true;
 969                         break;
 970                 default:
 971                         result = false;
 972                         break;
 973                 }
 974         } else if (tf->type == TF_TYPE_BYPASS)
 975                 dpp_base->funcs->dpp_set_degamma(dpp_base,
 976                                 IPP_DEGAMMA_MODE_BYPASS);
 977         else {
 978                 /*
 979                  * if we are here, we did not handle correctly.
 980                  * fix is required for this use case
 981                  */
 982                 BREAK_TO_DEBUGGER();
 983                 dpp_base->funcs->dpp_set_degamma(dpp_base,
 984                                 IPP_DEGAMMA_MODE_BYPASS);
 985         }
 986
 987         return result;
 988 }
 989
 990 void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)
 991 {
 992         struct pipe_ctx *odm_pipe;
 993         int opp_cnt = 1;
 994         int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst };
 995
 996         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
 997                 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;
 998                 opp_cnt++;
 999         }
1000
1001         if (opp_cnt > 1)
1002                 pipe_ctx->stream_res.tg->funcs->set_odm_combine(
1003                                 pipe_ctx->stream_res.tg,
1004                                 opp_inst, opp_cnt,
1005                                 &pipe_ctx->stream->timing);
1006         else
1007                 pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
1008                                 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
1009 }
1010
1011 void dcn20_blank_pixel_data(
1012                 struct dc *dc,
1013                 struct pipe_ctx *pipe_ctx,
1014                 bool blank)
1015 {
1016         struct tg_color black_color = {0};
1017         struct stream_resource *stream_res = &pipe_ctx->stream_res;
1018         struct dc_stream_state *stream = pipe_ctx->stream;
1019         enum dc_color_space color_space = stream->output_color_space;
1020         enum controller_dp_test_pattern test_pattern = CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR;
1021         enum controller_dp_color_space test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED;
1022         struct pipe_ctx *odm_pipe;
1023         int odm_cnt = 1;
1024
1025         int width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;
1026         int height = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top;
1027
1028         if (stream->link->test_pattern_enabled)
1029                 return;
1030
1031         /* get opp dpg blank color */
1032         color_space_to_black_color(dc, color_space, &black_color);
1033
1034         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
1035                 odm_cnt++;
1036
1037         width = width / odm_cnt;
1038
1039         if (blank) {
1040                 dc->hwss.set_abm_immediate_disable(pipe_ctx);
1041
1042                 if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) {
1043                         test_pattern = CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
1044                         test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_RGB;
1045                 }
1046         } else {
1047                 test_pattern = CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
1048         }
1049
1050         dc->hwss.set_disp_pattern_generator(dc,
1051                         pipe_ctx,
1052                         test_pattern,
1053                         test_pattern_color_space,
1054                         stream->timing.display_color_depth,
1055                         &black_color,
1056                         width,
1057                         height,
1058                         0);
1059
1060         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
1061                 dc->hwss.set_disp_pattern_generator(dc,
1062                                 odm_pipe,
1063                                 dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE && blank ?
1064                                                 CONTROLLER_DP_TEST_PATTERN_COLORRAMP : test_pattern,
1065                                 test_pattern_color_space,
1066                                 stream->timing.display_color_depth,
1067                                 &black_color,
1068                                 width,
1069                                 height,
1070                                 0);
1071         }
1072
1073         if (!blank)
1074                 if (stream_res->abm) {
1075                         dc->hwss.set_pipe(pipe_ctx);
1076                         stream_res->abm->funcs->set_abm_level(stream_res->abm, stream->abm_level);
1077                 }
1078 }
1079
1080
1081 static void dcn20_power_on_plane(
1082         struct dce_hwseq *hws,
1083         struct pipe_ctx *pipe_ctx)
1084 {
1085         DC_LOGGER_INIT(hws->ctx->logger);
1086         if (REG(DC_IP_REQUEST_CNTL)) {
1087                 REG_SET(DC_IP_REQUEST_CNTL, 0,
1088                                 IP_REQUEST_EN, 1);
1089
1090                 if (hws->funcs.dpp_pg_control)
1091                         hws->funcs.dpp_pg_control(hws, pipe_ctx->plane_res.dpp->inst, true);
1092
1093                 if (hws->funcs.hubp_pg_control)
1094                         hws->funcs.hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, true);
1095
1096                 REG_SET(DC_IP_REQUEST_CNTL, 0,
1097                                 IP_REQUEST_EN, 0);
1098                 DC_LOG_DEBUG(
1099                                 "Un-gated front end for pipe %d\n", pipe_ctx->plane_res.hubp->inst);
1100         }
1101 }
1102
1103 static void dcn20_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx,
1104                                struct dc_state *context)
1105 {
1106         //if (dc->debug.sanity_checks) {
1107         //      dcn10_verify_allow_pstate_change_high(dc);
1108         //}
1109         dcn20_power_on_plane(dc->hwseq, pipe_ctx);
1110
1111         /* enable DCFCLK current DCHUB */
1112         pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);
1113
1114         /* initialize HUBP on power up */
1115         pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp);
1116
1117         /* make sure OPP_PIPE_CLOCK_EN = 1 */
1118         pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
1119                         pipe_ctx->stream_res.opp,
1120                         true);
1121
1122 /* TODO: enable/disable in dm as per update type.
1123         if (plane_state) {
1124                 DC_LOG_DC(dc->ctx->logger,
1125                                 "Pipe:%d 0x%x: addr hi:0x%x, "
1126                                 "addr low:0x%x, "
1127                                 "src: %d, %d, %d,"
1128                                 " %d; dst: %d, %d, %d, %d;\n",
1129                                 pipe_ctx->pipe_idx,
1130                                 plane_state,
1131                                 plane_state->address.grph.addr.high_part,
1132                                 plane_state->address.grph.addr.low_part,
1133                                 plane_state->src_rect.x,
1134                                 plane_state->src_rect.y,
1135                                 plane_state->src_rect.width,
1136                                 plane_state->src_rect.height,
1137                                 plane_state->dst_rect.x,
1138                                 plane_state->dst_rect.y,
1139                                 plane_state->dst_rect.width,
1140                                 plane_state->dst_rect.height);
1141
1142                 DC_LOG_DC(dc->ctx->logger,
1143                                 "Pipe %d: width, height, x, y         format:%d\n"
1144                                 "viewport:%d, %d, %d, %d\n"
1145                                 "recout:  %d, %d, %d, %d\n",
1146                                 pipe_ctx->pipe_idx,
1147                                 plane_state->format,
1148                                 pipe_ctx->plane_res.scl_data.viewport.width,
1149                                 pipe_ctx->plane_res.scl_data.viewport.height,
1150                                 pipe_ctx->plane_res.scl_data.viewport.x,
1151                                 pipe_ctx->plane_res.scl_data.viewport.y,
1152                                 pipe_ctx->plane_res.scl_data.recout.width,
1153                                 pipe_ctx->plane_res.scl_data.recout.height,
1154                                 pipe_ctx->plane_res.scl_data.recout.x,
1155                                 pipe_ctx->plane_res.scl_data.recout.y);
1156                 print_rq_dlg_ttu(dc, pipe_ctx);
1157         }
1158 */
1159         if (dc->vm_pa_config.valid) {
1160                 struct vm_system_aperture_param apt;
1161
1162                 apt.sys_default.quad_part = 0;
1163
1164                 apt.sys_low.quad_part = dc->vm_pa_config.system_aperture.start_addr;
1165                 apt.sys_high.quad_part = dc->vm_pa_config.system_aperture.end_addr;
1166
1167                 // Program system aperture settings
1168                 pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt);
1169         }
1170
1171         if (!pipe_ctx->top_pipe
1172                 && pipe_ctx->plane_state
1173                 && pipe_ctx->plane_state->flip_int_enabled
1174                 && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int)
1175                         pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int(pipe_ctx->plane_res.hubp);
1176
1177 //      if (dc->debug.sanity_checks) {
1178 //              dcn10_verify_allow_pstate_change_high(dc);
1179 //      }
1180 }
1181
1182 void dcn20_pipe_control_lock(
1183         struct dc *dc,
1184         struct pipe_ctx *pipe,
1185         bool lock)
1186 {
1187         struct pipe_ctx *temp_pipe;
1188         bool flip_immediate = false;
1189
1190         /* use TG master update lock to lock everything on the TG
1191          * therefore only top pipe need to lock
1192          */
1193         if (!pipe || pipe->top_pipe)
1194                 return;
1195
1196         if (pipe->plane_state != NULL)
1197                 flip_immediate = pipe->plane_state->flip_immediate;
1198
1199         if  (pipe->stream_res.gsl_group > 0) {
1200             temp_pipe = pipe->bottom_pipe;
1201             while (!flip_immediate && temp_pipe) {
1202                     if (temp_pipe->plane_state != NULL)
1203                             flip_immediate = temp_pipe->plane_state->flip_immediate;
1204                     temp_pipe = temp_pipe->bottom_pipe;
1205             }
1206         }
1207
1208         if (flip_immediate && lock) {
1209                 const int TIMEOUT_FOR_FLIP_PENDING = 100000;
1210                 int i;
1211
1212                 temp_pipe = pipe;
1213                 while (temp_pipe) {
1214                         if (temp_pipe->plane_state && temp_pipe->plane_state->flip_immediate) {
1215                                 for (i = 0; i < TIMEOUT_FOR_FLIP_PENDING; ++i) {
1216                                         if (!temp_pipe->plane_res.hubp->funcs->hubp_is_flip_pending(temp_pipe->plane_res.hubp))
1217                                                 break;
1218                                         udelay(1);
1219                                 }
1220
1221                                 /* no reason it should take this long for immediate flips */
1222                                 ASSERT(i != TIMEOUT_FOR_FLIP_PENDING);
1223                         }
1224                         temp_pipe = temp_pipe->bottom_pipe;
1225                 }
1226         }
1227
1228         /* In flip immediate and pipe splitting case, we need to use GSL
1229          * for synchronization. Only do setup on locking and on flip type change.
1230          */
1231         if (lock && (pipe->bottom_pipe != NULL || !flip_immediate))
1232                 if ((flip_immediate && pipe->stream_res.gsl_group == 0) ||
1233                     (!flip_immediate && pipe->stream_res.gsl_group > 0))
1234                         dcn20_setup_gsl_group_as_lock(dc, pipe, flip_immediate);
1235
1236         if (pipe->plane_state != NULL)
1237                 flip_immediate = pipe->plane_state->flip_immediate;
1238
1239         temp_pipe = pipe->bottom_pipe;
1240         while (flip_immediate && temp_pipe) {
1241             if (temp_pipe->plane_state != NULL)
1242                 flip_immediate = temp_pipe->plane_state->flip_immediate;
1243             temp_pipe = temp_pipe->bottom_pipe;
1244         }
1245
1246         if (!lock && pipe->stream_res.gsl_group > 0 && pipe->plane_state &&
1247                 !flip_immediate)
1248             dcn20_setup_gsl_group_as_lock(dc, pipe, false);
1249
1250         if (pipe->stream && should_use_dmub_lock(pipe->stream->link)) {
1251                 union dmub_hw_lock_flags hw_locks = { 0 };
1252                 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
1253
1254                 hw_locks.bits.lock_pipe = 1;
1255                 inst_flags.otg_inst =  pipe->stream_res.tg->inst;
1256
1257                 if (pipe->plane_state != NULL)
1258                         hw_locks.bits.triple_buffer_lock = pipe->plane_state->triplebuffer_flips;
1259
1260                 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
1261                                         lock,
1262                                         &hw_locks,
1263                                         &inst_flags);
1264         } else if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
1265                 union dmub_inbox0_cmd_lock_hw hw_lock_cmd = { 0 };
1266                 hw_lock_cmd.bits.command_code = DMUB_INBOX0_CMD__HW_LOCK;
1267                 hw_lock_cmd.bits.hw_lock_client = HW_LOCK_CLIENT_DRIVER;
1268                 hw_lock_cmd.bits.lock_pipe = 1;
1269                 hw_lock_cmd.bits.otg_inst = pipe->stream_res.tg->inst;
1270                 hw_lock_cmd.bits.lock = lock;
1271                 if (!lock)
1272                         hw_lock_cmd.bits.should_release = 1;
1273                 dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd);
1274         } else if (pipe->plane_state != NULL && pipe->plane_state->triplebuffer_flips) {
1275                 if (lock)
1276                         pipe->stream_res.tg->funcs->triplebuffer_lock(pipe->stream_res.tg);
1277                 else
1278                         pipe->stream_res.tg->funcs->triplebuffer_unlock(pipe->stream_res.tg);
1279         } else {
1280                 if (lock)
1281                         pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);
1282                 else
1283                         pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);
1284         }
1285 }
1286
1287 static void dcn20_detect_pipe_changes(struct pipe_ctx *old_pipe, struct pipe_ctx *new_pipe)
1288 {
1289         new_pipe->update_flags.raw = 0;
1290
1291         /* Exit on unchanged, unused pipe */
1292         if (!old_pipe->plane_state && !new_pipe->plane_state)
1293                 return;
1294         /* Detect pipe enable/disable */
1295         if (!old_pipe->plane_state && new_pipe->plane_state) {
1296                 new_pipe->update_flags.bits.enable = 1;
1297                 new_pipe->update_flags.bits.mpcc = 1;
1298                 new_pipe->update_flags.bits.dppclk = 1;
1299                 new_pipe->update_flags.bits.hubp_interdependent = 1;
1300                 new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1;
1301                 new_pipe->update_flags.bits.gamut_remap = 1;
1302                 new_pipe->update_flags.bits.scaler = 1;
1303                 new_pipe->update_flags.bits.viewport = 1;
1304                 new_pipe->update_flags.bits.det_size = 1;
1305                 if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) {
1306                         new_pipe->update_flags.bits.odm = 1;
1307                         new_pipe->update_flags.bits.global_sync = 1;
1308                 }
1309                 return;
1310         }
1311         if (old_pipe->plane_state && !new_pipe->plane_state) {
1312                 new_pipe->update_flags.bits.disable = 1;
1313                 return;
1314         }
1315
1316         /* Detect plane change */
1317         if (old_pipe->plane_state != new_pipe->plane_state) {
1318                 new_pipe->update_flags.bits.plane_changed = true;
1319         }
1320
1321         /* Detect top pipe only changes */
1322         if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) {
1323                 /* Detect odm changes */
1324                 if ((old_pipe->next_odm_pipe && new_pipe->next_odm_pipe
1325                         && old_pipe->next_odm_pipe->pipe_idx != new_pipe->next_odm_pipe->pipe_idx)
1326                                 || (!old_pipe->next_odm_pipe && new_pipe->next_odm_pipe)
1327                                 || (old_pipe->next_odm_pipe && !new_pipe->next_odm_pipe)
1328                                 || old_pipe->stream_res.opp != new_pipe->stream_res.opp)
1329                         new_pipe->update_flags.bits.odm = 1;
1330
1331                 /* Detect global sync changes */
1332                 if (old_pipe->pipe_dlg_param.vready_offset != new_pipe->pipe_dlg_param.vready_offset
1333                                 || old_pipe->pipe_dlg_param.vstartup_start != new_pipe->pipe_dlg_param.vstartup_start
1334                                 || old_pipe->pipe_dlg_param.vupdate_offset != new_pipe->pipe_dlg_param.vupdate_offset
1335                                 || old_pipe->pipe_dlg_param.vupdate_width != new_pipe->pipe_dlg_param.vupdate_width)
1336                         new_pipe->update_flags.bits.global_sync = 1;
1337         }
1338
1339         if (old_pipe->det_buffer_size_kb != new_pipe->det_buffer_size_kb)
1340                 new_pipe->update_flags.bits.det_size = 1;
1341
1342         /*
1343          * Detect opp / tg change, only set on change, not on enable
1344          * Assume mpcc inst = pipe index, if not this code needs to be updated
1345          * since mpcc is what is affected by these. In fact all of our sequence
1346          * makes this assumption at the moment with how hubp reset is matched to
1347          * same index mpcc reset.
1348          */
1349         if (old_pipe->stream_res.opp != new_pipe->stream_res.opp)
1350                 new_pipe->update_flags.bits.opp_changed = 1;
1351         if (old_pipe->stream_res.tg != new_pipe->stream_res.tg)
1352                 new_pipe->update_flags.bits.tg_changed = 1;
1353
1354         /*
1355          * Detect mpcc blending changes, only dpp inst and opp matter here,
1356          * mpccs getting removed/inserted update connected ones during their own
1357          * programming
1358          */
1359         if (old_pipe->plane_res.dpp != new_pipe->plane_res.dpp
1360                         || old_pipe->stream_res.opp != new_pipe->stream_res.opp)
1361                 new_pipe->update_flags.bits.mpcc = 1;
1362
1363         /* Detect dppclk change */
1364         if (old_pipe->plane_res.bw.dppclk_khz != new_pipe->plane_res.bw.dppclk_khz)
1365                 new_pipe->update_flags.bits.dppclk = 1;
1366
1367         /* Check for scl update */
1368         if (memcmp(&old_pipe->plane_res.scl_data, &new_pipe->plane_res.scl_data, sizeof(struct scaler_data)))
1369                         new_pipe->update_flags.bits.scaler = 1;
1370         /* Check for vp update */
1371         if (memcmp(&old_pipe->plane_res.scl_data.viewport, &new_pipe->plane_res.scl_data.viewport, sizeof(struct rect))
1372                         || memcmp(&old_pipe->plane_res.scl_data.viewport_c,
1373                                 &new_pipe->plane_res.scl_data.viewport_c, sizeof(struct rect)))
1374                 new_pipe->update_flags.bits.viewport = 1;
1375
1376         /* Detect dlg/ttu/rq updates */
1377         {
1378                 struct _vcs_dpi_display_dlg_regs_st old_dlg_attr = old_pipe->dlg_regs;
1379                 struct _vcs_dpi_display_ttu_regs_st old_ttu_attr = old_pipe->ttu_regs;
1380                 struct _vcs_dpi_display_dlg_regs_st *new_dlg_attr = &new_pipe->dlg_regs;
1381                 struct _vcs_dpi_display_ttu_regs_st *new_ttu_attr = &new_pipe->ttu_regs;
1382
1383                 /* Detect pipe interdependent updates */
1384                 if (old_dlg_attr.dst_y_prefetch != new_dlg_attr->dst_y_prefetch ||
1385                                 old_dlg_attr.vratio_prefetch != new_dlg_attr->vratio_prefetch ||
1386                                 old_dlg_attr.vratio_prefetch_c != new_dlg_attr->vratio_prefetch_c ||
1387                                 old_dlg_attr.dst_y_per_vm_vblank != new_dlg_attr->dst_y_per_vm_vblank ||
1388                                 old_dlg_attr.dst_y_per_row_vblank != new_dlg_attr->dst_y_per_row_vblank ||
1389                                 old_dlg_attr.dst_y_per_vm_flip != new_dlg_attr->dst_y_per_vm_flip ||
1390                                 old_dlg_attr.dst_y_per_row_flip != new_dlg_attr->dst_y_per_row_flip ||
1391                                 old_dlg_attr.refcyc_per_meta_chunk_vblank_l != new_dlg_attr->refcyc_per_meta_chunk_vblank_l ||
1392                                 old_dlg_attr.refcyc_per_meta_chunk_vblank_c != new_dlg_attr->refcyc_per_meta_chunk_vblank_c ||
1393                                 old_dlg_attr.refcyc_per_meta_chunk_flip_l != new_dlg_attr->refcyc_per_meta_chunk_flip_l ||
1394                                 old_dlg_attr.refcyc_per_line_delivery_pre_l != new_dlg_attr->refcyc_per_line_delivery_pre_l ||
1395                                 old_dlg_attr.refcyc_per_line_delivery_pre_c != new_dlg_attr->refcyc_per_line_delivery_pre_c ||
1396                                 old_ttu_attr.refcyc_per_req_delivery_pre_l != new_ttu_attr->refcyc_per_req_delivery_pre_l ||
1397                                 old_ttu_attr.refcyc_per_req_delivery_pre_c != new_ttu_attr->refcyc_per_req_delivery_pre_c ||
1398                                 old_ttu_attr.refcyc_per_req_delivery_pre_cur0 != new_ttu_attr->refcyc_per_req_delivery_pre_cur0 ||
1399                                 old_ttu_attr.refcyc_per_req_delivery_pre_cur1 != new_ttu_attr->refcyc_per_req_delivery_pre_cur1 ||
1400                                 old_ttu_attr.min_ttu_vblank != new_ttu_attr->min_ttu_vblank ||
1401                                 old_ttu_attr.qos_level_flip != new_ttu_attr->qos_level_flip) {
1402                         old_dlg_attr.dst_y_prefetch = new_dlg_attr->dst_y_prefetch;
1403                         old_dlg_attr.vratio_prefetch = new_dlg_attr->vratio_prefetch;
1404                         old_dlg_attr.vratio_prefetch_c = new_dlg_attr->vratio_prefetch_c;
1405                         old_dlg_attr.dst_y_per_vm_vblank = new_dlg_attr->dst_y_per_vm_vblank;
1406                         old_dlg_attr.dst_y_per_row_vblank = new_dlg_attr->dst_y_per_row_vblank;
1407                         old_dlg_attr.dst_y_per_vm_flip = new_dlg_attr->dst_y_per_vm_flip;
1408                         old_dlg_attr.dst_y_per_row_flip = new_dlg_attr->dst_y_per_row_flip;
1409                         old_dlg_attr.refcyc_per_meta_chunk_vblank_l = new_dlg_attr->refcyc_per_meta_chunk_vblank_l;
1410                         old_dlg_attr.refcyc_per_meta_chunk_vblank_c = new_dlg_attr->refcyc_per_meta_chunk_vblank_c;
1411                         old_dlg_attr.refcyc_per_meta_chunk_flip_l = new_dlg_attr->refcyc_per_meta_chunk_flip_l;
1412                         old_dlg_attr.refcyc_per_line_delivery_pre_l = new_dlg_attr->refcyc_per_line_delivery_pre_l;
1413                         old_dlg_attr.refcyc_per_line_delivery_pre_c = new_dlg_attr->refcyc_per_line_delivery_pre_c;
1414                         old_ttu_attr.refcyc_per_req_delivery_pre_l = new_ttu_attr->refcyc_per_req_delivery_pre_l;
1415                         old_ttu_attr.refcyc_per_req_delivery_pre_c = new_ttu_attr->refcyc_per_req_delivery_pre_c;
1416                         old_ttu_attr.refcyc_per_req_delivery_pre_cur0 = new_ttu_attr->refcyc_per_req_delivery_pre_cur0;
1417                         old_ttu_attr.refcyc_per_req_delivery_pre_cur1 = new_ttu_attr->refcyc_per_req_delivery_pre_cur1;
1418                         old_ttu_attr.min_ttu_vblank = new_ttu_attr->min_ttu_vblank;
1419                         old_ttu_attr.qos_level_flip = new_ttu_attr->qos_level_flip;
1420                         new_pipe->update_flags.bits.hubp_interdependent = 1;
1421                 }
1422                 /* Detect any other updates to ttu/rq/dlg */
1423                 if (memcmp(&old_dlg_attr, &new_pipe->dlg_regs, sizeof(old_dlg_attr)) ||
1424                                 memcmp(&old_ttu_attr, &new_pipe->ttu_regs, sizeof(old_ttu_attr)) ||
1425                                 memcmp(&old_pipe->rq_regs, &new_pipe->rq_regs, sizeof(old_pipe->rq_regs)))
1426                         new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1;
1427         }
1428 }
1429
1430 static void dcn20_update_dchubp_dpp(
1431         struct dc *dc,
1432         struct pipe_ctx *pipe_ctx,
1433         struct dc_state *context)
1434 {
1435         struct dce_hwseq *hws = dc->hwseq;
1436         struct hubp *hubp = pipe_ctx->plane_res.hubp;
1437         struct dpp *dpp = pipe_ctx->plane_res.dpp;
1438         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1439         bool viewport_changed = false;
1440
1441         if (pipe_ctx->update_flags.bits.dppclk)
1442                 dpp->funcs->dpp_dppclk_control(dpp, false, true);
1443
1444         /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG
1445          * VTG is within DCHUBBUB which is commond block share by each pipe HUBP.
1446          * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG
1447          */
1448         if (pipe_ctx->update_flags.bits.hubp_rq_dlg_ttu) {
1449                 hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst);
1450
1451                 hubp->funcs->hubp_setup(
1452                         hubp,
1453                         &pipe_ctx->dlg_regs,
1454                         &pipe_ctx->ttu_regs,
1455                         &pipe_ctx->rq_regs,
1456                         &pipe_ctx->pipe_dlg_param);
1457
1458                 if (hubp->funcs->set_unbounded_requesting)
1459                         hubp->funcs->set_unbounded_requesting(hubp, pipe_ctx->unbounded_req);
1460         }
1461         if (pipe_ctx->update_flags.bits.hubp_interdependent)
1462                 hubp->funcs->hubp_setup_interdependent(
1463                         hubp,
1464                         &pipe_ctx->dlg_regs,
1465                         &pipe_ctx->ttu_regs);
1466
1467         if (pipe_ctx->update_flags.bits.enable ||
1468                         pipe_ctx->update_flags.bits.plane_changed ||
1469                         plane_state->update_flags.bits.bpp_change ||
1470                         plane_state->update_flags.bits.input_csc_change ||
1471                         plane_state->update_flags.bits.color_space_change ||
1472                         plane_state->update_flags.bits.coeff_reduction_change) {
1473                 struct dc_bias_and_scale bns_params = {0};
1474
1475                 // program the input csc
1476                 dpp->funcs->dpp_setup(dpp,
1477                                 plane_state->format,
1478                                 EXPANSION_MODE_ZERO,
1479                                 plane_state->input_csc_color_matrix,
1480                                 plane_state->color_space,
1481                                 NULL);
1482
1483                 if (dpp->funcs->dpp_program_bias_and_scale) {
1484                         //TODO :for CNVC set scale and bias registers if necessary
1485                         build_prescale_params(&bns_params, plane_state);
1486                         dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
1487                 }
1488         }
1489
1490         if (pipe_ctx->update_flags.bits.mpcc
1491                         || pipe_ctx->update_flags.bits.plane_changed
1492                         || plane_state->update_flags.bits.global_alpha_change
1493                         || plane_state->update_flags.bits.per_pixel_alpha_change) {
1494                 // MPCC inst is equal to pipe index in practice
1495                 int mpcc_inst = hubp->inst;
1496                 int opp_inst;
1497                 int opp_count = dc->res_pool->pipe_count;
1498
1499                 for (opp_inst = 0; opp_inst < opp_count; opp_inst++) {
1500                         if (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst]) {
1501                                 dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst);
1502                                 dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false;
1503                                 break;
1504                         }
1505                 }
1506                 hws->funcs.update_mpcc(dc, pipe_ctx);
1507         }
1508
1509         if (pipe_ctx->update_flags.bits.scaler ||
1510                         plane_state->update_flags.bits.scaling_change ||
1511                         plane_state->update_flags.bits.position_change ||
1512                         plane_state->update_flags.bits.per_pixel_alpha_change ||
1513                         pipe_ctx->stream->update_flags.bits.scaling) {
1514                 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->plane_state->per_pixel_alpha;
1515                 ASSERT(pipe_ctx->plane_res.scl_data.lb_params.depth == LB_PIXEL_DEPTH_36BPP);
1516                 /* scaler configuration */
1517                 pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(
1518                                 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);
1519         }
1520
1521         if (pipe_ctx->update_flags.bits.viewport ||
1522                         (context == dc->current_state && plane_state->update_flags.bits.position_change) ||
1523                         (context == dc->current_state && plane_state->update_flags.bits.scaling_change) ||
1524                         (context == dc->current_state && pipe_ctx->stream->update_flags.bits.scaling)) {
1525
1526                 hubp->funcs->mem_program_viewport(
1527                         hubp,
1528                         &pipe_ctx->plane_res.scl_data.viewport,
1529                         &pipe_ctx->plane_res.scl_data.viewport_c);
1530                 viewport_changed = true;
1531         }
1532
1533         /* Any updates are handled in dc interface, just need to apply existing for plane enable */
1534         if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed ||
1535                         pipe_ctx->update_flags.bits.scaler || viewport_changed == true) &&
1536                         pipe_ctx->stream->cursor_attributes.address.quad_part != 0) {
1537                 dc->hwss.set_cursor_position(pipe_ctx);
1538                 dc->hwss.set_cursor_attribute(pipe_ctx);
1539
1540                 if (dc->hwss.set_cursor_sdr_white_level)
1541                         dc->hwss.set_cursor_sdr_white_level(pipe_ctx);
1542         }
1543
1544         /* Any updates are handled in dc interface, just need
1545          * to apply existing for plane enable / opp change */
1546         if (pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed
1547                         || pipe_ctx->stream->update_flags.bits.gamut_remap
1548                         || pipe_ctx->stream->update_flags.bits.out_csc) {
1549                 /* dpp/cm gamut remap*/
1550                 dc->hwss.program_gamut_remap(pipe_ctx);
1551
1552                 /*call the dcn2 method which uses mpc csc*/
1553                 dc->hwss.program_output_csc(dc,
1554                                 pipe_ctx,
1555                                 pipe_ctx->stream->output_color_space,
1556                                 pipe_ctx->stream->csc_color_matrix.matrix,
1557                                 hubp->opp_id);
1558         }
1559
1560         if (pipe_ctx->update_flags.bits.enable ||
1561                         pipe_ctx->update_flags.bits.plane_changed ||
1562                         pipe_ctx->update_flags.bits.opp_changed ||
1563                         plane_state->update_flags.bits.pixel_format_change ||
1564                         plane_state->update_flags.bits.horizontal_mirror_change ||
1565                         plane_state->update_flags.bits.rotation_change ||
1566                         plane_state->update_flags.bits.swizzle_change ||
1567                         plane_state->update_flags.bits.dcc_change ||
1568                         plane_state->update_flags.bits.bpp_change ||
1569                         plane_state->update_flags.bits.scaling_change ||
1570                         plane_state->update_flags.bits.plane_size_change) {
1571                 struct plane_size size = plane_state->plane_size;
1572
1573                 size.surface_size = pipe_ctx->plane_res.scl_data.viewport;
1574                 hubp->funcs->hubp_program_surface_config(
1575                         hubp,
1576                         plane_state->format,
1577                         &plane_state->tiling_info,
1578                         &size,
1579                         plane_state->rotation,
1580                         &plane_state->dcc,
1581                         plane_state->horizontal_mirror,
1582                         0);
1583                 hubp->power_gated = false;
1584         }
1585
1586         if (pipe_ctx->update_flags.bits.enable ||
1587                 pipe_ctx->update_flags.bits.plane_changed ||
1588                 plane_state->update_flags.bits.addr_update)
1589                 hws->funcs.update_plane_addr(dc, pipe_ctx);
1590
1591         if (pipe_ctx->update_flags.bits.enable)
1592                 hubp->funcs->set_blank(hubp, false);
1593         /* If the stream paired with this plane is phantom, the plane is also phantom */
1594         if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.type == SUBVP_PHANTOM
1595                         && hubp->funcs->phantom_hubp_post_enable)
1596                 hubp->funcs->phantom_hubp_post_enable(hubp);
1597 }
1598
1599
1600 static void dcn20_program_pipe(
1601                 struct dc *dc,
1602                 struct pipe_ctx *pipe_ctx,
1603                 struct dc_state *context)
1604 {
1605         struct dce_hwseq *hws = dc->hwseq;
1606         /* Only need to unblank on top pipe */
1607
1608         if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.abm_level)
1609                         && !pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe)
1610                 hws->funcs.blank_pixel_data(dc, pipe_ctx, !pipe_ctx->plane_state->visible);
1611
1612         /* Only update TG on top pipe */
1613         if (pipe_ctx->update_flags.bits.global_sync && !pipe_ctx->top_pipe
1614                         && !pipe_ctx->prev_odm_pipe) {
1615                 pipe_ctx->stream_res.tg->funcs->program_global_sync(
1616                                 pipe_ctx->stream_res.tg,
1617                                 pipe_ctx->pipe_dlg_param.vready_offset,
1618                                 pipe_ctx->pipe_dlg_param.vstartup_start,
1619                                 pipe_ctx->pipe_dlg_param.vupdate_offset,
1620                                 pipe_ctx->pipe_dlg_param.vupdate_width);
1621
1622                 if (pipe_ctx->stream->mall_stream_config.type != SUBVP_PHANTOM) {
1623                         pipe_ctx->stream_res.tg->funcs->wait_for_state(
1624                                 pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK);
1625                         pipe_ctx->stream_res.tg->funcs->wait_for_state(
1626                                 pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);
1627                 }
1628
1629                 pipe_ctx->stream_res.tg->funcs->set_vtg_params(
1630                                 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true);
1631
1632                 if (hws->funcs.setup_vupdate_interrupt)
1633                         hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
1634         }
1635
1636         if (pipe_ctx->update_flags.bits.odm)
1637                 hws->funcs.update_odm(dc, context, pipe_ctx);
1638
1639         if (pipe_ctx->update_flags.bits.enable) {
1640                 dcn20_enable_plane(dc, pipe_ctx, context);
1641                 if (dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes)
1642                         dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes(dc->res_pool->hubbub);
1643         }
1644
1645         if (dc->res_pool->hubbub->funcs->program_det_size && pipe_ctx->update_flags.bits.det_size)
1646                 dc->res_pool->hubbub->funcs->program_det_size(
1647                         dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->det_buffer_size_kb);
1648
1649         if (pipe_ctx->update_flags.raw || pipe_ctx->plane_state->update_flags.raw || pipe_ctx->stream->update_flags.raw)
1650                 dcn20_update_dchubp_dpp(dc, pipe_ctx, context);
1651
1652         if (pipe_ctx->update_flags.bits.enable
1653                         || pipe_ctx->plane_state->update_flags.bits.hdr_mult)
1654                 hws->funcs.set_hdr_multiplier(pipe_ctx);
1655
1656         if (pipe_ctx->update_flags.bits.enable ||
1657                         pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
1658                         pipe_ctx->plane_state->update_flags.bits.gamma_change)
1659                 hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);
1660
1661         /* dcn10_translate_regamma_to_hw_format takes 750us to finish
1662          * only do gamma programming for powering on, internal memcmp to avoid
1663          * updating on slave planes
1664          */
1665         if (pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.out_tf)
1666                 hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
1667
1668         /* If the pipe has been enabled or has a different opp, we
1669          * should reprogram the fmt. This deals with cases where
1670          * interation between mpc and odm combine on different streams
1671          * causes a different pipe to be chosen to odm combine with.
1672          */
1673         if (pipe_ctx->update_flags.bits.enable
1674             || pipe_ctx->update_flags.bits.opp_changed) {
1675
1676                 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
1677                         pipe_ctx->stream_res.opp,
1678                         COLOR_SPACE_YCBCR601,
1679                         pipe_ctx->stream->timing.display_color_depth,
1680                         pipe_ctx->stream->signal);
1681
1682                 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
1683                         pipe_ctx->stream_res.opp,
1684                         &pipe_ctx->stream->bit_depth_params,
1685                         &pipe_ctx->stream->clamping);
1686         }
1687 }
1688
1689 void dcn20_program_front_end_for_ctx(
1690                 struct dc *dc,
1691                 struct dc_state *context)
1692 {
1693         int i;
1694         struct dce_hwseq *hws = dc->hwseq;
1695         DC_LOGGER_INIT(dc->ctx->logger);
1696
1697         /* Carry over GSL groups in case the context is changing. */
1698        for (i = 0; i < dc->res_pool->pipe_count; i++) {
1699                struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1700                struct pipe_ctx *old_pipe_ctx =
1701                        &dc->current_state->res_ctx.pipe_ctx[i];
1702
1703                if (pipe_ctx->stream == old_pipe_ctx->stream)
1704                        pipe_ctx->stream_res.gsl_group =
1705                                old_pipe_ctx->stream_res.gsl_group;
1706        }
1707
1708         if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {
1709                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1710                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1711
1712                         if (!pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe && pipe_ctx->plane_state) {
1713                                 ASSERT(!pipe_ctx->plane_state->triplebuffer_flips);
1714                                 /*turn off triple buffer for full update*/
1715                                 dc->hwss.program_triplebuffer(
1716                                                 dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);
1717                         }
1718                 }
1719         }
1720
1721         /* Set pipe update flags and lock pipes */
1722         for (i = 0; i < dc->res_pool->pipe_count; i++)
1723                 dcn20_detect_pipe_changes(&dc->current_state->res_ctx.pipe_ctx[i],
1724                                 &context->res_ctx.pipe_ctx[i]);
1725
1726         /* OTG blank before disabling all front ends */
1727         for (i = 0; i < dc->res_pool->pipe_count; i++)
1728                 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable
1729                                 && !context->res_ctx.pipe_ctx[i].top_pipe
1730                                 && !context->res_ctx.pipe_ctx[i].prev_odm_pipe
1731                                 && context->res_ctx.pipe_ctx[i].stream)
1732                         hws->funcs.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true);
1733
1734
1735         /* Disconnect mpcc */
1736         for (i = 0; i < dc->res_pool->pipe_count; i++)
1737                 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable
1738                                 || context->res_ctx.pipe_ctx[i].update_flags.bits.opp_changed) {
1739                         struct hubbub *hubbub = dc->res_pool->hubbub;
1740
1741                         if (hubbub->funcs->program_det_size && context->res_ctx.pipe_ctx[i].update_flags.bits.disable)
1742                                 hubbub->funcs->program_det_size(hubbub, dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0);
1743                         hws->funcs.plane_atomic_disconnect(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
1744                         DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx);
1745                 }
1746
1747         /*
1748          * Program all updated pipes, order matters for mpcc setup. Start with
1749          * top pipe and program all pipes that follow in order
1750          */
1751         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1752                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1753
1754                 if (pipe->plane_state && !pipe->top_pipe) {
1755                         while (pipe) {
1756                                 if (hws->funcs.program_pipe)
1757                                         hws->funcs.program_pipe(dc, pipe, context);
1758                                 else
1759                                         dcn20_program_pipe(dc, pipe, context);
1760
1761                                 pipe = pipe->bottom_pipe;
1762                         }
1763                 }
1764                 /* Program secondary blending tree and writeback pipes */
1765                 pipe = &context->res_ctx.pipe_ctx[i];
1766                 if (!pipe->top_pipe && !pipe->prev_odm_pipe
1767                                 && pipe->stream && pipe->stream->num_wb_info > 0
1768                                 && (pipe->update_flags.raw || (pipe->plane_state && pipe->plane_state->update_flags.raw)
1769                                         || pipe->stream->update_flags.raw)
1770                                 && hws->funcs.program_all_writeback_pipes_in_tree)
1771                         hws->funcs.program_all_writeback_pipes_in_tree(dc, pipe->stream, context);
1772
1773                 /* Avoid underflow by check of pipe line read when adding 2nd plane. */
1774                 if (hws->wa.wait_hubpret_read_start_during_mpo_transition &&
1775                         !pipe->top_pipe &&
1776                         pipe->stream &&
1777                         pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start &&
1778                         dc->current_state->stream_status[0].plane_count == 1 &&
1779                         context->stream_status[0].plane_count > 1) {
1780                         pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start(pipe->plane_res.hubp);
1781                 }
1782         }
1783         if (hws->funcs.program_mall_pipe_config)
1784                 hws->funcs.program_mall_pipe_config(dc, context);
1785 }
1786
1787 void dcn20_post_unlock_program_front_end(
1788                 struct dc *dc,
1789                 struct dc_state *context)
1790 {
1791         int i;
1792         const unsigned int TIMEOUT_FOR_PIPE_ENABLE_MS = 100;
1793         struct dce_hwseq *hwseq = dc->hwseq;
1794
1795         DC_LOGGER_INIT(dc->ctx->logger);
1796
1797         for (i = 0; i < dc->res_pool->pipe_count; i++)
1798                 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable)
1799                         dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
1800
1801         /*
1802          * If we are enabling a pipe, we need to wait for pending clear as this is a critical
1803          * part of the enable operation otherwise, DM may request an immediate flip which
1804          * will cause HW to perform an "immediate enable" (as opposed to "vsync enable") which
1805          * is unsupported on DCN.
1806          */
1807         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1808                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1809                 if (pipe->plane_state && !pipe->top_pipe && pipe->update_flags.bits.enable) {
1810                         struct hubp *hubp = pipe->plane_res.hubp;
1811                         int j = 0;
1812
1813                         for (j = 0; j < TIMEOUT_FOR_PIPE_ENABLE_MS*1000
1814                                         && hubp->funcs->hubp_is_flip_pending(hubp); j++)
1815                                 mdelay(1);
1816                 }
1817         }
1818
1819         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1820                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1821                 struct pipe_ctx *mpcc_pipe;
1822
1823                 if (pipe->vtp_locked) {
1824                         dc->hwseq->funcs.wait_for_blank_complete(pipe->stream_res.opp);
1825                         pipe->plane_res.hubp->funcs->set_blank(pipe->plane_res.hubp, true);
1826                         pipe->vtp_locked = false;
1827
1828                         for (mpcc_pipe = pipe->bottom_pipe; mpcc_pipe; mpcc_pipe = mpcc_pipe->bottom_pipe)
1829                                 mpcc_pipe->plane_res.hubp->funcs->set_blank(mpcc_pipe->plane_res.hubp, true);
1830
1831                         for (i = 0; i < dc->res_pool->pipe_count; i++)
1832                                 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable)
1833                                         dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
1834                 }
1835         }
1836         /* WA to apply WM setting*/
1837         if (hwseq->wa.DEGVIDCN21)
1838                 dc->res_pool->hubbub->funcs->apply_DEDCN21_147_wa(dc->res_pool->hubbub);
1839
1840
1841         /* WA for stutter underflow during MPO transitions when adding 2nd plane */
1842         if (hwseq->wa.disallow_self_refresh_during_multi_plane_transition) {
1843
1844                 if (dc->current_state->stream_status[0].plane_count == 1 &&
1845                                 context->stream_status[0].plane_count > 1) {
1846
1847                         struct timing_generator *tg = dc->res_pool->timing_generators[0];
1848
1849                         dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, false);
1850
1851                         hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied = true;
1852                         hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied_on_frame = tg->funcs->get_frame_count(tg);
1853                 }
1854         }
1855 }
1856
1857 void dcn20_prepare_bandwidth(
1858                 struct dc *dc,
1859                 struct dc_state *context)
1860 {
1861         struct hubbub *hubbub = dc->res_pool->hubbub;
1862         unsigned int compbuf_size_kb = 0;
1863
1864         dc->clk_mgr->funcs->update_clocks(
1865                         dc->clk_mgr,
1866                         context,
1867                         false);
1868
1869         /* program dchubbub watermarks */
1870         dc->wm_optimized_required = hubbub->funcs->program_watermarks(hubbub,
1871                                         &context->bw_ctx.bw.dcn.watermarks,
1872                                         dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
1873                                         false);
1874
1875         /* decrease compbuf size */
1876         if (hubbub->funcs->program_compbuf_size) {
1877                 if (context->bw_ctx.dml.ip.min_comp_buffer_size_kbytes)
1878                         compbuf_size_kb = context->bw_ctx.dml.ip.min_comp_buffer_size_kbytes;
1879                 else
1880                         compbuf_size_kb = context->bw_ctx.bw.dcn.compbuf_size_kb;
1881
1882                 hubbub->funcs->program_compbuf_size(hubbub, compbuf_size_kb, false);
1883         }
1884 }
1885
1886 void dcn20_optimize_bandwidth(
1887                 struct dc *dc,
1888                 struct dc_state *context)
1889 {
1890         struct hubbub *hubbub = dc->res_pool->hubbub;
1891         int i;
1892
1893         /* program dchubbub watermarks */
1894         hubbub->funcs->program_watermarks(hubbub,
1895                                         &context->bw_ctx.bw.dcn.watermarks,
1896                                         dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
1897                                         true);
1898
1899         if (dc->clk_mgr->dc_mode_softmax_enabled)
1900                 if (dc->clk_mgr->clks.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 &&
1901                                 context->bw_ctx.bw.dcn.clk.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)
1902                         dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->dc_mode_softmax_memclk);
1903
1904         dc->clk_mgr->funcs->update_clocks(
1905                         dc->clk_mgr,
1906                         context,
1907                         true);
1908         if (dc_extended_blank_supported(dc) && context->bw_ctx.bw.dcn.clk.zstate_support == DCN_ZSTATE_SUPPORT_ALLOW) {
1909                 for (i = 0; i < dc->res_pool->pipe_count; ++i) {
1910                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1911
1912                         if (pipe_ctx->stream && pipe_ctx->plane_res.hubp->funcs->program_extended_blank
1913                                 && pipe_ctx->stream->adjust.v_total_min == pipe_ctx->stream->adjust.v_total_max
1914                                 && pipe_ctx->stream->adjust.v_total_max > pipe_ctx->stream->timing.v_total)
1915                                         pipe_ctx->plane_res.hubp->funcs->program_extended_blank(pipe_ctx->plane_res.hubp,
1916                                                 pipe_ctx->dlg_regs.optimized_min_dst_y_next_start);
1917                 }
1918         }
1919         /* increase compbuf size */
1920         if (hubbub->funcs->program_compbuf_size)
1921                 hubbub->funcs->program_compbuf_size(hubbub, context->bw_ctx.bw.dcn.compbuf_size_kb, true);
1922 }
1923
1924 bool dcn20_update_bandwidth(
1925                 struct dc *dc,
1926                 struct dc_state *context)
1927 {
1928         int i;
1929         struct dce_hwseq *hws = dc->hwseq;
1930
1931         /* recalculate DML parameters */
1932         if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false))
1933                 return false;
1934
1935         /* apply updated bandwidth parameters */
1936         dc->hwss.prepare_bandwidth(dc, context);
1937
1938         /* update hubp configs for all pipes */
1939         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1940                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1941
1942                 if (pipe_ctx->plane_state == NULL)
1943                         continue;
1944
1945                 if (pipe_ctx->top_pipe == NULL) {
1946                         bool blank = !is_pipe_tree_visible(pipe_ctx);
1947
1948                         pipe_ctx->stream_res.tg->funcs->program_global_sync(
1949                                         pipe_ctx->stream_res.tg,
1950                                         pipe_ctx->pipe_dlg_param.vready_offset,
1951                                         pipe_ctx->pipe_dlg_param.vstartup_start,
1952                                         pipe_ctx->pipe_dlg_param.vupdate_offset,
1953                                         pipe_ctx->pipe_dlg_param.vupdate_width);
1954
1955                         pipe_ctx->stream_res.tg->funcs->set_vtg_params(
1956                                         pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, false);
1957
1958                         if (pipe_ctx->prev_odm_pipe == NULL)
1959                                 hws->funcs.blank_pixel_data(dc, pipe_ctx, blank);
1960
1961                         if (hws->funcs.setup_vupdate_interrupt)
1962                                 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
1963                 }
1964
1965                 pipe_ctx->plane_res.hubp->funcs->hubp_setup(
1966                                 pipe_ctx->plane_res.hubp,
1967                                         &pipe_ctx->dlg_regs,
1968                                         &pipe_ctx->ttu_regs,
1969                                         &pipe_ctx->rq_regs,
1970                                         &pipe_ctx->pipe_dlg_param);
1971         }
1972
1973         return true;
1974 }
1975
1976 void dcn20_enable_writeback(
1977                 struct dc *dc,
1978                 struct dc_writeback_info *wb_info,
1979                 struct dc_state *context)
1980 {
1981         struct dwbc *dwb;
1982         struct mcif_wb *mcif_wb;
1983         struct timing_generator *optc;
1984
1985         ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES);
1986         ASSERT(wb_info->wb_enabled);
1987         dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
1988         mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];
1989
1990         /* set the OPTC source mux */
1991         optc = dc->res_pool->timing_generators[dwb->otg_inst];
1992         optc->funcs->set_dwb_source(optc, wb_info->dwb_pipe_inst);
1993         /* set MCIF_WB buffer and arbitration configuration */
1994         mcif_wb->funcs->config_mcif_buf(mcif_wb, &wb_info->mcif_buf_params, wb_info->dwb_params.dest_height);
1995         mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]);
1996         /* Enable MCIF_WB */
1997         mcif_wb->funcs->enable_mcif(mcif_wb);
1998         /* Enable DWB */
1999         dwb->funcs->enable(dwb, &wb_info->dwb_params);
2000         /* TODO: add sequence to enable/disable warmup */
2001 }
2002
2003 void dcn20_disable_writeback(
2004                 struct dc *dc,
2005                 unsigned int dwb_pipe_inst)
2006 {
2007         struct dwbc *dwb;
2008         struct mcif_wb *mcif_wb;
2009
2010         ASSERT(dwb_pipe_inst < MAX_DWB_PIPES);
2011         dwb = dc->res_pool->dwbc[dwb_pipe_inst];
2012         mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst];
2013
2014         dwb->funcs->disable(dwb);
2015         mcif_wb->funcs->disable_mcif(mcif_wb);
2016 }
2017
2018 bool dcn20_wait_for_blank_complete(
2019                 struct output_pixel_processor *opp)
2020 {
2021         int counter;
2022
2023         for (counter = 0; counter < 1000; counter++) {
2024                 if (opp->funcs->dpg_is_blanked(opp))
2025                         break;
2026
2027                 udelay(100);
2028         }
2029
2030         if (counter == 1000) {
2031                 dm_error("DC: failed to blank crtc!\n");
2032                 return false;
2033         }
2034
2035         return true;
2036 }
2037
2038 bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx)
2039 {
2040         struct hubp *hubp = pipe_ctx->plane_res.hubp;
2041
2042         if (!hubp)
2043                 return false;
2044         return hubp->funcs->dmdata_status_done(hubp);
2045 }
2046
2047 void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)
2048 {
2049         struct dce_hwseq *hws = dc->hwseq;
2050
2051         if (pipe_ctx->stream_res.dsc) {
2052                 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
2053
2054                 hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, true);
2055                 while (odm_pipe) {
2056                         hws->funcs.dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, true);
2057                         odm_pipe = odm_pipe->next_odm_pipe;
2058                 }
2059         }
2060 }
2061
2062 void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)
2063 {
2064         struct dce_hwseq *hws = dc->hwseq;
2065
2066         if (pipe_ctx->stream_res.dsc) {
2067                 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
2068
2069                 hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, false);
2070                 while (odm_pipe) {
2071                         hws->funcs.dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, false);
2072                         odm_pipe = odm_pipe->next_odm_pipe;
2073                 }
2074         }
2075 }
2076
2077 void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx)
2078 {
2079         struct dc_dmdata_attributes attr = { 0 };
2080         struct hubp *hubp = pipe_ctx->plane_res.hubp;
2081
2082         attr.dmdata_mode = DMDATA_HW_MODE;
2083         attr.dmdata_size =
2084                 dc_is_hdmi_signal(pipe_ctx->stream->signal) ? 32 : 36;
2085         attr.address.quad_part =
2086                         pipe_ctx->stream->dmdata_address.quad_part;
2087         attr.dmdata_dl_delta = 0;
2088         attr.dmdata_qos_mode = 0;
2089         attr.dmdata_qos_level = 0;
2090         attr.dmdata_repeat = 1; /* always repeat */
2091         attr.dmdata_updated = 1;
2092         attr.dmdata_sw_data = NULL;
2093
2094         hubp->funcs->dmdata_set_attributes(hubp, &attr);
2095 }
2096
2097 void dcn20_init_vm_ctx(
2098                 struct dce_hwseq *hws,
2099                 struct dc *dc,
2100                 struct dc_virtual_addr_space_config *va_config,
2101                 int vmid)
2102 {
2103         struct dcn_hubbub_virt_addr_config config;
2104
2105         if (vmid == 0) {
2106                 ASSERT(0); /* VMID cannot be 0 for vm context */
2107                 return;
2108         }
2109
2110         config.page_table_start_addr = va_config->page_table_start_addr;
2111         config.page_table_end_addr = va_config->page_table_end_addr;
2112         config.page_table_block_size = va_config->page_table_block_size_in_bytes;
2113         config.page_table_depth = va_config->page_table_depth;
2114         config.page_table_base_addr = va_config->page_table_base_addr;
2115
2116         dc->res_pool->hubbub->funcs->init_vm_ctx(dc->res_pool->hubbub, &config, vmid);
2117 }
2118
2119 int dcn20_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)
2120 {
2121         struct dcn_hubbub_phys_addr_config config;
2122
2123         config.system_aperture.fb_top = pa_config->system_aperture.fb_top;
2124         config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset;
2125         config.system_aperture.fb_base = pa_config->system_aperture.fb_base;
2126         config.system_aperture.agp_top = pa_config->system_aperture.agp_top;
2127         config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot;
2128         config.system_aperture.agp_base = pa_config->system_aperture.agp_base;
2129         config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr;
2130         config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr;
2131         config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr;
2132         config.page_table_default_page_addr = pa_config->page_table_default_page_addr;
2133
2134         return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config);
2135 }
2136
2137 static bool patch_address_for_sbs_tb_stereo(
2138                 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr)
2139 {
2140         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2141         bool sec_split = pipe_ctx->top_pipe &&
2142                         pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
2143         if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2144                         (pipe_ctx->stream->timing.timing_3d_format ==
2145                         TIMING_3D_FORMAT_SIDE_BY_SIDE ||
2146                         pipe_ctx->stream->timing.timing_3d_format ==
2147                         TIMING_3D_FORMAT_TOP_AND_BOTTOM)) {
2148                 *addr = plane_state->address.grph_stereo.left_addr;
2149                 plane_state->address.grph_stereo.left_addr =
2150                                 plane_state->address.grph_stereo.right_addr;
2151                 return true;
2152         }
2153
2154         if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE &&
2155                         plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) {
2156                 plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO;
2157                 plane_state->address.grph_stereo.right_addr =
2158                                 plane_state->address.grph_stereo.left_addr;
2159                 plane_state->address.grph_stereo.right_meta_addr =
2160                                 plane_state->address.grph_stereo.left_meta_addr;
2161         }
2162         return false;
2163 }
2164
2165 void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)
2166 {
2167         bool addr_patched = false;
2168         PHYSICAL_ADDRESS_LOC addr;
2169         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2170
2171         if (plane_state == NULL)
2172                 return;
2173
2174         addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);
2175
2176         // Call Helper to track VMID use
2177         vm_helper_mark_vmid_used(dc->vm_helper, plane_state->address.vmid, pipe_ctx->plane_res.hubp->inst);
2178
2179         pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(
2180                         pipe_ctx->plane_res.hubp,
2181                         &plane_state->address,
2182                         plane_state->flip_immediate);
2183
2184         plane_state->status.requested_address = plane_state->address;
2185
2186         if (plane_state->flip_immediate)
2187                 plane_state->status.current_address = plane_state->address;
2188
2189         if (addr_patched)
2190                 pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;
2191 }
2192
2193 void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx,
2194                 struct dc_link_settings *link_settings)
2195 {
2196         struct encoder_unblank_param params = {0};
2197         struct dc_stream_state *stream = pipe_ctx->stream;
2198         struct dc_link *link = stream->link;
2199         struct dce_hwseq *hws = link->dc->hwseq;
2200         struct pipe_ctx *odm_pipe;
2201
2202         params.opp_cnt = 1;
2203         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
2204                 params.opp_cnt++;
2205         }
2206         /* only 3 items below are used by unblank */
2207         params.timing = pipe_ctx->stream->timing;
2208
2209         params.link_settings.link_rate = link_settings->link_rate;
2210
2211         if (is_dp_128b_132b_signal(pipe_ctx)) {
2212                 /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */
2213                 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_unblank(
2214                                 pipe_ctx->stream_res.hpo_dp_stream_enc,
2215                                 pipe_ctx->stream_res.tg->inst);
2216         } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
2217                 if (optc2_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1)
2218                         params.timing.pix_clk_100hz /= 2;
2219                 pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine(
2220                                 pipe_ctx->stream_res.stream_enc, params.opp_cnt > 1);
2221                 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, &params);
2222         }
2223
2224         if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
2225                 hws->funcs.edp_backlight_control(link, true);
2226         }
2227 }
2228
2229 void dcn20_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx)
2230 {
2231         struct timing_generator *tg = pipe_ctx->stream_res.tg;
2232         int start_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);
2233
2234         if (start_line < 0)
2235                 start_line = 0;
2236
2237         if (tg->funcs->setup_vertical_interrupt2)
2238                 tg->funcs->setup_vertical_interrupt2(tg, start_line);
2239 }
2240
2241 static void dcn20_reset_back_end_for_pipe(
2242                 struct dc *dc,
2243                 struct pipe_ctx *pipe_ctx,
2244                 struct dc_state *context)
2245 {
2246         int i;
2247         struct dc_link *link;
2248         DC_LOGGER_INIT(dc->ctx->logger);
2249         if (pipe_ctx->stream_res.stream_enc == NULL) {
2250                 pipe_ctx->stream = NULL;
2251                 return;
2252         }
2253
2254         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
2255                 link = pipe_ctx->stream->link;
2256                 /* DPMS may already disable or */
2257                 /* dpms_off status is incorrect due to fastboot
2258                  * feature. When system resume from S4 with second
2259                  * screen only, the dpms_off would be true but
2260                  * VBIOS lit up eDP, so check link status too.
2261                  */
2262                 if (!pipe_ctx->stream->dpms_off || link->link_status.link_active)
2263                         core_link_disable_stream(pipe_ctx);
2264                 else if (pipe_ctx->stream_res.audio)
2265                         dc->hwss.disable_audio_stream(pipe_ctx);
2266
2267                 /* free acquired resources */
2268                 if (pipe_ctx->stream_res.audio) {
2269                         /*disable az_endpoint*/
2270                         pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
2271
2272                         /*free audio*/
2273                         if (dc->caps.dynamic_audio == true) {
2274                                 /*we have to dynamic arbitrate the audio endpoints*/
2275                                 /*we free the resource, need reset is_audio_acquired*/
2276                                 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
2277                                                 pipe_ctx->stream_res.audio, false);
2278                                 pipe_ctx->stream_res.audio = NULL;
2279                         }
2280                 }
2281         }
2282         else if (pipe_ctx->stream_res.dsc) {
2283                 dp_set_dsc_enable(pipe_ctx, false);
2284         }
2285
2286         /* by upper caller loop, parent pipe: pipe0, will be reset last.
2287          * back end share by all pipes and will be disable only when disable
2288          * parent pipe.
2289          */
2290         if (pipe_ctx->top_pipe == NULL) {
2291
2292                 dc->hwss.set_abm_immediate_disable(pipe_ctx);
2293
2294                 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
2295
2296                 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
2297                 if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass)
2298                         pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
2299                                         pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
2300
2301                 if (pipe_ctx->stream_res.tg->funcs->set_drr)
2302                         pipe_ctx->stream_res.tg->funcs->set_drr(
2303                                         pipe_ctx->stream_res.tg, NULL);
2304         }
2305
2306         for (i = 0; i < dc->res_pool->pipe_count; i++)
2307                 if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx)
2308                         break;
2309
2310         if (i == dc->res_pool->pipe_count)
2311                 return;
2312
2313         pipe_ctx->stream = NULL;
2314         DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n",
2315                                         pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
2316 }
2317
2318 void dcn20_reset_hw_ctx_wrap(
2319                 struct dc *dc,
2320                 struct dc_state *context)
2321 {
2322         int i;
2323         struct dce_hwseq *hws = dc->hwseq;
2324
2325         /* Reset Back End*/
2326         for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
2327                 struct pipe_ctx *pipe_ctx_old =
2328                         &dc->current_state->res_ctx.pipe_ctx[i];
2329                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2330
2331                 if (!pipe_ctx_old->stream)
2332                         continue;
2333
2334                 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe)
2335                         continue;
2336
2337                 if (!pipe_ctx->stream ||
2338                                 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
2339                         struct clock_source *old_clk = pipe_ctx_old->clock_source;
2340
2341                         dcn20_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
2342                         if (hws->funcs.enable_stream_gating)
2343                                 hws->funcs.enable_stream_gating(dc, pipe_ctx_old);
2344                         if (old_clk)
2345                                 old_clk->funcs->cs_power_down(old_clk);
2346                 }
2347         }
2348 }
2349
2350 void dcn20_update_visual_confirm_color(struct dc *dc, struct pipe_ctx *pipe_ctx, struct tg_color *color, int mpcc_id)
2351 {
2352         struct mpc *mpc = dc->res_pool->mpc;
2353
2354         // input to MPCC is always RGB, by default leave black_color at 0
2355         if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR)
2356                 get_hdr_visual_confirm_color(pipe_ctx, color);
2357         else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE)
2358                 get_surface_visual_confirm_color(pipe_ctx, color);
2359         else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE)
2360                 get_mpctree_visual_confirm_color(pipe_ctx, color);
2361         else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SWIZZLE)
2362                 get_surface_tile_visual_confirm_color(pipe_ctx, color);
2363
2364         if (mpc->funcs->set_bg_color)
2365                 mpc->funcs->set_bg_color(mpc, color, mpcc_id);
2366 }
2367
2368 void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
2369 {
2370         struct hubp *hubp = pipe_ctx->plane_res.hubp;
2371         struct mpcc_blnd_cfg blnd_cfg = {0};
2372         bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha;
2373         int mpcc_id;
2374         struct mpcc *new_mpcc;
2375         struct mpc *mpc = dc->res_pool->mpc;
2376         struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);
2377
2378         blnd_cfg.overlap_only = false;
2379         blnd_cfg.global_gain = 0xff;
2380
2381         if (per_pixel_alpha) {
2382                 blnd_cfg.pre_multiplied_alpha = pipe_ctx->plane_state->pre_multiplied_alpha;
2383                 if (pipe_ctx->plane_state->global_alpha) {
2384                         blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN;
2385                         blnd_cfg.global_gain = pipe_ctx->plane_state->global_alpha_value;
2386                 } else {
2387                         blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;
2388                 }
2389         } else {
2390                 blnd_cfg.pre_multiplied_alpha = false;
2391                 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA;
2392         }
2393
2394         if (pipe_ctx->plane_state->global_alpha)
2395                 blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value;
2396         else
2397                 blnd_cfg.global_alpha = 0xff;
2398
2399         blnd_cfg.background_color_bpc = 4;
2400         blnd_cfg.bottom_gain_mode = 0;
2401         blnd_cfg.top_gain = 0x1f000;
2402         blnd_cfg.bottom_inside_gain = 0x1f000;
2403         blnd_cfg.bottom_outside_gain = 0x1f000;
2404
2405         if (pipe_ctx->plane_state->format
2406                         == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA)
2407                 blnd_cfg.pre_multiplied_alpha = false;
2408
2409         /*
2410          * TODO: remove hack
2411          * Note: currently there is a bug in init_hw such that
2412          * on resume from hibernate, BIOS sets up MPCC0, and
2413          * we do mpcc_remove but the mpcc cannot go to idle
2414          * after remove. This cause us to pick mpcc1 here,
2415          * which causes a pstate hang for yet unknown reason.
2416          */
2417         mpcc_id = hubp->inst;
2418
2419         /* If there is no full update, don't need to touch MPC tree*/
2420         if (!pipe_ctx->plane_state->update_flags.bits.full_update &&
2421                 !pipe_ctx->update_flags.bits.mpcc) {
2422                 mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id);
2423                 dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id);
2424                 return;
2425         }
2426
2427         /* check if this MPCC is already being used */
2428         new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id);
2429         /* remove MPCC if being used */
2430         if (new_mpcc != NULL)
2431                 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc);
2432         else
2433                 if (dc->debug.sanity_checks)
2434                         mpc->funcs->assert_mpcc_idle_before_connect(
2435                                         dc->res_pool->mpc, mpcc_id);
2436
2437         /* Call MPC to insert new plane */
2438         new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,
2439                         mpc_tree_params,
2440                         &blnd_cfg,
2441                         NULL,
2442                         NULL,
2443                         hubp->inst,
2444                         mpcc_id);
2445
2446         dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id);
2447
2448         ASSERT(new_mpcc != NULL);
2449         hubp->opp_id = pipe_ctx->stream_res.opp->inst;
2450         hubp->mpcc_id = mpcc_id;
2451 }
2452
2453 void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)
2454 {
2455         enum dc_lane_count lane_count =
2456                 pipe_ctx->stream->link->cur_link_settings.lane_count;
2457
2458         struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
2459         struct dc_link *link = pipe_ctx->stream->link;
2460
2461         uint32_t active_total_with_borders;
2462         uint32_t early_control = 0;
2463         struct timing_generator *tg = pipe_ctx->stream_res.tg;
2464         const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
2465         struct dc *dc = pipe_ctx->stream->ctx->dc;
2466
2467         if (is_dp_128b_132b_signal(pipe_ctx)) {
2468                 if (dc->hwseq->funcs.setup_hpo_hw_control)
2469                         dc->hwseq->funcs.setup_hpo_hw_control(dc->hwseq, true);
2470         }
2471
2472         link_hwss->setup_stream_encoder(pipe_ctx);
2473
2474         if (pipe_ctx->plane_state && pipe_ctx->plane_state->flip_immediate != 1) {
2475                 if (dc->hwss.program_dmdata_engine)
2476                         dc->hwss.program_dmdata_engine(pipe_ctx);
2477         }
2478
2479         dc->hwss.update_info_frame(pipe_ctx);
2480
2481         if (dc_is_dp_signal(pipe_ctx->stream->signal))
2482                 dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME);
2483
2484         /* enable early control to avoid corruption on DP monitor*/
2485         active_total_with_borders =
2486                         timing->h_addressable
2487                                 + timing->h_border_left
2488                                 + timing->h_border_right;
2489
2490         if (lane_count != 0)
2491                 early_control = active_total_with_borders % lane_count;
2492
2493         if (early_control == 0)
2494                 early_control = lane_count;
2495
2496         tg->funcs->set_early_control(tg, early_control);
2497
2498         if (pipe_ctx->stream_res.stream_enc->funcs->set_input_mode)
2499                 pipe_ctx->stream_res.stream_enc->funcs->set_input_mode(pipe_ctx->stream_res.stream_enc,
2500                         timing->pixel_encoding == PIXEL_ENCODING_YCBCR420 ? 2 : 1);
2501
2502         /* enable audio only within mode set */
2503         if (pipe_ctx->stream_res.audio != NULL) {
2504                 if (is_dp_128b_132b_signal(pipe_ctx))
2505                         pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.hpo_dp_stream_enc);
2506                 else if (dc_is_dp_signal(pipe_ctx->stream->signal))
2507                         pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
2508         }
2509 }
2510
2511 void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx)
2512 {
2513         struct dc_stream_state    *stream     = pipe_ctx->stream;
2514         struct hubp               *hubp       = pipe_ctx->plane_res.hubp;
2515         bool                       enable     = false;
2516         struct stream_encoder     *stream_enc = pipe_ctx->stream_res.stream_enc;
2517         enum dynamic_metadata_mode mode       = dc_is_dp_signal(stream->signal)
2518                                                         ? dmdata_dp
2519                                                         : dmdata_hdmi;
2520
2521         /* if using dynamic meta, don't set up generic infopackets */
2522         if (pipe_ctx->stream->dmdata_address.quad_part != 0) {
2523                 pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false;
2524                 enable = true;
2525         }
2526
2527         if (!hubp)
2528                 return;
2529
2530         if (!stream_enc || !stream_enc->funcs->set_dynamic_metadata)
2531                 return;
2532
2533         stream_enc->funcs->set_dynamic_metadata(stream_enc, enable,
2534                                                 hubp->inst, mode);
2535 }
2536
2537 void dcn20_fpga_init_hw(struct dc *dc)
2538 {
2539         int i, j;
2540         struct dce_hwseq *hws = dc->hwseq;
2541         struct resource_pool *res_pool = dc->res_pool;
2542         struct dc_state  *context = dc->current_state;
2543
2544         if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
2545                 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
2546
2547         // Initialize the dccg
2548         if (res_pool->dccg->funcs->dccg_init)
2549                 res_pool->dccg->funcs->dccg_init(res_pool->dccg);
2550
2551         //Enable ability to power gate / don't force power on permanently
2552         hws->funcs.enable_power_gating_plane(hws, true);
2553
2554         // Specific to FPGA dccg and registers
2555         REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF);
2556         REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF);
2557
2558         hws->funcs.dccg_init(hws);
2559
2560         REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2);
2561         REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
2562         if (REG(REFCLK_CNTL))
2563                 REG_WRITE(REFCLK_CNTL, 0);
2564         //
2565
2566
2567         /* Blank pixel data with OPP DPG */
2568         for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
2569                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2570
2571                 if (tg->funcs->is_tg_enabled(tg))
2572                         dcn20_init_blank(dc, tg);
2573         }
2574
2575         for (i = 0; i < res_pool->timing_generator_count; i++) {
2576                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2577
2578                 if (tg->funcs->is_tg_enabled(tg))
2579                         tg->funcs->lock(tg);
2580         }
2581
2582         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2583                 struct dpp *dpp = res_pool->dpps[i];
2584
2585                 dpp->funcs->dpp_reset(dpp);
2586         }
2587
2588         /* Reset all MPCC muxes */
2589         res_pool->mpc->funcs->mpc_init(res_pool->mpc);
2590
2591         /* initialize OPP mpc_tree parameter */
2592         for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {
2593                 res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst;
2594                 res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
2595                 for (j = 0; j < MAX_PIPES; j++)
2596                         res_pool->opps[i]->mpcc_disconnect_pending[j] = false;
2597         }
2598
2599         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2600                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2601                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2602                 struct hubp *hubp = dc->res_pool->hubps[i];
2603                 struct dpp *dpp = dc->res_pool->dpps[i];
2604
2605                 pipe_ctx->stream_res.tg = tg;
2606                 pipe_ctx->pipe_idx = i;
2607
2608                 pipe_ctx->plane_res.hubp = hubp;
2609                 pipe_ctx->plane_res.dpp = dpp;
2610                 pipe_ctx->plane_res.mpcc_inst = dpp->inst;
2611                 hubp->mpcc_id = dpp->inst;
2612                 hubp->opp_id = OPP_ID_INVALID;
2613                 hubp->power_gated = false;
2614                 pipe_ctx->stream_res.opp = NULL;
2615
2616                 hubp->funcs->hubp_init(hubp);
2617
2618                 //dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
2619                 //dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
2620                 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
2621                 pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
2622                 /*to do*/
2623                 hws->funcs.plane_atomic_disconnect(dc, pipe_ctx);
2624         }
2625
2626         /* initialize DWB pointer to MCIF_WB */
2627         for (i = 0; i < res_pool->res_cap->num_dwb; i++)
2628                 res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i];
2629
2630         for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
2631                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2632
2633                 if (tg->funcs->is_tg_enabled(tg))
2634                         tg->funcs->unlock(tg);
2635         }
2636
2637         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2638                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2639
2640                 dc->hwss.disable_plane(dc, pipe_ctx);
2641
2642                 pipe_ctx->stream_res.tg = NULL;
2643                 pipe_ctx->plane_res.hubp = NULL;
2644         }
2645
2646         for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
2647                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2648
2649                 tg->funcs->tg_init(tg);
2650         }
2651
2652         if (dc->res_pool->hubbub->funcs->init_crb)
2653                 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);
2654 }
2655 #ifndef TRIM_FSFT
2656 bool dcn20_optimize_timing_for_fsft(struct dc *dc,
2657                 struct dc_crtc_timing *timing,
2658                 unsigned int max_input_rate_in_khz)
2659 {
2660         unsigned int old_v_front_porch;
2661         unsigned int old_v_total;
2662         unsigned int max_input_rate_in_100hz;
2663         unsigned long long new_v_total;
2664
2665         max_input_rate_in_100hz = max_input_rate_in_khz * 10;
2666         if (max_input_rate_in_100hz < timing->pix_clk_100hz)
2667                 return false;
2668
2669         old_v_total = timing->v_total;
2670         old_v_front_porch = timing->v_front_porch;
2671
2672         timing->fast_transport_output_rate_100hz = timing->pix_clk_100hz;
2673         timing->pix_clk_100hz = max_input_rate_in_100hz;
2674
2675         new_v_total = div_u64((unsigned long long)old_v_total * max_input_rate_in_100hz, timing->pix_clk_100hz);
2676
2677         timing->v_total = new_v_total;
2678         timing->v_front_porch = old_v_front_porch + (timing->v_total - old_v_total);
2679         return true;
2680 }
2681 #endif
2682
2683 void dcn20_set_disp_pattern_generator(const struct dc *dc,
2684                 struct pipe_ctx *pipe_ctx,
2685                 enum controller_dp_test_pattern test_pattern,
2686                 enum controller_dp_color_space color_space,
2687                 enum dc_color_depth color_depth,
2688                 const struct tg_color *solid_color,
2689                 int width, int height, int offset)
2690 {
2691         pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern,
2692                         color_space, color_depth, solid_color, width, height, offset);
2693 }