2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <linux/delay.h>
27 #include "dm_services.h"
28 #include "basics/dc_common.h"
29 #include "dm_helpers.h"
30 #include "core_types.h"
32 #include "dcn20_resource.h"
33 #include "dcn20_hwseq.h"
34 #include "dce/dce_hwseq.h"
35 #include "dcn20_dsc.h"
36 #include "dcn20_optc.h"
41 #include "timing_generator.h"
47 #include "reg_helper.h"
48 #include "dcn10/dcn10_cm_common.h"
49 #include "dc_link_dp.h"
50 #include "vm_helper.h"
53 #define DC_LOGGER_INIT(logger)
61 #define FN(reg_name, field_name) \
62 hws->shifts->field_name, hws->masks->field_name
64 static int find_free_gsl_group(const struct dc *dc)
66 if (dc->res_pool->gsl_groups.gsl_0 == 0)
68 if (dc->res_pool->gsl_groups.gsl_1 == 0)
70 if (dc->res_pool->gsl_groups.gsl_2 == 0)
76 /* NOTE: This is not a generic setup_gsl function (hence the suffix as_lock)
77 * This is only used to lock pipes in pipe splitting case with immediate flip
78 * Ordinary MPC/OTG locks suppress VUPDATE which doesn't help with immediate,
79 * so we get tearing with freesync since we cannot flip multiple pipes
81 * We use GSL for this:
82 * - immediate flip: find first available GSL group if not already assigned
83 * program gsl with that group, set current OTG as master
84 * and always us 0x4 = AND of flip_ready from all pipes
85 * - vsync flip: disable GSL if used
87 * Groups in stream_res are stored as +1 from HW registers, i.e.
88 * gsl_0 <=> pipe_ctx->stream_res.gsl_group == 1
89 * Using a magic value like -1 would require tracking all inits/resets
91 static void dcn20_setup_gsl_group_as_lock(
93 struct pipe_ctx *pipe_ctx,
96 struct gsl_params gsl;
99 memset(&gsl, 0, sizeof(struct gsl_params));
102 /* return if group already assigned since GSL was set up
103 * for vsync flip, we would unassign so it can't be "left over"
105 if (pipe_ctx->stream_res.gsl_group > 0)
108 group_idx = find_free_gsl_group(dc);
109 ASSERT(group_idx != 0);
110 pipe_ctx->stream_res.gsl_group = group_idx;
112 /* set gsl group reg field and mark resource used */
116 dc->res_pool->gsl_groups.gsl_0 = 1;
120 dc->res_pool->gsl_groups.gsl_1 = 1;
124 dc->res_pool->gsl_groups.gsl_2 = 1;
128 return; // invalid case
130 gsl.gsl_master_en = 1;
132 group_idx = pipe_ctx->stream_res.gsl_group;
134 return; // if not in use, just return
136 pipe_ctx->stream_res.gsl_group = 0;
138 /* unset gsl group reg field and mark resource free */
142 dc->res_pool->gsl_groups.gsl_0 = 0;
146 dc->res_pool->gsl_groups.gsl_1 = 0;
150 dc->res_pool->gsl_groups.gsl_2 = 0;
156 gsl.gsl_master_en = 0;
159 /* at this point we want to program whether it's to enable or disable */
160 if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL &&
161 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) {
162 pipe_ctx->stream_res.tg->funcs->set_gsl(
163 pipe_ctx->stream_res.tg,
166 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select(
167 pipe_ctx->stream_res.tg, group_idx, enable ? 4 : 0);
172 void dcn20_set_flip_control_gsl(
173 struct pipe_ctx *pipe_ctx,
176 if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl)
177 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl(
178 pipe_ctx->plane_res.hubp, flip_immediate);
182 void dcn20_enable_power_gating_plane(
183 struct dce_hwseq *hws,
186 bool force_on = true; /* disable power gating */
191 /* DCHUBP0/1/2/3/4/5 */
192 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on);
193 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on);
194 REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on);
195 REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on);
196 if (REG(DOMAIN8_PG_CONFIG))
197 REG_UPDATE(DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on);
198 if (REG(DOMAIN10_PG_CONFIG))
199 REG_UPDATE(DOMAIN10_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on);
202 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on);
203 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on);
204 REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on);
205 REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);
206 if (REG(DOMAIN9_PG_CONFIG))
207 REG_UPDATE(DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on);
208 if (REG(DOMAIN11_PG_CONFIG))
209 REG_UPDATE(DOMAIN11_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on);
212 REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, force_on);
213 REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, force_on);
214 REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, force_on);
215 if (REG(DOMAIN19_PG_CONFIG))
216 REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, force_on);
217 if (REG(DOMAIN20_PG_CONFIG))
218 REG_UPDATE(DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, force_on);
219 if (REG(DOMAIN21_PG_CONFIG))
220 REG_UPDATE(DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, force_on);
223 void dcn20_dccg_init(struct dce_hwseq *hws)
226 * set MICROSECOND_TIME_BASE_DIV
227 * 100Mhz refclk -> 0x120264
228 * 27Mhz refclk -> 0x12021b
229 * 48Mhz refclk -> 0x120230
232 REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x120264);
235 * set MILLISECOND_TIME_BASE_DIV
236 * 100Mhz refclk -> 0x1186a0
237 * 27Mhz refclk -> 0x106978
238 * 48Mhz refclk -> 0x10bb80
241 REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x1186a0);
243 /* This value is dependent on the hardware pipeline delay so set once per SOC */
244 REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0x801003c);
247 void dcn20_disable_vga(
248 struct dce_hwseq *hws)
250 REG_WRITE(D1VGA_CONTROL, 0);
251 REG_WRITE(D2VGA_CONTROL, 0);
252 REG_WRITE(D3VGA_CONTROL, 0);
253 REG_WRITE(D4VGA_CONTROL, 0);
254 REG_WRITE(D5VGA_CONTROL, 0);
255 REG_WRITE(D6VGA_CONTROL, 0);
258 void dcn20_program_triple_buffer(
260 struct pipe_ctx *pipe_ctx,
261 bool enable_triple_buffer)
263 if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) {
264 pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer(
265 pipe_ctx->plane_res.hubp,
266 enable_triple_buffer);
270 /* Blank pixel data during initialization */
271 void dcn20_init_blank(
273 struct timing_generator *tg)
275 struct dce_hwseq *hws = dc->hwseq;
276 enum dc_color_space color_space;
277 struct tg_color black_color = {0};
278 struct output_pixel_processor *opp = NULL;
279 struct output_pixel_processor *bottom_opp = NULL;
280 uint32_t num_opps, opp_id_src0, opp_id_src1;
281 uint32_t otg_active_width, otg_active_height;
283 /* program opp dpg blank color */
284 color_space = COLOR_SPACE_SRGB;
285 color_space_to_black_color(dc, color_space, &black_color);
287 /* get the OTG active size */
288 tg->funcs->get_otg_active_size(tg,
292 /* get the OPTC source */
293 tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1);
294 ASSERT(opp_id_src0 < dc->res_pool->res_cap->num_opp);
295 opp = dc->res_pool->opps[opp_id_src0];
298 otg_active_width = otg_active_width / 2;
299 ASSERT(opp_id_src1 < dc->res_pool->res_cap->num_opp);
300 bottom_opp = dc->res_pool->opps[opp_id_src1];
303 opp->funcs->opp_set_disp_pattern_generator(
305 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,
306 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
307 COLOR_DEPTH_UNDEFINED,
313 bottom_opp->funcs->opp_set_disp_pattern_generator(
315 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,
316 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
317 COLOR_DEPTH_UNDEFINED,
323 hws->funcs.wait_for_blank_complete(opp);
326 void dcn20_dsc_pg_control(
327 struct dce_hwseq *hws,
328 unsigned int dsc_inst,
331 uint32_t power_gate = power_on ? 0 : 1;
332 uint32_t pwr_status = power_on ? 0 : 2;
333 uint32_t org_ip_request_cntl = 0;
335 if (hws->ctx->dc->debug.disable_dsc_power_gate)
338 if (REG(DOMAIN16_PG_CONFIG) == 0)
341 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
342 if (org_ip_request_cntl == 0)
343 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
347 REG_UPDATE(DOMAIN16_PG_CONFIG,
348 DOMAIN16_POWER_GATE, power_gate);
350 REG_WAIT(DOMAIN16_PG_STATUS,
351 DOMAIN16_PGFSM_PWR_STATUS, pwr_status,
355 REG_UPDATE(DOMAIN17_PG_CONFIG,
356 DOMAIN17_POWER_GATE, power_gate);
358 REG_WAIT(DOMAIN17_PG_STATUS,
359 DOMAIN17_PGFSM_PWR_STATUS, pwr_status,
363 REG_UPDATE(DOMAIN18_PG_CONFIG,
364 DOMAIN18_POWER_GATE, power_gate);
366 REG_WAIT(DOMAIN18_PG_STATUS,
367 DOMAIN18_PGFSM_PWR_STATUS, pwr_status,
371 REG_UPDATE(DOMAIN19_PG_CONFIG,
372 DOMAIN19_POWER_GATE, power_gate);
374 REG_WAIT(DOMAIN19_PG_STATUS,
375 DOMAIN19_PGFSM_PWR_STATUS, pwr_status,
379 REG_UPDATE(DOMAIN20_PG_CONFIG,
380 DOMAIN20_POWER_GATE, power_gate);
382 REG_WAIT(DOMAIN20_PG_STATUS,
383 DOMAIN20_PGFSM_PWR_STATUS, pwr_status,
387 REG_UPDATE(DOMAIN21_PG_CONFIG,
388 DOMAIN21_POWER_GATE, power_gate);
390 REG_WAIT(DOMAIN21_PG_STATUS,
391 DOMAIN21_PGFSM_PWR_STATUS, pwr_status,
399 if (org_ip_request_cntl == 0)
400 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
403 void dcn20_dpp_pg_control(
404 struct dce_hwseq *hws,
405 unsigned int dpp_inst,
408 uint32_t power_gate = power_on ? 0 : 1;
409 uint32_t pwr_status = power_on ? 0 : 2;
411 if (hws->ctx->dc->debug.disable_dpp_power_gate)
413 if (REG(DOMAIN1_PG_CONFIG) == 0)
418 REG_UPDATE(DOMAIN1_PG_CONFIG,
419 DOMAIN1_POWER_GATE, power_gate);
421 REG_WAIT(DOMAIN1_PG_STATUS,
422 DOMAIN1_PGFSM_PWR_STATUS, pwr_status,
426 REG_UPDATE(DOMAIN3_PG_CONFIG,
427 DOMAIN3_POWER_GATE, power_gate);
429 REG_WAIT(DOMAIN3_PG_STATUS,
430 DOMAIN3_PGFSM_PWR_STATUS, pwr_status,
434 REG_UPDATE(DOMAIN5_PG_CONFIG,
435 DOMAIN5_POWER_GATE, power_gate);
437 REG_WAIT(DOMAIN5_PG_STATUS,
438 DOMAIN5_PGFSM_PWR_STATUS, pwr_status,
442 REG_UPDATE(DOMAIN7_PG_CONFIG,
443 DOMAIN7_POWER_GATE, power_gate);
445 REG_WAIT(DOMAIN7_PG_STATUS,
446 DOMAIN7_PGFSM_PWR_STATUS, pwr_status,
450 REG_UPDATE(DOMAIN9_PG_CONFIG,
451 DOMAIN9_POWER_GATE, power_gate);
453 REG_WAIT(DOMAIN9_PG_STATUS,
454 DOMAIN9_PGFSM_PWR_STATUS, pwr_status,
459 * Do not power gate DPP5, should be left at HW default, power on permanently.
460 * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard
462 * REG_UPDATE(DOMAIN11_PG_CONFIG,
463 * DOMAIN11_POWER_GATE, power_gate);
465 * REG_WAIT(DOMAIN11_PG_STATUS,
466 * DOMAIN11_PGFSM_PWR_STATUS, pwr_status,
477 void dcn20_hubp_pg_control(
478 struct dce_hwseq *hws,
479 unsigned int hubp_inst,
482 uint32_t power_gate = power_on ? 0 : 1;
483 uint32_t pwr_status = power_on ? 0 : 2;
485 if (hws->ctx->dc->debug.disable_hubp_power_gate)
487 if (REG(DOMAIN0_PG_CONFIG) == 0)
491 case 0: /* DCHUBP0 */
492 REG_UPDATE(DOMAIN0_PG_CONFIG,
493 DOMAIN0_POWER_GATE, power_gate);
495 REG_WAIT(DOMAIN0_PG_STATUS,
496 DOMAIN0_PGFSM_PWR_STATUS, pwr_status,
499 case 1: /* DCHUBP1 */
500 REG_UPDATE(DOMAIN2_PG_CONFIG,
501 DOMAIN2_POWER_GATE, power_gate);
503 REG_WAIT(DOMAIN2_PG_STATUS,
504 DOMAIN2_PGFSM_PWR_STATUS, pwr_status,
507 case 2: /* DCHUBP2 */
508 REG_UPDATE(DOMAIN4_PG_CONFIG,
509 DOMAIN4_POWER_GATE, power_gate);
511 REG_WAIT(DOMAIN4_PG_STATUS,
512 DOMAIN4_PGFSM_PWR_STATUS, pwr_status,
515 case 3: /* DCHUBP3 */
516 REG_UPDATE(DOMAIN6_PG_CONFIG,
517 DOMAIN6_POWER_GATE, power_gate);
519 REG_WAIT(DOMAIN6_PG_STATUS,
520 DOMAIN6_PGFSM_PWR_STATUS, pwr_status,
523 case 4: /* DCHUBP4 */
524 REG_UPDATE(DOMAIN8_PG_CONFIG,
525 DOMAIN8_POWER_GATE, power_gate);
527 REG_WAIT(DOMAIN8_PG_STATUS,
528 DOMAIN8_PGFSM_PWR_STATUS, pwr_status,
531 case 5: /* DCHUBP5 */
533 * Do not power gate DCHUB5, should be left at HW default, power on permanently.
534 * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard
536 * REG_UPDATE(DOMAIN10_PG_CONFIG,
537 * DOMAIN10_POWER_GATE, power_gate);
539 * REG_WAIT(DOMAIN10_PG_STATUS,
540 * DOMAIN10_PGFSM_PWR_STATUS, pwr_status,
551 /* disable HW used by plane.
552 * note: cannot disable until disconnect is complete
554 void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
556 struct dce_hwseq *hws = dc->hwseq;
557 struct hubp *hubp = pipe_ctx->plane_res.hubp;
558 struct dpp *dpp = pipe_ctx->plane_res.dpp;
560 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);
562 /* In flip immediate with pipe splitting case GSL is used for
563 * synchronization so we must disable it when the plane is disabled.
565 if (pipe_ctx->stream_res.gsl_group != 0)
566 dcn20_setup_gsl_group_as_lock(dc, pipe_ctx, false);
568 dc->hwss.set_flip_control_gsl(pipe_ctx, false);
570 hubp->funcs->hubp_clk_cntl(hubp, false);
572 dpp->funcs->dpp_dppclk_control(dpp, false, false);
574 hubp->power_gated = true;
576 hws->funcs.plane_atomic_power_down(dc,
577 pipe_ctx->plane_res.dpp,
578 pipe_ctx->plane_res.hubp);
580 pipe_ctx->stream = NULL;
581 memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res));
582 memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res));
583 pipe_ctx->top_pipe = NULL;
584 pipe_ctx->bottom_pipe = NULL;
585 pipe_ctx->plane_state = NULL;
589 void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
591 DC_LOGGER_INIT(dc->ctx->logger);
593 if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)
596 dcn20_plane_atomic_disable(dc, pipe_ctx);
598 DC_LOG_DC("Power down front end %d\n",
602 enum dc_status dcn20_enable_stream_timing(
603 struct pipe_ctx *pipe_ctx,
604 struct dc_state *context,
607 struct dce_hwseq *hws = dc->hwseq;
608 struct dc_stream_state *stream = pipe_ctx->stream;
609 struct drr_params params = {0};
610 unsigned int event_triggers = 0;
611 struct pipe_ctx *odm_pipe;
613 int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst };
615 /* by upper caller loop, pipe0 is parent pipe and be called first.
616 * back end is set up by for pipe0. Other children pipe share back end
617 * with pipe 0. No program is needed.
619 if (pipe_ctx->top_pipe != NULL)
622 /* TODO check if timing_changed, disable stream if timing changed */
624 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
625 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;
630 pipe_ctx->stream_res.tg->funcs->set_odm_combine(
631 pipe_ctx->stream_res.tg,
633 &pipe_ctx->stream->timing);
635 /* HW program guide assume display already disable
636 * by unplug sequence. OTG assume stop.
638 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true);
640 if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
641 pipe_ctx->clock_source,
642 &pipe_ctx->stream_res.pix_clk_params,
643 &pipe_ctx->pll_settings)) {
645 return DC_ERROR_UNEXPECTED;
648 pipe_ctx->stream_res.tg->funcs->program_timing(
649 pipe_ctx->stream_res.tg,
651 pipe_ctx->pipe_dlg_param.vready_offset,
652 pipe_ctx->pipe_dlg_param.vstartup_start,
653 pipe_ctx->pipe_dlg_param.vupdate_offset,
654 pipe_ctx->pipe_dlg_param.vupdate_width,
655 pipe_ctx->stream->signal,
658 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
659 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control(
660 odm_pipe->stream_res.opp,
663 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
664 pipe_ctx->stream_res.opp,
667 hws->funcs.blank_pixel_data(dc, pipe_ctx, true);
669 /* VTG is within DCHUB command block. DCFCLK is always on */
670 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {
672 return DC_ERROR_UNEXPECTED;
675 hws->funcs.wait_for_blank_complete(pipe_ctx->stream_res.opp);
677 params.vertical_total_min = stream->adjust.v_total_min;
678 params.vertical_total_max = stream->adjust.v_total_max;
679 params.vertical_total_mid = stream->adjust.v_total_mid;
680 params.vertical_total_mid_frame_num = stream->adjust.v_total_mid_frame_num;
681 if (pipe_ctx->stream_res.tg->funcs->set_drr)
682 pipe_ctx->stream_res.tg->funcs->set_drr(
683 pipe_ctx->stream_res.tg, ¶ms);
685 // DRR should set trigger event to monitor surface update event
686 if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0)
687 event_triggers = 0x80;
688 /* Event triggers and num frames initialized for DRR, but can be
689 * later updated for PSR use. Note DRR trigger events are generated
690 * regardless of whether num frames met.
692 if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)
693 pipe_ctx->stream_res.tg->funcs->set_static_screen_control(
694 pipe_ctx->stream_res.tg, event_triggers, 2);
696 /* TODO program crtc source select for non-virtual signal*/
697 /* TODO program FMT */
698 /* TODO setup link_enc */
699 /* TODO set stream attributes */
700 /* TODO program audio */
701 /* TODO enable stream if timing changed */
702 /* TODO unblank stream if DP */
707 void dcn20_program_output_csc(struct dc *dc,
708 struct pipe_ctx *pipe_ctx,
709 enum dc_color_space colorspace,
713 struct mpc *mpc = dc->res_pool->mpc;
714 enum mpc_output_csc_mode ocsc_mode = MPC_OUTPUT_CSC_COEF_A;
715 int mpcc_id = pipe_ctx->plane_res.hubp->inst;
717 if (mpc->funcs->power_on_mpc_mem_pwr)
718 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true);
720 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
721 if (mpc->funcs->set_output_csc != NULL)
722 mpc->funcs->set_output_csc(mpc,
727 if (mpc->funcs->set_ocsc_default != NULL)
728 mpc->funcs->set_ocsc_default(mpc,
735 bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
736 const struct dc_stream_state *stream)
738 int mpcc_id = pipe_ctx->plane_res.hubp->inst;
739 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
740 struct pwl_params *params = NULL;
742 * program OGAM only for the top pipe
743 * if there is a pipe split then fix diagnostic is required:
744 * how to pass OGAM parameter for stream.
745 * if programming for all pipes is required then remove condition
746 * pipe_ctx->top_pipe == NULL ,but then fix the diagnostic.
748 if (mpc->funcs->power_on_mpc_mem_pwr)
749 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true);
750 if (pipe_ctx->top_pipe == NULL
751 && mpc->funcs->set_output_gamma && stream->out_transfer_func) {
752 if (stream->out_transfer_func->type == TF_TYPE_HWPWL)
753 params = &stream->out_transfer_func->pwl;
754 else if (pipe_ctx->stream->out_transfer_func->type ==
755 TF_TYPE_DISTRIBUTED_POINTS &&
756 cm_helper_translate_curve_to_hw_format(
757 stream->out_transfer_func,
758 &mpc->blender_params, false))
759 params = &mpc->blender_params;
763 if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED)
767 * if above if is not executed then 'params' equal to 0 and set in bypass
769 mpc->funcs->set_output_gamma(mpc, mpcc_id, params);
774 bool dcn20_set_blend_lut(
775 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
777 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
779 struct pwl_params *blend_lut = NULL;
781 if (plane_state->blend_tf) {
782 if (plane_state->blend_tf->type == TF_TYPE_HWPWL)
783 blend_lut = &plane_state->blend_tf->pwl;
784 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) {
785 cm_helper_translate_curve_to_hw_format(
786 plane_state->blend_tf,
787 &dpp_base->regamma_params, false);
788 blend_lut = &dpp_base->regamma_params;
791 result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut);
796 bool dcn20_set_shaper_3dlut(
797 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
799 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
801 struct pwl_params *shaper_lut = NULL;
803 if (plane_state->in_shaper_func) {
804 if (plane_state->in_shaper_func->type == TF_TYPE_HWPWL)
805 shaper_lut = &plane_state->in_shaper_func->pwl;
806 else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) {
807 cm_helper_translate_curve_to_hw_format(
808 plane_state->in_shaper_func,
809 &dpp_base->shaper_params, true);
810 shaper_lut = &dpp_base->shaper_params;
814 result = dpp_base->funcs->dpp_program_shaper_lut(dpp_base, shaper_lut);
815 if (plane_state->lut3d_func &&
816 plane_state->lut3d_func->state.bits.initialized == 1)
817 result = dpp_base->funcs->dpp_program_3dlut(dpp_base,
818 &plane_state->lut3d_func->lut_3d);
820 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, NULL);
825 bool dcn20_set_input_transfer_func(struct dc *dc,
826 struct pipe_ctx *pipe_ctx,
827 const struct dc_plane_state *plane_state)
829 struct dce_hwseq *hws = dc->hwseq;
830 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
831 const struct dc_transfer_func *tf = NULL;
833 bool use_degamma_ram = false;
835 if (dpp_base == NULL || plane_state == NULL)
838 hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state);
839 hws->funcs.set_blend_lut(pipe_ctx, plane_state);
841 if (plane_state->in_transfer_func)
842 tf = plane_state->in_transfer_func;
846 dpp_base->funcs->dpp_set_degamma(dpp_base,
847 IPP_DEGAMMA_MODE_BYPASS);
851 if (tf->type == TF_TYPE_HWPWL || tf->type == TF_TYPE_DISTRIBUTED_POINTS)
852 use_degamma_ram = true;
854 if (use_degamma_ram == true) {
855 if (tf->type == TF_TYPE_HWPWL)
856 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base,
858 else if (tf->type == TF_TYPE_DISTRIBUTED_POINTS) {
859 cm_helper_translate_curve_to_degamma_hw_format(tf,
860 &dpp_base->degamma_params);
861 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base,
862 &dpp_base->degamma_params);
866 /* handle here the optimized cases when de-gamma ROM could be used.
869 if (tf->type == TF_TYPE_PREDEFINED) {
871 case TRANSFER_FUNCTION_SRGB:
872 dpp_base->funcs->dpp_set_degamma(dpp_base,
873 IPP_DEGAMMA_MODE_HW_sRGB);
875 case TRANSFER_FUNCTION_BT709:
876 dpp_base->funcs->dpp_set_degamma(dpp_base,
877 IPP_DEGAMMA_MODE_HW_xvYCC);
879 case TRANSFER_FUNCTION_LINEAR:
880 dpp_base->funcs->dpp_set_degamma(dpp_base,
881 IPP_DEGAMMA_MODE_BYPASS);
883 case TRANSFER_FUNCTION_PQ:
884 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_USER_PWL);
885 cm_helper_translate_curve_to_degamma_hw_format(tf, &dpp_base->degamma_params);
886 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, &dpp_base->degamma_params);
893 } else if (tf->type == TF_TYPE_BYPASS)
894 dpp_base->funcs->dpp_set_degamma(dpp_base,
895 IPP_DEGAMMA_MODE_BYPASS);
898 * if we are here, we did not handle correctly.
899 * fix is required for this use case
902 dpp_base->funcs->dpp_set_degamma(dpp_base,
903 IPP_DEGAMMA_MODE_BYPASS);
909 void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)
911 struct pipe_ctx *odm_pipe;
913 int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst };
915 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
916 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;
921 pipe_ctx->stream_res.tg->funcs->set_odm_combine(
922 pipe_ctx->stream_res.tg,
924 &pipe_ctx->stream->timing);
926 pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
927 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
930 void dcn20_blank_pixel_data(
932 struct pipe_ctx *pipe_ctx,
935 struct tg_color black_color = {0};
936 struct stream_resource *stream_res = &pipe_ctx->stream_res;
937 struct dc_stream_state *stream = pipe_ctx->stream;
938 enum dc_color_space color_space = stream->output_color_space;
939 enum controller_dp_test_pattern test_pattern = CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR;
940 enum controller_dp_color_space test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED;
941 struct pipe_ctx *odm_pipe;
944 int width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;
945 int height = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top;
947 if (stream->link->test_pattern_enabled)
950 /* get opp dpg blank color */
951 color_space_to_black_color(dc, color_space, &black_color);
953 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
956 width = width / odm_cnt;
960 stream_res->abm->funcs->set_abm_immediate_disable(stream_res->abm);
962 if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) {
963 test_pattern = CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
964 test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_RGB;
967 test_pattern = CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
970 stream_res->opp->funcs->opp_set_disp_pattern_generator(
973 test_pattern_color_space,
974 stream->timing.display_color_depth,
979 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
980 odm_pipe->stream_res.opp->funcs->opp_set_disp_pattern_generator(
981 odm_pipe->stream_res.opp,
982 dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE && blank ?
983 CONTROLLER_DP_TEST_PATTERN_COLORRAMP : test_pattern,
984 test_pattern_color_space,
985 stream->timing.display_color_depth,
992 if (stream_res->abm) {
993 stream_res->abm->funcs->set_pipe(stream_res->abm, stream_res->tg->inst + 1);
994 stream_res->abm->funcs->set_abm_level(stream_res->abm, stream->abm_level);
999 static void dcn20_power_on_plane(
1000 struct dce_hwseq *hws,
1001 struct pipe_ctx *pipe_ctx)
1003 DC_LOGGER_INIT(hws->ctx->logger);
1004 if (REG(DC_IP_REQUEST_CNTL)) {
1005 REG_SET(DC_IP_REQUEST_CNTL, 0,
1007 dcn20_dpp_pg_control(hws, pipe_ctx->plane_res.dpp->inst, true);
1008 dcn20_hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, true);
1009 REG_SET(DC_IP_REQUEST_CNTL, 0,
1012 "Un-gated front end for pipe %d\n", pipe_ctx->plane_res.hubp->inst);
1016 void dcn20_enable_plane(
1018 struct pipe_ctx *pipe_ctx,
1019 struct dc_state *context)
1021 //if (dc->debug.sanity_checks) {
1022 // dcn10_verify_allow_pstate_change_high(dc);
1024 dcn20_power_on_plane(dc->hwseq, pipe_ctx);
1026 /* enable DCFCLK current DCHUB */
1027 pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);
1029 /* initialize HUBP on power up */
1030 pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp);
1032 /* make sure OPP_PIPE_CLOCK_EN = 1 */
1033 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
1034 pipe_ctx->stream_res.opp,
1037 /* TODO: enable/disable in dm as per update type.
1039 DC_LOG_DC(dc->ctx->logger,
1040 "Pipe:%d 0x%x: addr hi:0x%x, "
1043 " %d; dst: %d, %d, %d, %d;\n",
1046 plane_state->address.grph.addr.high_part,
1047 plane_state->address.grph.addr.low_part,
1048 plane_state->src_rect.x,
1049 plane_state->src_rect.y,
1050 plane_state->src_rect.width,
1051 plane_state->src_rect.height,
1052 plane_state->dst_rect.x,
1053 plane_state->dst_rect.y,
1054 plane_state->dst_rect.width,
1055 plane_state->dst_rect.height);
1057 DC_LOG_DC(dc->ctx->logger,
1058 "Pipe %d: width, height, x, y format:%d\n"
1059 "viewport:%d, %d, %d, %d\n"
1060 "recout: %d, %d, %d, %d\n",
1062 plane_state->format,
1063 pipe_ctx->plane_res.scl_data.viewport.width,
1064 pipe_ctx->plane_res.scl_data.viewport.height,
1065 pipe_ctx->plane_res.scl_data.viewport.x,
1066 pipe_ctx->plane_res.scl_data.viewport.y,
1067 pipe_ctx->plane_res.scl_data.recout.width,
1068 pipe_ctx->plane_res.scl_data.recout.height,
1069 pipe_ctx->plane_res.scl_data.recout.x,
1070 pipe_ctx->plane_res.scl_data.recout.y);
1071 print_rq_dlg_ttu(dc, pipe_ctx);
1074 if (dc->vm_pa_config.valid) {
1075 struct vm_system_aperture_param apt;
1077 apt.sys_default.quad_part = 0;
1079 apt.sys_low.quad_part = dc->vm_pa_config.system_aperture.start_addr;
1080 apt.sys_high.quad_part = dc->vm_pa_config.system_aperture.end_addr;
1082 // Program system aperture settings
1083 pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt);
1086 // if (dc->debug.sanity_checks) {
1087 // dcn10_verify_allow_pstate_change_high(dc);
1091 void dcn20_pipe_control_lock(
1093 struct pipe_ctx *pipe,
1096 bool flip_immediate = false;
1098 /* use TG master update lock to lock everything on the TG
1099 * therefore only top pipe need to lock
1101 if (!pipe || pipe->top_pipe)
1104 if (pipe->plane_state != NULL)
1105 flip_immediate = pipe->plane_state->flip_immediate;
1107 if (flip_immediate && lock) {
1108 const int TIMEOUT_FOR_FLIP_PENDING = 100000;
1111 for (i = 0; i < TIMEOUT_FOR_FLIP_PENDING; ++i) {
1112 if (!pipe->plane_res.hubp->funcs->hubp_is_flip_pending(pipe->plane_res.hubp))
1117 if (pipe->bottom_pipe != NULL) {
1118 for (i = 0; i < TIMEOUT_FOR_FLIP_PENDING; ++i) {
1119 if (!pipe->bottom_pipe->plane_res.hubp->funcs->hubp_is_flip_pending(pipe->bottom_pipe->plane_res.hubp))
1126 /* In flip immediate and pipe splitting case, we need to use GSL
1127 * for synchronization. Only do setup on locking and on flip type change.
1129 if (lock && pipe->bottom_pipe != NULL)
1130 if ((flip_immediate && pipe->stream_res.gsl_group == 0) ||
1131 (!flip_immediate && pipe->stream_res.gsl_group > 0))
1132 dcn20_setup_gsl_group_as_lock(dc, pipe, flip_immediate);
1134 if (pipe->plane_state != NULL && pipe->plane_state->triplebuffer_flips) {
1136 pipe->stream_res.tg->funcs->triplebuffer_lock(pipe->stream_res.tg);
1138 pipe->stream_res.tg->funcs->triplebuffer_unlock(pipe->stream_res.tg);
1141 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);
1143 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);
1147 static void dcn20_detect_pipe_changes(struct pipe_ctx *old_pipe, struct pipe_ctx *new_pipe)
1149 new_pipe->update_flags.raw = 0;
1151 /* Exit on unchanged, unused pipe */
1152 if (!old_pipe->plane_state && !new_pipe->plane_state)
1154 /* Detect pipe enable/disable */
1155 if (!old_pipe->plane_state && new_pipe->plane_state) {
1156 new_pipe->update_flags.bits.enable = 1;
1157 new_pipe->update_flags.bits.mpcc = 1;
1158 new_pipe->update_flags.bits.dppclk = 1;
1159 new_pipe->update_flags.bits.hubp_interdependent = 1;
1160 new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1;
1161 new_pipe->update_flags.bits.gamut_remap = 1;
1162 new_pipe->update_flags.bits.scaler = 1;
1163 new_pipe->update_flags.bits.viewport = 1;
1164 if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) {
1165 new_pipe->update_flags.bits.odm = 1;
1166 new_pipe->update_flags.bits.global_sync = 1;
1170 if (old_pipe->plane_state && !new_pipe->plane_state) {
1171 new_pipe->update_flags.bits.disable = 1;
1175 /* Detect top pipe only changes */
1176 if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) {
1177 /* Detect odm changes */
1178 if ((old_pipe->next_odm_pipe && new_pipe->next_odm_pipe
1179 && old_pipe->next_odm_pipe->pipe_idx != new_pipe->next_odm_pipe->pipe_idx)
1180 || (!old_pipe->next_odm_pipe && new_pipe->next_odm_pipe)
1181 || (old_pipe->next_odm_pipe && !new_pipe->next_odm_pipe)
1182 || old_pipe->stream_res.opp != new_pipe->stream_res.opp)
1183 new_pipe->update_flags.bits.odm = 1;
1185 /* Detect global sync changes */
1186 if (old_pipe->pipe_dlg_param.vready_offset != new_pipe->pipe_dlg_param.vready_offset
1187 || old_pipe->pipe_dlg_param.vstartup_start != new_pipe->pipe_dlg_param.vstartup_start
1188 || old_pipe->pipe_dlg_param.vupdate_offset != new_pipe->pipe_dlg_param.vupdate_offset
1189 || old_pipe->pipe_dlg_param.vupdate_width != new_pipe->pipe_dlg_param.vupdate_width)
1190 new_pipe->update_flags.bits.global_sync = 1;
1194 * Detect opp / tg change, only set on change, not on enable
1195 * Assume mpcc inst = pipe index, if not this code needs to be updated
1196 * since mpcc is what is affected by these. In fact all of our sequence
1197 * makes this assumption at the moment with how hubp reset is matched to
1198 * same index mpcc reset.
1200 if (old_pipe->stream_res.opp != new_pipe->stream_res.opp)
1201 new_pipe->update_flags.bits.opp_changed = 1;
1202 if (old_pipe->stream_res.tg != new_pipe->stream_res.tg)
1203 new_pipe->update_flags.bits.tg_changed = 1;
1205 /* Detect mpcc blending changes, only dpp inst and bot matter here */
1206 if (old_pipe->plane_res.dpp != new_pipe->plane_res.dpp
1207 || old_pipe->stream_res.opp != new_pipe->stream_res.opp
1208 || (!old_pipe->bottom_pipe && new_pipe->bottom_pipe)
1209 || (old_pipe->bottom_pipe && !new_pipe->bottom_pipe)
1210 || (old_pipe->bottom_pipe && new_pipe->bottom_pipe
1211 && old_pipe->bottom_pipe->plane_res.mpcc_inst
1212 != new_pipe->bottom_pipe->plane_res.mpcc_inst))
1213 new_pipe->update_flags.bits.mpcc = 1;
1215 /* Detect dppclk change */
1216 if (old_pipe->plane_res.bw.dppclk_khz != new_pipe->plane_res.bw.dppclk_khz)
1217 new_pipe->update_flags.bits.dppclk = 1;
1219 /* Check for scl update */
1220 if (memcmp(&old_pipe->plane_res.scl_data, &new_pipe->plane_res.scl_data, sizeof(struct scaler_data)))
1221 new_pipe->update_flags.bits.scaler = 1;
1222 /* Check for vp update */
1223 if (memcmp(&old_pipe->plane_res.scl_data.viewport, &new_pipe->plane_res.scl_data.viewport, sizeof(struct rect))
1224 || memcmp(&old_pipe->plane_res.scl_data.viewport_c,
1225 &new_pipe->plane_res.scl_data.viewport_c, sizeof(struct rect)))
1226 new_pipe->update_flags.bits.viewport = 1;
1228 /* Detect dlg/ttu/rq updates */
1230 struct _vcs_dpi_display_dlg_regs_st old_dlg_attr = old_pipe->dlg_regs;
1231 struct _vcs_dpi_display_ttu_regs_st old_ttu_attr = old_pipe->ttu_regs;
1232 struct _vcs_dpi_display_dlg_regs_st *new_dlg_attr = &new_pipe->dlg_regs;
1233 struct _vcs_dpi_display_ttu_regs_st *new_ttu_attr = &new_pipe->ttu_regs;
1235 /* Detect pipe interdependent updates */
1236 if (old_dlg_attr.dst_y_prefetch != new_dlg_attr->dst_y_prefetch ||
1237 old_dlg_attr.vratio_prefetch != new_dlg_attr->vratio_prefetch ||
1238 old_dlg_attr.vratio_prefetch_c != new_dlg_attr->vratio_prefetch_c ||
1239 old_dlg_attr.dst_y_per_vm_vblank != new_dlg_attr->dst_y_per_vm_vblank ||
1240 old_dlg_attr.dst_y_per_row_vblank != new_dlg_attr->dst_y_per_row_vblank ||
1241 old_dlg_attr.dst_y_per_vm_flip != new_dlg_attr->dst_y_per_vm_flip ||
1242 old_dlg_attr.dst_y_per_row_flip != new_dlg_attr->dst_y_per_row_flip ||
1243 old_dlg_attr.refcyc_per_meta_chunk_vblank_l != new_dlg_attr->refcyc_per_meta_chunk_vblank_l ||
1244 old_dlg_attr.refcyc_per_meta_chunk_vblank_c != new_dlg_attr->refcyc_per_meta_chunk_vblank_c ||
1245 old_dlg_attr.refcyc_per_meta_chunk_flip_l != new_dlg_attr->refcyc_per_meta_chunk_flip_l ||
1246 old_dlg_attr.refcyc_per_line_delivery_pre_l != new_dlg_attr->refcyc_per_line_delivery_pre_l ||
1247 old_dlg_attr.refcyc_per_line_delivery_pre_c != new_dlg_attr->refcyc_per_line_delivery_pre_c ||
1248 old_ttu_attr.refcyc_per_req_delivery_pre_l != new_ttu_attr->refcyc_per_req_delivery_pre_l ||
1249 old_ttu_attr.refcyc_per_req_delivery_pre_c != new_ttu_attr->refcyc_per_req_delivery_pre_c ||
1250 old_ttu_attr.refcyc_per_req_delivery_pre_cur0 != new_ttu_attr->refcyc_per_req_delivery_pre_cur0 ||
1251 old_ttu_attr.refcyc_per_req_delivery_pre_cur1 != new_ttu_attr->refcyc_per_req_delivery_pre_cur1 ||
1252 old_ttu_attr.min_ttu_vblank != new_ttu_attr->min_ttu_vblank ||
1253 old_ttu_attr.qos_level_flip != new_ttu_attr->qos_level_flip) {
1254 old_dlg_attr.dst_y_prefetch = new_dlg_attr->dst_y_prefetch;
1255 old_dlg_attr.vratio_prefetch = new_dlg_attr->vratio_prefetch;
1256 old_dlg_attr.vratio_prefetch_c = new_dlg_attr->vratio_prefetch_c;
1257 old_dlg_attr.dst_y_per_vm_vblank = new_dlg_attr->dst_y_per_vm_vblank;
1258 old_dlg_attr.dst_y_per_row_vblank = new_dlg_attr->dst_y_per_row_vblank;
1259 old_dlg_attr.dst_y_per_vm_flip = new_dlg_attr->dst_y_per_vm_flip;
1260 old_dlg_attr.dst_y_per_row_flip = new_dlg_attr->dst_y_per_row_flip;
1261 old_dlg_attr.refcyc_per_meta_chunk_vblank_l = new_dlg_attr->refcyc_per_meta_chunk_vblank_l;
1262 old_dlg_attr.refcyc_per_meta_chunk_vblank_c = new_dlg_attr->refcyc_per_meta_chunk_vblank_c;
1263 old_dlg_attr.refcyc_per_meta_chunk_flip_l = new_dlg_attr->refcyc_per_meta_chunk_flip_l;
1264 old_dlg_attr.refcyc_per_line_delivery_pre_l = new_dlg_attr->refcyc_per_line_delivery_pre_l;
1265 old_dlg_attr.refcyc_per_line_delivery_pre_c = new_dlg_attr->refcyc_per_line_delivery_pre_c;
1266 old_ttu_attr.refcyc_per_req_delivery_pre_l = new_ttu_attr->refcyc_per_req_delivery_pre_l;
1267 old_ttu_attr.refcyc_per_req_delivery_pre_c = new_ttu_attr->refcyc_per_req_delivery_pre_c;
1268 old_ttu_attr.refcyc_per_req_delivery_pre_cur0 = new_ttu_attr->refcyc_per_req_delivery_pre_cur0;
1269 old_ttu_attr.refcyc_per_req_delivery_pre_cur1 = new_ttu_attr->refcyc_per_req_delivery_pre_cur1;
1270 old_ttu_attr.min_ttu_vblank = new_ttu_attr->min_ttu_vblank;
1271 old_ttu_attr.qos_level_flip = new_ttu_attr->qos_level_flip;
1272 new_pipe->update_flags.bits.hubp_interdependent = 1;
1274 /* Detect any other updates to ttu/rq/dlg */
1275 if (memcmp(&old_dlg_attr, &new_pipe->dlg_regs, sizeof(old_dlg_attr)) ||
1276 memcmp(&old_ttu_attr, &new_pipe->ttu_regs, sizeof(old_ttu_attr)) ||
1277 memcmp(&old_pipe->rq_regs, &new_pipe->rq_regs, sizeof(old_pipe->rq_regs)))
1278 new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1;
1282 static void dcn20_update_dchubp_dpp(
1284 struct pipe_ctx *pipe_ctx,
1285 struct dc_state *context)
1287 struct dce_hwseq *hws = dc->hwseq;
1288 struct hubp *hubp = pipe_ctx->plane_res.hubp;
1289 struct dpp *dpp = pipe_ctx->plane_res.dpp;
1290 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1291 bool viewport_changed = false;
1293 if (pipe_ctx->update_flags.bits.dppclk)
1294 dpp->funcs->dpp_dppclk_control(dpp, false, true);
1296 /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG
1297 * VTG is within DCHUBBUB which is commond block share by each pipe HUBP.
1298 * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG
1300 if (pipe_ctx->update_flags.bits.hubp_rq_dlg_ttu) {
1301 hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst);
1303 hubp->funcs->hubp_setup(
1305 &pipe_ctx->dlg_regs,
1306 &pipe_ctx->ttu_regs,
1308 &pipe_ctx->pipe_dlg_param);
1310 if (pipe_ctx->update_flags.bits.hubp_interdependent)
1311 hubp->funcs->hubp_setup_interdependent(
1313 &pipe_ctx->dlg_regs,
1314 &pipe_ctx->ttu_regs);
1316 if (pipe_ctx->update_flags.bits.enable ||
1317 plane_state->update_flags.bits.bpp_change ||
1318 plane_state->update_flags.bits.input_csc_change ||
1319 plane_state->update_flags.bits.color_space_change ||
1320 plane_state->update_flags.bits.coeff_reduction_change) {
1321 struct dc_bias_and_scale bns_params = {0};
1323 // program the input csc
1324 dpp->funcs->dpp_setup(dpp,
1325 plane_state->format,
1326 EXPANSION_MODE_ZERO,
1327 plane_state->input_csc_color_matrix,
1328 plane_state->color_space,
1331 if (dpp->funcs->dpp_program_bias_and_scale) {
1332 //TODO :for CNVC set scale and bias registers if necessary
1333 build_prescale_params(&bns_params, plane_state);
1334 dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
1338 if (pipe_ctx->update_flags.bits.mpcc
1339 || plane_state->update_flags.bits.global_alpha_change
1340 || plane_state->update_flags.bits.per_pixel_alpha_change) {
1341 // MPCC inst is equal to pipe index in practice
1342 int mpcc_inst = hubp->inst;
1344 int opp_count = dc->res_pool->pipe_count;
1346 for (opp_inst = 0; opp_inst < opp_count; opp_inst++) {
1347 if (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst]) {
1348 dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst);
1349 dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false;
1353 hws->funcs.update_mpcc(dc, pipe_ctx);
1356 if (pipe_ctx->update_flags.bits.scaler ||
1357 plane_state->update_flags.bits.scaling_change ||
1358 plane_state->update_flags.bits.position_change ||
1359 plane_state->update_flags.bits.per_pixel_alpha_change ||
1360 pipe_ctx->stream->update_flags.bits.scaling) {
1361 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->plane_state->per_pixel_alpha;
1362 ASSERT(pipe_ctx->plane_res.scl_data.lb_params.depth == LB_PIXEL_DEPTH_30BPP);
1363 /* scaler configuration */
1364 pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(
1365 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);
1368 if (pipe_ctx->update_flags.bits.viewport ||
1369 (context == dc->current_state && plane_state->update_flags.bits.scaling_change) ||
1370 (context == dc->current_state && pipe_ctx->stream->update_flags.bits.scaling)) {
1372 hubp->funcs->mem_program_viewport(
1374 &pipe_ctx->plane_res.scl_data.viewport,
1375 &pipe_ctx->plane_res.scl_data.viewport_c);
1376 viewport_changed = true;
1379 /* Any updates are handled in dc interface, just need to apply existing for plane enable */
1380 if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed ||
1381 pipe_ctx->update_flags.bits.scaler || pipe_ctx->update_flags.bits.viewport)
1382 && pipe_ctx->stream->cursor_attributes.address.quad_part != 0) {
1383 dc->hwss.set_cursor_position(pipe_ctx);
1384 dc->hwss.set_cursor_attribute(pipe_ctx);
1386 if (dc->hwss.set_cursor_sdr_white_level)
1387 dc->hwss.set_cursor_sdr_white_level(pipe_ctx);
1390 /* Any updates are handled in dc interface, just need
1391 * to apply existing for plane enable / opp change */
1392 if (pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed
1393 || pipe_ctx->stream->update_flags.bits.gamut_remap
1394 || pipe_ctx->stream->update_flags.bits.out_csc) {
1395 /* dpp/cm gamut remap*/
1396 dc->hwss.program_gamut_remap(pipe_ctx);
1398 /*call the dcn2 method which uses mpc csc*/
1399 dc->hwss.program_output_csc(dc,
1401 pipe_ctx->stream->output_color_space,
1402 pipe_ctx->stream->csc_color_matrix.matrix,
1406 if (pipe_ctx->update_flags.bits.enable ||
1407 pipe_ctx->update_flags.bits.opp_changed ||
1408 plane_state->update_flags.bits.pixel_format_change ||
1409 plane_state->update_flags.bits.horizontal_mirror_change ||
1410 plane_state->update_flags.bits.rotation_change ||
1411 plane_state->update_flags.bits.swizzle_change ||
1412 plane_state->update_flags.bits.dcc_change ||
1413 plane_state->update_flags.bits.bpp_change ||
1414 plane_state->update_flags.bits.scaling_change ||
1415 plane_state->update_flags.bits.plane_size_change) {
1416 struct plane_size size = plane_state->plane_size;
1418 size.surface_size = pipe_ctx->plane_res.scl_data.viewport;
1419 hubp->funcs->hubp_program_surface_config(
1421 plane_state->format,
1422 &plane_state->tiling_info,
1424 plane_state->rotation,
1426 plane_state->horizontal_mirror,
1428 hubp->power_gated = false;
1431 if (hubp->funcs->apply_PLAT_54186_wa && viewport_changed)
1432 hubp->funcs->apply_PLAT_54186_wa(hubp, &plane_state->address);
1434 if (pipe_ctx->update_flags.bits.enable || plane_state->update_flags.bits.addr_update)
1435 hws->funcs.update_plane_addr(dc, pipe_ctx);
1439 if (pipe_ctx->update_flags.bits.enable)
1440 hubp->funcs->set_blank(hubp, false);
1444 static void dcn20_program_pipe(
1446 struct pipe_ctx *pipe_ctx,
1447 struct dc_state *context)
1449 struct dce_hwseq *hws = dc->hwseq;
1450 /* Only need to unblank on top pipe */
1451 if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.abm_level)
1452 && !pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe)
1453 hws->funcs.blank_pixel_data(dc, pipe_ctx, !pipe_ctx->plane_state->visible);
1455 if (pipe_ctx->update_flags.bits.global_sync) {
1456 pipe_ctx->stream_res.tg->funcs->program_global_sync(
1457 pipe_ctx->stream_res.tg,
1458 pipe_ctx->pipe_dlg_param.vready_offset,
1459 pipe_ctx->pipe_dlg_param.vstartup_start,
1460 pipe_ctx->pipe_dlg_param.vupdate_offset,
1461 pipe_ctx->pipe_dlg_param.vupdate_width);
1463 pipe_ctx->stream_res.tg->funcs->set_vtg_params(
1464 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
1466 if (hws->funcs.setup_vupdate_interrupt)
1467 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
1470 if (pipe_ctx->update_flags.bits.odm)
1471 hws->funcs.update_odm(dc, context, pipe_ctx);
1473 if (pipe_ctx->update_flags.bits.enable)
1474 dcn20_enable_plane(dc, pipe_ctx, context);
1476 if (pipe_ctx->update_flags.raw || pipe_ctx->plane_state->update_flags.raw || pipe_ctx->stream->update_flags.raw)
1477 dcn20_update_dchubp_dpp(dc, pipe_ctx, context);
1479 if (pipe_ctx->update_flags.bits.enable
1480 || pipe_ctx->plane_state->update_flags.bits.hdr_mult)
1481 hws->funcs.set_hdr_multiplier(pipe_ctx);
1483 if (pipe_ctx->update_flags.bits.enable ||
1484 pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
1485 pipe_ctx->plane_state->update_flags.bits.gamma_change)
1486 hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);
1488 /* dcn10_translate_regamma_to_hw_format takes 750us to finish
1489 * only do gamma programming for powering on, internal memcmp to avoid
1490 * updating on slave planes
1492 if (pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.out_tf)
1493 hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
1495 /* If the pipe has been enabled or has a different opp, we
1496 * should reprogram the fmt. This deals with cases where
1497 * interation between mpc and odm combine on different streams
1498 * causes a different pipe to be chosen to odm combine with.
1500 if (pipe_ctx->update_flags.bits.enable
1501 || pipe_ctx->update_flags.bits.opp_changed) {
1503 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
1504 pipe_ctx->stream_res.opp,
1505 COLOR_SPACE_YCBCR601,
1506 pipe_ctx->stream->timing.display_color_depth,
1507 pipe_ctx->stream->signal);
1509 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
1510 pipe_ctx->stream_res.opp,
1511 &pipe_ctx->stream->bit_depth_params,
1512 &pipe_ctx->stream->clamping);
1516 void dcn20_program_front_end_for_ctx(
1518 struct dc_state *context)
1521 struct dce_hwseq *hws = dc->hwseq;
1522 DC_LOGGER_INIT(dc->ctx->logger);
1524 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1525 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1527 if (!pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe && pipe_ctx->plane_state) {
1528 ASSERT(!pipe_ctx->plane_state->triplebuffer_flips);
1529 if (dc->hwss.program_triplebuffer != NULL &&
1530 !dc->debug.disable_tri_buf) {
1531 /*turn off triple buffer for full update*/
1532 dc->hwss.program_triplebuffer(
1533 dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);
1538 /* Set pipe update flags and lock pipes */
1539 for (i = 0; i < dc->res_pool->pipe_count; i++)
1540 dcn20_detect_pipe_changes(&dc->current_state->res_ctx.pipe_ctx[i],
1541 &context->res_ctx.pipe_ctx[i]);
1543 /* OTG blank before disabling all front ends */
1544 for (i = 0; i < dc->res_pool->pipe_count; i++)
1545 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable
1546 && !context->res_ctx.pipe_ctx[i].top_pipe
1547 && !context->res_ctx.pipe_ctx[i].prev_odm_pipe
1548 && context->res_ctx.pipe_ctx[i].stream)
1549 hws->funcs.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true);
1551 /* Disconnect mpcc */
1552 for (i = 0; i < dc->res_pool->pipe_count; i++)
1553 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable
1554 || context->res_ctx.pipe_ctx[i].update_flags.bits.opp_changed) {
1555 hws->funcs.plane_atomic_disconnect(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
1556 DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx);
1560 * Program all updated pipes, order matters for mpcc setup. Start with
1561 * top pipe and program all pipes that follow in order
1563 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1564 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1566 if (pipe->plane_state && !pipe->top_pipe) {
1568 dcn20_program_pipe(dc, pipe, context);
1569 pipe = pipe->bottom_pipe;
1571 /* Program secondary blending tree and writeback pipes */
1572 pipe = &context->res_ctx.pipe_ctx[i];
1573 if (!pipe->prev_odm_pipe && pipe->stream->num_wb_info > 0
1574 && (pipe->update_flags.raw || pipe->plane_state->update_flags.raw || pipe->stream->update_flags.raw)
1575 && hws->funcs.program_all_writeback_pipes_in_tree)
1576 hws->funcs.program_all_writeback_pipes_in_tree(dc, pipe->stream, context);
1581 void dcn20_post_unlock_program_front_end(
1583 struct dc_state *context)
1586 const unsigned int TIMEOUT_FOR_PIPE_ENABLE_MS = 100;
1587 struct dce_hwseq *hwseq = dc->hwseq;
1589 DC_LOGGER_INIT(dc->ctx->logger);
1591 for (i = 0; i < dc->res_pool->pipe_count; i++)
1592 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable)
1593 dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
1596 * If we are enabling a pipe, we need to wait for pending clear as this is a critical
1597 * part of the enable operation otherwise, DM may request an immediate flip which
1598 * will cause HW to perform an "immediate enable" (as opposed to "vsync enable") which
1599 * is unsupported on DCN.
1601 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1602 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1604 if (pipe->plane_state && !pipe->top_pipe && pipe->update_flags.bits.enable) {
1605 struct hubp *hubp = pipe->plane_res.hubp;
1608 for (j = 0; j < TIMEOUT_FOR_PIPE_ENABLE_MS*1000
1609 && hubp->funcs->hubp_is_flip_pending(hubp); j++)
1614 /* WA to apply WM setting*/
1615 if (hwseq->wa.DEGVIDCN21)
1616 dc->res_pool->hubbub->funcs->apply_DEDCN21_147_wa(dc->res_pool->hubbub);
1619 /* WA for stutter underflow during MPO transitions when adding 2nd plane */
1620 if (hwseq->wa.disallow_self_refresh_during_multi_plane_transition) {
1622 if (dc->current_state->stream_status[0].plane_count == 1 &&
1623 context->stream_status[0].plane_count > 1) {
1625 struct timing_generator *tg = dc->res_pool->timing_generators[0];
1627 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, false);
1629 hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied = true;
1630 hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied_on_frame = tg->funcs->get_frame_count(tg);
1635 void dcn20_prepare_bandwidth(
1637 struct dc_state *context)
1639 struct hubbub *hubbub = dc->res_pool->hubbub;
1641 dc->clk_mgr->funcs->update_clocks(
1646 /* program dchubbub watermarks */
1647 dc->wm_optimized_required = hubbub->funcs->program_watermarks(hubbub,
1648 &context->bw_ctx.bw.dcn.watermarks,
1649 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
1653 void dcn20_optimize_bandwidth(
1655 struct dc_state *context)
1657 struct hubbub *hubbub = dc->res_pool->hubbub;
1659 if (dc->wm_optimized_required || IS_DIAG_DC(dc->ctx->dce_environment)) {
1660 /* program dchubbub watermarks */
1661 hubbub->funcs->program_watermarks(hubbub,
1662 &context->bw_ctx.bw.dcn.watermarks,
1663 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
1665 dc->wm_optimized_required = false;
1668 if (dc->clk_optimized_required || IS_DIAG_DC(dc->ctx->dce_environment)) {
1669 dc->clk_mgr->funcs->update_clocks(
1673 dc->wm_optimized_required = false;
1677 bool dcn20_update_bandwidth(
1679 struct dc_state *context)
1682 struct dce_hwseq *hws = dc->hwseq;
1684 /* recalculate DML parameters */
1685 if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false))
1688 /* apply updated bandwidth parameters */
1689 dc->hwss.prepare_bandwidth(dc, context);
1691 /* update hubp configs for all pipes */
1692 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1693 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1695 if (pipe_ctx->plane_state == NULL)
1698 if (pipe_ctx->top_pipe == NULL) {
1699 bool blank = !is_pipe_tree_visible(pipe_ctx);
1701 pipe_ctx->stream_res.tg->funcs->program_global_sync(
1702 pipe_ctx->stream_res.tg,
1703 pipe_ctx->pipe_dlg_param.vready_offset,
1704 pipe_ctx->pipe_dlg_param.vstartup_start,
1705 pipe_ctx->pipe_dlg_param.vupdate_offset,
1706 pipe_ctx->pipe_dlg_param.vupdate_width);
1708 pipe_ctx->stream_res.tg->funcs->set_vtg_params(
1709 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
1711 if (pipe_ctx->prev_odm_pipe == NULL)
1712 hws->funcs.blank_pixel_data(dc, pipe_ctx, blank);
1714 if (hws->funcs.setup_vupdate_interrupt)
1715 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
1718 pipe_ctx->plane_res.hubp->funcs->hubp_setup(
1719 pipe_ctx->plane_res.hubp,
1720 &pipe_ctx->dlg_regs,
1721 &pipe_ctx->ttu_regs,
1723 &pipe_ctx->pipe_dlg_param);
1729 void dcn20_enable_writeback(
1731 struct dc_writeback_info *wb_info,
1732 struct dc_state *context)
1735 struct mcif_wb *mcif_wb;
1736 struct timing_generator *optc;
1738 ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES);
1739 ASSERT(wb_info->wb_enabled);
1740 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
1741 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];
1743 /* set the OPTC source mux */
1744 optc = dc->res_pool->timing_generators[dwb->otg_inst];
1745 optc->funcs->set_dwb_source(optc, wb_info->dwb_pipe_inst);
1746 /* set MCIF_WB buffer and arbitration configuration */
1747 mcif_wb->funcs->config_mcif_buf(mcif_wb, &wb_info->mcif_buf_params, wb_info->dwb_params.dest_height);
1748 mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]);
1749 /* Enable MCIF_WB */
1750 mcif_wb->funcs->enable_mcif(mcif_wb);
1752 dwb->funcs->enable(dwb, &wb_info->dwb_params);
1753 /* TODO: add sequence to enable/disable warmup */
1756 void dcn20_disable_writeback(
1758 unsigned int dwb_pipe_inst)
1761 struct mcif_wb *mcif_wb;
1763 ASSERT(dwb_pipe_inst < MAX_DWB_PIPES);
1764 dwb = dc->res_pool->dwbc[dwb_pipe_inst];
1765 mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst];
1767 dwb->funcs->disable(dwb);
1768 mcif_wb->funcs->disable_mcif(mcif_wb);
1771 bool dcn20_wait_for_blank_complete(
1772 struct output_pixel_processor *opp)
1776 for (counter = 0; counter < 1000; counter++) {
1777 if (opp->funcs->dpg_is_blanked(opp))
1783 if (counter == 1000) {
1784 dm_error("DC: failed to blank crtc!\n");
1791 bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx)
1793 struct hubp *hubp = pipe_ctx->plane_res.hubp;
1797 return hubp->funcs->dmdata_status_done(hubp);
1800 void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)
1802 struct dce_hwseq *hws = dc->hwseq;
1804 if (pipe_ctx->stream_res.dsc) {
1805 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
1807 dcn20_dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, true);
1809 dcn20_dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, true);
1810 odm_pipe = odm_pipe->next_odm_pipe;
1815 void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)
1817 struct dce_hwseq *hws = dc->hwseq;
1819 if (pipe_ctx->stream_res.dsc) {
1820 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
1822 dcn20_dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, false);
1824 dcn20_dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, false);
1825 odm_pipe = odm_pipe->next_odm_pipe;
1830 void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx)
1832 struct dc_dmdata_attributes attr = { 0 };
1833 struct hubp *hubp = pipe_ctx->plane_res.hubp;
1835 attr.dmdata_mode = DMDATA_HW_MODE;
1837 dc_is_hdmi_signal(pipe_ctx->stream->signal) ? 32 : 36;
1838 attr.address.quad_part =
1839 pipe_ctx->stream->dmdata_address.quad_part;
1840 attr.dmdata_dl_delta = 0;
1841 attr.dmdata_qos_mode = 0;
1842 attr.dmdata_qos_level = 0;
1843 attr.dmdata_repeat = 1; /* always repeat */
1844 attr.dmdata_updated = 1;
1845 attr.dmdata_sw_data = NULL;
1847 hubp->funcs->dmdata_set_attributes(hubp, &attr);
1850 void dcn20_init_vm_ctx(
1851 struct dce_hwseq *hws,
1853 struct dc_virtual_addr_space_config *va_config,
1856 struct dcn_hubbub_virt_addr_config config;
1859 ASSERT(0); /* VMID cannot be 0 for vm context */
1863 config.page_table_start_addr = va_config->page_table_start_addr;
1864 config.page_table_end_addr = va_config->page_table_end_addr;
1865 config.page_table_block_size = va_config->page_table_block_size_in_bytes;
1866 config.page_table_depth = va_config->page_table_depth;
1867 config.page_table_base_addr = va_config->page_table_base_addr;
1869 dc->res_pool->hubbub->funcs->init_vm_ctx(dc->res_pool->hubbub, &config, vmid);
1872 int dcn20_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)
1874 struct dcn_hubbub_phys_addr_config config;
1876 config.system_aperture.fb_top = pa_config->system_aperture.fb_top;
1877 config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset;
1878 config.system_aperture.fb_base = pa_config->system_aperture.fb_base;
1879 config.system_aperture.agp_top = pa_config->system_aperture.agp_top;
1880 config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot;
1881 config.system_aperture.agp_base = pa_config->system_aperture.agp_base;
1882 config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr;
1883 config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr;
1884 config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr;
1885 config.page_table_default_page_addr = pa_config->page_table_default_page_addr;
1887 return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config);
1890 static bool patch_address_for_sbs_tb_stereo(
1891 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr)
1893 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1894 bool sec_split = pipe_ctx->top_pipe &&
1895 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
1896 if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
1897 (pipe_ctx->stream->timing.timing_3d_format ==
1898 TIMING_3D_FORMAT_SIDE_BY_SIDE ||
1899 pipe_ctx->stream->timing.timing_3d_format ==
1900 TIMING_3D_FORMAT_TOP_AND_BOTTOM)) {
1901 *addr = plane_state->address.grph_stereo.left_addr;
1902 plane_state->address.grph_stereo.left_addr =
1903 plane_state->address.grph_stereo.right_addr;
1907 if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE &&
1908 plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) {
1909 plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO;
1910 plane_state->address.grph_stereo.right_addr =
1911 plane_state->address.grph_stereo.left_addr;
1916 void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)
1918 bool addr_patched = false;
1919 PHYSICAL_ADDRESS_LOC addr;
1920 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1922 if (plane_state == NULL)
1925 addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);
1927 // Call Helper to track VMID use
1928 vm_helper_mark_vmid_used(dc->vm_helper, plane_state->address.vmid, pipe_ctx->plane_res.hubp->inst);
1930 pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(
1931 pipe_ctx->plane_res.hubp,
1932 &plane_state->address,
1933 plane_state->flip_immediate);
1935 plane_state->status.requested_address = plane_state->address;
1937 if (plane_state->flip_immediate)
1938 plane_state->status.current_address = plane_state->address;
1941 pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;
1944 void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx,
1945 struct dc_link_settings *link_settings)
1947 struct encoder_unblank_param params = { { 0 } };
1948 struct dc_stream_state *stream = pipe_ctx->stream;
1949 struct dc_link *link = stream->link;
1950 struct dce_hwseq *hws = link->dc->hwseq;
1951 struct pipe_ctx *odm_pipe;
1954 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
1957 /* only 3 items below are used by unblank */
1958 params.timing = pipe_ctx->stream->timing;
1960 params.link_settings.link_rate = link_settings->link_rate;
1962 if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
1963 if (optc2_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1)
1964 params.timing.pix_clk_100hz /= 2;
1965 pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine(
1966 pipe_ctx->stream_res.stream_enc, params.opp_cnt > 1);
1967 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, ¶ms);
1970 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1971 hws->funcs.edp_backlight_control(link, true);
1975 void dcn20_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx)
1977 struct timing_generator *tg = pipe_ctx->stream_res.tg;
1978 int start_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);
1983 if (tg->funcs->setup_vertical_interrupt2)
1984 tg->funcs->setup_vertical_interrupt2(tg, start_line);
1987 static void dcn20_reset_back_end_for_pipe(
1989 struct pipe_ctx *pipe_ctx,
1990 struct dc_state *context)
1993 struct dc_link *link;
1994 DC_LOGGER_INIT(dc->ctx->logger);
1995 if (pipe_ctx->stream_res.stream_enc == NULL) {
1996 pipe_ctx->stream = NULL;
2000 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
2001 link = pipe_ctx->stream->link;
2002 /* DPMS may already disable or */
2003 /* dpms_off status is incorrect due to fastboot
2004 * feature. When system resume from S4 with second
2005 * screen only, the dpms_off would be true but
2006 * VBIOS lit up eDP, so check link status too.
2008 if (!pipe_ctx->stream->dpms_off || link->link_status.link_active)
2009 core_link_disable_stream(pipe_ctx);
2010 else if (pipe_ctx->stream_res.audio)
2011 dc->hwss.disable_audio_stream(pipe_ctx);
2013 /* free acquired resources */
2014 if (pipe_ctx->stream_res.audio) {
2015 /*disable az_endpoint*/
2016 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
2019 if (dc->caps.dynamic_audio == true) {
2020 /*we have to dynamic arbitrate the audio endpoints*/
2021 /*we free the resource, need reset is_audio_acquired*/
2022 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
2023 pipe_ctx->stream_res.audio, false);
2024 pipe_ctx->stream_res.audio = NULL;
2028 else if (pipe_ctx->stream_res.dsc) {
2029 dp_set_dsc_enable(pipe_ctx, false);
2032 /* by upper caller loop, parent pipe: pipe0, will be reset last.
2033 * back end share by all pipes and will be disable only when disable
2036 if (pipe_ctx->top_pipe == NULL) {
2038 if (pipe_ctx->stream_res.abm)
2039 pipe_ctx->stream_res.abm->funcs->set_abm_immediate_disable(pipe_ctx->stream_res.abm);
2041 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
2043 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
2044 if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass)
2045 pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
2046 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
2048 if (pipe_ctx->stream_res.tg->funcs->set_drr)
2049 pipe_ctx->stream_res.tg->funcs->set_drr(
2050 pipe_ctx->stream_res.tg, NULL);
2053 for (i = 0; i < dc->res_pool->pipe_count; i++)
2054 if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx)
2057 if (i == dc->res_pool->pipe_count)
2060 pipe_ctx->stream = NULL;
2061 DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n",
2062 pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
2065 void dcn20_reset_hw_ctx_wrap(
2067 struct dc_state *context)
2070 struct dce_hwseq *hws = dc->hwseq;
2073 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
2074 struct pipe_ctx *pipe_ctx_old =
2075 &dc->current_state->res_ctx.pipe_ctx[i];
2076 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2078 if (!pipe_ctx_old->stream)
2081 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe)
2084 if (!pipe_ctx->stream ||
2085 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
2086 struct clock_source *old_clk = pipe_ctx_old->clock_source;
2088 dcn20_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
2089 if (hws->funcs.enable_stream_gating)
2090 hws->funcs.enable_stream_gating(dc, pipe_ctx);
2092 old_clk->funcs->cs_power_down(old_clk);
2097 void dcn20_get_mpctree_visual_confirm_color(
2098 struct pipe_ctx *pipe_ctx,
2099 struct tg_color *color)
2101 const struct tg_color pipe_colors[6] = {
2102 {MAX_TG_COLOR_VALUE, 0, 0}, // red
2103 {MAX_TG_COLOR_VALUE, 0, MAX_TG_COLOR_VALUE}, // yellow
2104 {0, MAX_TG_COLOR_VALUE, 0}, // blue
2105 {MAX_TG_COLOR_VALUE / 2, 0, MAX_TG_COLOR_VALUE / 2}, // purple
2106 {0, 0, MAX_TG_COLOR_VALUE}, // green
2107 {MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE * 2 / 3, 0}, // orange
2110 struct pipe_ctx *top_pipe = pipe_ctx;
2112 while (top_pipe->top_pipe) {
2113 top_pipe = top_pipe->top_pipe;
2116 *color = pipe_colors[top_pipe->pipe_idx];
2119 void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
2121 struct dce_hwseq *hws = dc->hwseq;
2122 struct hubp *hubp = pipe_ctx->plane_res.hubp;
2123 struct mpcc_blnd_cfg blnd_cfg = { {0} };
2124 bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha;
2126 struct mpcc *new_mpcc;
2127 struct mpc *mpc = dc->res_pool->mpc;
2128 struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);
2130 // input to MPCC is always RGB, by default leave black_color at 0
2131 if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) {
2132 hws->funcs.get_hdr_visual_confirm_color(
2133 pipe_ctx, &blnd_cfg.black_color);
2134 } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) {
2135 hws->funcs.get_surface_visual_confirm_color(
2136 pipe_ctx, &blnd_cfg.black_color);
2137 } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE) {
2138 dcn20_get_mpctree_visual_confirm_color(
2139 pipe_ctx, &blnd_cfg.black_color);
2142 if (per_pixel_alpha)
2143 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;
2145 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA;
2147 blnd_cfg.overlap_only = false;
2148 blnd_cfg.global_gain = 0xff;
2150 if (pipe_ctx->plane_state->global_alpha)
2151 blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value;
2153 blnd_cfg.global_alpha = 0xff;
2155 blnd_cfg.background_color_bpc = 4;
2156 blnd_cfg.bottom_gain_mode = 0;
2157 blnd_cfg.top_gain = 0x1f000;
2158 blnd_cfg.bottom_inside_gain = 0x1f000;
2159 blnd_cfg.bottom_outside_gain = 0x1f000;
2160 blnd_cfg.pre_multiplied_alpha = per_pixel_alpha;
2164 * Note: currently there is a bug in init_hw such that
2165 * on resume from hibernate, BIOS sets up MPCC0, and
2166 * we do mpcc_remove but the mpcc cannot go to idle
2167 * after remove. This cause us to pick mpcc1 here,
2168 * which causes a pstate hang for yet unknown reason.
2170 mpcc_id = hubp->inst;
2172 /* check if this MPCC is already being used */
2173 new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id);
2174 /* remove MPCC if being used */
2175 if (new_mpcc != NULL)
2176 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc);
2178 if (dc->debug.sanity_checks)
2179 mpc->funcs->assert_mpcc_idle_before_connect(
2180 dc->res_pool->mpc, mpcc_id);
2182 /* Call MPC to insert new plane */
2183 new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,
2191 ASSERT(new_mpcc != NULL);
2192 hubp->opp_id = pipe_ctx->stream_res.opp->inst;
2193 hubp->mpcc_id = mpcc_id;
2196 void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)
2198 enum dc_lane_count lane_count =
2199 pipe_ctx->stream->link->cur_link_settings.lane_count;
2201 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
2202 struct dc_link *link = pipe_ctx->stream->link;
2204 uint32_t active_total_with_borders;
2205 uint32_t early_control = 0;
2206 struct timing_generator *tg = pipe_ctx->stream_res.tg;
2208 /* For MST, there are multiply stream go to only one link.
2209 * connect DIG back_end to front_end while enable_stream and
2210 * disconnect them during disable_stream
2211 * BY this, it is logic clean to separate stream and link
2213 link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
2214 pipe_ctx->stream_res.stream_enc->id, true);
2216 if (pipe_ctx->plane_state && pipe_ctx->plane_state->flip_immediate != 1) {
2217 if (link->dc->hwss.program_dmdata_engine)
2218 link->dc->hwss.program_dmdata_engine(pipe_ctx);
2221 link->dc->hwss.update_info_frame(pipe_ctx);
2223 /* enable early control to avoid corruption on DP monitor*/
2224 active_total_with_borders =
2225 timing->h_addressable
2226 + timing->h_border_left
2227 + timing->h_border_right;
2229 if (lane_count != 0)
2230 early_control = active_total_with_borders % lane_count;
2232 if (early_control == 0)
2233 early_control = lane_count;
2235 tg->funcs->set_early_control(tg, early_control);
2237 /* enable audio only within mode set */
2238 if (pipe_ctx->stream_res.audio != NULL) {
2239 if (dc_is_dp_signal(pipe_ctx->stream->signal))
2240 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
2244 void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx)
2246 struct dc_stream_state *stream = pipe_ctx->stream;
2247 struct hubp *hubp = pipe_ctx->plane_res.hubp;
2248 bool enable = false;
2249 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;
2250 enum dynamic_metadata_mode mode = dc_is_dp_signal(stream->signal)
2254 /* if using dynamic meta, don't set up generic infopackets */
2255 if (pipe_ctx->stream->dmdata_address.quad_part != 0) {
2256 pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false;
2263 if (!stream_enc || !stream_enc->funcs->set_dynamic_metadata)
2266 stream_enc->funcs->set_dynamic_metadata(stream_enc, enable,
2270 void dcn20_fpga_init_hw(struct dc *dc)
2273 struct dce_hwseq *hws = dc->hwseq;
2274 struct resource_pool *res_pool = dc->res_pool;
2275 struct dc_state *context = dc->current_state;
2277 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
2278 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
2280 // Initialize the dccg
2281 if (res_pool->dccg->funcs->dccg_init)
2282 res_pool->dccg->funcs->dccg_init(res_pool->dccg);
2284 //Enable ability to power gate / don't force power on permanently
2285 hws->funcs.enable_power_gating_plane(hws, true);
2287 // Specific to FPGA dccg and registers
2288 REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF);
2289 REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF);
2291 hws->funcs.dccg_init(hws);
2293 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2);
2294 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
2295 REG_WRITE(REFCLK_CNTL, 0);
2299 /* Blank pixel data with OPP DPG */
2300 for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
2301 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2303 if (tg->funcs->is_tg_enabled(tg))
2304 dcn20_init_blank(dc, tg);
2307 for (i = 0; i < res_pool->timing_generator_count; i++) {
2308 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2310 if (tg->funcs->is_tg_enabled(tg))
2311 tg->funcs->lock(tg);
2314 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2315 struct dpp *dpp = res_pool->dpps[i];
2317 dpp->funcs->dpp_reset(dpp);
2320 /* Reset all MPCC muxes */
2321 res_pool->mpc->funcs->mpc_init(res_pool->mpc);
2323 /* initialize OPP mpc_tree parameter */
2324 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {
2325 res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst;
2326 res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
2327 for (j = 0; j < MAX_PIPES; j++)
2328 res_pool->opps[i]->mpcc_disconnect_pending[j] = false;
2331 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2332 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2333 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2334 struct hubp *hubp = dc->res_pool->hubps[i];
2335 struct dpp *dpp = dc->res_pool->dpps[i];
2337 pipe_ctx->stream_res.tg = tg;
2338 pipe_ctx->pipe_idx = i;
2340 pipe_ctx->plane_res.hubp = hubp;
2341 pipe_ctx->plane_res.dpp = dpp;
2342 pipe_ctx->plane_res.mpcc_inst = dpp->inst;
2343 hubp->mpcc_id = dpp->inst;
2344 hubp->opp_id = OPP_ID_INVALID;
2345 hubp->power_gated = false;
2346 pipe_ctx->stream_res.opp = NULL;
2348 hubp->funcs->hubp_init(hubp);
2350 //dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
2351 //dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
2352 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
2353 pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
2355 hws->funcs.plane_atomic_disconnect(dc, pipe_ctx);
2358 /* initialize DWB pointer to MCIF_WB */
2359 for (i = 0; i < res_pool->res_cap->num_dwb; i++)
2360 res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i];
2362 for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
2363 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2365 if (tg->funcs->is_tg_enabled(tg))
2366 tg->funcs->unlock(tg);
2369 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2370 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2372 dc->hwss.disable_plane(dc, pipe_ctx);
2374 pipe_ctx->stream_res.tg = NULL;
2375 pipe_ctx->plane_res.hubp = NULL;
2378 for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
2379 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2381 tg->funcs->tg_init(tg);