2 * Copyright 2012-17 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #ifndef __DC_MEM_INPUT_DCN20_H__
27 #define __DC_MEM_INPUT_DCN20_H__
29 #include "../dcn10/dcn10_hubp.h"
31 #define TO_DCN20_HUBP(hubp)\
32 container_of(hubp, struct dcn20_hubp, base)
34 #define HUBP_REG_LIST_DCN2_COMMON(id)\
35 HUBP_REG_LIST_DCN(id),\
36 HUBP_REG_LIST_DCN_VM(id),\
37 SRI(PREFETCH_SETTINGS, HUBPREQ, id),\
38 SRI(PREFETCH_SETTINGS_C, HUBPREQ, id),\
39 SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, HUBPREQ, id),\
40 SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, HUBPREQ, id),\
41 SR(DCN_VM_FB_LOCATION_TOP),\
42 SR(DCN_VM_FB_LOCATION_BASE),\
43 SR(DCN_VM_FB_OFFSET),\
47 SRI(CURSOR_SETTINGS, HUBPREQ, id), \
48 SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR0_, id), \
49 SRI(CURSOR_SURFACE_ADDRESS, CURSOR0_, id), \
50 SRI(CURSOR_SIZE, CURSOR0_, id), \
51 SRI(CURSOR_CONTROL, CURSOR0_, id), \
52 SRI(CURSOR_POSITION, CURSOR0_, id), \
53 SRI(CURSOR_HOT_SPOT, CURSOR0_, id), \
54 SRI(CURSOR_DST_OFFSET, CURSOR0_, id), \
55 SRI(DMDATA_ADDRESS_HIGH, CURSOR0_, id), \
56 SRI(DMDATA_ADDRESS_LOW, CURSOR0_, id), \
57 SRI(DMDATA_CNTL, CURSOR0_, id), \
58 SRI(DMDATA_SW_CNTL, CURSOR0_, id), \
59 SRI(DMDATA_QOS_CNTL, CURSOR0_, id), \
60 SRI(DMDATA_SW_DATA, CURSOR0_, id), \
61 SRI(DMDATA_STATUS, CURSOR0_, id),\
62 SRI(FLIP_PARAMETERS_0, HUBPREQ, id),\
63 SRI(FLIP_PARAMETERS_1, HUBPREQ, id),\
64 SRI(FLIP_PARAMETERS_2, HUBPREQ, id),\
65 SRI(DCN_CUR1_TTU_CNTL1, HUBPREQ, id),\
66 SRI(DCSURF_FLIP_CONTROL2, HUBPREQ, id), \
67 SRI(VMID_SETTINGS_0, HUBPREQ, id)
69 #define HUBP_REG_LIST_DCN20(id)\
70 HUBP_REG_LIST_DCN2_COMMON(id),\
71 SR(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),\
72 SR(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB)
74 #define HUBP_MASK_SH_LIST_DCN2_COMMON(mask_sh)\
75 HUBP_MASK_SH_LIST_DCN(mask_sh),\
76 HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\
77 HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ROTATION_ANGLE, mask_sh),\
78 HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, H_MIRROR_EN, mask_sh),\
79 HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, DST_Y_PREFETCH, mask_sh),\
80 HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, VRATIO_PREFETCH, mask_sh),\
81 HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS_C, VRATIO_PREFETCH_C, mask_sh),\
82 HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR, MC_VM_SYSTEM_APERTURE_LOW_ADDR, mask_sh),\
83 HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mask_sh),\
84 HUBP_SF(DCN_VM_FB_LOCATION_TOP, FB_TOP, mask_sh),\
85 HUBP_SF(DCN_VM_FB_LOCATION_BASE, FB_BASE, mask_sh),\
86 HUBP_SF(DCN_VM_FB_OFFSET, FB_OFFSET, mask_sh),\
87 HUBP_SF(DCN_VM_AGP_BASE, AGP_BASE, mask_sh),\
88 HUBP_SF(DCN_VM_AGP_BOT, AGP_BOT, mask_sh),\
89 HUBP_SF(DCN_VM_AGP_TOP, AGP_TOP, mask_sh),\
90 HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_DST_Y_OFFSET, mask_sh), \
91 HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \
92 HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \
93 HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \
94 HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \
95 HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \
96 HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \
97 HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \
98 HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \
99 HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \
100 HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \
101 HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \
102 HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \
103 HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \
104 HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \
105 HUBP_SF(CURSOR0_0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh), \
106 HUBP_SF(CURSOR0_0_DMDATA_ADDRESS_HIGH, DMDATA_ADDRESS_HIGH, mask_sh), \
107 HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_MODE, mask_sh), \
108 HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_UPDATED, mask_sh), \
109 HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_REPEAT, mask_sh), \
110 HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_SIZE, mask_sh), \
111 HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_UPDATED, mask_sh), \
112 HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_REPEAT, mask_sh), \
113 HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_SIZE, mask_sh), \
114 HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_MODE, mask_sh), \
115 HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_LEVEL, mask_sh), \
116 HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_DL_DELTA, mask_sh), \
117 HUBP_SF(CURSOR0_0_DMDATA_STATUS, DMDATA_DONE, mask_sh),\
118 HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_VM_FLIP, mask_sh),\
119 HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_ROW_FLIP, mask_sh),\
120 HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_1, REFCYC_PER_PTE_GROUP_FLIP_L, mask_sh),\
121 HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_2, REFCYC_PER_META_CHUNK_FLIP_L, mask_sh),\
122 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, mask_sh),\
123 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_DISABLE_STOP_DATA_DURING_VM, mask_sh),\
124 HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, HUBPREQ_MASTER_UPDATE_LOCK_STATUS, mask_sh),\
125 HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_GSL_ENABLE, mask_sh),\
126 HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, mask_sh),\
127 HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh)
129 #define HUBP_MASK_SH_LIST_DCN20(mask_sh)\
130 HUBP_MASK_SH_LIST_DCN2_COMMON(mask_sh),\
131 HUBP_SF(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, mask_sh),\
132 HUBP_SF(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mask_sh),\
133 HUBP_SF(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mask_sh)
136 #define DCN2_HUBP_REG_COMMON_VARIABLE_LIST \
137 HUBP_COMMON_REG_VARIABLE_LIST; \
138 uint32_t DMDATA_ADDRESS_HIGH; \
139 uint32_t DMDATA_ADDRESS_LOW; \
140 uint32_t DMDATA_CNTL; \
141 uint32_t DMDATA_SW_CNTL; \
142 uint32_t DMDATA_QOS_CNTL; \
143 uint32_t DMDATA_SW_DATA; \
144 uint32_t DMDATA_STATUS;\
145 uint32_t DCSURF_FLIP_CONTROL2;\
146 uint32_t FLIP_PARAMETERS_0;\
147 uint32_t FLIP_PARAMETERS_1;\
148 uint32_t FLIP_PARAMETERS_2;\
149 uint32_t DCN_CUR1_TTU_CNTL1;\
150 uint32_t VMID_SETTINGS_0;\
151 uint32_t FLIP_PARAMETERS_3;\
152 uint32_t FLIP_PARAMETERS_4;\
153 uint32_t VBLANK_PARAMETERS_5;\
154 uint32_t VBLANK_PARAMETERS_6
156 #define DCN2_HUBP_REG_FIELD_VARIABLE_LIST(type) \
157 DCN_HUBP_REG_FIELD_LIST(type); \
158 type DMDATA_ADDRESS_HIGH;\
160 type DMDATA_UPDATED;\
163 type DMDATA_SW_UPDATED;\
164 type DMDATA_SW_REPEAT;\
165 type DMDATA_SW_SIZE;\
166 type DMDATA_QOS_MODE;\
167 type DMDATA_QOS_LEVEL;\
168 type DMDATA_DL_DELTA;\
170 type DST_Y_PER_VM_FLIP;\
171 type DST_Y_PER_ROW_FLIP;\
172 type REFCYC_PER_PTE_GROUP_FLIP_L;\
173 type REFCYC_PER_META_CHUNK_FLIP_L;\
174 type HUBP_VREADY_AT_OR_AFTER_VSYNC;\
175 type HUBP_DISABLE_STOP_DATA_DURING_VM;\
176 type HUBPREQ_MASTER_UPDATE_LOCK_STATUS;\
177 type SURFACE_GSL_ENABLE;\
178 type SURFACE_TRIPLE_BUFFER_ENABLE;\
182 struct dcn_hubp2_registers {
183 DCN2_HUBP_REG_COMMON_VARIABLE_LIST;
186 struct dcn_hubp2_shift {
187 DCN2_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t);
190 struct dcn_hubp2_mask {
191 DCN2_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t);
196 struct dcn_hubp_state state;
197 const struct dcn_hubp2_registers *hubp_regs;
198 const struct dcn_hubp2_shift *hubp_shift;
199 const struct dcn_hubp2_mask *hubp_mask;
202 bool hubp2_construct(
203 struct dcn20_hubp *hubp2,
204 struct dc_context *ctx,
206 const struct dcn_hubp2_registers *hubp_regs,
207 const struct dcn_hubp2_shift *hubp_shift,
208 const struct dcn_hubp2_mask *hubp_mask);
210 void hubp2_setup_interdependent(
212 struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
213 struct _vcs_dpi_display_ttu_regs_st *ttu_attr);
215 void hubp2_vready_at_or_After_vsync(struct hubp *hubp,
216 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest);
218 void hubp2_update_dchub(
220 struct dchub_init_data *dh_data);
222 void hubp2_cursor_set_attributes(
224 const struct dc_cursor_attributes *attr);
226 void hubp2_set_vm_system_aperture_settings(struct hubp *hubp,
227 struct vm_system_aperture_param *apt);
229 enum cursor_lines_per_chunk hubp2_get_lines_per_chunk(
230 unsigned int cursor_width,
231 enum dc_cursor_color_format cursor_mode);
233 void hubp2_dmdata_set_attributes(
235 const struct dc_dmdata_attributes *attr);
237 void hubp2_dmdata_load(
239 uint32_t dmdata_sw_size,
240 const uint32_t *dmdata_sw_data);
242 bool hubp2_dmdata_status_done(struct hubp *hubp);
244 void hubp2_enable_triplebuffer(
248 bool hubp2_is_triplebuffer_enabled(
251 void hubp2_set_flip_control_surface_gsl(struct hubp *hubp, bool enable);
253 void hubp2_program_deadline(
255 struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
256 struct _vcs_dpi_display_ttu_regs_st *ttu_attr);
258 bool hubp2_program_surface_flip_and_addr(
260 const struct dc_plane_address *address,
264 void hubp2_program_surface_config(
266 enum surface_pixel_format format,
267 union dc_tiling_info *tiling_info,
268 union plane_size *plane_size,
269 enum dc_rotation_angle rotation,
270 struct dc_plane_dcc_param *dcc,
271 bool horizontal_mirror,
272 unsigned int compat_level);
274 #endif /* __DC_MEM_INPUT_DCN20_H__ */