2 * Copyright 2016 Advanced Micro Devices, Inc.
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5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
27 #include "dcn20_hubbub.h"
28 #include "reg_helper.h"
38 #define FN(reg_name, field_name) \
39 hubbub1->shifts->field_name, hubbub1->masks->field_name
48 #define FN(reg_name, field_name) \
49 hubbub1->shifts->field_name, hubbub1->masks->field_name
56 bool hubbub2_dcc_support_swizzle(
57 enum swizzle_mode_values swizzle,
58 unsigned int bytes_per_element,
59 enum segment_order *segment_order_horz,
60 enum segment_order *segment_order_vert)
62 bool standard_swizzle = false;
63 bool display_swizzle = false;
64 bool render_swizzle = false;
73 standard_swizzle = true;
76 render_swizzle = true;
84 display_swizzle = true;
90 if (standard_swizzle) {
91 if (bytes_per_element == 1) {
92 *segment_order_horz = segment_order__contiguous;
93 *segment_order_vert = segment_order__na;
96 if (bytes_per_element == 2) {
97 *segment_order_horz = segment_order__non_contiguous;
98 *segment_order_vert = segment_order__contiguous;
101 if (bytes_per_element == 4) {
102 *segment_order_horz = segment_order__non_contiguous;
103 *segment_order_vert = segment_order__contiguous;
106 if (bytes_per_element == 8) {
107 *segment_order_horz = segment_order__na;
108 *segment_order_vert = segment_order__contiguous;
112 if (render_swizzle) {
113 if (bytes_per_element == 2) {
114 *segment_order_horz = segment_order__contiguous;
115 *segment_order_vert = segment_order__contiguous;
118 if (bytes_per_element == 4) {
119 *segment_order_horz = segment_order__non_contiguous;
120 *segment_order_vert = segment_order__contiguous;
123 if (bytes_per_element == 8) {
124 *segment_order_horz = segment_order__contiguous;
125 *segment_order_vert = segment_order__non_contiguous;
129 if (display_swizzle && bytes_per_element == 8) {
130 *segment_order_horz = segment_order__contiguous;
131 *segment_order_vert = segment_order__non_contiguous;
138 bool hubbub2_dcc_support_pixel_format(
139 enum surface_pixel_format format,
140 unsigned int *bytes_per_element)
142 /* DML: get_bytes_per_element */
144 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
145 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
146 *bytes_per_element = 2;
148 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
149 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
150 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
151 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
152 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX:
153 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX:
154 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT:
155 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT:
156 case SURFACE_PIXEL_FORMAT_GRPH_RGBE:
157 case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
158 *bytes_per_element = 4;
160 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
161 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
162 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
163 *bytes_per_element = 8;
170 static void hubbub2_get_blk256_size(unsigned int *blk256_width, unsigned int *blk256_height,
171 unsigned int bytes_per_element)
173 /* copied from DML. might want to refactor DML to leverage from DML */
174 /* DML : get_blk256_size */
175 if (bytes_per_element == 1) {
178 } else if (bytes_per_element == 2) {
181 } else if (bytes_per_element == 4) {
184 } else if (bytes_per_element == 8) {
190 static void hubbub2_det_request_size(
191 unsigned int detile_buf_size,
195 bool *req128_horz_wc,
196 bool *req128_vert_wc)
198 unsigned int blk256_height = 0;
199 unsigned int blk256_width = 0;
200 unsigned int swath_bytes_horz_wc, swath_bytes_vert_wc;
202 hubbub2_get_blk256_size(&blk256_width, &blk256_height, bpe);
204 swath_bytes_horz_wc = width * blk256_height * bpe;
205 swath_bytes_vert_wc = height * blk256_width * bpe;
207 *req128_horz_wc = (2 * swath_bytes_horz_wc <= detile_buf_size) ?
208 false : /* full 256B request */
209 true; /* half 128b request */
211 *req128_vert_wc = (2 * swath_bytes_vert_wc <= detile_buf_size) ?
212 false : /* full 256B request */
213 true; /* half 128b request */
216 bool hubbub2_get_dcc_compression_cap(struct hubbub *hubbub,
217 const struct dc_dcc_surface_param *input,
218 struct dc_surface_dcc_cap *output)
220 struct dc *dc = hubbub->ctx->dc;
221 /* implement section 1.6.2.1 of DCN1_Programming_Guide.docx */
222 enum dcc_control dcc_control;
224 enum segment_order segment_order_horz, segment_order_vert;
225 bool req128_horz_wc, req128_vert_wc;
227 memset(output, 0, sizeof(*output));
229 if (dc->debug.disable_dcc == DCC_DISABLE)
232 if (!hubbub->funcs->dcc_support_pixel_format(input->format,
236 if (!hubbub->funcs->dcc_support_swizzle(input->swizzle_mode, bpe,
237 &segment_order_horz, &segment_order_vert))
240 hubbub2_det_request_size(TO_DCN20_HUBBUB(hubbub)->detile_buf_size,
241 input->surface_size.height, input->surface_size.width,
242 bpe, &req128_horz_wc, &req128_vert_wc);
244 if (!req128_horz_wc && !req128_vert_wc) {
245 dcc_control = dcc_control__256_256_xxx;
246 } else if (input->scan == SCAN_DIRECTION_HORIZONTAL) {
248 dcc_control = dcc_control__256_256_xxx;
249 else if (segment_order_horz == segment_order__contiguous)
250 dcc_control = dcc_control__128_128_xxx;
252 dcc_control = dcc_control__256_64_64;
253 } else if (input->scan == SCAN_DIRECTION_VERTICAL) {
255 dcc_control = dcc_control__256_256_xxx;
256 else if (segment_order_vert == segment_order__contiguous)
257 dcc_control = dcc_control__128_128_xxx;
259 dcc_control = dcc_control__256_64_64;
261 if ((req128_horz_wc &&
262 segment_order_horz == segment_order__non_contiguous) ||
264 segment_order_vert == segment_order__non_contiguous))
265 /* access_dir not known, must use most constraining */
266 dcc_control = dcc_control__256_64_64;
268 /* reg128 is true for either horz and vert
269 * but segment_order is contiguous
271 dcc_control = dcc_control__128_128_xxx;
274 /* Exception for 64KB_R_X */
275 if ((bpe == 2) && (input->swizzle_mode == DC_SW_64KB_R_X))
276 dcc_control = dcc_control__128_128_xxx;
278 if (dc->debug.disable_dcc == DCC_HALF_REQ_DISALBE &&
279 dcc_control != dcc_control__256_256_xxx)
282 switch (dcc_control) {
283 case dcc_control__256_256_xxx:
284 output->grph.rgb.max_uncompressed_blk_size = 256;
285 output->grph.rgb.max_compressed_blk_size = 256;
286 output->grph.rgb.independent_64b_blks = false;
288 case dcc_control__128_128_xxx:
289 output->grph.rgb.max_uncompressed_blk_size = 128;
290 output->grph.rgb.max_compressed_blk_size = 128;
291 output->grph.rgb.independent_64b_blks = false;
293 case dcc_control__256_64_64:
294 output->grph.rgb.max_uncompressed_blk_size = 256;
295 output->grph.rgb.max_compressed_blk_size = 64;
296 output->grph.rgb.independent_64b_blks = true;
302 output->capable = true;
303 output->const_color_support = true;
308 static enum dcn_hubbub_page_table_depth page_table_depth_to_hw(unsigned int page_table_depth)
310 enum dcn_hubbub_page_table_depth depth = 0;
312 switch (page_table_depth) {
314 depth = DCN_PAGE_TABLE_DEPTH_1_LEVEL;
317 depth = DCN_PAGE_TABLE_DEPTH_2_LEVEL;
320 depth = DCN_PAGE_TABLE_DEPTH_3_LEVEL;
323 depth = DCN_PAGE_TABLE_DEPTH_4_LEVEL;
333 static enum dcn_hubbub_page_table_block_size page_table_block_size_to_hw(unsigned int page_table_block_size)
335 enum dcn_hubbub_page_table_block_size block_size = 0;
337 switch (page_table_block_size) {
339 block_size = DCN_PAGE_TABLE_BLOCK_SIZE_4KB;
342 block_size = DCN_PAGE_TABLE_BLOCK_SIZE_64KB;
345 block_size = DCN_PAGE_TABLE_BLOCK_SIZE_32KB;
349 block_size = page_table_block_size;
356 void hubbub2_init_vm_ctx(struct hubbub *hubbub,
357 struct dcn_hubbub_virt_addr_config *va_config,
360 struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
361 struct dcn_vmid_page_table_config virt_config;
363 virt_config.page_table_start_addr = va_config->page_table_start_addr >> 12;
364 virt_config.page_table_end_addr = va_config->page_table_end_addr >> 12;
365 virt_config.depth = page_table_depth_to_hw(va_config->page_table_depth);
366 virt_config.block_size = page_table_block_size_to_hw(va_config->page_table_block_size);
367 virt_config.page_table_base_addr = va_config->page_table_base_addr;
369 dcn20_vmid_setup(&hubbub1->vmid[vmid], &virt_config);
372 int hubbub2_init_dchub_sys_ctx(struct hubbub *hubbub,
373 struct dcn_hubbub_phys_addr_config *pa_config)
375 struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
376 struct dcn_vmid_page_table_config phys_config;
378 REG_SET(DCN_VM_FB_LOCATION_BASE, 0,
379 FB_BASE, pa_config->system_aperture.fb_base >> 24);
380 REG_SET(DCN_VM_FB_LOCATION_TOP, 0,
381 FB_TOP, pa_config->system_aperture.fb_top >> 24);
382 REG_SET(DCN_VM_FB_OFFSET, 0,
383 FB_OFFSET, pa_config->system_aperture.fb_offset >> 24);
384 REG_SET(DCN_VM_AGP_BOT, 0,
385 AGP_BOT, pa_config->system_aperture.agp_bot >> 24);
386 REG_SET(DCN_VM_AGP_TOP, 0,
387 AGP_TOP, pa_config->system_aperture.agp_top >> 24);
388 REG_SET(DCN_VM_AGP_BASE, 0,
389 AGP_BASE, pa_config->system_aperture.agp_base >> 24);
391 REG_SET(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, 0,
392 DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, (pa_config->page_table_default_page_addr >> 44) & 0xF);
393 REG_SET(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB, 0,
394 DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB, (pa_config->page_table_default_page_addr >> 12) & 0xFFFFFFFF);
396 if (pa_config->gart_config.page_table_start_addr != pa_config->gart_config.page_table_end_addr) {
397 phys_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr >> 12;
398 phys_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr >> 12;
399 phys_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr;
400 phys_config.depth = 0;
401 phys_config.block_size = 0;
402 // Init VMID 0 based on PA config
403 dcn20_vmid_setup(&hubbub1->vmid[0], &phys_config);
409 void hubbub2_update_dchub(struct hubbub *hubbub,
410 struct dchub_init_data *dh_data)
412 struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
414 if (REG(DCN_VM_FB_LOCATION_TOP) == 0)
417 switch (dh_data->fb_mode) {
418 case FRAME_BUFFER_MODE_ZFB_ONLY:
419 /*For ZFB case need to put DCHUB FB BASE and TOP upside down to indicate ZFB mode*/
420 REG_UPDATE(DCN_VM_FB_LOCATION_TOP,
423 REG_UPDATE(DCN_VM_FB_LOCATION_BASE,
426 /*This field defines the 24 MSBs, bits [47:24] of the 48 bit AGP Base*/
427 REG_UPDATE(DCN_VM_AGP_BASE,
428 AGP_BASE, dh_data->zfb_phys_addr_base >> 24);
430 /*This field defines the bottom range of the AGP aperture and represents the 24*/
431 /*MSBs, bits [47:24] of the 48 address bits*/
432 REG_UPDATE(DCN_VM_AGP_BOT,
433 AGP_BOT, dh_data->zfb_mc_base_addr >> 24);
435 /*This field defines the top range of the AGP aperture and represents the 24*/
436 /*MSBs, bits [47:24] of the 48 address bits*/
437 REG_UPDATE(DCN_VM_AGP_TOP,
438 AGP_TOP, (dh_data->zfb_mc_base_addr +
439 dh_data->zfb_size_in_byte - 1) >> 24);
441 case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL:
442 /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
444 /*This field defines the 24 MSBs, bits [47:24] of the 48 bit AGP Base*/
445 REG_UPDATE(DCN_VM_AGP_BASE,
446 AGP_BASE, dh_data->zfb_phys_addr_base >> 24);
448 /*This field defines the bottom range of the AGP aperture and represents the 24*/
449 /*MSBs, bits [47:24] of the 48 address bits*/
450 REG_UPDATE(DCN_VM_AGP_BOT,
451 AGP_BOT, dh_data->zfb_mc_base_addr >> 24);
453 /*This field defines the top range of the AGP aperture and represents the 24*/
454 /*MSBs, bits [47:24] of the 48 address bits*/
455 REG_UPDATE(DCN_VM_AGP_TOP,
456 AGP_TOP, (dh_data->zfb_mc_base_addr +
457 dh_data->zfb_size_in_byte - 1) >> 24);
459 case FRAME_BUFFER_MODE_LOCAL_ONLY:
460 /*Should not touch FB LOCATION (should be done by VBIOS)*/
462 /*This field defines the 24 MSBs, bits [47:24] of the 48 bit AGP Base*/
463 REG_UPDATE(DCN_VM_AGP_BASE,
466 /*This field defines the bottom range of the AGP aperture and represents the 24*/
467 /*MSBs, bits [47:24] of the 48 address bits*/
468 REG_UPDATE(DCN_VM_AGP_BOT,
471 /*This field defines the top range of the AGP aperture and represents the 24*/
472 /*MSBs, bits [47:24] of the 48 address bits*/
473 REG_UPDATE(DCN_VM_AGP_TOP,
480 dh_data->dchub_initialzied = true;
481 dh_data->dchub_info_valid = false;
484 void hubbub2_wm_read_state(struct hubbub *hubbub,
485 struct dcn_hubbub_wm *wm)
487 struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
489 struct dcn_hubbub_wm_set *s;
491 memset(wm, 0, sizeof(struct dcn_hubbub_wm));
495 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A);
496 if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A))
497 s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A);
498 if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A)) {
499 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A);
500 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A);
502 s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A);
506 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B);
507 if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B))
508 s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B);
509 if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B)) {
510 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B);
511 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B);
513 s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B);
517 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C);
518 if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C))
519 s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C);
520 if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C)) {
521 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C);
522 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C);
524 s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C);
528 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D);
529 if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D))
530 s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D);
531 if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D)) {
532 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D);
533 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D);
535 s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D);
538 void hubbub2_get_dchub_ref_freq(struct hubbub *hubbub,
539 unsigned int dccg_ref_freq_inKhz,
540 unsigned int *dchub_ref_freq_inKhz)
542 struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
543 uint32_t ref_div = 0;
546 REG_GET_2(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, &ref_div,
547 DCHUBBUB_GLOBAL_TIMER_ENABLE, &ref_en);
551 *dchub_ref_freq_inKhz = dccg_ref_freq_inKhz / 2;
553 *dchub_ref_freq_inKhz = dccg_ref_freq_inKhz;
555 // DC hub reference frequency must be around 50Mhz, otherwise there may be
556 // overflow/underflow issues when doing HUBBUB programming
557 if (*dchub_ref_freq_inKhz < 40000 || *dchub_ref_freq_inKhz > 60000)
558 ASSERT_CRITICAL(false);
562 *dchub_ref_freq_inKhz = dccg_ref_freq_inKhz;
564 // HUBBUB global timer must be enabled.
565 ASSERT_CRITICAL(false);
570 static bool hubbub2_program_watermarks(
571 struct hubbub *hubbub,
572 struct dcn_watermark_set *watermarks,
573 unsigned int refclk_mhz,
576 struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
577 bool wm_pending = false;
579 * Need to clamp to max of the register values (i.e. no wrap)
580 * for dcn1, all wm registers are 21-bit wide
582 if (hubbub1_program_urgent_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower))
585 if (hubbub1_program_stutter_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower))
589 * There's a special case when going from p-state support to p-state unsupported
590 * here we are going to LOWER watermarks to go to dummy p-state only, but this has
591 * to be done prepare_bandwidth, not optimize
593 if (hubbub1->base.ctx->dc->clk_mgr->clks.prev_p_state_change_support == true &&
594 hubbub1->base.ctx->dc->clk_mgr->clks.p_state_change_support == false)
595 safe_to_lower = true;
597 hubbub1_program_pstate_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower);
599 REG_SET(DCHUBBUB_ARB_SAT_LEVEL, 0,
600 DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz);
601 REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 180);
603 hubbub->funcs->allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);
607 static const struct hubbub_funcs hubbub2_funcs = {
608 .update_dchub = hubbub2_update_dchub,
609 .init_dchub_sys_ctx = hubbub2_init_dchub_sys_ctx,
610 .init_vm_ctx = hubbub2_init_vm_ctx,
611 .dcc_support_swizzle = hubbub2_dcc_support_swizzle,
612 .dcc_support_pixel_format = hubbub2_dcc_support_pixel_format,
613 .get_dcc_compression_cap = hubbub2_get_dcc_compression_cap,
614 .wm_read_state = hubbub2_wm_read_state,
615 .get_dchub_ref_freq = hubbub2_get_dchub_ref_freq,
616 .program_watermarks = hubbub2_program_watermarks,
617 .is_allow_self_refresh_enabled = hubbub1_is_allow_self_refresh_enabled,
618 .allow_self_refresh_control = hubbub1_allow_self_refresh_control,
621 void hubbub2_construct(struct dcn20_hubbub *hubbub,
622 struct dc_context *ctx,
623 const struct dcn_hubbub_registers *hubbub_regs,
624 const struct dcn_hubbub_shift *hubbub_shift,
625 const struct dcn_hubbub_mask *hubbub_mask)
627 hubbub->base.ctx = ctx;
629 hubbub->base.funcs = &hubbub2_funcs;
631 hubbub->regs = hubbub_regs;
632 hubbub->shifts = hubbub_shift;
633 hubbub->masks = hubbub_mask;
635 hubbub->debug_test_index_pstate = 0xB;
636 hubbub->detile_buf_size = 164 * 1024; /* 164KB for DCN2.0 */