drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  *  and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26
  27 #include "dc_bios_types.h"
  28 #include "dcn10_stream_encoder.h"
  29 #include "reg_helper.h"
  30 #include "hw_shared.h"
  31
  32 #define DC_LOGGER \
  33                 enc1->base.ctx->logger
  34
  35
  36 #define REG(reg)\
  37         (enc1->regs->reg)
  38
  39 #undef FN
  40 #define FN(reg_name, field_name) \
  41         enc1->se_shift->field_name, enc1->se_mask->field_name
  42
  43 #define VBI_LINE_0 0
  44 #define DP_BLANK_MAX_RETRY 20
  45 #define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000
  46
  47
  48 enum {
  49         DP_MST_UPDATE_MAX_RETRY = 50
  50 };
  51
  52 #define CTX \
  53         enc1->base.ctx
  54
  55 void enc1_update_generic_info_packet(
  56         struct dcn10_stream_encoder *enc1,
  57         uint32_t packet_index,
  58         const struct dc_info_packet *info_packet)
  59 {
  60         uint32_t regval;
  61         /* TODOFPGA Figure out a proper number for max_retries polling for lock
  62          * use 50 for now.
  63          */
  64         uint32_t max_retries = 50;
  65
  66         /*we need turn on clock before programming AFMT block*/
  67         REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
  68
  69         if (packet_index >= 8)
  70                 ASSERT(0);
  71
  72         /* poll dig_update_lock is not locked -> asic internal signal
  73          * assume otg master lock will unlock it
  74          */
  75 /*              REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS,
  76                         0, 10, max_retries);*/
  77
  78         /* check if HW reading GSP memory */
  79         REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,
  80                         0, 10, max_retries);
  81
  82         /* HW does is not reading GSP memory not reading too long ->
  83          * something wrong. clear GPS memory access and notify?
  84          * hw SW is writing to GSP memory
  85          */
  86         REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1);
  87
  88         /* choose which generic packet to use */
  89         regval = REG_READ(AFMT_VBI_PACKET_CONTROL);
  90         REG_UPDATE(AFMT_VBI_PACKET_CONTROL,
  91                         AFMT_GENERIC_INDEX, packet_index);
  92
  93         /* write generic packet header
  94          * (4th byte is for GENERIC0 only)
  95          */
  96         REG_SET_4(AFMT_GENERIC_HDR, 0,
  97                         AFMT_GENERIC_HB0, info_packet->hb0,
  98                         AFMT_GENERIC_HB1, info_packet->hb1,
  99                         AFMT_GENERIC_HB2, info_packet->hb2,
 100                         AFMT_GENERIC_HB3, info_packet->hb3);
 101
 102         /* write generic packet contents
 103          * (we never use last 4 bytes)
 104          * there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers
 105          */
 106         {
 107                 const uint32_t *content =
 108                         (const uint32_t *) &info_packet->sb[0];
 109
 110                 REG_WRITE(AFMT_GENERIC_0, *content++);
 111                 REG_WRITE(AFMT_GENERIC_1, *content++);
 112                 REG_WRITE(AFMT_GENERIC_2, *content++);
 113                 REG_WRITE(AFMT_GENERIC_3, *content++);
 114                 REG_WRITE(AFMT_GENERIC_4, *content++);
 115                 REG_WRITE(AFMT_GENERIC_5, *content++);
 116                 REG_WRITE(AFMT_GENERIC_6, *content++);
 117                 REG_WRITE(AFMT_GENERIC_7, *content);
 118         }
 119
 120         switch (packet_index) {
 121         case 0:
 122                 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 123                                 AFMT_GENERIC0_FRAME_UPDATE, 1);
 124                 break;
 125         case 1:
 126                 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 127                                 AFMT_GENERIC1_FRAME_UPDATE, 1);
 128                 break;
 129         case 2:
 130                 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 131                                 AFMT_GENERIC2_FRAME_UPDATE, 1);
 132                 break;
 133         case 3:
 134                 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 135                                 AFMT_GENERIC3_FRAME_UPDATE, 1);
 136                 break;
 137         case 4:
 138                 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 139                                 AFMT_GENERIC4_FRAME_UPDATE, 1);
 140                 break;
 141         case 5:
 142                 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 143                                 AFMT_GENERIC5_FRAME_UPDATE, 1);
 144                 break;
 145         case 6:
 146                 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 147                                 AFMT_GENERIC6_FRAME_UPDATE, 1);
 148                 break;
 149         case 7:
 150                 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 151                                 AFMT_GENERIC7_FRAME_UPDATE, 1);
 152                 break;
 153         default:
 154                 break;
 155         }
 156 }
 157
 158 static void enc1_update_hdmi_info_packet(
 159         struct dcn10_stream_encoder *enc1,
 160         uint32_t packet_index,
 161         const struct dc_info_packet *info_packet)
 162 {
 163         uint32_t cont, send, line;
 164
 165         if (info_packet->valid) {
 166                 enc1_update_generic_info_packet(
 167                         enc1,
 168                         packet_index,
 169                         info_packet);
 170
 171                 /* enable transmission of packet(s) -
 172                  * packet transmission begins on the next frame
 173                  */
 174                 cont = 1;
 175                 /* send packet(s) every frame */
 176                 send = 1;
 177                 /* select line number to send packets on */
 178                 line = 2;
 179         } else {
 180                 cont = 0;
 181                 send = 0;
 182                 line = 0;
 183         }
 184
 185         /* choose which generic packet control to use */
 186         switch (packet_index) {
 187         case 0:
 188                 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
 189                                 HDMI_GENERIC0_CONT, cont,
 190                                 HDMI_GENERIC0_SEND, send,
 191                                 HDMI_GENERIC0_LINE, line);
 192                 break;
 193         case 1:
 194                 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
 195                                 HDMI_GENERIC1_CONT, cont,
 196                                 HDMI_GENERIC1_SEND, send,
 197                                 HDMI_GENERIC1_LINE, line);
 198                 break;
 199         case 2:
 200                 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
 201                                 HDMI_GENERIC0_CONT, cont,
 202                                 HDMI_GENERIC0_SEND, send,
 203                                 HDMI_GENERIC0_LINE, line);
 204                 break;
 205         case 3:
 206                 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
 207                                 HDMI_GENERIC1_CONT, cont,
 208                                 HDMI_GENERIC1_SEND, send,
 209                                 HDMI_GENERIC1_LINE, line);
 210                 break;
 211         case 4:
 212                 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
 213                                 HDMI_GENERIC0_CONT, cont,
 214                                 HDMI_GENERIC0_SEND, send,
 215                                 HDMI_GENERIC0_LINE, line);
 216                 break;
 217         case 5:
 218                 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
 219                                 HDMI_GENERIC1_CONT, cont,
 220                                 HDMI_GENERIC1_SEND, send,
 221                                 HDMI_GENERIC1_LINE, line);
 222                 break;
 223         case 6:
 224                 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,
 225                                 HDMI_GENERIC0_CONT, cont,
 226                                 HDMI_GENERIC0_SEND, send,
 227                                 HDMI_GENERIC0_LINE, line);
 228                 break;
 229         case 7:
 230                 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,
 231                                 HDMI_GENERIC1_CONT, cont,
 232                                 HDMI_GENERIC1_SEND, send,
 233                                 HDMI_GENERIC1_LINE, line);
 234                 break;
 235         default:
 236                 /* invalid HW packet index */
 237                 DC_LOG_WARNING(
 238                         "Invalid HW packet index: %s()\n",
 239                         __func__);
 240                 return;
 241         }
 242 }
 243
 244 /* setup stream encoder in dp mode */
 245 void enc1_stream_encoder_dp_set_stream_attribute(
 246         struct stream_encoder *enc,
 247         struct dc_crtc_timing *crtc_timing,
 248         enum dc_color_space output_color_space,
 249         uint32_t enable_sdp_splitting)
 250 {
 251         uint32_t h_active_start;
 252         uint32_t v_active_start;
 253         uint32_t misc0 = 0;
 254         uint32_t misc1 = 0;
 255         uint32_t h_blank;
 256         uint32_t h_back_porch;
 257         uint8_t synchronous_clock = 0; /* asynchronous mode */
 258         uint8_t colorimetry_bpc;
 259         uint8_t dynamic_range_rgb = 0; /*full range*/
 260         uint8_t dynamic_range_ycbcr = 1; /*bt709*/
 261         uint8_t dp_pixel_encoding = 0;
 262         uint8_t dp_component_depth = 0;
 263
 264         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
 265         struct dc_crtc_timing hw_crtc_timing = *crtc_timing;
 266
 267         if (hw_crtc_timing.flags.INTERLACE) {
 268                 /*the input timing is in VESA spec format with Interlace flag =1*/
 269                 hw_crtc_timing.v_total /= 2;
 270                 hw_crtc_timing.v_border_top /= 2;
 271                 hw_crtc_timing.v_addressable /= 2;
 272                 hw_crtc_timing.v_border_bottom /= 2;
 273                 hw_crtc_timing.v_front_porch /= 2;
 274                 hw_crtc_timing.v_sync_width /= 2;
 275         }
 276
 277
 278         /* set pixel encoding */
 279         switch (hw_crtc_timing.pixel_encoding) {
 280         case PIXEL_ENCODING_YCBCR422:
 281                 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR422;
 282                 break;
 283         case PIXEL_ENCODING_YCBCR444:
 284                 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR444;
 285
 286                 if (hw_crtc_timing.flags.Y_ONLY)
 287                         if (hw_crtc_timing.display_color_depth != COLOR_DEPTH_666)
 288                                 /* HW testing only, no use case yet.
 289                                  * Color depth of Y-only could be
 290                                  * 8, 10, 12, 16 bits
 291                                  */
 292                                 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_Y_ONLY;
 293
 294                 /* Note: DP_MSA_MISC1 bit 7 is the indicator
 295                  * of Y-only mode.
 296                  * This bit is set in HW if register
 297                  * DP_PIXEL_ENCODING is programmed to 0x4
 298                  */
 299                 break;
 300         case PIXEL_ENCODING_YCBCR420:
 301                 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR420;
 302                 break;
 303         default:
 304                 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_RGB444;
 305                 break;
 306         }
 307
 308         misc1 = REG_READ(DP_MSA_MISC);
 309         /* For YCbCr420 and BT2020 Colorimetry Formats, VSC SDP shall be used.
 310          * When MISC1, bit 6, is Set to 1, a Source device uses a VSC SDP to indicate the
 311          * Pixel Encoding/Colorimetry Format and that a Sink device shall ignore MISC1, bit 7,
 312          * and MISC0, bits 7:1 (MISC1, bit 7, and MISC0, bits 7:1, become "don't care").
 313          */
 314         if ((hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) ||
 315                         (output_color_space == COLOR_SPACE_2020_YCBCR) ||
 316                         (output_color_space == COLOR_SPACE_2020_RGB_FULLRANGE) ||
 317                         (output_color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE))
 318                 misc1 = misc1 | 0x40;
 319         else
 320                 misc1 = misc1 & ~0x40;
 321
 322         /* set color depth */
 323         switch (hw_crtc_timing.display_color_depth) {
 324         case COLOR_DEPTH_666:
 325                 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_6BPC;
 326                 break;
 327         case COLOR_DEPTH_888:
 328                 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_8BPC;
 329                 break;
 330         case COLOR_DEPTH_101010:
 331                 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_10BPC;
 332                 break;
 333         case COLOR_DEPTH_121212:
 334                 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_12BPC;
 335                 break;
 336         case COLOR_DEPTH_161616:
 337                 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_16BPC;
 338                 break;
 339         default:
 340                 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_6BPC;
 341                 break;
 342         }
 343
 344         /* Set DP pixel encoding and component depth */
 345         REG_UPDATE_2(DP_PIXEL_FORMAT,
 346                         DP_PIXEL_ENCODING, dp_pixel_encoding,
 347                         DP_COMPONENT_DEPTH, dp_component_depth);
 348
 349         /* set dynamic range and YCbCr range */
 350
 351         switch (hw_crtc_timing.display_color_depth) {
 352         case COLOR_DEPTH_666:
 353                 colorimetry_bpc = 0;
 354                 break;
 355         case COLOR_DEPTH_888:
 356                 colorimetry_bpc = 1;
 357                 break;
 358         case COLOR_DEPTH_101010:
 359                 colorimetry_bpc = 2;
 360                 break;
 361         case COLOR_DEPTH_121212:
 362                 colorimetry_bpc = 3;
 363                 break;
 364         default:
 365                 colorimetry_bpc = 0;
 366                 break;
 367         }
 368
 369         misc0 = misc0 | synchronous_clock;
 370         misc0 = colorimetry_bpc << 5;
 371
 372         switch (output_color_space) {
 373         case COLOR_SPACE_SRGB:
 374                 misc1 = misc1 & ~0x80; /* bit7 = 0*/
 375                 dynamic_range_rgb = 0; /*full range*/
 376                 break;
 377         case COLOR_SPACE_SRGB_LIMITED:
 378                 misc0 = misc0 | 0x8; /* bit3=1 */
 379                 misc1 = misc1 & ~0x80; /* bit7 = 0*/
 380                 dynamic_range_rgb = 1; /*limited range*/
 381                 break;
 382         case COLOR_SPACE_YCBCR601:
 383         case COLOR_SPACE_YCBCR601_LIMITED:
 384                 misc0 = misc0 | 0x8; /* bit3=1, bit4=0 */
 385                 misc1 = misc1 & ~0x80; /* bit7 = 0*/
 386                 dynamic_range_ycbcr = 0; /*bt601*/
 387                 if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
 388                         misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
 389                 else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444)
 390                         misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
 391                 break;
 392         case COLOR_SPACE_YCBCR709:
 393         case COLOR_SPACE_YCBCR709_LIMITED:
 394                 misc0 = misc0 | 0x18; /* bit3=1, bit4=1 */
 395                 misc1 = misc1 & ~0x80; /* bit7 = 0*/
 396                 dynamic_range_ycbcr = 1; /*bt709*/
 397                 if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
 398                         misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
 399                 else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444)
 400                         misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
 401                 break;
 402         case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
 403                 dynamic_range_rgb = 1; /*limited range*/
 404                 break;
 405         case COLOR_SPACE_2020_RGB_FULLRANGE:
 406         case COLOR_SPACE_2020_YCBCR:
 407         case COLOR_SPACE_XR_RGB:
 408         case COLOR_SPACE_MSREF_SCRGB:
 409         case COLOR_SPACE_ADOBERGB:
 410         case COLOR_SPACE_DCIP3:
 411         case COLOR_SPACE_XV_YCC_709:
 412         case COLOR_SPACE_XV_YCC_601:
 413         case COLOR_SPACE_DISPLAYNATIVE:
 414         case COLOR_SPACE_DOLBYVISION:
 415         case COLOR_SPACE_APPCTRL:
 416         case COLOR_SPACE_CUSTOMPOINTS:
 417         case COLOR_SPACE_UNKNOWN:
 418                 /* do nothing */
 419                 break;
 420         }
 421
 422         REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0);
 423         REG_WRITE(DP_MSA_MISC, misc1);   /* MSA_MISC1 */
 424
 425         /* dcn new register
 426          * dc_crtc_timing is vesa dmt struct. data from edid
 427          */
 428         REG_SET_2(DP_MSA_TIMING_PARAM1, 0,
 429                         DP_MSA_HTOTAL, hw_crtc_timing.h_total,
 430                         DP_MSA_VTOTAL, hw_crtc_timing.v_total);
 431
 432         /* calculate from vesa timing parameters
 433          * h_active_start related to leading edge of sync
 434          */
 435
 436         h_blank = hw_crtc_timing.h_total - hw_crtc_timing.h_border_left -
 437                         hw_crtc_timing.h_addressable - hw_crtc_timing.h_border_right;
 438
 439         h_back_porch = h_blank - hw_crtc_timing.h_front_porch -
 440                         hw_crtc_timing.h_sync_width;
 441
 442         /* start at beginning of left border */
 443         h_active_start = hw_crtc_timing.h_sync_width + h_back_porch;
 444
 445
 446         v_active_start = hw_crtc_timing.v_total - hw_crtc_timing.v_border_top -
 447                         hw_crtc_timing.v_addressable - hw_crtc_timing.v_border_bottom -
 448                         hw_crtc_timing.v_front_porch;
 449
 450
 451         /* start at beginning of left border */
 452         REG_SET_2(DP_MSA_TIMING_PARAM2, 0,
 453                 DP_MSA_HSTART, h_active_start,
 454                 DP_MSA_VSTART, v_active_start);
 455
 456         REG_SET_4(DP_MSA_TIMING_PARAM3, 0,
 457                         DP_MSA_HSYNCWIDTH,
 458                         hw_crtc_timing.h_sync_width,
 459                         DP_MSA_HSYNCPOLARITY,
 460                         !hw_crtc_timing.flags.HSYNC_POSITIVE_POLARITY,
 461                         DP_MSA_VSYNCWIDTH,
 462                         hw_crtc_timing.v_sync_width,
 463                         DP_MSA_VSYNCPOLARITY,
 464                         !hw_crtc_timing.flags.VSYNC_POSITIVE_POLARITY);
 465
 466         /* HWDITH include border or overscan */
 467         REG_SET_2(DP_MSA_TIMING_PARAM4, 0,
 468                 DP_MSA_HWIDTH, hw_crtc_timing.h_border_left +
 469                 hw_crtc_timing.h_addressable + hw_crtc_timing.h_border_right,
 470                 DP_MSA_VHEIGHT, hw_crtc_timing.v_border_top +
 471                 hw_crtc_timing.v_addressable + hw_crtc_timing.v_border_bottom);
 472 }
 473
 474 static void enc1_stream_encoder_set_stream_attribute_helper(
 475                 struct dcn10_stream_encoder *enc1,
 476                 struct dc_crtc_timing *crtc_timing)
 477 {
 478         switch (crtc_timing->pixel_encoding) {
 479         case PIXEL_ENCODING_YCBCR422:
 480                 REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 1);
 481                 break;
 482         default:
 483                 REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 0);
 484                 break;
 485         }
 486         REG_UPDATE(DIG_FE_CNTL, TMDS_COLOR_FORMAT, 0);
 487 }
 488
 489 /* setup stream encoder in hdmi mode */
 490 void enc1_stream_encoder_hdmi_set_stream_attribute(
 491         struct stream_encoder *enc,
 492         struct dc_crtc_timing *crtc_timing,
 493         int actual_pix_clk_khz,
 494         bool enable_audio)
 495 {
 496         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
 497         struct bp_encoder_control cntl = {0};
 498
 499         cntl.action = ENCODER_CONTROL_SETUP;
 500         cntl.engine_id = enc1->base.id;
 501         cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
 502         cntl.enable_dp_audio = enable_audio;
 503         cntl.pixel_clock = actual_pix_clk_khz;
 504         cntl.lanes_number = LANE_COUNT_FOUR;
 505
 506         if (enc1->base.bp->funcs->encoder_control(
 507                         enc1->base.bp, &cntl) != BP_RESULT_OK)
 508                 return;
 509
 510         enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing);
 511
 512         /* setup HDMI engine */
 513         REG_UPDATE_5(HDMI_CONTROL,
 514                 HDMI_PACKET_GEN_VERSION, 1,
 515                 HDMI_KEEPOUT_MODE, 1,
 516                 HDMI_DEEP_COLOR_ENABLE, 0,
 517                 HDMI_DATA_SCRAMBLE_EN, 0,
 518                 HDMI_CLOCK_CHANNEL_RATE, 0);
 519
 520
 521         switch (crtc_timing->display_color_depth) {
 522         case COLOR_DEPTH_888:
 523                 REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
 524                 break;
 525         case COLOR_DEPTH_101010:
 526                 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
 527                         REG_UPDATE_2(HDMI_CONTROL,
 528                                         HDMI_DEEP_COLOR_DEPTH, 1,
 529                                         HDMI_DEEP_COLOR_ENABLE, 0);
 530                 } else {
 531                         REG_UPDATE_2(HDMI_CONTROL,
 532                                         HDMI_DEEP_COLOR_DEPTH, 1,
 533                                         HDMI_DEEP_COLOR_ENABLE, 1);
 534                         }
 535                 break;
 536         case COLOR_DEPTH_121212:
 537                 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
 538                         REG_UPDATE_2(HDMI_CONTROL,
 539                                         HDMI_DEEP_COLOR_DEPTH, 2,
 540                                         HDMI_DEEP_COLOR_ENABLE, 0);
 541                 } else {
 542                         REG_UPDATE_2(HDMI_CONTROL,
 543                                         HDMI_DEEP_COLOR_DEPTH, 2,
 544                                         HDMI_DEEP_COLOR_ENABLE, 1);
 545                         }
 546                 break;
 547         case COLOR_DEPTH_161616:
 548                 REG_UPDATE_2(HDMI_CONTROL,
 549                                 HDMI_DEEP_COLOR_DEPTH, 3,
 550                                 HDMI_DEEP_COLOR_ENABLE, 1);
 551                 break;
 552         default:
 553                 break;
 554         }
 555
 556         if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) {
 557                 /* enable HDMI data scrambler
 558                  * HDMI_CLOCK_CHANNEL_RATE_MORE_340M
 559                  * Clock channel frequency is 1/4 of character rate.
 560                  */
 561                 REG_UPDATE_2(HDMI_CONTROL,
 562                         HDMI_DATA_SCRAMBLE_EN, 1,
 563                         HDMI_CLOCK_CHANNEL_RATE, 1);
 564         } else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) {
 565
 566                 /* TODO: New feature for DCE11, still need to implement */
 567
 568                 /* enable HDMI data scrambler
 569                  * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE
 570                  * Clock channel frequency is the same
 571                  * as character rate
 572                  */
 573                 REG_UPDATE_2(HDMI_CONTROL,
 574                         HDMI_DATA_SCRAMBLE_EN, 1,
 575                         HDMI_CLOCK_CHANNEL_RATE, 0);
 576         }
 577
 578
 579         REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL,
 580                 HDMI_GC_CONT, 1,
 581                 HDMI_GC_SEND, 1,
 582                 HDMI_NULL_SEND, 1);
 583
 584         /* following belongs to audio */
 585         REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
 586
 587         REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
 588
 589         REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,
 590                                 VBI_LINE_0 + 2);
 591
 592         REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);
 593 }
 594
 595 /* setup stream encoder in dvi mode */
 596 void enc1_stream_encoder_dvi_set_stream_attribute(
 597         struct stream_encoder *enc,
 598         struct dc_crtc_timing *crtc_timing,
 599         bool is_dual_link)
 600 {
 601         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
 602         struct bp_encoder_control cntl = {0};
 603
 604         cntl.action = ENCODER_CONTROL_SETUP;
 605         cntl.engine_id = enc1->base.id;
 606         cntl.signal = is_dual_link ?
 607                         SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK;
 608         cntl.enable_dp_audio = false;
 609         cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10;
 610         cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
 611
 612         if (enc1->base.bp->funcs->encoder_control(
 613                         enc1->base.bp, &cntl) != BP_RESULT_OK)
 614                 return;
 615
 616         ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB);
 617         ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888);
 618         enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing);
 619 }
 620
 621 void enc1_stream_encoder_set_mst_bandwidth(
 622         struct stream_encoder *enc,
 623         struct fixed31_32 avg_time_slots_per_mtp)
 624 {
 625         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
 626         uint32_t x = dc_fixpt_floor(
 627                 avg_time_slots_per_mtp);
 628         uint32_t y = dc_fixpt_ceil(
 629                 dc_fixpt_shl(
 630                         dc_fixpt_sub_int(
 631                                 avg_time_slots_per_mtp,
 632                                 x),
 633                         26));
 634
 635         REG_SET_2(DP_MSE_RATE_CNTL, 0,
 636                 DP_MSE_RATE_X, x,
 637                 DP_MSE_RATE_Y, y);
 638
 639         /* wait for update to be completed on the link */
 640         /* i.e. DP_MSE_RATE_UPDATE_PENDING field (read only) */
 641         /* is reset to 0 (not pending) */
 642         REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING,
 643                         0,
 644                         10, DP_MST_UPDATE_MAX_RETRY);
 645 }
 646
 647 static void enc1_stream_encoder_update_hdmi_info_packets(
 648         struct stream_encoder *enc,
 649         const struct encoder_info_frame *info_frame)
 650 {
 651         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
 652
 653         /* for bring up, disable dp double  TODO */
 654         REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1);
 655
 656         enc1_update_hdmi_info_packet(enc1, 0, &info_frame->avi);
 657         enc1_update_hdmi_info_packet(enc1, 1, &info_frame->vendor);
 658         enc1_update_hdmi_info_packet(enc1, 2, &info_frame->gamut);
 659         enc1_update_hdmi_info_packet(enc1, 3, &info_frame->spd);
 660         enc1_update_hdmi_info_packet(enc1, 4, &info_frame->hdrsmd);
 661 }
 662
 663 static void enc1_stream_encoder_stop_hdmi_info_packets(
 664         struct stream_encoder *enc)
 665 {
 666         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
 667
 668         /* stop generic packets 0 & 1 on HDMI */
 669         REG_SET_6(HDMI_GENERIC_PACKET_CONTROL0, 0,
 670                 HDMI_GENERIC1_CONT, 0,
 671                 HDMI_GENERIC1_LINE, 0,
 672                 HDMI_GENERIC1_SEND, 0,
 673                 HDMI_GENERIC0_CONT, 0,
 674                 HDMI_GENERIC0_LINE, 0,
 675                 HDMI_GENERIC0_SEND, 0);
 676
 677         /* stop generic packets 2 & 3 on HDMI */
 678         REG_SET_6(HDMI_GENERIC_PACKET_CONTROL1, 0,
 679                 HDMI_GENERIC0_CONT, 0,
 680                 HDMI_GENERIC0_LINE, 0,
 681                 HDMI_GENERIC0_SEND, 0,
 682                 HDMI_GENERIC1_CONT, 0,
 683                 HDMI_GENERIC1_LINE, 0,
 684                 HDMI_GENERIC1_SEND, 0);
 685
 686         /* stop generic packets 2 & 3 on HDMI */
 687         REG_SET_6(HDMI_GENERIC_PACKET_CONTROL2, 0,
 688                 HDMI_GENERIC0_CONT, 0,
 689                 HDMI_GENERIC0_LINE, 0,
 690                 HDMI_GENERIC0_SEND, 0,
 691                 HDMI_GENERIC1_CONT, 0,
 692                 HDMI_GENERIC1_LINE, 0,
 693                 HDMI_GENERIC1_SEND, 0);
 694
 695         REG_SET_6(HDMI_GENERIC_PACKET_CONTROL3, 0,
 696                 HDMI_GENERIC0_CONT, 0,
 697                 HDMI_GENERIC0_LINE, 0,
 698                 HDMI_GENERIC0_SEND, 0,
 699                 HDMI_GENERIC1_CONT, 0,
 700                 HDMI_GENERIC1_LINE, 0,
 701                 HDMI_GENERIC1_SEND, 0);
 702 }
 703
 704 void enc1_stream_encoder_update_dp_info_packets(
 705         struct stream_encoder *enc,
 706         const struct encoder_info_frame *info_frame)
 707 {
 708         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
 709         uint32_t value = 0;
 710
 711         if (info_frame->vsc.valid)
 712                 enc1_update_generic_info_packet(
 713                                         enc1,
 714                                         0,  /* packetIndex */
 715                                         &info_frame->vsc);
 716
 717         if (info_frame->spd.valid)
 718                 enc1_update_generic_info_packet(
 719                                 enc1,
 720                                 2,  /* packetIndex */
 721                                 &info_frame->spd);
 722
 723         if (info_frame->hdrsmd.valid)
 724                 enc1_update_generic_info_packet(
 725                                 enc1,
 726                                 3,  /* packetIndex */
 727                                 &info_frame->hdrsmd);
 728
 729         if (info_frame->dpsdp.valid)
 730                 enc1_update_generic_info_packet(
 731                                 enc1,
 732                                 4,/* packetIndex */
 733                                 &info_frame->dpsdp);
 734
 735         /* enable/disable transmission of packet(s).
 736          * If enabled, packet transmission begins on the next frame
 737          */
 738         REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid);
 739         REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid);
 740         REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid);
 741         REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP4_ENABLE, info_frame->dpsdp.valid);
 742
 743         /* This bit is the master enable bit.
 744          * When enabling secondary stream engine,
 745          * this master bit must also be set.
 746          * This register shared with audio info frame.
 747          * Therefore we need to enable master bit
 748          * if at least on of the fields is not 0
 749          */
 750         value = REG_READ(DP_SEC_CNTL);
 751         if (value)
 752                 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
 753 }
 754
 755 void enc1_stream_encoder_stop_dp_info_packets(
 756         struct stream_encoder *enc)
 757 {
 758         /* stop generic packets on DP */
 759         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
 760         uint32_t value = 0;
 761
 762         REG_SET_10(DP_SEC_CNTL, 0,
 763                 DP_SEC_GSP0_ENABLE, 0,
 764                 DP_SEC_GSP1_ENABLE, 0,
 765                 DP_SEC_GSP2_ENABLE, 0,
 766                 DP_SEC_GSP3_ENABLE, 0,
 767                 DP_SEC_GSP4_ENABLE, 0,
 768                 DP_SEC_GSP5_ENABLE, 0,
 769                 DP_SEC_GSP6_ENABLE, 0,
 770                 DP_SEC_GSP7_ENABLE, 0,
 771                 DP_SEC_MPG_ENABLE, 0,
 772                 DP_SEC_STREAM_ENABLE, 0);
 773
 774         /* this register shared with audio info frame.
 775          * therefore we need to keep master enabled
 776          * if at least one of the fields is not 0 */
 777         value = REG_READ(DP_SEC_CNTL);
 778         if (value)
 779                 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
 780
 781 }
 782
 783 void enc1_stream_encoder_dp_blank(
 784         struct stream_encoder *enc)
 785 {
 786         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
 787         uint32_t  reg1 = 0;
 788         uint32_t max_retries = DP_BLANK_MAX_RETRY * 10;
 789
 790         /* Note: For CZ, we are changing driver default to disable
 791          * stream deferred to next VBLANK. If results are positive, we
 792          * will make the same change to all DCE versions. There are a
 793          * handful of panels that cannot handle disable stream at
 794          * HBLANK and will result in a white line flash across the
 795          * screen on stream disable.
 796          */
 797         REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, &reg1);
 798         if ((reg1 & 0x1) == 0)
 799                 /*stream not enabled*/
 800                 return;
 801         /* Specify the video stream disable point
 802          * (2 = start of the next vertical blank)
 803          */
 804         REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2);
 805         /* Larger delay to wait until VBLANK - use max retry of
 806          * 10us*5000=50ms. This covers 41.7ms of minimum 24 Hz mode +
 807          * a little more because we may not trust delay accuracy.
 808          */
 809         max_retries = DP_BLANK_MAX_RETRY * 250;
 810
 811         /* disable DP stream */
 812         REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
 813
 814         /* the encoder stops sending the video stream
 815          * at the start of the vertical blanking.
 816          * Poll for DP_VID_STREAM_STATUS == 0
 817          */
 818
 819         REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS,
 820                         0,
 821                         10, max_retries);
 822
 823         /* Tell the DP encoder to ignore timing from CRTC, must be done after
 824          * the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is
 825          * complete, stream status will be stuck in video stream enabled state,
 826          * i.e. DP_VID_STREAM_STATUS stuck at 1.
 827          */
 828
 829         REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, true);
 830 }
 831
 832 /* output video stream to link encoder */
 833 void enc1_stream_encoder_dp_unblank(
 834         struct stream_encoder *enc,
 835         const struct encoder_unblank_param *param)
 836 {
 837         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
 838
 839         if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) {
 840                 uint32_t n_vid = 0x8000;
 841                 uint32_t m_vid;
 842                 uint32_t n_multiply = 0;
 843                 uint64_t m_vid_l = n_vid;
 844
 845                 /* YCbCr 4:2:0 : Computed VID_M will be 2X the input rate */
 846                 if (param->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
 847                         /*this param->pixel_clk_khz is half of 444 rate for 420 already*/
 848                         n_multiply = 1;
 849                 }
 850                 /* M / N = Fstream / Flink
 851                  * m_vid / n_vid = pixel rate / link rate
 852                  */
 853
 854                 m_vid_l *= param->timing.pix_clk_100hz / 10;
 855                 m_vid_l = div_u64(m_vid_l,
 856                         param->link_settings.link_rate
 857                                 * LINK_RATE_REF_FREQ_IN_KHZ);
 858
 859                 m_vid = (uint32_t) m_vid_l;
 860
 861                 /* enable auto measurement */
 862
 863                 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);
 864
 865                 /* auto measurement need 1 full 0x8000 symbol cycle to kick in,
 866                  * therefore program initial value for Mvid and Nvid
 867                  */
 868
 869                 REG_UPDATE(DP_VID_N, DP_VID_N, n_vid);
 870
 871                 REG_UPDATE(DP_VID_M, DP_VID_M, m_vid);
 872
 873                 REG_UPDATE_2(DP_VID_TIMING,
 874                                 DP_VID_M_N_GEN_EN, 1,
 875                                 DP_VID_N_MUL, n_multiply);
 876         }
 877
 878         /* set DIG_START to 0x1 to resync FIFO */
 879
 880         REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);
 881
 882         /* switch DP encoder to CRTC data */
 883
 884         REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0);
 885
 886         /* wait 100us for DIG/DP logic to prime
 887          * (i.e. a few video lines)
 888          */
 889         udelay(100);
 890
 891         /* the hardware would start sending video at the start of the next DP
 892          * frame (i.e. rising edge of the vblank).
 893          * NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this
 894          * register has no effect on enable transition! HW always guarantees
 895          * VID_STREAM enable at start of next frame, and this is not
 896          * programmable
 897          */
 898
 899         REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);
 900 }
 901
 902 void enc1_stream_encoder_set_avmute(
 903         struct stream_encoder *enc,
 904         bool enable)
 905 {
 906         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
 907         unsigned int value = enable ? 1 : 0;
 908
 909         REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, value);
 910 }
 911
 912
 913 #define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000
 914 #define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1
 915
 916 #include "include/audio_types.h"
 917
 918 /**
 919 * speakersToChannels
 920 *
 921 * @brief
 922 *  translate speakers to channels
 923 *
 924 *  FL  - Front Left
 925 *  FR  - Front Right
 926 *  RL  - Rear Left
 927 *  RR  - Rear Right
 928 *  RC  - Rear Center
 929 *  FC  - Front Center
 930 *  FLC - Front Left Center
 931 *  FRC - Front Right Center
 932 *  RLC - Rear Left Center
 933 *  RRC - Rear Right Center
 934 *  LFE - Low Freq Effect
 935 *
 936 *               FC
 937 *          FLC      FRC
 938 *    FL                    FR
 939 *
 940 *                    LFE
 941 *              ()
 942 *
 943 *
 944 *    RL                    RR
 945 *          RLC      RRC
 946 *               RC
 947 *
 948 *             ch  8   7   6   5   4   3   2   1
 949 * 0b00000011      -   -   -   -   -   -   FR  FL
 950 * 0b00000111      -   -   -   -   -   LFE FR  FL
 951 * 0b00001011      -   -   -   -   FC  -   FR  FL
 952 * 0b00001111      -   -   -   -   FC  LFE FR  FL
 953 * 0b00010011      -   -   -   RC  -   -   FR  FL
 954 * 0b00010111      -   -   -   RC  -   LFE FR  FL
 955 * 0b00011011      -   -   -   RC  FC  -   FR  FL
 956 * 0b00011111      -   -   -   RC  FC  LFE FR  FL
 957 * 0b00110011      -   -   RR  RL  -   -   FR  FL
 958 * 0b00110111      -   -   RR  RL  -   LFE FR  FL
 959 * 0b00111011      -   -   RR  RL  FC  -   FR  FL
 960 * 0b00111111      -   -   RR  RL  FC  LFE FR  FL
 961 * 0b01110011      -   RC  RR  RL  -   -   FR  FL
 962 * 0b01110111      -   RC  RR  RL  -   LFE FR  FL
 963 * 0b01111011      -   RC  RR  RL  FC  -   FR  FL
 964 * 0b01111111      -   RC  RR  RL  FC  LFE FR  FL
 965 * 0b11110011      RRC RLC RR  RL  -   -   FR  FL
 966 * 0b11110111      RRC RLC RR  RL  -   LFE FR  FL
 967 * 0b11111011      RRC RLC RR  RL  FC  -   FR  FL
 968 * 0b11111111      RRC RLC RR  RL  FC  LFE FR  FL
 969 * 0b11000011      FRC FLC -   -   -   -   FR  FL
 970 * 0b11000111      FRC FLC -   -   -   LFE FR  FL
 971 * 0b11001011      FRC FLC -   -   FC  -   FR  FL
 972 * 0b11001111      FRC FLC -   -   FC  LFE FR  FL
 973 * 0b11010011      FRC FLC -   RC  -   -   FR  FL
 974 * 0b11010111      FRC FLC -   RC  -   LFE FR  FL
 975 * 0b11011011      FRC FLC -   RC  FC  -   FR  FL
 976 * 0b11011111      FRC FLC -   RC  FC  LFE FR  FL
 977 * 0b11110011      FRC FLC RR  RL  -   -   FR  FL
 978 * 0b11110111      FRC FLC RR  RL  -   LFE FR  FL
 979 * 0b11111011      FRC FLC RR  RL  FC  -   FR  FL
 980 * 0b11111111      FRC FLC RR  RL  FC  LFE FR  FL
 981 *
 982 * @param
 983 *  speakers - speaker information as it comes from CEA audio block
 984 */
 985 /* translate speakers to channels */
 986
 987 union audio_cea_channels {
 988         uint8_t all;
 989         struct audio_cea_channels_bits {
 990                 uint32_t FL:1;
 991                 uint32_t FR:1;
 992                 uint32_t LFE:1;
 993                 uint32_t FC:1;
 994                 uint32_t RL_RC:1;
 995                 uint32_t RR:1;
 996                 uint32_t RC_RLC_FLC:1;
 997                 uint32_t RRC_FRC:1;
 998         } channels;
 999 };
1000
1001 struct audio_clock_info {
1002         /* pixel clock frequency*/
1003         uint32_t pixel_clock_in_10khz;
1004         /* N - 32KHz audio */
1005         uint32_t n_32khz;
1006         /* CTS - 32KHz audio*/
1007         uint32_t cts_32khz;
1008         uint32_t n_44khz;
1009         uint32_t cts_44khz;
1010         uint32_t n_48khz;
1011         uint32_t cts_48khz;
1012 };
1013
1014 /* 25.2MHz/1.001*/
1015 /* 25.2MHz/1.001*/
1016 /* 25.2MHz*/
1017 /* 27MHz */
1018 /* 27MHz*1.001*/
1019 /* 27MHz*1.001*/
1020 /* 54MHz*/
1021 /* 54MHz*1.001*/
1022 /* 74.25MHz/1.001*/
1023 /* 74.25MHz*/
1024 /* 148.5MHz/1.001*/
1025 /* 148.5MHz*/
1026
1027 static const struct audio_clock_info audio_clock_info_table[16] = {
1028         {2517, 4576, 28125, 7007, 31250, 6864, 28125},
1029         {2518, 4576, 28125, 7007, 31250, 6864, 28125},
1030         {2520, 4096, 25200, 6272, 28000, 6144, 25200},
1031         {2700, 4096, 27000, 6272, 30000, 6144, 27000},
1032         {2702, 4096, 27027, 6272, 30030, 6144, 27027},
1033         {2703, 4096, 27027, 6272, 30030, 6144, 27027},
1034         {5400, 4096, 54000, 6272, 60000, 6144, 54000},
1035         {5405, 4096, 54054, 6272, 60060, 6144, 54054},
1036         {7417, 11648, 210937, 17836, 234375, 11648, 140625},
1037         {7425, 4096, 74250, 6272, 82500, 6144, 74250},
1038         {14835, 11648, 421875, 8918, 234375, 5824, 140625},
1039         {14850, 4096, 148500, 6272, 165000, 6144, 148500},
1040         {29670, 5824, 421875, 4459, 234375, 5824, 281250},
1041         {29700, 3072, 222750, 4704, 247500, 5120, 247500},
1042         {59340, 5824, 843750, 8918, 937500, 5824, 562500},
1043         {59400, 3072, 445500, 9408, 990000, 6144, 594000}
1044 };
1045
1046 static const struct audio_clock_info audio_clock_info_table_36bpc[14] = {
1047         {2517,  9152,  84375,  7007,  48875,  9152,  56250},
1048         {2518,  9152,  84375,  7007,  48875,  9152,  56250},
1049         {2520,  4096,  37800,  6272,  42000,  6144,  37800},
1050         {2700,  4096,  40500,  6272,  45000,  6144,  40500},
1051         {2702,  8192,  81081,  6272,  45045,  8192,  54054},
1052         {2703,  8192,  81081,  6272,  45045,  8192,  54054},
1053         {5400,  4096,  81000,  6272,  90000,  6144,  81000},
1054         {5405,  4096,  81081,  6272,  90090,  6144,  81081},
1055         {7417, 11648, 316406, 17836, 351562, 11648, 210937},
1056         {7425, 4096, 111375,  6272, 123750,  6144, 111375},
1057         {14835, 11648, 632812, 17836, 703125, 11648, 421875},
1058         {14850, 4096, 222750,  6272, 247500,  6144, 222750},
1059         {29670, 5824, 632812,  8918, 703125,  5824, 421875},
1060         {29700, 4096, 445500,  4704, 371250,  5120, 371250}
1061 };
1062
1063 static const struct audio_clock_info audio_clock_info_table_48bpc[14] = {
1064         {2517,  4576,  56250,  7007,  62500,  6864,  56250},
1065         {2518,  4576,  56250,  7007,  62500,  6864,  56250},
1066         {2520,  4096,  50400,  6272,  56000,  6144,  50400},
1067         {2700,  4096,  54000,  6272,  60000,  6144,  54000},
1068         {2702,  4096,  54054,  6267,  60060,  8192,  54054},
1069         {2703,  4096,  54054,  6272,  60060,  8192,  54054},
1070         {5400,  4096, 108000,  6272, 120000,  6144, 108000},
1071         {5405,  4096, 108108,  6272, 120120,  6144, 108108},
1072         {7417, 11648, 421875, 17836, 468750, 11648, 281250},
1073         {7425,  4096, 148500,  6272, 165000,  6144, 148500},
1074         {14835, 11648, 843750,  8918, 468750, 11648, 281250},
1075         {14850, 4096, 297000,  6272, 330000,  6144, 297000},
1076         {29670, 5824, 843750,  4459, 468750,  5824, 562500},
1077         {29700, 3072, 445500,  4704, 495000,  5120, 495000}
1078
1079
1080 };
1081
1082 static union audio_cea_channels speakers_to_channels(
1083         struct audio_speaker_flags speaker_flags)
1084 {
1085         union audio_cea_channels cea_channels = {0};
1086
1087         /* these are one to one */
1088         cea_channels.channels.FL = speaker_flags.FL_FR;
1089         cea_channels.channels.FR = speaker_flags.FL_FR;
1090         cea_channels.channels.LFE = speaker_flags.LFE;
1091         cea_channels.channels.FC = speaker_flags.FC;
1092
1093         /* if Rear Left and Right exist move RC speaker to channel 7
1094          * otherwise to channel 5
1095          */
1096         if (speaker_flags.RL_RR) {
1097                 cea_channels.channels.RL_RC = speaker_flags.RL_RR;
1098                 cea_channels.channels.RR = speaker_flags.RL_RR;
1099                 cea_channels.channels.RC_RLC_FLC = speaker_flags.RC;
1100         } else {
1101                 cea_channels.channels.RL_RC = speaker_flags.RC;
1102         }
1103
1104         /* FRONT Left Right Center and REAR Left Right Center are exclusive */
1105         if (speaker_flags.FLC_FRC) {
1106                 cea_channels.channels.RC_RLC_FLC = speaker_flags.FLC_FRC;
1107                 cea_channels.channels.RRC_FRC = speaker_flags.FLC_FRC;
1108         } else {
1109                 cea_channels.channels.RC_RLC_FLC = speaker_flags.RLC_RRC;
1110                 cea_channels.channels.RRC_FRC = speaker_flags.RLC_RRC;
1111         }
1112
1113         return cea_channels;
1114 }
1115
1116 static void get_audio_clock_info(
1117         enum dc_color_depth color_depth,
1118         uint32_t crtc_pixel_clock_in_khz,
1119         uint32_t actual_pixel_clock_in_khz,
1120         struct audio_clock_info *audio_clock_info)
1121 {
1122         const struct audio_clock_info *clock_info;
1123         uint32_t index;
1124         uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_in_khz / 10;
1125         uint32_t audio_array_size;
1126
1127         switch (color_depth) {
1128         case COLOR_DEPTH_161616:
1129                 clock_info = audio_clock_info_table_48bpc;
1130                 audio_array_size = ARRAY_SIZE(
1131                                 audio_clock_info_table_48bpc);
1132                 break;
1133         case COLOR_DEPTH_121212:
1134                 clock_info = audio_clock_info_table_36bpc;
1135                 audio_array_size = ARRAY_SIZE(
1136                                 audio_clock_info_table_36bpc);
1137                 break;
1138         default:
1139                 clock_info = audio_clock_info_table;
1140                 audio_array_size = ARRAY_SIZE(
1141                                 audio_clock_info_table);
1142                 break;
1143         }
1144
1145         if (clock_info != NULL) {
1146                 /* search for exact pixel clock in table */
1147                 for (index = 0; index < audio_array_size; index++) {
1148                         if (clock_info[index].pixel_clock_in_10khz >
1149                                 crtc_pixel_clock_in_10khz)
1150                                 break;  /* not match */
1151                         else if (clock_info[index].pixel_clock_in_10khz ==
1152                                         crtc_pixel_clock_in_10khz) {
1153                                 /* match found */
1154                                 *audio_clock_info = clock_info[index];
1155                                 return;
1156                         }
1157                 }
1158         }
1159
1160         /* not found */
1161         if (actual_pixel_clock_in_khz == 0)
1162                 actual_pixel_clock_in_khz = crtc_pixel_clock_in_khz;
1163
1164         /* See HDMI spec  the table entry under
1165          *  pixel clock of "Other". */
1166         audio_clock_info->pixel_clock_in_10khz =
1167                         actual_pixel_clock_in_khz / 10;
1168         audio_clock_info->cts_32khz = actual_pixel_clock_in_khz;
1169         audio_clock_info->cts_44khz = actual_pixel_clock_in_khz;
1170         audio_clock_info->cts_48khz = actual_pixel_clock_in_khz;
1171
1172         audio_clock_info->n_32khz = 4096;
1173         audio_clock_info->n_44khz = 6272;
1174         audio_clock_info->n_48khz = 6144;
1175 }
1176
1177 static void enc1_se_audio_setup(
1178         struct stream_encoder *enc,
1179         unsigned int az_inst,
1180         struct audio_info *audio_info)
1181 {
1182         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1183
1184         uint32_t speakers = 0;
1185         uint32_t channels = 0;
1186
1187         ASSERT(audio_info);
1188         if (audio_info == NULL)
1189                 /* This should not happen.it does so we don't get BSOD*/
1190                 return;
1191
1192         speakers = audio_info->flags.info.ALLSPEAKERS;
1193         channels = speakers_to_channels(audio_info->flags.speaker_flags).all;
1194
1195         /* setup the audio stream source select (audio -> dig mapping) */
1196         REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst);
1197
1198         /* Channel allocation */
1199         REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, channels);
1200 }
1201
1202 static void enc1_se_setup_hdmi_audio(
1203         struct stream_encoder *enc,
1204         const struct audio_crtc_info *crtc_info)
1205 {
1206         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1207
1208         struct audio_clock_info audio_clock_info = {0};
1209
1210         /* HDMI_AUDIO_PACKET_CONTROL */
1211         REG_UPDATE(HDMI_AUDIO_PACKET_CONTROL,
1212                         HDMI_AUDIO_DELAY_EN, 1);
1213
1214         /* AFMT_AUDIO_PACKET_CONTROL */
1215         REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1216
1217         /* AFMT_AUDIO_PACKET_CONTROL2 */
1218         REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
1219                         AFMT_AUDIO_LAYOUT_OVRD, 0,
1220                         AFMT_60958_OSF_OVRD, 0);
1221
1222         /* HDMI_ACR_PACKET_CONTROL */
1223         REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL,
1224                         HDMI_ACR_AUTO_SEND, 1,
1225                         HDMI_ACR_SOURCE, 0,
1226                         HDMI_ACR_AUDIO_PRIORITY, 0);
1227
1228         /* Program audio clock sample/regeneration parameters */
1229         get_audio_clock_info(crtc_info->color_depth,
1230                              crtc_info->requested_pixel_clock,
1231                              crtc_info->calculated_pixel_clock,
1232                              &audio_clock_info);
1233         DC_LOG_HW_AUDIO(
1234                         "\n%s:Input::requested_pixel_clock = %d"        \
1235                         "calculated_pixel_clock = %d \n", __func__,     \
1236                         crtc_info->requested_pixel_clock,               \
1237                         crtc_info->calculated_pixel_clock);
1238
1239         /* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */
1240         REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz);
1241
1242         /* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */
1243         REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz);
1244
1245         /* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */
1246         REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz);
1247
1248         /* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */
1249         REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz);
1250
1251         /* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */
1252         REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz);
1253
1254         /* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */
1255         REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz);
1256
1257         /* Video driver cannot know in advance which sample rate will
1258          * be used by HD Audio driver
1259          * HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is
1260          * programmed below in interruppt callback
1261          */
1262
1263         /* AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK &
1264          * AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK
1265          */
1266         REG_UPDATE_2(AFMT_60958_0,
1267                         AFMT_60958_CS_CHANNEL_NUMBER_L, 1,
1268                         AFMT_60958_CS_CLOCK_ACCURACY, 0);
1269
1270         /* AFMT_60958_1 AFMT_60958_CS_CHALNNEL_NUMBER_R */
1271         REG_UPDATE(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1272
1273         /* AFMT_60958_2 now keep this settings until
1274          * Programming guide comes out
1275          */
1276         REG_UPDATE_6(AFMT_60958_2,
1277                         AFMT_60958_CS_CHANNEL_NUMBER_2, 3,
1278                         AFMT_60958_CS_CHANNEL_NUMBER_3, 4,
1279                         AFMT_60958_CS_CHANNEL_NUMBER_4, 5,
1280                         AFMT_60958_CS_CHANNEL_NUMBER_5, 6,
1281                         AFMT_60958_CS_CHANNEL_NUMBER_6, 7,
1282                         AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1283 }
1284
1285 static void enc1_se_setup_dp_audio(
1286         struct stream_encoder *enc)
1287 {
1288         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1289
1290         /* --- DP Audio packet configurations --- */
1291
1292         /* ATP Configuration */
1293         REG_SET(DP_SEC_AUD_N, 0,
1294                         DP_SEC_AUD_N, DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT);
1295
1296         /* Async/auto-calc timestamp mode */
1297         REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE,
1298                         DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC);
1299
1300         /* --- The following are the registers
1301          *  copied from the SetupHDMI ---
1302          */
1303
1304         /* AFMT_AUDIO_PACKET_CONTROL */
1305         REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1306
1307         /* AFMT_AUDIO_PACKET_CONTROL2 */
1308         /* Program the ATP and AIP next */
1309         REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
1310                         AFMT_AUDIO_LAYOUT_OVRD, 0,
1311                         AFMT_60958_OSF_OVRD, 0);
1312
1313         /* AFMT_INFOFRAME_CONTROL0 */
1314         REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1315
1316         /* AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */
1317         REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0);
1318 }
1319
1320 static void enc1_se_enable_audio_clock(
1321         struct stream_encoder *enc,
1322         bool enable)
1323 {
1324         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1325
1326         if (REG(AFMT_CNTL) == 0)
1327                 return;   /* DCE8/10 does not have this register */
1328
1329         REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, !!enable);
1330
1331         /* wait for AFMT clock to turn on,
1332          * expectation: this should complete in 1-2 reads
1333          *
1334          * REG_WAIT(AFMT_CNTL, AFMT_AUDIO_CLOCK_ON, !!enable, 1, 10);
1335          *
1336          * TODO: wait for clock_on does not work well. May need HW
1337          * program sequence. But audio seems work normally even without wait
1338          * for clock_on status change
1339          */
1340 }
1341
1342 static void enc1_se_enable_dp_audio(
1343         struct stream_encoder *enc)
1344 {
1345         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1346
1347         /* Enable Audio packets */
1348         REG_UPDATE(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1);
1349
1350         /* Program the ATP and AIP next */
1351         REG_UPDATE_2(DP_SEC_CNTL,
1352                         DP_SEC_ATP_ENABLE, 1,
1353                         DP_SEC_AIP_ENABLE, 1);
1354
1355         /* Program STREAM_ENABLE after all the other enables. */
1356         REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
1357 }
1358
1359 static void enc1_se_disable_dp_audio(
1360         struct stream_encoder *enc)
1361 {
1362         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1363         uint32_t value = 0;
1364
1365         /* Disable Audio packets */
1366         REG_UPDATE_5(DP_SEC_CNTL,
1367                         DP_SEC_ASP_ENABLE, 0,
1368                         DP_SEC_ATP_ENABLE, 0,
1369                         DP_SEC_AIP_ENABLE, 0,
1370                         DP_SEC_ACM_ENABLE, 0,
1371                         DP_SEC_STREAM_ENABLE, 0);
1372
1373         /* This register shared with encoder info frame. Therefore we need to
1374          * keep master enabled if at least on of the fields is not 0
1375          */
1376         value = REG_READ(DP_SEC_CNTL);
1377         if (value != 0)
1378                 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
1379
1380 }
1381
1382 void enc1_se_audio_mute_control(
1383         struct stream_encoder *enc,
1384         bool mute)
1385 {
1386         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1387
1388         REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, !mute);
1389 }
1390
1391 void enc1_se_dp_audio_setup(
1392         struct stream_encoder *enc,
1393         unsigned int az_inst,
1394         struct audio_info *info)
1395 {
1396         enc1_se_audio_setup(enc, az_inst, info);
1397 }
1398
1399 void enc1_se_dp_audio_enable(
1400         struct stream_encoder *enc)
1401 {
1402         enc1_se_enable_audio_clock(enc, true);
1403         enc1_se_setup_dp_audio(enc);
1404         enc1_se_enable_dp_audio(enc);
1405 }
1406
1407 void enc1_se_dp_audio_disable(
1408         struct stream_encoder *enc)
1409 {
1410         enc1_se_disable_dp_audio(enc);
1411         enc1_se_enable_audio_clock(enc, false);
1412 }
1413
1414 void enc1_se_hdmi_audio_setup(
1415         struct stream_encoder *enc,
1416         unsigned int az_inst,
1417         struct audio_info *info,
1418         struct audio_crtc_info *audio_crtc_info)
1419 {
1420         enc1_se_enable_audio_clock(enc, true);
1421         enc1_se_setup_hdmi_audio(enc, audio_crtc_info);
1422         enc1_se_audio_setup(enc, az_inst, info);
1423 }
1424
1425 void enc1_se_hdmi_audio_disable(
1426         struct stream_encoder *enc)
1427 {
1428         enc1_se_enable_audio_clock(enc, false);
1429 }
1430
1431
1432 void enc1_setup_stereo_sync(
1433         struct stream_encoder *enc,
1434         int tg_inst, bool enable)
1435 {
1436         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1437         REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst);
1438         REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable);
1439 }
1440
1441 void enc1_dig_connect_to_otg(
1442         struct stream_encoder *enc,
1443         int tg_inst)
1444 {
1445         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1446
1447         REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst);
1448 }
1449
1450 static const struct stream_encoder_funcs dcn10_str_enc_funcs = {
1451         .dp_set_stream_attribute =
1452                 enc1_stream_encoder_dp_set_stream_attribute,
1453         .hdmi_set_stream_attribute =
1454                 enc1_stream_encoder_hdmi_set_stream_attribute,
1455         .dvi_set_stream_attribute =
1456                 enc1_stream_encoder_dvi_set_stream_attribute,
1457         .set_mst_bandwidth =
1458                 enc1_stream_encoder_set_mst_bandwidth,
1459         .update_hdmi_info_packets =
1460                 enc1_stream_encoder_update_hdmi_info_packets,
1461         .stop_hdmi_info_packets =
1462                 enc1_stream_encoder_stop_hdmi_info_packets,
1463         .update_dp_info_packets =
1464                 enc1_stream_encoder_update_dp_info_packets,
1465         .stop_dp_info_packets =
1466                 enc1_stream_encoder_stop_dp_info_packets,
1467         .dp_blank =
1468                 enc1_stream_encoder_dp_blank,
1469         .dp_unblank =
1470                 enc1_stream_encoder_dp_unblank,
1471         .audio_mute_control = enc1_se_audio_mute_control,
1472
1473         .dp_audio_setup = enc1_se_dp_audio_setup,
1474         .dp_audio_enable = enc1_se_dp_audio_enable,
1475         .dp_audio_disable = enc1_se_dp_audio_disable,
1476
1477         .hdmi_audio_setup = enc1_se_hdmi_audio_setup,
1478         .hdmi_audio_disable = enc1_se_hdmi_audio_disable,
1479         .setup_stereo_sync  = enc1_setup_stereo_sync,
1480         .set_avmute = enc1_stream_encoder_set_avmute,
1481         .dig_connect_to_otg  = enc1_dig_connect_to_otg,
1482 };
1483
1484 void dcn10_stream_encoder_construct(
1485         struct dcn10_stream_encoder *enc1,
1486         struct dc_context *ctx,
1487         struct dc_bios *bp,
1488         enum engine_id eng_id,
1489         const struct dcn10_stream_enc_registers *regs,
1490         const struct dcn10_stream_encoder_shift *se_shift,
1491         const struct dcn10_stream_encoder_mask *se_mask)
1492 {
1493         enc1->base.funcs = &dcn10_str_enc_funcs;
1494         enc1->base.ctx = ctx;
1495         enc1->base.id = eng_id;
1496         enc1->base.bp = bp;
1497         enc1->regs = regs;
1498         enc1->se_shift = se_shift;
1499         enc1->se_mask = se_mask;
1500 }
1501