drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c

   1 /*
   2 * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/slab.h>
  27
  28 #include "dm_services.h"
  29 #include "dc.h"
  30
  31 #include "dcn10_init.h"
  32
  33 #include "resource.h"
  34 #include "include/irq_service_interface.h"
  35 #include "dcn10_resource.h"
  36 #include "dcn10_ipp.h"
  37 #include "dcn10_mpc.h"
  38 #include "irq/dcn10/irq_service_dcn10.h"
  39 #include "dcn10_dpp.h"
  40 #include "dcn10_optc.h"
  41 #include "dcn10_hw_sequencer.h"
  42 #include "dce110/dce110_hw_sequencer.h"
  43 #include "dcn10_opp.h"
  44 #include "dcn10_link_encoder.h"
  45 #include "dcn10_stream_encoder.h"
  46 #include "dce/dce_clock_source.h"
  47 #include "dce/dce_audio.h"
  48 #include "dce/dce_hwseq.h"
  49 #include "virtual/virtual_stream_encoder.h"
  50 #include "dce110/dce110_resource.h"
  51 #include "dce112/dce112_resource.h"
  52 #include "dcn10_hubp.h"
  53 #include "dcn10_hubbub.h"
  54
  55 #include "soc15_hw_ip.h"
  56 #include "vega10_ip_offset.h"
  57
  58 #include "dcn/dcn_1_0_offset.h"
  59 #include "dcn/dcn_1_0_sh_mask.h"
  60
  61 #include "nbio/nbio_7_0_offset.h"
  62
  63 #include "mmhub/mmhub_9_1_offset.h"
  64 #include "mmhub/mmhub_9_1_sh_mask.h"
  65
  66 #include "reg_helper.h"
  67 #include "dce/dce_abm.h"
  68 #include "dce/dce_dmcu.h"
  69 #include "dce/dce_aux.h"
  70 #include "dce/dce_i2c.h"
  71
  72 const struct _vcs_dpi_ip_params_st dcn1_0_ip = {
  73         .rob_buffer_size_kbytes = 64,
  74         .det_buffer_size_kbytes = 164,
  75         .dpte_buffer_size_in_pte_reqs_luma = 42,
  76         .dpp_output_buffer_pixels = 2560,
  77         .opp_output_buffer_lines = 1,
  78         .pixel_chunk_size_kbytes = 8,
  79         .pte_enable = 1,
  80         .pte_chunk_size_kbytes = 2,
  81         .meta_chunk_size_kbytes = 2,
  82         .writeback_chunk_size_kbytes = 2,
  83         .line_buffer_size_bits = 589824,
  84         .max_line_buffer_lines = 12,
  85         .IsLineBufferBppFixed = 0,
  86         .LineBufferFixedBpp = -1,
  87         .writeback_luma_buffer_size_kbytes = 12,
  88         .writeback_chroma_buffer_size_kbytes = 8,
  89         .max_num_dpp = 4,
  90         .max_num_wb = 2,
  91         .max_dchub_pscl_bw_pix_per_clk = 4,
  92         .max_pscl_lb_bw_pix_per_clk = 2,
  93         .max_lb_vscl_bw_pix_per_clk = 4,
  94         .max_vscl_hscl_bw_pix_per_clk = 4,
  95         .max_hscl_ratio = 4,
  96         .max_vscl_ratio = 4,
  97         .hscl_mults = 4,
  98         .vscl_mults = 4,
  99         .max_hscl_taps = 8,
 100         .max_vscl_taps = 8,
 101         .dispclk_ramp_margin_percent = 1,
 102         .underscan_factor = 1.10,
 103         .min_vblank_lines = 14,
 104         .dppclk_delay_subtotal = 90,
 105         .dispclk_delay_subtotal = 42,
 106         .dcfclk_cstate_latency = 10,
 107         .max_inter_dcn_tile_repeaters = 8,
 108         .can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one = 0,
 109         .bug_forcing_LC_req_same_size_fixed = 0,
 110 };
 111
 112 const struct _vcs_dpi_soc_bounding_box_st dcn1_0_soc = {
 113         .sr_exit_time_us = 9.0,
 114         .sr_enter_plus_exit_time_us = 11.0,
 115         .urgent_latency_us = 4.0,
 116         .writeback_latency_us = 12.0,
 117         .ideal_dram_bw_after_urgent_percent = 80.0,
 118         .max_request_size_bytes = 256,
 119         .downspread_percent = 0.5,
 120         .dram_page_open_time_ns = 50.0,
 121         .dram_rw_turnaround_time_ns = 17.5,
 122         .dram_return_buffer_per_channel_bytes = 8192,
 123         .round_trip_ping_latency_dcfclk_cycles = 128,
 124         .urgent_out_of_order_return_per_channel_bytes = 256,
 125         .channel_interleave_bytes = 256,
 126         .num_banks = 8,
 127         .num_chans = 2,
 128         .vmm_page_size_bytes = 4096,
 129         .dram_clock_change_latency_us = 17.0,
 130         .writeback_dram_clock_change_latency_us = 23.0,
 131         .return_bus_width_bytes = 64,
 132 };
 133
 134 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
 135         #define mmDP0_DP_DPHY_INTERNAL_CTRL             0x210f
 136         #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
 137         #define mmDP1_DP_DPHY_INTERNAL_CTRL             0x220f
 138         #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
 139         #define mmDP2_DP_DPHY_INTERNAL_CTRL             0x230f
 140         #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
 141         #define mmDP3_DP_DPHY_INTERNAL_CTRL             0x240f
 142         #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
 143         #define mmDP4_DP_DPHY_INTERNAL_CTRL             0x250f
 144         #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
 145         #define mmDP5_DP_DPHY_INTERNAL_CTRL             0x260f
 146         #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
 147         #define mmDP6_DP_DPHY_INTERNAL_CTRL             0x270f
 148         #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
 149 #endif
 150
 151
 152 enum dcn10_clk_src_array_id {
 153         DCN10_CLK_SRC_PLL0,
 154         DCN10_CLK_SRC_PLL1,
 155         DCN10_CLK_SRC_PLL2,
 156         DCN10_CLK_SRC_PLL3,
 157         DCN10_CLK_SRC_TOTAL,
 158         DCN101_CLK_SRC_TOTAL = DCN10_CLK_SRC_PLL3
 159 };
 160
 161 /* begin *********************
 162  * macros to expend register list macro defined in HW object header file */
 163
 164 /* DCN */
 165 #define BASE_INNER(seg) \
 166         DCE_BASE__INST0_SEG ## seg
 167
 168 #define BASE(seg) \
 169         BASE_INNER(seg)
 170
 171 #define SR(reg_name)\
 172                 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
 173                                         mm ## reg_name
 174
 175 #define SRI(reg_name, block, id)\
 176         .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 177                                         mm ## block ## id ## _ ## reg_name
 178
 179
 180 #define SRII(reg_name, block, id)\
 181         .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 182                                         mm ## block ## id ## _ ## reg_name
 183
 184 /* NBIO */
 185 #define NBIO_BASE_INNER(seg) \
 186         NBIF_BASE__INST0_SEG ## seg
 187
 188 #define NBIO_BASE(seg) \
 189         NBIO_BASE_INNER(seg)
 190
 191 #define NBIO_SR(reg_name)\
 192                 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) +  \
 193                                         mm ## reg_name
 194
 195 /* MMHUB */
 196 #define MMHUB_BASE_INNER(seg) \
 197         MMHUB_BASE__INST0_SEG ## seg
 198
 199 #define MMHUB_BASE(seg) \
 200         MMHUB_BASE_INNER(seg)
 201
 202 #define MMHUB_SR(reg_name)\
 203                 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) +  \
 204                                         mm ## reg_name
 205
 206 /* macros to expend register list macro defined in HW object header file
 207  * end *********************/
 208
 209
 210 static const struct dce_dmcu_registers dmcu_regs = {
 211                 DMCU_DCN10_REG_LIST()
 212 };
 213
 214 static const struct dce_dmcu_shift dmcu_shift = {
 215                 DMCU_MASK_SH_LIST_DCN10(__SHIFT)
 216 };
 217
 218 static const struct dce_dmcu_mask dmcu_mask = {
 219                 DMCU_MASK_SH_LIST_DCN10(_MASK)
 220 };
 221
 222 static const struct dce_abm_registers abm_regs = {
 223                 ABM_DCN10_REG_LIST(0)
 224 };
 225
 226 static const struct dce_abm_shift abm_shift = {
 227                 ABM_MASK_SH_LIST_DCN10(__SHIFT)
 228 };
 229
 230 static const struct dce_abm_mask abm_mask = {
 231                 ABM_MASK_SH_LIST_DCN10(_MASK)
 232 };
 233
 234 #define stream_enc_regs(id)\
 235 [id] = {\
 236         SE_DCN_REG_LIST(id)\
 237 }
 238
 239 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
 240         stream_enc_regs(0),
 241         stream_enc_regs(1),
 242         stream_enc_regs(2),
 243         stream_enc_regs(3),
 244 };
 245
 246 static const struct dcn10_stream_encoder_shift se_shift = {
 247                 SE_COMMON_MASK_SH_LIST_DCN10(__SHIFT)
 248 };
 249
 250 static const struct dcn10_stream_encoder_mask se_mask = {
 251                 SE_COMMON_MASK_SH_LIST_DCN10(_MASK)
 252 };
 253
 254 #define audio_regs(id)\
 255 [id] = {\
 256                 AUD_COMMON_REG_LIST(id)\
 257 }
 258
 259 static const struct dce_audio_registers audio_regs[] = {
 260         audio_regs(0),
 261         audio_regs(1),
 262         audio_regs(2),
 263         audio_regs(3),
 264 };
 265
 266 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
 267                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
 268                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
 269                 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
 270
 271 static const struct dce_audio_shift audio_shift = {
 272                 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
 273 };
 274
 275 static const struct dce_audio_mask audio_mask = {
 276                 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
 277 };
 278
 279 #define aux_regs(id)\
 280 [id] = {\
 281         AUX_REG_LIST(id)\
 282 }
 283
 284 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
 285                 aux_regs(0),
 286                 aux_regs(1),
 287                 aux_regs(2),
 288                 aux_regs(3)
 289 };
 290
 291 #define hpd_regs(id)\
 292 [id] = {\
 293         HPD_REG_LIST(id)\
 294 }
 295
 296 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
 297                 hpd_regs(0),
 298                 hpd_regs(1),
 299                 hpd_regs(2),
 300                 hpd_regs(3)
 301 };
 302
 303 #define link_regs(id)\
 304 [id] = {\
 305         LE_DCN10_REG_LIST(id), \
 306         SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
 307 }
 308
 309 static const struct dcn10_link_enc_registers link_enc_regs[] = {
 310         link_regs(0),
 311         link_regs(1),
 312         link_regs(2),
 313         link_regs(3)
 314 };
 315
 316 static const struct dcn10_link_enc_shift le_shift = {
 317                 LINK_ENCODER_MASK_SH_LIST_DCN10(__SHIFT)
 318 };
 319
 320 static const struct dcn10_link_enc_mask le_mask = {
 321                 LINK_ENCODER_MASK_SH_LIST_DCN10(_MASK)
 322 };
 323
 324 static const struct dce110_aux_registers_shift aux_shift = {
 325         DCN10_AUX_MASK_SH_LIST(__SHIFT)
 326 };
 327
 328 static const struct dce110_aux_registers_mask aux_mask = {
 329         DCN10_AUX_MASK_SH_LIST(_MASK)
 330 };
 331
 332 #define ipp_regs(id)\
 333 [id] = {\
 334         IPP_REG_LIST_DCN10(id),\
 335 }
 336
 337 static const struct dcn10_ipp_registers ipp_regs[] = {
 338         ipp_regs(0),
 339         ipp_regs(1),
 340         ipp_regs(2),
 341         ipp_regs(3),
 342 };
 343
 344 static const struct dcn10_ipp_shift ipp_shift = {
 345                 IPP_MASK_SH_LIST_DCN10(__SHIFT)
 346 };
 347
 348 static const struct dcn10_ipp_mask ipp_mask = {
 349                 IPP_MASK_SH_LIST_DCN10(_MASK),
 350 };
 351
 352 #define opp_regs(id)\
 353 [id] = {\
 354         OPP_REG_LIST_DCN10(id),\
 355 }
 356
 357 static const struct dcn10_opp_registers opp_regs[] = {
 358         opp_regs(0),
 359         opp_regs(1),
 360         opp_regs(2),
 361         opp_regs(3),
 362 };
 363
 364 static const struct dcn10_opp_shift opp_shift = {
 365                 OPP_MASK_SH_LIST_DCN10(__SHIFT)
 366 };
 367
 368 static const struct dcn10_opp_mask opp_mask = {
 369                 OPP_MASK_SH_LIST_DCN10(_MASK),
 370 };
 371
 372 #define aux_engine_regs(id)\
 373 [id] = {\
 374         AUX_COMMON_REG_LIST(id), \
 375         .AUX_RESET_MASK = 0 \
 376 }
 377
 378 static const struct dce110_aux_registers aux_engine_regs[] = {
 379                 aux_engine_regs(0),
 380                 aux_engine_regs(1),
 381                 aux_engine_regs(2),
 382                 aux_engine_regs(3),
 383                 aux_engine_regs(4),
 384                 aux_engine_regs(5)
 385 };
 386
 387 #define tf_regs(id)\
 388 [id] = {\
 389         TF_REG_LIST_DCN10(id),\
 390 }
 391
 392 static const struct dcn_dpp_registers tf_regs[] = {
 393         tf_regs(0),
 394         tf_regs(1),
 395         tf_regs(2),
 396         tf_regs(3),
 397 };
 398
 399 static const struct dcn_dpp_shift tf_shift = {
 400         TF_REG_LIST_SH_MASK_DCN10(__SHIFT),
 401         TF_DEBUG_REG_LIST_SH_DCN10
 402
 403 };
 404
 405 static const struct dcn_dpp_mask tf_mask = {
 406         TF_REG_LIST_SH_MASK_DCN10(_MASK),
 407         TF_DEBUG_REG_LIST_MASK_DCN10
 408 };
 409
 410 static const struct dcn_mpc_registers mpc_regs = {
 411                 MPC_COMMON_REG_LIST_DCN1_0(0),
 412                 MPC_COMMON_REG_LIST_DCN1_0(1),
 413                 MPC_COMMON_REG_LIST_DCN1_0(2),
 414                 MPC_COMMON_REG_LIST_DCN1_0(3),
 415                 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(0),
 416                 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(1),
 417                 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(2),
 418                 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(3)
 419 };
 420
 421 static const struct dcn_mpc_shift mpc_shift = {
 422         MPC_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT)
 423 };
 424
 425 static const struct dcn_mpc_mask mpc_mask = {
 426         MPC_COMMON_MASK_SH_LIST_DCN1_0(_MASK),
 427 };
 428
 429 #define tg_regs(id)\
 430 [id] = {TG_COMMON_REG_LIST_DCN1_0(id)}
 431
 432 static const struct dcn_optc_registers tg_regs[] = {
 433         tg_regs(0),
 434         tg_regs(1),
 435         tg_regs(2),
 436         tg_regs(3),
 437 };
 438
 439 static const struct dcn_optc_shift tg_shift = {
 440         TG_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT)
 441 };
 442
 443 static const struct dcn_optc_mask tg_mask = {
 444         TG_COMMON_MASK_SH_LIST_DCN1_0(_MASK)
 445 };
 446
 447 static const struct bios_registers bios_regs = {
 448                 NBIO_SR(BIOS_SCRATCH_3),
 449                 NBIO_SR(BIOS_SCRATCH_6)
 450 };
 451
 452 #define hubp_regs(id)\
 453 [id] = {\
 454         HUBP_REG_LIST_DCN10(id)\
 455 }
 456
 457 static const struct dcn_mi_registers hubp_regs[] = {
 458         hubp_regs(0),
 459         hubp_regs(1),
 460         hubp_regs(2),
 461         hubp_regs(3),
 462 };
 463
 464 static const struct dcn_mi_shift hubp_shift = {
 465                 HUBP_MASK_SH_LIST_DCN10(__SHIFT)
 466 };
 467
 468 static const struct dcn_mi_mask hubp_mask = {
 469                 HUBP_MASK_SH_LIST_DCN10(_MASK)
 470 };
 471
 472 static const struct dcn_hubbub_registers hubbub_reg = {
 473                 HUBBUB_REG_LIST_DCN10(0)
 474 };
 475
 476 static const struct dcn_hubbub_shift hubbub_shift = {
 477                 HUBBUB_MASK_SH_LIST_DCN10(__SHIFT)
 478 };
 479
 480 static const struct dcn_hubbub_mask hubbub_mask = {
 481                 HUBBUB_MASK_SH_LIST_DCN10(_MASK)
 482 };
 483
 484 static int map_transmitter_id_to_phy_instance(
 485         enum transmitter transmitter)
 486 {
 487         switch (transmitter) {
 488         case TRANSMITTER_UNIPHY_A:
 489                 return 0;
 490         break;
 491         case TRANSMITTER_UNIPHY_B:
 492                 return 1;
 493         break;
 494         case TRANSMITTER_UNIPHY_C:
 495                 return 2;
 496         break;
 497         case TRANSMITTER_UNIPHY_D:
 498                 return 3;
 499         break;
 500         default:
 501                 ASSERT(0);
 502                 return 0;
 503         }
 504 }
 505
 506 #define clk_src_regs(index, pllid)\
 507 [index] = {\
 508         CS_COMMON_REG_LIST_DCN1_0(index, pllid),\
 509 }
 510
 511 static const struct dce110_clk_src_regs clk_src_regs[] = {
 512         clk_src_regs(0, A),
 513         clk_src_regs(1, B),
 514         clk_src_regs(2, C),
 515         clk_src_regs(3, D)
 516 };
 517
 518 static const struct dce110_clk_src_shift cs_shift = {
 519                 CS_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT)
 520 };
 521
 522 static const struct dce110_clk_src_mask cs_mask = {
 523                 CS_COMMON_MASK_SH_LIST_DCN1_0(_MASK)
 524 };
 525
 526 static const struct resource_caps res_cap = {
 527                 .num_timing_generator = 4,
 528                 .num_opp = 4,
 529                 .num_video_plane = 4,
 530                 .num_audio = 4,
 531                 .num_stream_encoder = 4,
 532                 .num_pll = 4,
 533                 .num_ddc = 4,
 534 };
 535
 536 static const struct resource_caps rv2_res_cap = {
 537                 .num_timing_generator = 3,
 538                 .num_opp = 3,
 539                 .num_video_plane = 3,
 540                 .num_audio = 3,
 541                 .num_stream_encoder = 3,
 542                 .num_pll = 3,
 543                 .num_ddc = 4,
 544 };
 545
 546 static const struct dc_plane_cap plane_cap = {
 547         .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
 548         .blends_with_above = true,
 549         .blends_with_below = true,
 550         .per_pixel_alpha = true,
 551
 552         .pixel_format_support = {
 553                         .argb8888 = true,
 554                         .nv12 = true,
 555                         .fp16 = true,
 556                         .p010 = true
 557         },
 558
 559         .max_upscale_factor = {
 560                         .argb8888 = 16000,
 561                         .nv12 = 16000,
 562                         .fp16 = 1
 563         },
 564
 565         .max_downscale_factor = {
 566                         .argb8888 = 250,
 567                         .nv12 = 250,
 568                         .fp16 = 1
 569         }
 570 };
 571
 572 static const struct dc_debug_options debug_defaults_drv = {
 573                 .sanity_checks = true,
 574                 .disable_dmcu = false,
 575                 .force_abm_enable = false,
 576                 .timing_trace = false,
 577                 .clock_trace = true,
 578
 579                 /* raven smu dones't allow 0 disp clk,
 580                  * smu min disp clk limit is 50Mhz
 581                  * keep min disp clk 100Mhz avoid smu hang
 582                  */
 583                 .min_disp_clk_khz = 100000,
 584
 585                 .disable_pplib_clock_request = false,
 586                 .disable_pplib_wm_range = false,
 587                 .pplib_wm_report_mode = WM_REPORT_DEFAULT,
 588                 .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
 589                 .force_single_disp_pipe_split = true,
 590                 .disable_dcc = DCC_ENABLE,
 591                 .voltage_align_fclk = true,
 592                 .disable_stereo_support = true,
 593                 .vsr_support = true,
 594                 .performance_trace = false,
 595                 .az_endpoint_mute_only = true,
 596                 .recovery_enabled = false, /*enable this by default after testing.*/
 597                 .max_downscale_src_width = 3840,
 598                 .underflow_assert_delay_us = 0xFFFFFFFF,
 599 };
 600
 601 static const struct dc_debug_options debug_defaults_diags = {
 602                 .disable_dmcu = false,
 603                 .force_abm_enable = false,
 604                 .timing_trace = true,
 605                 .clock_trace = true,
 606                 .disable_stutter = true,
 607                 .disable_pplib_clock_request = true,
 608                 .disable_pplib_wm_range = true,
 609                 .underflow_assert_delay_us = 0xFFFFFFFF,
 610 };
 611
 612 static void dcn10_dpp_destroy(struct dpp **dpp)
 613 {
 614         kfree(TO_DCN10_DPP(*dpp));
 615         *dpp = NULL;
 616 }
 617
 618 static struct dpp *dcn10_dpp_create(
 619         struct dc_context *ctx,
 620         uint32_t inst)
 621 {
 622         struct dcn10_dpp *dpp =
 623                 kzalloc(sizeof(struct dcn10_dpp), GFP_KERNEL);
 624
 625         if (!dpp)
 626                 return NULL;
 627
 628         dpp1_construct(dpp, ctx, inst,
 629                        &tf_regs[inst], &tf_shift, &tf_mask);
 630         return &dpp->base;
 631 }
 632
 633 static struct input_pixel_processor *dcn10_ipp_create(
 634         struct dc_context *ctx, uint32_t inst)
 635 {
 636         struct dcn10_ipp *ipp =
 637                 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);
 638
 639         if (!ipp) {
 640                 BREAK_TO_DEBUGGER();
 641                 return NULL;
 642         }
 643
 644         dcn10_ipp_construct(ipp, ctx, inst,
 645                         &ipp_regs[inst], &ipp_shift, &ipp_mask);
 646         return &ipp->base;
 647 }
 648
 649
 650 static struct output_pixel_processor *dcn10_opp_create(
 651         struct dc_context *ctx, uint32_t inst)
 652 {
 653         struct dcn10_opp *opp =
 654                 kzalloc(sizeof(struct dcn10_opp), GFP_KERNEL);
 655
 656         if (!opp) {
 657                 BREAK_TO_DEBUGGER();
 658                 return NULL;
 659         }
 660
 661         dcn10_opp_construct(opp, ctx, inst,
 662                         &opp_regs[inst], &opp_shift, &opp_mask);
 663         return &opp->base;
 664 }
 665
 666 struct dce_aux *dcn10_aux_engine_create(
 667         struct dc_context *ctx,
 668         uint32_t inst)
 669 {
 670         struct aux_engine_dce110 *aux_engine =
 671                 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
 672
 673         if (!aux_engine)
 674                 return NULL;
 675
 676         dce110_aux_engine_construct(aux_engine, ctx, inst,
 677                                     SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
 678                                     &aux_engine_regs[inst],
 679                                         &aux_mask,
 680                                         &aux_shift,
 681                                         ctx->dc->caps.extended_aux_timeout_support);
 682
 683         return &aux_engine->base;
 684 }
 685 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
 686
 687 static const struct dce_i2c_registers i2c_hw_regs[] = {
 688                 i2c_inst_regs(1),
 689                 i2c_inst_regs(2),
 690                 i2c_inst_regs(3),
 691                 i2c_inst_regs(4),
 692                 i2c_inst_regs(5),
 693                 i2c_inst_regs(6),
 694 };
 695
 696 static const struct dce_i2c_shift i2c_shifts = {
 697                 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
 698 };
 699
 700 static const struct dce_i2c_mask i2c_masks = {
 701                 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
 702 };
 703
 704 struct dce_i2c_hw *dcn10_i2c_hw_create(
 705         struct dc_context *ctx,
 706         uint32_t inst)
 707 {
 708         struct dce_i2c_hw *dce_i2c_hw =
 709                 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
 710
 711         if (!dce_i2c_hw)
 712                 return NULL;
 713
 714         dcn1_i2c_hw_construct(dce_i2c_hw, ctx, inst,
 715                                     &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
 716
 717         return dce_i2c_hw;
 718 }
 719 static struct mpc *dcn10_mpc_create(struct dc_context *ctx)
 720 {
 721         struct dcn10_mpc *mpc10 = kzalloc(sizeof(struct dcn10_mpc),
 722                                           GFP_KERNEL);
 723
 724         if (!mpc10)
 725                 return NULL;
 726
 727         dcn10_mpc_construct(mpc10, ctx,
 728                         &mpc_regs,
 729                         &mpc_shift,
 730                         &mpc_mask,
 731                         4);
 732
 733         return &mpc10->base;
 734 }
 735
 736 static struct hubbub *dcn10_hubbub_create(struct dc_context *ctx)
 737 {
 738         struct dcn10_hubbub *dcn10_hubbub = kzalloc(sizeof(struct dcn10_hubbub),
 739                                           GFP_KERNEL);
 740
 741         if (!dcn10_hubbub)
 742                 return NULL;
 743
 744         hubbub1_construct(&dcn10_hubbub->base, ctx,
 745                         &hubbub_reg,
 746                         &hubbub_shift,
 747                         &hubbub_mask);
 748
 749         return &dcn10_hubbub->base;
 750 }
 751
 752 static struct timing_generator *dcn10_timing_generator_create(
 753                 struct dc_context *ctx,
 754                 uint32_t instance)
 755 {
 756         struct optc *tgn10 =
 757                 kzalloc(sizeof(struct optc), GFP_KERNEL);
 758
 759         if (!tgn10)
 760                 return NULL;
 761
 762         tgn10->base.inst = instance;
 763         tgn10->base.ctx = ctx;
 764
 765         tgn10->tg_regs = &tg_regs[instance];
 766         tgn10->tg_shift = &tg_shift;
 767         tgn10->tg_mask = &tg_mask;
 768
 769         dcn10_timing_generator_init(tgn10);
 770
 771         return &tgn10->base;
 772 }
 773
 774 static const struct encoder_feature_support link_enc_feature = {
 775                 .max_hdmi_deep_color = COLOR_DEPTH_121212,
 776                 .max_hdmi_pixel_clock = 600000,
 777                 .hdmi_ycbcr420_supported = true,
 778                 .dp_ycbcr420_supported = false,
 779                 .flags.bits.IS_HBR2_CAPABLE = true,
 780                 .flags.bits.IS_HBR3_CAPABLE = true,
 781                 .flags.bits.IS_TPS3_CAPABLE = true,
 782                 .flags.bits.IS_TPS4_CAPABLE = true
 783 };
 784
 785 struct link_encoder *dcn10_link_encoder_create(
 786         const struct encoder_init_data *enc_init_data)
 787 {
 788         struct dcn10_link_encoder *enc10 =
 789                 kzalloc(sizeof(struct dcn10_link_encoder), GFP_KERNEL);
 790         int link_regs_id;
 791
 792         if (!enc10)
 793                 return NULL;
 794
 795         link_regs_id =
 796                 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
 797
 798         dcn10_link_encoder_construct(enc10,
 799                                       enc_init_data,
 800                                       &link_enc_feature,
 801                                       &link_enc_regs[link_regs_id],
 802                                       &link_enc_aux_regs[enc_init_data->channel - 1],
 803                                       &link_enc_hpd_regs[enc_init_data->hpd_source],
 804                                       &le_shift,
 805                                       &le_mask);
 806
 807         return &enc10->base;
 808 }
 809
 810 struct clock_source *dcn10_clock_source_create(
 811         struct dc_context *ctx,
 812         struct dc_bios *bios,
 813         enum clock_source_id id,
 814         const struct dce110_clk_src_regs *regs,
 815         bool dp_clk_src)
 816 {
 817         struct dce110_clk_src *clk_src =
 818                 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
 819
 820         if (!clk_src)
 821                 return NULL;
 822
 823         if (dce112_clk_src_construct(clk_src, ctx, bios, id,
 824                         regs, &cs_shift, &cs_mask)) {
 825                 clk_src->base.dp_clk_src = dp_clk_src;
 826                 return &clk_src->base;
 827         }
 828
 829         kfree(clk_src);
 830         BREAK_TO_DEBUGGER();
 831         return NULL;
 832 }
 833
 834 static void read_dce_straps(
 835         struct dc_context *ctx,
 836         struct resource_straps *straps)
 837 {
 838         generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
 839                 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
 840 }
 841
 842 static struct audio *create_audio(
 843                 struct dc_context *ctx, unsigned int inst)
 844 {
 845         return dce_audio_create(ctx, inst,
 846                         &audio_regs[inst], &audio_shift, &audio_mask);
 847 }
 848
 849 static struct stream_encoder *dcn10_stream_encoder_create(
 850         enum engine_id eng_id,
 851         struct dc_context *ctx)
 852 {
 853         struct dcn10_stream_encoder *enc1 =
 854                 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
 855
 856         if (!enc1)
 857                 return NULL;
 858
 859         dcn10_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
 860                                         &stream_enc_regs[eng_id],
 861                                         &se_shift, &se_mask);
 862         return &enc1->base;
 863 }
 864
 865 static const struct dce_hwseq_registers hwseq_reg = {
 866                 HWSEQ_DCN1_REG_LIST()
 867 };
 868
 869 static const struct dce_hwseq_shift hwseq_shift = {
 870                 HWSEQ_DCN1_MASK_SH_LIST(__SHIFT)
 871 };
 872
 873 static const struct dce_hwseq_mask hwseq_mask = {
 874                 HWSEQ_DCN1_MASK_SH_LIST(_MASK)
 875 };
 876
 877 static struct dce_hwseq *dcn10_hwseq_create(
 878         struct dc_context *ctx)
 879 {
 880         struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
 881
 882         if (hws) {
 883                 hws->ctx = ctx;
 884                 hws->regs = &hwseq_reg;
 885                 hws->shifts = &hwseq_shift;
 886                 hws->masks = &hwseq_mask;
 887                 hws->wa.DEGVIDCN10_253 = true;
 888                 hws->wa.false_optc_underflow = true;
 889                 hws->wa.DEGVIDCN10_254 = true;
 890         }
 891         return hws;
 892 }
 893
 894 static const struct resource_create_funcs res_create_funcs = {
 895         .read_dce_straps = read_dce_straps,
 896         .create_audio = create_audio,
 897         .create_stream_encoder = dcn10_stream_encoder_create,
 898         .create_hwseq = dcn10_hwseq_create,
 899 };
 900
 901 static const struct resource_create_funcs res_create_maximus_funcs = {
 902         .read_dce_straps = NULL,
 903         .create_audio = NULL,
 904         .create_stream_encoder = NULL,
 905         .create_hwseq = dcn10_hwseq_create,
 906 };
 907
 908 void dcn10_clock_source_destroy(struct clock_source **clk_src)
 909 {
 910         kfree(TO_DCE110_CLK_SRC(*clk_src));
 911         *clk_src = NULL;
 912 }
 913
 914 static struct pp_smu_funcs *dcn10_pp_smu_create(struct dc_context *ctx)
 915 {
 916         struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
 917
 918         if (!pp_smu)
 919                 return pp_smu;
 920
 921         dm_pp_get_funcs(ctx, pp_smu);
 922         return pp_smu;
 923 }
 924
 925 static void dcn10_resource_destruct(struct dcn10_resource_pool *pool)
 926 {
 927         unsigned int i;
 928
 929         for (i = 0; i < pool->base.stream_enc_count; i++) {
 930                 if (pool->base.stream_enc[i] != NULL) {
 931                         kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
 932                         pool->base.stream_enc[i] = NULL;
 933                 }
 934         }
 935
 936         if (pool->base.mpc != NULL) {
 937                 kfree(TO_DCN10_MPC(pool->base.mpc));
 938                 pool->base.mpc = NULL;
 939         }
 940
 941         if (pool->base.hubbub != NULL) {
 942                 kfree(pool->base.hubbub);
 943                 pool->base.hubbub = NULL;
 944         }
 945
 946         for (i = 0; i < pool->base.pipe_count; i++) {
 947                 if (pool->base.opps[i] != NULL)
 948                         pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
 949
 950                 if (pool->base.dpps[i] != NULL)
 951                         dcn10_dpp_destroy(&pool->base.dpps[i]);
 952
 953                 if (pool->base.ipps[i] != NULL)
 954                         pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
 955
 956                 if (pool->base.hubps[i] != NULL) {
 957                         kfree(TO_DCN10_HUBP(pool->base.hubps[i]));
 958                         pool->base.hubps[i] = NULL;
 959                 }
 960
 961                 if (pool->base.irqs != NULL) {
 962                         dal_irq_service_destroy(&pool->base.irqs);
 963                 }
 964
 965                 if (pool->base.timing_generators[i] != NULL)    {
 966                         kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
 967                         pool->base.timing_generators[i] = NULL;
 968                 }
 969         }
 970
 971         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
 972                 if (pool->base.engines[i] != NULL)
 973                         dce110_engine_destroy(&pool->base.engines[i]);
 974                 if (pool->base.hw_i2cs[i] != NULL) {
 975                         kfree(pool->base.hw_i2cs[i]);
 976                         pool->base.hw_i2cs[i] = NULL;
 977                 }
 978                 if (pool->base.sw_i2cs[i] != NULL) {
 979                         kfree(pool->base.sw_i2cs[i]);
 980                         pool->base.sw_i2cs[i] = NULL;
 981                 }
 982         }
 983
 984         for (i = 0; i < pool->base.audio_count; i++) {
 985                 if (pool->base.audios[i])
 986                         dce_aud_destroy(&pool->base.audios[i]);
 987         }
 988
 989         for (i = 0; i < pool->base.clk_src_count; i++) {
 990                 if (pool->base.clock_sources[i] != NULL) {
 991                         dcn10_clock_source_destroy(&pool->base.clock_sources[i]);
 992                         pool->base.clock_sources[i] = NULL;
 993                 }
 994         }
 995
 996         if (pool->base.dp_clock_source != NULL) {
 997                 dcn10_clock_source_destroy(&pool->base.dp_clock_source);
 998                 pool->base.dp_clock_source = NULL;
 999         }
1000
1001         if (pool->base.abm != NULL)
1002                 dce_abm_destroy(&pool->base.abm);
1003
1004         if (pool->base.dmcu != NULL)
1005                 dce_dmcu_destroy(&pool->base.dmcu);
1006
1007         kfree(pool->base.pp_smu);
1008 }
1009
1010 static struct hubp *dcn10_hubp_create(
1011         struct dc_context *ctx,
1012         uint32_t inst)
1013 {
1014         struct dcn10_hubp *hubp1 =
1015                 kzalloc(sizeof(struct dcn10_hubp), GFP_KERNEL);
1016
1017         if (!hubp1)
1018                 return NULL;
1019
1020         dcn10_hubp_construct(hubp1, ctx, inst,
1021                              &hubp_regs[inst], &hubp_shift, &hubp_mask);
1022         return &hubp1->base;
1023 }
1024
1025 static void get_pixel_clock_parameters(
1026         const struct pipe_ctx *pipe_ctx,
1027         struct pixel_clk_params *pixel_clk_params)
1028 {
1029         const struct dc_stream_state *stream = pipe_ctx->stream;
1030         pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
1031         pixel_clk_params->encoder_object_id = stream->link->link_enc->id;
1032         pixel_clk_params->signal_type = pipe_ctx->stream->signal;
1033         pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
1034         /* TODO: un-hardcode*/
1035         pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
1036                 LINK_RATE_REF_FREQ_IN_KHZ;
1037         pixel_clk_params->flags.ENABLE_SS = 0;
1038         pixel_clk_params->color_depth =
1039                 stream->timing.display_color_depth;
1040         pixel_clk_params->flags.DISPLAY_BLANKED = 1;
1041         pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
1042
1043         if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
1044                 pixel_clk_params->color_depth = COLOR_DEPTH_888;
1045
1046         if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
1047                 pixel_clk_params->requested_pix_clk_100hz  /= 2;
1048         if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1049                 pixel_clk_params->requested_pix_clk_100hz *= 2;
1050
1051 }
1052
1053 static void build_clamping_params(struct dc_stream_state *stream)
1054 {
1055         stream->clamping.clamping_level = CLAMPING_FULL_RANGE;
1056         stream->clamping.c_depth = stream->timing.display_color_depth;
1057         stream->clamping.pixel_encoding = stream->timing.pixel_encoding;
1058 }
1059
1060 static void build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
1061 {
1062
1063         get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
1064
1065         pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
1066                 pipe_ctx->clock_source,
1067                 &pipe_ctx->stream_res.pix_clk_params,
1068                 &pipe_ctx->pll_settings);
1069
1070         pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
1071
1072         resource_build_bit_depth_reduction_params(pipe_ctx->stream,
1073                                         &pipe_ctx->stream->bit_depth_params);
1074         build_clamping_params(pipe_ctx->stream);
1075 }
1076
1077 static enum dc_status build_mapped_resource(
1078                 const struct dc *dc,
1079                 struct dc_state *context,
1080                 struct dc_stream_state *stream)
1081 {
1082         struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
1083
1084         /*TODO Seems unneeded anymore */
1085         /*      if (old_context && resource_is_stream_unchanged(old_context, stream)) {
1086                         if (stream != NULL && old_context->streams[i] != NULL) {
1087                                  todo: shouldn't have to copy missing parameter here
1088                                 resource_build_bit_depth_reduction_params(stream,
1089                                                 &stream->bit_depth_params);
1090                                 stream->clamping.pixel_encoding =
1091                                                 stream->timing.pixel_encoding;
1092
1093                                 resource_build_bit_depth_reduction_params(stream,
1094                                                                 &stream->bit_depth_params);
1095                                 build_clamping_params(stream);
1096
1097                                 continue;
1098                         }
1099                 }
1100         */
1101
1102         if (!pipe_ctx)
1103                 return DC_ERROR_UNEXPECTED;
1104
1105         build_pipe_hw_param(pipe_ctx);
1106         return DC_OK;
1107 }
1108
1109 enum dc_status dcn10_add_stream_to_ctx(
1110                 struct dc *dc,
1111                 struct dc_state *new_ctx,
1112                 struct dc_stream_state *dc_stream)
1113 {
1114         enum dc_status result = DC_ERROR_UNEXPECTED;
1115
1116         result = resource_map_pool_resources(dc, new_ctx, dc_stream);
1117
1118         if (result == DC_OK)
1119                 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
1120
1121
1122         if (result == DC_OK)
1123                 result = build_mapped_resource(dc, new_ctx, dc_stream);
1124
1125         return result;
1126 }
1127
1128 static struct pipe_ctx *dcn10_acquire_idle_pipe_for_layer(
1129                 struct dc_state *context,
1130                 const struct resource_pool *pool,
1131                 struct dc_stream_state *stream)
1132 {
1133         struct resource_context *res_ctx = &context->res_ctx;
1134         struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
1135         struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool, head_pipe);
1136
1137         if (!head_pipe) {
1138                 ASSERT(0);
1139                 return NULL;
1140         }
1141
1142         if (!idle_pipe)
1143                 return NULL;
1144
1145         idle_pipe->stream = head_pipe->stream;
1146         idle_pipe->stream_res.tg = head_pipe->stream_res.tg;
1147         idle_pipe->stream_res.abm = head_pipe->stream_res.abm;
1148         idle_pipe->stream_res.opp = head_pipe->stream_res.opp;
1149
1150         idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
1151         idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
1152         idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
1153         idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
1154
1155         return idle_pipe;
1156 }
1157
1158 static bool dcn10_get_dcc_compression_cap(const struct dc *dc,
1159                 const struct dc_dcc_surface_param *input,
1160                 struct dc_surface_dcc_cap *output)
1161 {
1162         return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(
1163                         dc->res_pool->hubbub,
1164                         input,
1165                         output);
1166 }
1167
1168 static void dcn10_destroy_resource_pool(struct resource_pool **pool)
1169 {
1170         struct dcn10_resource_pool *dcn10_pool = TO_DCN10_RES_POOL(*pool);
1171
1172         dcn10_resource_destruct(dcn10_pool);
1173         kfree(dcn10_pool);
1174         *pool = NULL;
1175 }
1176
1177 static enum dc_status dcn10_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps)
1178 {
1179         if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
1180                         && caps->max_video_width != 0
1181                         && plane_state->src_rect.width > caps->max_video_width)
1182                 return DC_FAIL_SURFACE_VALIDATE;
1183
1184         return DC_OK;
1185 }
1186
1187 static enum dc_status dcn10_validate_global(struct dc *dc, struct dc_state *context)
1188 {
1189         int i, j;
1190         bool video_down_scaled = false;
1191         bool video_large = false;
1192         bool desktop_large = false;
1193         bool dcc_disabled = false;
1194
1195         for (i = 0; i < context->stream_count; i++) {
1196                 if (context->stream_status[i].plane_count == 0)
1197                         continue;
1198
1199                 if (context->stream_status[i].plane_count > 2)
1200                         return DC_FAIL_UNSUPPORTED_1;
1201
1202                 for (j = 0; j < context->stream_status[i].plane_count; j++) {
1203                         struct dc_plane_state *plane =
1204                                 context->stream_status[i].plane_states[j];
1205
1206
1207                         if (plane->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
1208
1209                                 if (plane->src_rect.width > plane->dst_rect.width ||
1210                                                 plane->src_rect.height > plane->dst_rect.height)
1211                                         video_down_scaled = true;
1212
1213                                 if (plane->src_rect.width >= 3840)
1214                                         video_large = true;
1215
1216                         } else {
1217                                 if (plane->src_rect.width >= 3840)
1218                                         desktop_large = true;
1219                                 if (!plane->dcc.enable)
1220                                         dcc_disabled = true;
1221                         }
1222                 }
1223         }
1224
1225         /*
1226          * Workaround: On DCN10 there is UMC issue that causes underflow when
1227          * playing 4k video on 4k desktop with video downscaled and single channel
1228          * memory
1229          */
1230         if (video_large && desktop_large && video_down_scaled && dcc_disabled &&
1231                         dc->dcn_soc->number_of_channels == 1)
1232                 return DC_FAIL_SURFACE_VALIDATE;
1233
1234         return DC_OK;
1235 }
1236
1237 static enum dc_status dcn10_patch_unknown_plane_state(struct dc_plane_state *plane_state)
1238 {
1239         enum dc_status result = DC_OK;
1240
1241         enum surface_pixel_format surf_pix_format = plane_state->format;
1242         unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format);
1243
1244         enum swizzle_mode_values swizzle = DC_SW_LINEAR;
1245
1246         if (bpp == 64)
1247                 swizzle = DC_SW_64KB_D;
1248         else
1249                 swizzle = DC_SW_64KB_S;
1250
1251         plane_state->tiling_info.gfx9.swizzle = swizzle;
1252         return result;
1253 }
1254
1255 struct stream_encoder *dcn10_find_first_free_match_stream_enc_for_link(
1256                 struct resource_context *res_ctx,
1257                 const struct resource_pool *pool,
1258                 struct dc_stream_state *stream)
1259 {
1260         int i;
1261         int j = -1;
1262         struct dc_link *link = stream->link;
1263
1264         for (i = 0; i < pool->stream_enc_count; i++) {
1265                 if (!res_ctx->is_stream_enc_acquired[i] &&
1266                                 pool->stream_enc[i]) {
1267                         /* Store first available for MST second display
1268                          * in daisy chain use case
1269                          */
1270                         j = i;
1271                         if (pool->stream_enc[i]->id ==
1272                                         link->link_enc->preferred_engine)
1273                                 return pool->stream_enc[i];
1274                 }
1275         }
1276
1277         /*
1278          * For CZ and later, we can allow DIG FE and BE to differ for all display types
1279          */
1280
1281         if (j >= 0)
1282                 return pool->stream_enc[j];
1283
1284         return NULL;
1285 }
1286
1287 static const struct dc_cap_funcs cap_funcs = {
1288         .get_dcc_compression_cap = dcn10_get_dcc_compression_cap
1289 };
1290
1291 static const struct resource_funcs dcn10_res_pool_funcs = {
1292         .destroy = dcn10_destroy_resource_pool,
1293         .link_enc_create = dcn10_link_encoder_create,
1294         .validate_bandwidth = dcn_validate_bandwidth,
1295         .acquire_idle_pipe_for_layer = dcn10_acquire_idle_pipe_for_layer,
1296         .validate_plane = dcn10_validate_plane,
1297         .validate_global = dcn10_validate_global,
1298         .add_stream_to_ctx = dcn10_add_stream_to_ctx,
1299         .patch_unknown_plane_state = dcn10_patch_unknown_plane_state,
1300         .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link
1301 };
1302
1303 static uint32_t read_pipe_fuses(struct dc_context *ctx)
1304 {
1305         uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0);
1306         /* RV1 support max 4 pipes */
1307         value = value & 0xf;
1308         return value;
1309 }
1310
1311 static bool dcn10_resource_construct(
1312         uint8_t num_virtual_links,
1313         struct dc *dc,
1314         struct dcn10_resource_pool *pool)
1315 {
1316         int i;
1317         int j;
1318         struct dc_context *ctx = dc->ctx;
1319         uint32_t pipe_fuses = read_pipe_fuses(ctx);
1320
1321         ctx->dc_bios->regs = &bios_regs;
1322
1323         if (ctx->dce_version == DCN_VERSION_1_01)
1324                 pool->base.res_cap = &rv2_res_cap;
1325         else
1326                 pool->base.res_cap = &res_cap;
1327         pool->base.funcs = &dcn10_res_pool_funcs;
1328
1329         /*
1330          * TODO fill in from actual raven resource when we create
1331          * more than virtual encoder
1332          */
1333
1334         /*************************************************
1335          *  Resource + asic cap harcoding                *
1336          *************************************************/
1337         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1338
1339         /* max pipe num for ASIC before check pipe fuses */
1340         pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1341
1342         if (dc->ctx->dce_version == DCN_VERSION_1_01)
1343                 pool->base.pipe_count = 3;
1344         dc->caps.max_video_width = 3840;
1345         dc->caps.max_downscale_ratio = 200;
1346         dc->caps.i2c_speed_in_khz = 100;
1347         dc->caps.max_cursor_size = 256;
1348         dc->caps.max_slave_planes = 1;
1349         dc->caps.is_apu = true;
1350         dc->caps.post_blend_color_processing = false;
1351         dc->caps.extended_aux_timeout_support = false;
1352
1353         /* Raven DP PHY HBR2 eye diagram pattern is not stable. Use TP4 */
1354         dc->caps.force_dp_tps4_for_cp2520 = true;
1355
1356         if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1357                 dc->debug = debug_defaults_drv;
1358         else
1359                 dc->debug = debug_defaults_diags;
1360
1361         /*************************************************
1362          *  Create resources                             *
1363          *************************************************/
1364
1365         pool->base.clock_sources[DCN10_CLK_SRC_PLL0] =
1366                         dcn10_clock_source_create(ctx, ctx->dc_bios,
1367                                 CLOCK_SOURCE_COMBO_PHY_PLL0,
1368                                 &clk_src_regs[0], false);
1369         pool->base.clock_sources[DCN10_CLK_SRC_PLL1] =
1370                         dcn10_clock_source_create(ctx, ctx->dc_bios,
1371                                 CLOCK_SOURCE_COMBO_PHY_PLL1,
1372                                 &clk_src_regs[1], false);
1373         pool->base.clock_sources[DCN10_CLK_SRC_PLL2] =
1374                         dcn10_clock_source_create(ctx, ctx->dc_bios,
1375                                 CLOCK_SOURCE_COMBO_PHY_PLL2,
1376                                 &clk_src_regs[2], false);
1377
1378         if (dc->ctx->dce_version == DCN_VERSION_1_0) {
1379                 pool->base.clock_sources[DCN10_CLK_SRC_PLL3] =
1380                                 dcn10_clock_source_create(ctx, ctx->dc_bios,
1381                                         CLOCK_SOURCE_COMBO_PHY_PLL3,
1382                                         &clk_src_regs[3], false);
1383         }
1384
1385         pool->base.clk_src_count = DCN10_CLK_SRC_TOTAL;
1386
1387         if (dc->ctx->dce_version == DCN_VERSION_1_01)
1388                 pool->base.clk_src_count = DCN101_CLK_SRC_TOTAL;
1389
1390         pool->base.dp_clock_source =
1391                         dcn10_clock_source_create(ctx, ctx->dc_bios,
1392                                 CLOCK_SOURCE_ID_DP_DTO,
1393                                 /* todo: not reuse phy_pll registers */
1394                                 &clk_src_regs[0], true);
1395
1396         for (i = 0; i < pool->base.clk_src_count; i++) {
1397                 if (pool->base.clock_sources[i] == NULL) {
1398                         dm_error("DC: failed to create clock sources!\n");
1399                         BREAK_TO_DEBUGGER();
1400                         goto fail;
1401                 }
1402         }
1403
1404         pool->base.dmcu = dcn10_dmcu_create(ctx,
1405                         &dmcu_regs,
1406                         &dmcu_shift,
1407                         &dmcu_mask);
1408         if (pool->base.dmcu == NULL) {
1409                 dm_error("DC: failed to create dmcu!\n");
1410                 BREAK_TO_DEBUGGER();
1411                 goto fail;
1412         }
1413
1414         pool->base.abm = dce_abm_create(ctx,
1415                         &abm_regs,
1416                         &abm_shift,
1417                         &abm_mask);
1418         if (pool->base.abm == NULL) {
1419                 dm_error("DC: failed to create abm!\n");
1420                 BREAK_TO_DEBUGGER();
1421                 goto fail;
1422         }
1423
1424         dml_init_instance(&dc->dml, &dcn1_0_soc, &dcn1_0_ip, DML_PROJECT_RAVEN1);
1425         memcpy(dc->dcn_ip, &dcn10_ip_defaults, sizeof(dcn10_ip_defaults));
1426         memcpy(dc->dcn_soc, &dcn10_soc_defaults, sizeof(dcn10_soc_defaults));
1427
1428         if (dc->ctx->dce_version == DCN_VERSION_1_01) {
1429                 struct dcn_soc_bounding_box *dcn_soc = dc->dcn_soc;
1430                 struct dcn_ip_params *dcn_ip = dc->dcn_ip;
1431                 struct display_mode_lib *dml = &dc->dml;
1432
1433                 dml->ip.max_num_dpp = 3;
1434                 /* TODO how to handle 23.84? */
1435                 dcn_soc->dram_clock_change_latency = 23;
1436                 dcn_ip->max_num_dpp = 3;
1437         }
1438         if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) {
1439                 dc->dcn_soc->urgent_latency = 3;
1440                 dc->debug.disable_dmcu = true;
1441                 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 41.60f;
1442         }
1443
1444
1445         dc->dcn_soc->number_of_channels = dc->ctx->asic_id.vram_width / ddr4_dram_width;
1446         ASSERT(dc->dcn_soc->number_of_channels < 3);
1447         if (dc->dcn_soc->number_of_channels == 0)/*old sbios bug*/
1448                 dc->dcn_soc->number_of_channels = 2;
1449
1450         if (dc->dcn_soc->number_of_channels == 1) {
1451                 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 19.2f;
1452                 dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 = 17.066f;
1453                 dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = 14.933f;
1454                 dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = 12.8f;
1455                 if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) {
1456                         dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 20.80f;
1457                 }
1458         }
1459
1460         pool->base.pp_smu = dcn10_pp_smu_create(ctx);
1461
1462         /*
1463          * Right now SMU/PPLIB and DAL all have the AZ D3 force PME notification *
1464          * implemented. So AZ D3 should work.For issue 197007.                   *
1465          */
1466         if (pool->base.pp_smu != NULL
1467                         && pool->base.pp_smu->rv_funcs.set_pme_wa_enable != NULL)
1468                 dc->debug.az_endpoint_mute_only = false;
1469
1470         if (!dc->debug.disable_pplib_clock_request)
1471                 dcn_bw_update_from_pplib(dc);
1472         dcn_bw_sync_calcs_and_dml(dc);
1473         if (!dc->debug.disable_pplib_wm_range) {
1474                 dc->res_pool = &pool->base;
1475                 dcn_bw_notify_pplib_of_wm_ranges(dc);
1476         }
1477
1478         {
1479                 struct irq_service_init_data init_data;
1480                 init_data.ctx = dc->ctx;
1481                 pool->base.irqs = dal_irq_service_dcn10_create(&init_data);
1482                 if (!pool->base.irqs)
1483                         goto fail;
1484         }
1485
1486         /* index to valid pipe resource  */
1487         j = 0;
1488         /* mem input -> ipp -> dpp -> opp -> TG */
1489         for (i = 0; i < pool->base.pipe_count; i++) {
1490                 /* if pipe is disabled, skip instance of HW pipe,
1491                  * i.e, skip ASIC register instance
1492                  */
1493                 if ((pipe_fuses & (1 << i)) != 0)
1494                         continue;
1495
1496                 pool->base.hubps[j] = dcn10_hubp_create(ctx, i);
1497                 if (pool->base.hubps[j] == NULL) {
1498                         BREAK_TO_DEBUGGER();
1499                         dm_error(
1500                                 "DC: failed to create memory input!\n");
1501                         goto fail;
1502                 }
1503
1504                 pool->base.ipps[j] = dcn10_ipp_create(ctx, i);
1505                 if (pool->base.ipps[j] == NULL) {
1506                         BREAK_TO_DEBUGGER();
1507                         dm_error(
1508                                 "DC: failed to create input pixel processor!\n");
1509                         goto fail;
1510                 }
1511
1512                 pool->base.dpps[j] = dcn10_dpp_create(ctx, i);
1513                 if (pool->base.dpps[j] == NULL) {
1514                         BREAK_TO_DEBUGGER();
1515                         dm_error(
1516                                 "DC: failed to create dpp!\n");
1517                         goto fail;
1518                 }
1519
1520                 pool->base.opps[j] = dcn10_opp_create(ctx, i);
1521                 if (pool->base.opps[j] == NULL) {
1522                         BREAK_TO_DEBUGGER();
1523                         dm_error(
1524                                 "DC: failed to create output pixel processor!\n");
1525                         goto fail;
1526                 }
1527
1528                 pool->base.timing_generators[j] = dcn10_timing_generator_create(
1529                                 ctx, i);
1530                 if (pool->base.timing_generators[j] == NULL) {
1531                         BREAK_TO_DEBUGGER();
1532                         dm_error("DC: failed to create tg!\n");
1533                         goto fail;
1534                 }
1535                 /* check next valid pipe */
1536                 j++;
1537         }
1538
1539         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1540                 pool->base.engines[i] = dcn10_aux_engine_create(ctx, i);
1541                 if (pool->base.engines[i] == NULL) {
1542                         BREAK_TO_DEBUGGER();
1543                         dm_error(
1544                                 "DC:failed to create aux engine!!\n");
1545                         goto fail;
1546                 }
1547                 pool->base.hw_i2cs[i] = dcn10_i2c_hw_create(ctx, i);
1548                 if (pool->base.hw_i2cs[i] == NULL) {
1549                         BREAK_TO_DEBUGGER();
1550                         dm_error(
1551                                 "DC:failed to create hw i2c!!\n");
1552                         goto fail;
1553                 }
1554                 pool->base.sw_i2cs[i] = NULL;
1555         }
1556
1557         /* valid pipe num */
1558         pool->base.pipe_count = j;
1559         pool->base.timing_generator_count = j;
1560
1561         /* within dml lib, it is hard code to 4. If ASIC pipe is fused,
1562          * the value may be changed
1563          */
1564         dc->dml.ip.max_num_dpp = pool->base.pipe_count;
1565         dc->dcn_ip->max_num_dpp = pool->base.pipe_count;
1566
1567         pool->base.mpc = dcn10_mpc_create(ctx);
1568         if (pool->base.mpc == NULL) {
1569                 BREAK_TO_DEBUGGER();
1570                 dm_error("DC: failed to create mpc!\n");
1571                 goto fail;
1572         }
1573
1574         pool->base.hubbub = dcn10_hubbub_create(ctx);
1575         if (pool->base.hubbub == NULL) {
1576                 BREAK_TO_DEBUGGER();
1577                 dm_error("DC: failed to create hubbub!\n");
1578                 goto fail;
1579         }
1580
1581         if (!resource_construct(num_virtual_links, dc, &pool->base,
1582                         (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
1583                         &res_create_funcs : &res_create_maximus_funcs)))
1584                         goto fail;
1585
1586         dcn10_hw_sequencer_construct(dc);
1587         dc->caps.max_planes =  pool->base.pipe_count;
1588
1589         for (i = 0; i < dc->caps.max_planes; ++i)
1590                 dc->caps.planes[i] = plane_cap;
1591
1592         dc->cap_funcs = cap_funcs;
1593
1594         return true;
1595
1596 fail:
1597
1598         dcn10_resource_destruct(pool);
1599
1600         return false;
1601 }
1602
1603 struct resource_pool *dcn10_create_resource_pool(
1604                 const struct dc_init_data *init_data,
1605                 struct dc *dc)
1606 {
1607         struct dcn10_resource_pool *pool =
1608                 kzalloc(sizeof(struct dcn10_resource_pool), GFP_KERNEL);
1609
1610         if (!pool)
1611                 return NULL;
1612
1613         if (dcn10_resource_construct(init_data->num_virtual_links, dc, pool))
1614                 return &pool->base;
1615
1616         kfree(pool);
1617         BREAK_TO_DEBUGGER();
1618         return NULL;
1619 }