1 /* Copyright 2012-15 Advanced Micro Devices, Inc.
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
10 * The above copyright notice and this permission notice shall be included in
11 * all copies or substantial portions of the Software.
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
19 * OTHER DEALINGS IN THE SOFTWARE.
25 #ifndef __DC_MEM_INPUT_DCN10_H__
26 #define __DC_MEM_INPUT_DCN10_H__
28 #include "mem_input.h"
30 #define TO_DCN10_MEM_INPUT(mi)\
31 container_of(mi, struct dcn10_mem_input, base)
33 #define MI_REG_LIST_DCN(id)\
34 SRI(DCHUBP_CNTL, HUBP, id),\
35 SRI(HUBPREQ_DEBUG_DB, HUBP, id),\
36 SRI(DCSURF_ADDR_CONFIG, HUBP, id),\
37 SRI(DCSURF_TILING_CONFIG, HUBP, id),\
38 SRI(DCSURF_SURFACE_PITCH, HUBPREQ, id),\
39 SRI(DCSURF_SURFACE_PITCH_C, HUBPREQ, id),\
40 SRI(DCSURF_SURFACE_CONFIG, HUBP, id),\
41 SRI(DCSURF_FLIP_CONTROL, HUBPREQ, id),\
42 SRI(DCSURF_PRI_VIEWPORT_DIMENSION, HUBP, id), \
43 SRI(DCSURF_PRI_VIEWPORT_START, HUBP, id), \
44 SRI(DCSURF_SEC_VIEWPORT_DIMENSION, HUBP, id), \
45 SRI(DCSURF_SEC_VIEWPORT_START, HUBP, id), \
46 SRI(DCSURF_PRI_VIEWPORT_DIMENSION_C, HUBP, id), \
47 SRI(DCSURF_PRI_VIEWPORT_START_C, HUBP, id), \
48 SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
49 SRI(DCSURF_PRIMARY_SURFACE_ADDRESS, HUBPREQ, id),\
50 SRI(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
51 SRI(DCSURF_SECONDARY_SURFACE_ADDRESS, HUBPREQ, id),\
52 SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
53 SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS, HUBPREQ, id),\
54 SRI(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
55 SRI(DCSURF_SECONDARY_META_SURFACE_ADDRESS, HUBPREQ, id),\
56 SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\
57 SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_C, HUBPREQ, id),\
58 SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\
59 SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, HUBPREQ, id),\
60 SRI(DCSURF_SURFACE_INUSE, HUBPREQ, id),\
61 SRI(DCSURF_SURFACE_INUSE_HIGH, HUBPREQ, id),\
62 SRI(DCSURF_SURFACE_INUSE_C, HUBPREQ, id),\
63 SRI(DCSURF_SURFACE_INUSE_HIGH_C, HUBPREQ, id),\
64 SRI(DCSURF_SURFACE_EARLIEST_INUSE, HUBPREQ, id),\
65 SRI(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, HUBPREQ, id),\
66 SRI(DCSURF_SURFACE_EARLIEST_INUSE_C, HUBPREQ, id),\
67 SRI(DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, HUBPREQ, id),\
68 SRI(DCSURF_SURFACE_CONTROL, HUBPREQ, id),\
69 SRI(HUBPRET_CONTROL, HUBPRET, id),\
70 SRI(DCN_EXPANSION_MODE, HUBPREQ, id),\
71 SRI(DCHUBP_REQ_SIZE_CONFIG, HUBP, id),\
72 SRI(DCHUBP_REQ_SIZE_CONFIG_C, HUBP, id),\
73 SRI(BLANK_OFFSET_0, HUBPREQ, id),\
74 SRI(BLANK_OFFSET_1, HUBPREQ, id),\
75 SRI(DST_DIMENSIONS, HUBPREQ, id),\
76 SRI(DST_AFTER_SCALER, HUBPREQ, id),\
77 SRI(VBLANK_PARAMETERS_0, HUBPREQ, id),\
78 SRI(REF_FREQ_TO_PIX_FREQ, HUBPREQ, id),\
79 SRI(VBLANK_PARAMETERS_1, HUBPREQ, id),\
80 SRI(VBLANK_PARAMETERS_3, HUBPREQ, id),\
81 SRI(NOM_PARAMETERS_0, HUBPREQ, id),\
82 SRI(NOM_PARAMETERS_1, HUBPREQ, id),\
83 SRI(NOM_PARAMETERS_4, HUBPREQ, id),\
84 SRI(NOM_PARAMETERS_5, HUBPREQ, id),\
85 SRI(PER_LINE_DELIVERY_PRE, HUBPREQ, id),\
86 SRI(PER_LINE_DELIVERY, HUBPREQ, id),\
87 SRI(VBLANK_PARAMETERS_2, HUBPREQ, id),\
88 SRI(VBLANK_PARAMETERS_4, HUBPREQ, id),\
89 SRI(NOM_PARAMETERS_2, HUBPREQ, id),\
90 SRI(NOM_PARAMETERS_3, HUBPREQ, id),\
91 SRI(NOM_PARAMETERS_6, HUBPREQ, id),\
92 SRI(NOM_PARAMETERS_7, HUBPREQ, id),\
93 SRI(DCN_TTU_QOS_WM, HUBPREQ, id),\
94 SRI(DCN_GLOBAL_TTU_CNTL, HUBPREQ, id),\
95 SRI(DCN_SURF0_TTU_CNTL0, HUBPREQ, id),\
96 SRI(DCN_SURF0_TTU_CNTL1, HUBPREQ, id),\
97 SRI(DCN_SURF1_TTU_CNTL0, HUBPREQ, id),\
98 SRI(DCN_SURF1_TTU_CNTL1, HUBPREQ, id),\
99 SRI(DCN_VM_MX_L1_TLB_CNTL, HUBPREQ, id)
101 #define MI_REG_LIST_DCN10(id)\
102 MI_REG_LIST_DCN(id),\
103 SRI(PREFETCH_SETTINS, HUBPREQ, id),\
104 SRI(PREFETCH_SETTINS_C, HUBPREQ, id),\
105 SRI(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, HUBPREQ, id),\
106 SRI(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, HUBPREQ, id),\
107 SRI(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, HUBPREQ, id),\
108 SRI(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, HUBPREQ, id),\
109 SRI(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, HUBPREQ, id),\
110 SRI(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, HUBPREQ, id),\
111 SRI(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, HUBPREQ, id),\
112 SRI(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, HUBPREQ, id),\
113 SRI(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, HUBPREQ, id),\
114 SRI(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, HUBPREQ, id),\
115 SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, HUBPREQ, id),\
116 SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, HUBPREQ, id),\
117 SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, HUBPREQ, id),\
118 SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, HUBPREQ, id),\
119 SR(DCHUBBUB_SDPIF_FB_BASE),\
120 SR(DCHUBBUB_SDPIF_FB_OFFSET),\
121 SRI(CURSOR_SETTINS, HUBPREQ, id), \
122 SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR, id), \
123 SRI(CURSOR_SURFACE_ADDRESS, CURSOR, id), \
124 SRI(CURSOR_SIZE, CURSOR, id), \
125 SRI(CURSOR_CONTROL, CURSOR, id), \
126 SRI(CURSOR_POSITION, CURSOR, id), \
127 SRI(CURSOR_HOT_SPOT, CURSOR, id), \
128 SRI(CURSOR_DST_OFFSET, CURSOR, id)
132 struct dcn_mi_registers {
133 uint32_t DCHUBP_CNTL;
134 uint32_t HUBPREQ_DEBUG_DB;
135 uint32_t DCSURF_ADDR_CONFIG;
136 uint32_t DCSURF_TILING_CONFIG;
137 uint32_t DCSURF_SURFACE_PITCH;
138 uint32_t DCSURF_SURFACE_PITCH_C;
139 uint32_t DCSURF_SURFACE_CONFIG;
140 uint32_t DCSURF_FLIP_CONTROL;
141 uint32_t DCSURF_PRI_VIEWPORT_DIMENSION;
142 uint32_t DCSURF_PRI_VIEWPORT_START;
143 uint32_t DCSURF_SEC_VIEWPORT_DIMENSION;
144 uint32_t DCSURF_SEC_VIEWPORT_START;
145 uint32_t DCSURF_PRI_VIEWPORT_DIMENSION_C;
146 uint32_t DCSURF_PRI_VIEWPORT_START_C;
147 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH;
148 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS;
149 uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH;
150 uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS;
151 uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH;
152 uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS;
153 uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH;
154 uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS;
155 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C;
156 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C;
157 uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C;
158 uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_C;
159 uint32_t DCSURF_SURFACE_INUSE;
160 uint32_t DCSURF_SURFACE_INUSE_HIGH;
161 uint32_t DCSURF_SURFACE_INUSE_C;
162 uint32_t DCSURF_SURFACE_INUSE_HIGH_C;
163 uint32_t DCSURF_SURFACE_EARLIEST_INUSE;
164 uint32_t DCSURF_SURFACE_EARLIEST_INUSE_HIGH;
165 uint32_t DCSURF_SURFACE_EARLIEST_INUSE_C;
166 uint32_t DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C;
167 uint32_t DCSURF_SURFACE_CONTROL;
168 uint32_t HUBPRET_CONTROL;
169 uint32_t DCN_EXPANSION_MODE;
170 uint32_t DCHUBP_REQ_SIZE_CONFIG;
171 uint32_t DCHUBP_REQ_SIZE_CONFIG_C;
172 uint32_t BLANK_OFFSET_0;
173 uint32_t BLANK_OFFSET_1;
174 uint32_t DST_DIMENSIONS;
175 uint32_t DST_AFTER_SCALER;
176 uint32_t PREFETCH_SETTINS;
177 uint32_t PREFETCH_SETTINGS;
178 uint32_t VBLANK_PARAMETERS_0;
179 uint32_t REF_FREQ_TO_PIX_FREQ;
180 uint32_t VBLANK_PARAMETERS_1;
181 uint32_t VBLANK_PARAMETERS_3;
182 uint32_t NOM_PARAMETERS_0;
183 uint32_t NOM_PARAMETERS_1;
184 uint32_t NOM_PARAMETERS_4;
185 uint32_t NOM_PARAMETERS_5;
186 uint32_t PER_LINE_DELIVERY_PRE;
187 uint32_t PER_LINE_DELIVERY;
188 uint32_t PREFETCH_SETTINS_C;
189 uint32_t PREFETCH_SETTINGS_C;
190 uint32_t VBLANK_PARAMETERS_2;
191 uint32_t VBLANK_PARAMETERS_4;
192 uint32_t NOM_PARAMETERS_2;
193 uint32_t NOM_PARAMETERS_3;
194 uint32_t NOM_PARAMETERS_6;
195 uint32_t NOM_PARAMETERS_7;
196 uint32_t DCN_TTU_QOS_WM;
197 uint32_t DCN_GLOBAL_TTU_CNTL;
198 uint32_t DCN_SURF0_TTU_CNTL0;
199 uint32_t DCN_SURF0_TTU_CNTL1;
200 uint32_t DCN_SURF1_TTU_CNTL0;
201 uint32_t DCN_SURF1_TTU_CNTL1;
202 uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB;
203 uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB;
204 uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB;
205 uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB;
206 uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB;
207 uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB;
208 uint32_t DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB;
209 uint32_t DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB;
210 uint32_t DCN_VM_MX_L1_TLB_CNTL;
211 uint32_t DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB;
212 uint32_t DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB;
213 uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB;
214 uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB;
215 uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB;
216 uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB;
217 uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR;
218 uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR;
219 uint32_t DCHUBBUB_SDPIF_FB_BASE;
220 uint32_t DCHUBBUB_SDPIF_FB_OFFSET;
221 uint32_t DCN_VM_FB_LOCATION_TOP;
222 uint32_t DCN_VM_FB_LOCATION_BASE;
223 uint32_t DCN_VM_FB_OFFSET;
224 uint32_t DCN_VM_AGP_BASE;
225 uint32_t DCN_VM_AGP_BOT;
226 uint32_t DCN_VM_AGP_TOP;
227 uint32_t CURSOR_SETTINS;
228 uint32_t CURSOR_SETTINGS;
229 uint32_t CURSOR_SURFACE_ADDRESS_HIGH;
230 uint32_t CURSOR_SURFACE_ADDRESS;
231 uint32_t CURSOR_SIZE;
232 uint32_t CURSOR_CONTROL;
233 uint32_t CURSOR_POSITION;
234 uint32_t CURSOR_HOT_SPOT;
235 uint32_t CURSOR_DST_OFFSET;
238 #define MI_SF(reg_name, field_name, post_fix)\
239 .field_name = reg_name ## __ ## field_name ## post_fix
241 #define MI_MASK_SH_LIST_DCN(mask_sh)\
242 MI_SF(HUBP0_DCHUBP_CNTL, HUBP_BLANK_EN, mask_sh),\
243 MI_SF(HUBP0_DCHUBP_CNTL, HUBP_TTU_DISABLE, mask_sh),\
244 MI_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_STATUS, mask_sh),\
245 MI_SF(HUBP0_DCHUBP_CNTL, HUBP_NO_OUTSTANDING_REQ, mask_sh),\
246 MI_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PIPES, mask_sh),\
247 MI_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_BANKS, mask_sh),\
248 MI_SF(HUBP0_DCSURF_ADDR_CONFIG, PIPE_INTERLEAVE, mask_sh),\
249 MI_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_SE, mask_sh),\
250 MI_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_RB_PER_SE, mask_sh),\
251 MI_SF(HUBP0_DCSURF_ADDR_CONFIG, MAX_COMPRESSED_FRAGS, mask_sh),\
252 MI_SF(HUBP0_DCSURF_TILING_CONFIG, SW_MODE, mask_sh),\
253 MI_SF(HUBP0_DCSURF_TILING_CONFIG, META_LINEAR, mask_sh),\
254 MI_SF(HUBP0_DCSURF_TILING_CONFIG, RB_ALIGNED, mask_sh),\
255 MI_SF(HUBP0_DCSURF_TILING_CONFIG, PIPE_ALIGNED, mask_sh),\
256 MI_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH, mask_sh),\
257 MI_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, META_PITCH, mask_sh),\
258 MI_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, PITCH_C, mask_sh),\
259 MI_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, META_PITCH_C, mask_sh),\
260 MI_SF(HUBP0_DCSURF_SURFACE_CONFIG, ROTATION_ANGLE, mask_sh),\
261 MI_SF(HUBP0_DCSURF_SURFACE_CONFIG, H_MIRROR_EN, mask_sh),\
262 MI_SF(HUBP0_DCSURF_SURFACE_CONFIG, SURFACE_PIXEL_FORMAT, mask_sh),\
263 MI_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_TYPE, mask_sh),\
264 MI_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_PENDING, mask_sh),\
265 MI_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, mask_sh),\
266 MI_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH, mask_sh),\
267 MI_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT, mask_sh),\
268 MI_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_X_START, mask_sh),\
269 MI_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_Y_START, mask_sh),\
270 MI_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_WIDTH, mask_sh),\
271 MI_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_HEIGHT, mask_sh),\
272 MI_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_X_START, mask_sh),\
273 MI_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_Y_START, mask_sh),\
274 MI_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_WIDTH_C, mask_sh),\
275 MI_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_HEIGHT_C, mask_sh),\
276 MI_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_X_START_C, mask_sh),\
277 MI_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_Y_START_C, mask_sh),\
278 MI_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, PRIMARY_SURFACE_ADDRESS_HIGH, mask_sh),\
279 MI_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS, PRIMARY_SURFACE_ADDRESS, mask_sh),\
280 MI_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, SECONDARY_SURFACE_ADDRESS_HIGH, mask_sh),\
281 MI_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS, SECONDARY_SURFACE_ADDRESS, mask_sh),\
282 MI_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, PRIMARY_META_SURFACE_ADDRESS_HIGH, mask_sh),\
283 MI_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS, PRIMARY_META_SURFACE_ADDRESS, mask_sh),\
284 MI_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, SECONDARY_META_SURFACE_ADDRESS_HIGH, mask_sh),\
285 MI_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS, SECONDARY_META_SURFACE_ADDRESS, mask_sh),\
286 MI_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, PRIMARY_SURFACE_ADDRESS_HIGH_C, mask_sh),\
287 MI_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C, PRIMARY_SURFACE_ADDRESS_C, mask_sh),\
288 MI_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, PRIMARY_META_SURFACE_ADDRESS_HIGH_C, mask_sh),\
289 MI_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, PRIMARY_META_SURFACE_ADDRESS_C, mask_sh),\
290 MI_SF(HUBPREQ0_DCSURF_SURFACE_INUSE, SURFACE_INUSE_ADDRESS, mask_sh),\
291 MI_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH, SURFACE_INUSE_ADDRESS_HIGH, mask_sh),\
292 MI_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_C, SURFACE_INUSE_ADDRESS_C, mask_sh),\
293 MI_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C, SURFACE_INUSE_ADDRESS_HIGH_C, mask_sh),\
294 MI_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE, SURFACE_EARLIEST_INUSE_ADDRESS, mask_sh),\
295 MI_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, mask_sh),\
296 MI_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C, SURFACE_EARLIEST_INUSE_ADDRESS_C, mask_sh),\
297 MI_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C, mask_sh),\
298 MI_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_TMZ, mask_sh),\
299 MI_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_EN, mask_sh),\
300 MI_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_IND_64B_BLK, mask_sh),\
301 MI_SF(HUBPRET0_HUBPRET_CONTROL, DET_BUF_PLANE1_BASE_ADDRESS, mask_sh),\
302 MI_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CB_B, mask_sh),\
303 MI_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CR_R, mask_sh),\
304 MI_SF(HUBPREQ0_DCN_EXPANSION_MODE, DRQ_EXPANSION_MODE, mask_sh),\
305 MI_SF(HUBPREQ0_DCN_EXPANSION_MODE, PRQ_EXPANSION_MODE, mask_sh),\
306 MI_SF(HUBPREQ0_DCN_EXPANSION_MODE, MRQ_EXPANSION_MODE, mask_sh),\
307 MI_SF(HUBPREQ0_DCN_EXPANSION_MODE, CRQ_EXPANSION_MODE, mask_sh),\
308 MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, CHUNK_SIZE, mask_sh),\
309 MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_CHUNK_SIZE, mask_sh),\
310 MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, META_CHUNK_SIZE, mask_sh),\
311 MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_META_CHUNK_SIZE, mask_sh),\
312 MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, DPTE_GROUP_SIZE, mask_sh),\
313 MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MPTE_GROUP_SIZE, mask_sh),\
314 MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, SWATH_HEIGHT, mask_sh),\
315 MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, PTE_ROW_HEIGHT_LINEAR, mask_sh),\
316 MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, CHUNK_SIZE_C, mask_sh),\
317 MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_CHUNK_SIZE_C, mask_sh),\
318 MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, META_CHUNK_SIZE_C, mask_sh),\
319 MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_META_CHUNK_SIZE_C, mask_sh),\
320 MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, DPTE_GROUP_SIZE_C, mask_sh),\
321 MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MPTE_GROUP_SIZE_C, mask_sh),\
322 MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, SWATH_HEIGHT_C, mask_sh),\
323 MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, PTE_ROW_HEIGHT_LINEAR_C, mask_sh),\
324 MI_SF(HUBPREQ0_BLANK_OFFSET_0, REFCYC_H_BLANK_END, mask_sh),\
325 MI_SF(HUBPREQ0_BLANK_OFFSET_0, DLG_V_BLANK_END, mask_sh),\
326 MI_SF(HUBPREQ0_BLANK_OFFSET_1, MIN_DST_Y_NEXT_START, mask_sh),\
327 MI_SF(HUBPREQ0_DST_DIMENSIONS, REFCYC_PER_HTOTAL, mask_sh),\
328 MI_SF(HUBPREQ0_DST_AFTER_SCALER, REFCYC_X_AFTER_SCALER, mask_sh),\
329 MI_SF(HUBPREQ0_DST_AFTER_SCALER, DST_Y_AFTER_SCALER, mask_sh),\
330 MI_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_VM_VBLANK, mask_sh),\
331 MI_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_ROW_VBLANK, mask_sh),\
332 MI_SF(HUBPREQ0_REF_FREQ_TO_PIX_FREQ, REF_FREQ_TO_PIX_FREQ, mask_sh),\
333 MI_SF(HUBPREQ0_VBLANK_PARAMETERS_1, REFCYC_PER_PTE_GROUP_VBLANK_L, mask_sh),\
334 MI_SF(HUBPREQ0_VBLANK_PARAMETERS_3, REFCYC_PER_META_CHUNK_VBLANK_L, mask_sh),\
335 MI_SF(HUBPREQ0_NOM_PARAMETERS_0, DST_Y_PER_PTE_ROW_NOM_L, mask_sh),\
336 MI_SF(HUBPREQ0_NOM_PARAMETERS_1, REFCYC_PER_PTE_GROUP_NOM_L, mask_sh),\
337 MI_SF(HUBPREQ0_NOM_PARAMETERS_4, DST_Y_PER_META_ROW_NOM_L, mask_sh),\
338 MI_SF(HUBPREQ0_NOM_PARAMETERS_5, REFCYC_PER_META_CHUNK_NOM_L, mask_sh),\
339 MI_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_L, mask_sh),\
340 MI_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_C, mask_sh),\
341 MI_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_L, mask_sh),\
342 MI_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_C, mask_sh),\
343 MI_SF(HUBPREQ0_VBLANK_PARAMETERS_2, REFCYC_PER_PTE_GROUP_VBLANK_C, mask_sh),\
344 MI_SF(HUBPREQ0_VBLANK_PARAMETERS_4, REFCYC_PER_META_CHUNK_VBLANK_C, mask_sh),\
345 MI_SF(HUBPREQ0_NOM_PARAMETERS_2, DST_Y_PER_PTE_ROW_NOM_C, mask_sh),\
346 MI_SF(HUBPREQ0_NOM_PARAMETERS_3, REFCYC_PER_PTE_GROUP_NOM_C, mask_sh),\
347 MI_SF(HUBPREQ0_NOM_PARAMETERS_6, DST_Y_PER_META_ROW_NOM_C, mask_sh),\
348 MI_SF(HUBPREQ0_NOM_PARAMETERS_7, REFCYC_PER_META_CHUNK_NOM_C, mask_sh),\
349 MI_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_LOW_WM, mask_sh),\
350 MI_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_HIGH_WM, mask_sh),\
351 MI_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, MIN_TTU_VBLANK, mask_sh),\
352 MI_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, QoS_LEVEL_FLIP, mask_sh),\
353 MI_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, REFCYC_PER_REQ_DELIVERY, mask_sh),\
354 MI_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_LEVEL_FIXED, mask_sh),\
355 MI_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\
356 MI_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh),\
357 MI_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, mask_sh),\
358 MI_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, mask_sh)
360 #define MI_MASK_SH_LIST_DCN10(mask_sh)\
361 MI_MASK_SH_LIST_DCN(mask_sh),\
362 MI_SF(HUBPREQ0_PREFETCH_SETTINS, DST_Y_PREFETCH, mask_sh),\
363 MI_SF(HUBPREQ0_PREFETCH_SETTINS, VRATIO_PREFETCH, mask_sh),\
364 MI_SF(HUBPREQ0_PREFETCH_SETTINS_C, VRATIO_PREFETCH_C, mask_sh),\
365 MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, mask_sh),\
366 MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, mask_sh),\
367 MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, mask_sh),\
368 MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, mask_sh),\
369 MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, mask_sh),\
370 MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, mask_sh),\
371 MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, mask_sh),\
372 MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM, mask_sh),\
373 MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, mask_sh),\
374 MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, mask_sh),\
375 MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, mask_sh),\
376 MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, mask_sh),\
377 MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, mask_sh),\
378 MI_SF(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh),\
379 MI_SF(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh),\
380 MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, mask_sh),\
381 MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mask_sh),\
382 MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mask_sh),\
383 MI_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_DST_Y_OFFSET, mask_sh), \
384 MI_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \
385 MI_SF(CURSOR0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \
386 MI_SF(CURSOR0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \
387 MI_SF(CURSOR0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \
388 MI_SF(CURSOR0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \
389 MI_SF(CURSOR0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \
390 MI_SF(CURSOR0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \
391 MI_SF(CURSOR0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \
392 MI_SF(CURSOR0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \
393 MI_SF(CURSOR0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \
394 MI_SF(CURSOR0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \
395 MI_SF(CURSOR0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \
396 MI_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \
397 MI_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \
398 MI_SF(CURSOR0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh)
400 #define DCN_MI_REG_FIELD_LIST(type) \
402 type HUBP_TTU_DISABLE;\
403 type HUBP_NO_OUTSTANDING_REQ;\
404 type HUBP_UNDERFLOW_STATUS;\
407 type PIPE_INTERLEAVE;\
410 type MAX_COMPRESSED_FRAGS;\
419 type ROTATION_ANGLE;\
421 type SURFACE_PIXEL_FORMAT;\
422 type SURFACE_FLIP_TYPE;\
423 type SURFACE_UPDATE_LOCK;\
424 type SURFACE_FLIP_PENDING;\
425 type PRI_VIEWPORT_WIDTH; \
426 type PRI_VIEWPORT_HEIGHT; \
427 type PRI_VIEWPORT_X_START; \
428 type PRI_VIEWPORT_Y_START; \
429 type SEC_VIEWPORT_WIDTH; \
430 type SEC_VIEWPORT_HEIGHT; \
431 type SEC_VIEWPORT_X_START; \
432 type SEC_VIEWPORT_Y_START; \
433 type PRI_VIEWPORT_WIDTH_C; \
434 type PRI_VIEWPORT_HEIGHT_C; \
435 type PRI_VIEWPORT_X_START_C; \
436 type PRI_VIEWPORT_Y_START_C; \
437 type PRIMARY_SURFACE_ADDRESS_HIGH;\
438 type PRIMARY_SURFACE_ADDRESS;\
439 type SECONDARY_SURFACE_ADDRESS_HIGH;\
440 type SECONDARY_SURFACE_ADDRESS;\
441 type PRIMARY_META_SURFACE_ADDRESS_HIGH;\
442 type PRIMARY_META_SURFACE_ADDRESS;\
443 type SECONDARY_META_SURFACE_ADDRESS_HIGH;\
444 type SECONDARY_META_SURFACE_ADDRESS;\
445 type PRIMARY_SURFACE_ADDRESS_HIGH_C;\
446 type PRIMARY_SURFACE_ADDRESS_C;\
447 type PRIMARY_META_SURFACE_ADDRESS_HIGH_C;\
448 type PRIMARY_META_SURFACE_ADDRESS_C;\
449 type SURFACE_INUSE_ADDRESS;\
450 type SURFACE_INUSE_ADDRESS_HIGH;\
451 type SURFACE_INUSE_ADDRESS_C;\
452 type SURFACE_INUSE_ADDRESS_HIGH_C;\
453 type SURFACE_EARLIEST_INUSE_ADDRESS;\
454 type SURFACE_EARLIEST_INUSE_ADDRESS_HIGH;\
455 type SURFACE_EARLIEST_INUSE_ADDRESS_C;\
456 type SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C;\
457 type PRIMARY_SURFACE_TMZ;\
458 type PRIMARY_SURFACE_DCC_EN;\
459 type PRIMARY_SURFACE_DCC_IND_64B_BLK;\
460 type DET_BUF_PLANE1_BASE_ADDRESS;\
461 type CROSSBAR_SRC_CB_B;\
462 type CROSSBAR_SRC_CR_R;\
463 type DRQ_EXPANSION_MODE;\
464 type PRQ_EXPANSION_MODE;\
465 type MRQ_EXPANSION_MODE;\
466 type CRQ_EXPANSION_MODE;\
468 type MIN_CHUNK_SIZE;\
469 type META_CHUNK_SIZE;\
470 type MIN_META_CHUNK_SIZE;\
471 type DPTE_GROUP_SIZE;\
472 type MPTE_GROUP_SIZE;\
474 type PTE_ROW_HEIGHT_LINEAR;\
476 type MIN_CHUNK_SIZE_C;\
477 type META_CHUNK_SIZE_C;\
478 type MIN_META_CHUNK_SIZE_C;\
479 type DPTE_GROUP_SIZE_C;\
480 type MPTE_GROUP_SIZE_C;\
481 type SWATH_HEIGHT_C;\
482 type PTE_ROW_HEIGHT_LINEAR_C;\
483 type REFCYC_H_BLANK_END;\
484 type DLG_V_BLANK_END;\
485 type MIN_DST_Y_NEXT_START;\
486 type REFCYC_PER_HTOTAL;\
487 type REFCYC_X_AFTER_SCALER;\
488 type DST_Y_AFTER_SCALER;\
489 type DST_Y_PREFETCH;\
490 type VRATIO_PREFETCH;\
491 type DST_Y_PER_VM_VBLANK;\
492 type DST_Y_PER_ROW_VBLANK;\
493 type REF_FREQ_TO_PIX_FREQ;\
494 type REFCYC_PER_PTE_GROUP_VBLANK_L;\
495 type REFCYC_PER_META_CHUNK_VBLANK_L;\
496 type DST_Y_PER_PTE_ROW_NOM_L;\
497 type REFCYC_PER_PTE_GROUP_NOM_L;\
498 type DST_Y_PER_META_ROW_NOM_L;\
499 type REFCYC_PER_META_CHUNK_NOM_L;\
500 type REFCYC_PER_LINE_DELIVERY_PRE_L;\
501 type REFCYC_PER_LINE_DELIVERY_PRE_C;\
502 type REFCYC_PER_LINE_DELIVERY_L;\
503 type REFCYC_PER_LINE_DELIVERY_C;\
504 type VRATIO_PREFETCH_C;\
505 type REFCYC_PER_PTE_GROUP_VBLANK_C;\
506 type REFCYC_PER_META_CHUNK_VBLANK_C;\
507 type DST_Y_PER_PTE_ROW_NOM_C;\
508 type REFCYC_PER_PTE_GROUP_NOM_C;\
509 type DST_Y_PER_META_ROW_NOM_C;\
510 type REFCYC_PER_META_CHUNK_NOM_C;\
511 type QoS_LEVEL_LOW_WM;\
512 type QoS_LEVEL_HIGH_WM;\
513 type MIN_TTU_VBLANK;\
514 type QoS_LEVEL_FLIP;\
515 type REFCYC_PER_REQ_DELIVERY;\
516 type QoS_LEVEL_FIXED;\
517 type QoS_RAMP_DISABLE;\
518 type REFCYC_PER_REQ_DELIVERY_PRE;\
519 type VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB;\
520 type VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB;\
521 type VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB;\
522 type VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB;\
523 type VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB;\
524 type VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB;\
525 type VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB;\
526 type VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM;\
527 type VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB;\
529 type SYSTEM_ACCESS_MODE;\
530 type MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM;\
531 type MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB;\
532 type MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB;\
533 type MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB;\
534 type MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB;\
535 type MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB;\
536 type MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB;\
537 type MC_VM_SYSTEM_APERTURE_LOW_ADDR;\
538 type MC_VM_SYSTEM_APERTURE_HIGH_ADDR;\
541 type SDPIF_FB_OFFSET;\
542 type SDPIF_AGP_BASE;\
551 /* todo: get these from GVM instead of reading registers ourselves */\
552 type PAGE_DIRECTORY_ENTRY_HI32;\
553 type PAGE_DIRECTORY_ENTRY_LO32;\
554 type LOGICAL_PAGE_NUMBER_HI4;\
555 type LOGICAL_PAGE_NUMBER_LO32;\
556 type PHYSICAL_PAGE_ADDR_HI4;\
557 type PHYSICAL_PAGE_ADDR_LO32;\
558 type PHYSICAL_PAGE_NUMBER_MSB;\
559 type PHYSICAL_PAGE_NUMBER_LSB;\
561 type CURSOR0_DST_Y_OFFSET; \
562 type CURSOR0_CHUNK_HDL_ADJUST; \
563 type CURSOR_SURFACE_ADDRESS_HIGH; \
564 type CURSOR_SURFACE_ADDRESS; \
566 type CURSOR_HEIGHT; \
568 type CURSOR_2X_MAGNIFY; \
570 type CURSOR_LINES_PER_CHUNK; \
571 type CURSOR_ENABLE; \
572 type CURSOR_X_POSITION; \
573 type CURSOR_Y_POSITION; \
574 type CURSOR_HOT_SPOT_X; \
575 type CURSOR_HOT_SPOT_Y; \
576 type CURSOR_DST_X_OFFSET; \
579 struct dcn_mi_shift {
580 DCN_MI_REG_FIELD_LIST(uint8_t);
584 DCN_MI_REG_FIELD_LIST(uint32_t);
587 struct dcn10_mem_input {
588 struct mem_input base;
589 const struct dcn_mi_registers *mi_regs;
590 const struct dcn_mi_shift *mi_shift;
591 const struct dcn_mi_mask *mi_mask;
594 void hubp1_program_deadline(
595 struct mem_input *mem_input,
596 struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
597 struct _vcs_dpi_display_ttu_regs_st *ttu_attr);
599 void hubp1_program_requestor(
600 struct mem_input *mem_input,
601 struct _vcs_dpi_display_rq_regs_st *rq_regs);
603 void hubp1_program_pixel_format(
604 struct dcn10_mem_input *mi,
605 enum surface_pixel_format format);
607 void hubp1_program_size_and_rotation(
608 struct dcn10_mem_input *mi,
609 enum dc_rotation_angle rotation,
610 enum surface_pixel_format format,
611 const union plane_size *plane_size,
612 struct dc_plane_dcc_param *dcc,
613 bool horizontal_mirror);
615 void hubp1_program_tiling(
616 struct dcn10_mem_input *mi,
617 const union dc_tiling_info *info,
618 const enum surface_pixel_format pixel_format);
620 void hubp1_dcc_control(struct mem_input *mem_input,
622 bool independent_64b_blks);
624 void hubp1_program_display_marks(
625 struct mem_input *mem_input,
626 struct dce_watermarks nbp,
627 struct dce_watermarks stutter,
628 struct dce_watermarks urgent,
629 uint32_t total_dest_line_time_ns);
631 bool hubp1_program_surface_flip_and_addr(
632 struct mem_input *mem_input,
633 const struct dc_plane_address *address,
634 bool flip_immediate);
636 bool hubp1_is_flip_pending(struct mem_input *mem_input);
638 void hubp1_cursor_set_attributes(
639 struct mem_input *mem_input,
640 const struct dc_cursor_attributes *attr);
642 void hubp1_cursor_set_position(
643 struct mem_input *mem_input,
644 const struct dc_cursor_position *pos,
645 const struct dc_cursor_mi_param *param);
647 void hubp1_set_blank(struct mem_input *mem_input, bool blank);
649 void min_set_viewport(struct mem_input *mem_input,
650 const struct rect *viewport,
651 const struct rect *viewport_c);
653 void dcn10_mem_input_construct(
654 struct dcn10_mem_input *mi,
655 struct dc_context *ctx,
657 const struct dcn_mi_registers *mi_regs,
658 const struct dcn_mi_shift *mi_shift,
659 const struct dcn_mi_mask *mi_mask);
662 struct dcn_hubp_state {
663 uint32_t pixel_format;
664 uint32_t inuse_addr_hi;
665 uint32_t viewport_width;
666 uint32_t viewport_height;
667 uint32_t rotation_angle;
668 uint32_t h_mirror_en;
672 uint32_t underflow_status;
673 uint32_t ttu_disable;
674 uint32_t min_ttu_vblank;
675 uint32_t qos_level_low_wm;
676 uint32_t qos_level_high_wm;
678 void dcn10_mem_input_read_state(struct dcn10_mem_input *mi,
679 struct dcn_hubp_state *s);