2 * Copyright 2012-15 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <linux/delay.h>
27 #include <linux/slab.h>
29 #include "reg_helper.h"
31 #include "core_types.h"
32 #include "link_encoder.h"
33 #include "dcn10_link_encoder.h"
34 #include "stream_encoder.h"
35 #include "i2caux_interface.h"
36 #include "dc_bios_types.h"
38 #include "gpio_service_interface.h"
43 enc10->base.ctx->logger
46 (enc10->link_regs->reg)
49 #define FN(reg_name, field_name) \
50 enc10->link_shift->field_name, enc10->link_mask->field_name
55 * Trigger Source Select
56 * ASIC-dependent, actual values for register programming
58 #define DCN10_DIG_FE_SOURCE_SELECT_INVALID 0x0
59 #define DCN10_DIG_FE_SOURCE_SELECT_DIGA 0x1
60 #define DCN10_DIG_FE_SOURCE_SELECT_DIGB 0x2
61 #define DCN10_DIG_FE_SOURCE_SELECT_DIGC 0x4
62 #define DCN10_DIG_FE_SOURCE_SELECT_DIGD 0x08
63 #define DCN10_DIG_FE_SOURCE_SELECT_DIGE 0x10
64 #define DCN10_DIG_FE_SOURCE_SELECT_DIGF 0x20
65 #define DCN10_DIG_FE_SOURCE_SELECT_DIGG 0x40
68 DP_MST_UPDATE_MAX_RETRY = 50
71 static const struct link_encoder_funcs dcn10_lnk_enc_funcs = {
72 .validate_output_with_stream =
73 dcn10_link_encoder_validate_output_with_stream,
74 .hw_init = dcn10_link_encoder_hw_init,
75 .setup = dcn10_link_encoder_setup,
76 .enable_tmds_output = dcn10_link_encoder_enable_tmds_output,
77 .enable_dp_output = dcn10_link_encoder_enable_dp_output,
78 .enable_dp_mst_output = dcn10_link_encoder_enable_dp_mst_output,
79 .disable_output = dcn10_link_encoder_disable_output,
80 .dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,
81 .dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,
82 .update_mst_stream_allocation_table =
83 dcn10_link_encoder_update_mst_stream_allocation_table,
84 .psr_program_dp_dphy_fast_training =
85 dcn10_psr_program_dp_dphy_fast_training,
86 .psr_program_secondary_packet = dcn10_psr_program_secondary_packet,
87 .connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe,
88 .enable_hpd = dcn10_link_encoder_enable_hpd,
89 .disable_hpd = dcn10_link_encoder_disable_hpd,
90 .is_dig_enabled = dcn10_is_dig_enabled,
91 .get_dig_frontend = dcn10_get_dig_frontend,
92 .get_dig_mode = dcn10_get_dig_mode,
93 .destroy = dcn10_link_encoder_destroy
96 static enum bp_result link_transmitter_control(
97 struct dcn10_link_encoder *enc10,
98 struct bp_transmitter_control *cntl)
100 enum bp_result result;
101 struct dc_bios *bp = enc10->base.ctx->dc_bios;
103 result = bp->funcs->transmitter_control(bp, cntl);
108 static void enable_phy_bypass_mode(
109 struct dcn10_link_encoder *enc10,
112 /* This register resides in DP back end block;
113 * transmitter is used for the offset
115 REG_UPDATE(DP_DPHY_CNTL, DPHY_BYPASS, enable);
119 static void disable_prbs_symbols(
120 struct dcn10_link_encoder *enc10,
123 /* This register resides in DP back end block;
124 * transmitter is used for the offset
126 REG_UPDATE_4(DP_DPHY_CNTL,
127 DPHY_ATEST_SEL_LANE0, disable,
128 DPHY_ATEST_SEL_LANE1, disable,
129 DPHY_ATEST_SEL_LANE2, disable,
130 DPHY_ATEST_SEL_LANE3, disable);
133 static void disable_prbs_mode(
134 struct dcn10_link_encoder *enc10)
136 REG_UPDATE(DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN, 0);
139 static void program_pattern_symbols(
140 struct dcn10_link_encoder *enc10,
141 uint16_t pattern_symbols[8])
143 /* This register resides in DP back end block;
144 * transmitter is used for the offset
146 REG_SET_3(DP_DPHY_SYM0, 0,
147 DPHY_SYM1, pattern_symbols[0],
148 DPHY_SYM2, pattern_symbols[1],
149 DPHY_SYM3, pattern_symbols[2]);
151 /* This register resides in DP back end block;
152 * transmitter is used for the offset
154 REG_SET_3(DP_DPHY_SYM1, 0,
155 DPHY_SYM4, pattern_symbols[3],
156 DPHY_SYM5, pattern_symbols[4],
157 DPHY_SYM6, pattern_symbols[5]);
159 /* This register resides in DP back end block;
160 * transmitter is used for the offset
162 REG_SET_2(DP_DPHY_SYM2, 0,
163 DPHY_SYM7, pattern_symbols[6],
164 DPHY_SYM8, pattern_symbols[7]);
167 static void set_dp_phy_pattern_d102(
168 struct dcn10_link_encoder *enc10)
170 /* Disable PHY Bypass mode to setup the test pattern */
171 enable_phy_bypass_mode(enc10, false);
173 /* For 10-bit PRBS or debug symbols
174 * please use the following sequence:
176 * Enable debug symbols on the lanes
178 disable_prbs_symbols(enc10, true);
180 /* Disable PRBS mode */
181 disable_prbs_mode(enc10);
183 /* Program debug symbols to be output */
185 uint16_t pattern_symbols[8] = {
186 0x2AA, 0x2AA, 0x2AA, 0x2AA,
187 0x2AA, 0x2AA, 0x2AA, 0x2AA
190 program_pattern_symbols(enc10, pattern_symbols);
193 /* Enable phy bypass mode to enable the test pattern */
195 enable_phy_bypass_mode(enc10, true);
198 static void set_link_training_complete(
199 struct dcn10_link_encoder *enc10,
202 /* This register resides in DP back end block;
203 * transmitter is used for the offset
205 REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, complete);
209 void dcn10_link_encoder_set_dp_phy_pattern_training_pattern(
210 struct link_encoder *enc,
213 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
214 /* Write Training Pattern */
216 REG_WRITE(DP_DPHY_TRAINING_PATTERN_SEL, index);
218 /* Set HW Register Training Complete to false */
220 set_link_training_complete(enc10, false);
222 /* Disable PHY Bypass mode to output Training Pattern */
224 enable_phy_bypass_mode(enc10, false);
226 /* Disable PRBS mode */
227 disable_prbs_mode(enc10);
230 static void setup_panel_mode(
231 struct dcn10_link_encoder *enc10,
232 enum dp_panel_mode panel_mode)
236 if (!REG(DP_DPHY_INTERNAL_CTRL))
239 value = REG_READ(DP_DPHY_INTERNAL_CTRL);
241 switch (panel_mode) {
242 case DP_PANEL_MODE_EDP:
245 case DP_PANEL_MODE_SPECIAL:
253 REG_WRITE(DP_DPHY_INTERNAL_CTRL, value);
256 static void set_dp_phy_pattern_symbol_error(
257 struct dcn10_link_encoder *enc10)
259 /* Disable PHY Bypass mode to setup the test pattern */
260 enable_phy_bypass_mode(enc10, false);
262 /* program correct panel mode*/
263 setup_panel_mode(enc10, DP_PANEL_MODE_DEFAULT);
265 /* A PRBS23 pattern is used for most DP electrical measurements. */
267 /* Enable PRBS symbols on the lanes */
268 disable_prbs_symbols(enc10, false);
270 /* For PRBS23 Set bit DPHY_PRBS_SEL=1 and Set bit DPHY_PRBS_EN=1 */
271 REG_UPDATE_2(DP_DPHY_PRBS_CNTL,
275 /* Enable phy bypass mode to enable the test pattern */
276 enable_phy_bypass_mode(enc10, true);
279 static void set_dp_phy_pattern_prbs7(
280 struct dcn10_link_encoder *enc10)
282 /* Disable PHY Bypass mode to setup the test pattern */
283 enable_phy_bypass_mode(enc10, false);
285 /* A PRBS7 pattern is used for most DP electrical measurements. */
287 /* Enable PRBS symbols on the lanes */
288 disable_prbs_symbols(enc10, false);
290 /* For PRBS7 Set bit DPHY_PRBS_SEL=0 and Set bit DPHY_PRBS_EN=1 */
291 REG_UPDATE_2(DP_DPHY_PRBS_CNTL,
295 /* Enable phy bypass mode to enable the test pattern */
296 enable_phy_bypass_mode(enc10, true);
299 static void set_dp_phy_pattern_80bit_custom(
300 struct dcn10_link_encoder *enc10,
301 const uint8_t *pattern)
303 /* Disable PHY Bypass mode to setup the test pattern */
304 enable_phy_bypass_mode(enc10, false);
306 /* Enable debug symbols on the lanes */
308 disable_prbs_symbols(enc10, true);
310 /* Enable PHY bypass mode to enable the test pattern */
311 /* TODO is it really needed ? */
313 enable_phy_bypass_mode(enc10, true);
315 /* Program 80 bit custom pattern */
317 uint16_t pattern_symbols[8];
320 ((pattern[1] & 0x03) << 8) | pattern[0];
322 ((pattern[2] & 0x0f) << 6) | ((pattern[1] >> 2) & 0x3f);
324 ((pattern[3] & 0x3f) << 4) | ((pattern[2] >> 4) & 0x0f);
326 (pattern[4] << 2) | ((pattern[3] >> 6) & 0x03);
328 ((pattern[6] & 0x03) << 8) | pattern[5];
330 ((pattern[7] & 0x0f) << 6) | ((pattern[6] >> 2) & 0x3f);
332 ((pattern[8] & 0x3f) << 4) | ((pattern[7] >> 4) & 0x0f);
334 (pattern[9] << 2) | ((pattern[8] >> 6) & 0x03);
336 program_pattern_symbols(enc10, pattern_symbols);
339 /* Enable phy bypass mode to enable the test pattern */
341 enable_phy_bypass_mode(enc10, true);
344 static void set_dp_phy_pattern_hbr2_compliance_cp2520_2(
345 struct dcn10_link_encoder *enc10,
346 unsigned int cp2520_pattern)
349 /* previously there is a register DP_HBR2_EYE_PATTERN
350 * that is enabled to get the pattern.
351 * But it does not work with the latest spec change,
352 * so we are programming the following registers manually.
354 * The following settings have been confirmed
355 * by Nick Chorney and Sandra Liu
358 /* Disable PHY Bypass mode to setup the test pattern */
360 enable_phy_bypass_mode(enc10, false);
362 /* Setup DIG encoder in DP SST mode */
363 enc10->base.funcs->setup(&enc10->base, SIGNAL_TYPE_DISPLAY_PORT);
365 /* ensure normal panel mode. */
366 setup_panel_mode(enc10, DP_PANEL_MODE_DEFAULT);
368 /* no vbid after BS (SR)
369 * DP_LINK_FRAMING_CNTL changed history Sandra Liu
370 * 11000260 / 11000104 / 110000FC
372 REG_UPDATE_3(DP_LINK_FRAMING_CNTL,
373 DP_IDLE_BS_INTERVAL, 0xFC,
375 DP_VID_ENHANCED_FRAME_MODE, 1);
377 /* swap every BS with SR */
378 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0);
380 /* select cp2520 patterns */
381 if (REG(DP_DPHY_HBR2_PATTERN_CONTROL))
382 REG_UPDATE(DP_DPHY_HBR2_PATTERN_CONTROL,
383 DP_DPHY_HBR2_PATTERN_CONTROL, cp2520_pattern);
385 /* pre-DCE11 can only generate CP2520 pattern 2 */
386 ASSERT(cp2520_pattern == 2);
388 /* set link training complete */
389 set_link_training_complete(enc10, true);
391 /* disable video stream */
392 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
394 /* Disable PHY Bypass mode to setup the test pattern */
395 enable_phy_bypass_mode(enc10, false);
398 static void set_dp_phy_pattern_passthrough_mode(
399 struct dcn10_link_encoder *enc10,
400 enum dp_panel_mode panel_mode)
402 /* program correct panel mode */
403 setup_panel_mode(enc10, panel_mode);
405 /* restore LINK_FRAMING_CNTL and DPHY_SCRAMBLER_BS_COUNT
406 * in case we were doing HBR2 compliance pattern before
408 REG_UPDATE_3(DP_LINK_FRAMING_CNTL,
409 DP_IDLE_BS_INTERVAL, 0x2000,
411 DP_VID_ENHANCED_FRAME_MODE, 1);
413 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0x1FF);
415 /* set link training complete */
416 set_link_training_complete(enc10, true);
418 /* Disable PHY Bypass mode to setup the test pattern */
419 enable_phy_bypass_mode(enc10, false);
421 /* Disable PRBS mode */
422 disable_prbs_mode(enc10);
425 /* return value is bit-vector */
426 static uint8_t get_frontend_source(
427 enum engine_id engine)
431 return DCN10_DIG_FE_SOURCE_SELECT_DIGA;
433 return DCN10_DIG_FE_SOURCE_SELECT_DIGB;
435 return DCN10_DIG_FE_SOURCE_SELECT_DIGC;
437 return DCN10_DIG_FE_SOURCE_SELECT_DIGD;
439 return DCN10_DIG_FE_SOURCE_SELECT_DIGE;
441 return DCN10_DIG_FE_SOURCE_SELECT_DIGF;
443 return DCN10_DIG_FE_SOURCE_SELECT_DIGG;
445 ASSERT_CRITICAL(false);
446 return DCN10_DIG_FE_SOURCE_SELECT_INVALID;
450 unsigned int dcn10_get_dig_frontend(struct link_encoder *enc)
452 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
454 enum engine_id result;
456 REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &value);
459 case DCN10_DIG_FE_SOURCE_SELECT_DIGA:
460 result = ENGINE_ID_DIGA;
462 case DCN10_DIG_FE_SOURCE_SELECT_DIGB:
463 result = ENGINE_ID_DIGB;
465 case DCN10_DIG_FE_SOURCE_SELECT_DIGC:
466 result = ENGINE_ID_DIGC;
468 case DCN10_DIG_FE_SOURCE_SELECT_DIGD:
469 result = ENGINE_ID_DIGD;
471 case DCN10_DIG_FE_SOURCE_SELECT_DIGE:
472 result = ENGINE_ID_DIGE;
474 case DCN10_DIG_FE_SOURCE_SELECT_DIGF:
475 result = ENGINE_ID_DIGF;
477 case DCN10_DIG_FE_SOURCE_SELECT_DIGG:
478 result = ENGINE_ID_DIGG;
481 // invalid source select DIG
483 result = ENGINE_ID_UNKNOWN;
490 void enc1_configure_encoder(
491 struct dcn10_link_encoder *enc10,
492 const struct dc_link_settings *link_settings)
494 /* set number of lanes */
495 REG_SET(DP_CONFIG, 0,
496 DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE);
498 /* setup scrambler */
499 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, 1);
502 void dcn10_psr_program_dp_dphy_fast_training(struct link_encoder *enc,
503 bool exit_link_training_required)
505 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
507 if (exit_link_training_required)
508 REG_UPDATE(DP_DPHY_FAST_TRAINING,
509 DPHY_RX_FAST_TRAINING_CAPABLE, 1);
511 REG_UPDATE(DP_DPHY_FAST_TRAINING,
512 DPHY_RX_FAST_TRAINING_CAPABLE, 0);
513 /*In DCE 11, we are able to pre-program a Force SR register
514 * to be able to trigger SR symbol after 5 idle patterns
515 * transmitted. Upon PSR Exit, DMCU can trigger
516 * DPHY_LOAD_BS_COUNT_START = 1. Upon writing 1 to
517 * DPHY_LOAD_BS_COUNT_START and the internal counter
518 * reaches DPHY_LOAD_BS_COUNT, the next BS symbol will be
519 * replaced by SR symbol once.
522 REG_UPDATE(DP_DPHY_BS_SR_SWAP_CNTL, DPHY_LOAD_BS_COUNT, 0x5);
526 void dcn10_psr_program_secondary_packet(struct link_encoder *enc,
527 unsigned int sdp_transmit_line_num_deadline)
529 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
531 REG_UPDATE_2(DP_SEC_CNTL1,
532 DP_SEC_GSP0_LINE_NUM, sdp_transmit_line_num_deadline,
533 DP_SEC_GSP0_PRIORITY, 1);
536 bool dcn10_is_dig_enabled(struct link_encoder *enc)
538 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
541 REG_GET(DIG_BE_EN_CNTL, DIG_ENABLE, &value);
545 static void link_encoder_disable(struct dcn10_link_encoder *enc10)
547 /* reset training pattern */
548 REG_SET(DP_DPHY_TRAINING_PATTERN_SEL, 0,
549 DPHY_TRAINING_PATTERN_SEL, 0);
551 /* reset training complete */
552 REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, 0);
554 /* reset panel mode */
555 setup_panel_mode(enc10, DP_PANEL_MODE_DEFAULT);
558 static void hpd_initialize(
559 struct dcn10_link_encoder *enc10)
561 /* Associate HPD with DIG_BE */
562 enum hpd_source_id hpd_source = enc10->base.hpd_source;
564 REG_UPDATE(DIG_BE_CNTL, DIG_HPD_SELECT, hpd_source);
567 bool dcn10_link_encoder_validate_dvi_output(
568 const struct dcn10_link_encoder *enc10,
569 enum signal_type connector_signal,
570 enum signal_type signal,
571 const struct dc_crtc_timing *crtc_timing)
573 uint32_t max_pixel_clock = TMDS_MAX_PIXEL_CLOCK;
575 if (signal == SIGNAL_TYPE_DVI_DUAL_LINK)
576 max_pixel_clock *= 2;
578 /* This handles the case of HDMI downgrade to DVI we don't want to
579 * we don't want to cap the pixel clock if the DDI is not DVI.
581 if (connector_signal != SIGNAL_TYPE_DVI_DUAL_LINK &&
582 connector_signal != SIGNAL_TYPE_DVI_SINGLE_LINK)
583 max_pixel_clock = enc10->base.features.max_hdmi_pixel_clock;
585 /* DVI only support RGB pixel encoding */
586 if (crtc_timing->pixel_encoding != PIXEL_ENCODING_RGB)
589 /*connect DVI via adpater's HDMI connector*/
590 if ((connector_signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
591 connector_signal == SIGNAL_TYPE_HDMI_TYPE_A) &&
592 signal != SIGNAL_TYPE_HDMI_TYPE_A &&
593 crtc_timing->pix_clk_100hz > (TMDS_MAX_PIXEL_CLOCK * 10))
595 if (crtc_timing->pix_clk_100hz < (TMDS_MIN_PIXEL_CLOCK * 10))
598 if (crtc_timing->pix_clk_100hz > (max_pixel_clock * 10))
601 /* DVI supports 6/8bpp single-link and 10/16bpp dual-link */
602 switch (crtc_timing->display_color_depth) {
603 case COLOR_DEPTH_666:
604 case COLOR_DEPTH_888:
606 case COLOR_DEPTH_101010:
607 case COLOR_DEPTH_161616:
608 if (signal != SIGNAL_TYPE_DVI_DUAL_LINK)
618 static bool dcn10_link_encoder_validate_hdmi_output(
619 const struct dcn10_link_encoder *enc10,
620 const struct dc_crtc_timing *crtc_timing,
621 int adjusted_pix_clk_100hz)
623 enum dc_color_depth max_deep_color =
624 enc10->base.features.max_hdmi_deep_color;
626 if (max_deep_color < crtc_timing->display_color_depth)
629 if (crtc_timing->display_color_depth < COLOR_DEPTH_888)
631 if (adjusted_pix_clk_100hz < (TMDS_MIN_PIXEL_CLOCK * 10))
634 if ((adjusted_pix_clk_100hz == 0) ||
635 (adjusted_pix_clk_100hz > (enc10->base.features.max_hdmi_pixel_clock * 10)))
638 /* DCE11 HW does not support 420 */
639 if (!enc10->base.features.hdmi_ycbcr420_supported &&
640 crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
643 if (!enc10->base.features.flags.bits.HDMI_6GB_EN &&
644 adjusted_pix_clk_100hz >= 3000000)
646 if (enc10->base.ctx->dc->debug.hdmi20_disable &&
647 crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
652 bool dcn10_link_encoder_validate_dp_output(
653 const struct dcn10_link_encoder *enc10,
654 const struct dc_crtc_timing *crtc_timing)
656 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) {
657 if (!enc10->base.features.dp_ycbcr420_supported)
664 void dcn10_link_encoder_construct(
665 struct dcn10_link_encoder *enc10,
666 const struct encoder_init_data *init_data,
667 const struct encoder_feature_support *enc_features,
668 const struct dcn10_link_enc_registers *link_regs,
669 const struct dcn10_link_enc_aux_registers *aux_regs,
670 const struct dcn10_link_enc_hpd_registers *hpd_regs,
671 const struct dcn10_link_enc_shift *link_shift,
672 const struct dcn10_link_enc_mask *link_mask)
674 struct bp_encoder_cap_info bp_cap_info = {0};
675 const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
676 enum bp_result result = BP_RESULT_OK;
678 enc10->base.funcs = &dcn10_lnk_enc_funcs;
679 enc10->base.ctx = init_data->ctx;
680 enc10->base.id = init_data->encoder;
682 enc10->base.hpd_source = init_data->hpd_source;
683 enc10->base.connector = init_data->connector;
685 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
687 enc10->base.features = *enc_features;
689 enc10->base.transmitter = init_data->transmitter;
691 /* set the flag to indicate whether driver poll the I2C data pin
692 * while doing the DP sink detect
695 /* if (dal_adapter_service_is_feature_supported(as,
696 FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
697 enc10->base.features.flags.bits.
698 DP_SINK_DETECT_POLL_DATA_PIN = true;*/
700 enc10->base.output_signals =
701 SIGNAL_TYPE_DVI_SINGLE_LINK |
702 SIGNAL_TYPE_DVI_DUAL_LINK |
704 SIGNAL_TYPE_DISPLAY_PORT |
705 SIGNAL_TYPE_DISPLAY_PORT_MST |
707 SIGNAL_TYPE_HDMI_TYPE_A;
709 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE.
710 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY.
711 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer
712 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS.
713 * Prefer DIG assignment is decided by board design.
714 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design
715 * and VBIOS will filter out 7 UNIPHY for DCE 8.0.
716 * By this, adding DIGG should not hurt DCE 8.0.
717 * This will let DCE 8.1 share DCE 8.0 as much as possible
720 enc10->link_regs = link_regs;
721 enc10->aux_regs = aux_regs;
722 enc10->hpd_regs = hpd_regs;
723 enc10->link_shift = link_shift;
724 enc10->link_mask = link_mask;
726 switch (enc10->base.transmitter) {
727 case TRANSMITTER_UNIPHY_A:
728 enc10->base.preferred_engine = ENGINE_ID_DIGA;
730 case TRANSMITTER_UNIPHY_B:
731 enc10->base.preferred_engine = ENGINE_ID_DIGB;
733 case TRANSMITTER_UNIPHY_C:
734 enc10->base.preferred_engine = ENGINE_ID_DIGC;
736 case TRANSMITTER_UNIPHY_D:
737 enc10->base.preferred_engine = ENGINE_ID_DIGD;
739 case TRANSMITTER_UNIPHY_E:
740 enc10->base.preferred_engine = ENGINE_ID_DIGE;
742 case TRANSMITTER_UNIPHY_F:
743 enc10->base.preferred_engine = ENGINE_ID_DIGF;
745 case TRANSMITTER_UNIPHY_G:
746 enc10->base.preferred_engine = ENGINE_ID_DIGG;
749 ASSERT_CRITICAL(false);
750 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
753 /* default to one to mirror Windows behavior */
754 enc10->base.features.flags.bits.HDMI_6GB_EN = 1;
756 result = bp_funcs->get_encoder_cap_info(enc10->base.ctx->dc_bios,
757 enc10->base.id, &bp_cap_info);
759 /* Override features with DCE-specific values */
760 if (result == BP_RESULT_OK) {
761 enc10->base.features.flags.bits.IS_HBR2_CAPABLE =
762 bp_cap_info.DP_HBR2_EN;
763 enc10->base.features.flags.bits.IS_HBR3_CAPABLE =
764 bp_cap_info.DP_HBR3_EN;
765 enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
766 enc10->base.features.flags.bits.DP_IS_USB_C =
767 bp_cap_info.DP_IS_USB_C;
769 DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
773 if (enc10->base.ctx->dc->debug.hdmi20_disable) {
774 enc10->base.features.flags.bits.HDMI_6GB_EN = 0;
778 bool dcn10_link_encoder_validate_output_with_stream(
779 struct link_encoder *enc,
780 const struct dc_stream_state *stream)
782 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
785 switch (stream->signal) {
786 case SIGNAL_TYPE_DVI_SINGLE_LINK:
787 case SIGNAL_TYPE_DVI_DUAL_LINK:
788 is_valid = dcn10_link_encoder_validate_dvi_output(
790 stream->link->connector_signal,
794 case SIGNAL_TYPE_HDMI_TYPE_A:
795 is_valid = dcn10_link_encoder_validate_hdmi_output(
798 stream->phy_pix_clk * 10);
800 case SIGNAL_TYPE_DISPLAY_PORT:
801 case SIGNAL_TYPE_DISPLAY_PORT_MST:
802 is_valid = dcn10_link_encoder_validate_dp_output(
803 enc10, &stream->timing);
805 case SIGNAL_TYPE_EDP:
806 is_valid = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ? true : false;
808 case SIGNAL_TYPE_VIRTUAL:
819 void dcn10_link_encoder_hw_init(
820 struct link_encoder *enc)
822 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
823 struct bp_transmitter_control cntl = { 0 };
824 enum bp_result result;
826 cntl.action = TRANSMITTER_CONTROL_INIT;
827 cntl.engine_id = ENGINE_ID_UNKNOWN;
828 cntl.transmitter = enc10->base.transmitter;
829 cntl.connector_obj_id = enc10->base.connector;
830 cntl.lanes_number = LANE_COUNT_FOUR;
831 cntl.coherent = false;
832 cntl.hpd_sel = enc10->base.hpd_source;
834 if (enc10->base.connector.id == CONNECTOR_ID_EDP)
835 cntl.signal = SIGNAL_TYPE_EDP;
837 result = link_transmitter_control(enc10, &cntl);
839 if (result != BP_RESULT_OK) {
840 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
846 if (enc10->base.connector.id == CONNECTOR_ID_LVDS) {
847 cntl.action = TRANSMITTER_CONTROL_BACKLIGHT_BRIGHTNESS;
849 result = link_transmitter_control(enc10, &cntl);
851 ASSERT(result == BP_RESULT_OK);
854 dcn10_aux_initialize(enc10);
857 * hpd_initialize() will pass DIG_FE id to HW context.
858 * All other routine within HW context will use fe_engine_offset
859 * as DIG_FE id even caller pass DIG_FE id.
860 * So this routine must be called first.
862 hpd_initialize(enc10);
865 void dcn10_link_encoder_destroy(struct link_encoder **enc)
867 kfree(TO_DCN10_LINK_ENC(*enc));
871 void dcn10_link_encoder_setup(
872 struct link_encoder *enc,
873 enum signal_type signal)
875 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
878 case SIGNAL_TYPE_EDP:
879 case SIGNAL_TYPE_DISPLAY_PORT:
881 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 0);
883 case SIGNAL_TYPE_LVDS:
885 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 1);
887 case SIGNAL_TYPE_DVI_SINGLE_LINK:
888 case SIGNAL_TYPE_DVI_DUAL_LINK:
890 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 2);
892 case SIGNAL_TYPE_HDMI_TYPE_A:
894 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 3);
896 case SIGNAL_TYPE_DISPLAY_PORT_MST:
898 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 5);
901 ASSERT_CRITICAL(false);
908 /* TODO: still need depth or just pass in adjusted pixel clock? */
909 void dcn10_link_encoder_enable_tmds_output(
910 struct link_encoder *enc,
911 enum clock_source_id clock_source,
912 enum dc_color_depth color_depth,
913 enum signal_type signal,
914 uint32_t pixel_clock)
916 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
917 struct bp_transmitter_control cntl = { 0 };
918 enum bp_result result;
922 cntl.action = TRANSMITTER_CONTROL_ENABLE;
923 cntl.engine_id = enc->preferred_engine;
924 cntl.transmitter = enc10->base.transmitter;
925 cntl.pll_id = clock_source;
926 cntl.signal = signal;
927 if (cntl.signal == SIGNAL_TYPE_DVI_DUAL_LINK)
928 cntl.lanes_number = 8;
930 cntl.lanes_number = 4;
932 cntl.hpd_sel = enc10->base.hpd_source;
934 cntl.pixel_clock = pixel_clock;
935 cntl.color_depth = color_depth;
937 result = link_transmitter_control(enc10, &cntl);
939 if (result != BP_RESULT_OK) {
940 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
946 /* enables DP PHY output */
947 void dcn10_link_encoder_enable_dp_output(
948 struct link_encoder *enc,
949 const struct dc_link_settings *link_settings,
950 enum clock_source_id clock_source)
952 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
953 struct bp_transmitter_control cntl = { 0 };
954 enum bp_result result;
958 /* number_of_lanes is used for pixel clock adjust,
959 * but it's not passed to asic_control.
960 * We need to set number of lanes manually.
962 enc1_configure_encoder(enc10, link_settings);
964 cntl.action = TRANSMITTER_CONTROL_ENABLE;
965 cntl.engine_id = enc->preferred_engine;
966 cntl.transmitter = enc10->base.transmitter;
967 cntl.pll_id = clock_source;
968 cntl.signal = SIGNAL_TYPE_DISPLAY_PORT;
969 cntl.lanes_number = link_settings->lane_count;
970 cntl.hpd_sel = enc10->base.hpd_source;
971 cntl.pixel_clock = link_settings->link_rate
972 * LINK_RATE_REF_FREQ_IN_KHZ;
973 /* TODO: check if undefined works */
974 cntl.color_depth = COLOR_DEPTH_UNDEFINED;
976 result = link_transmitter_control(enc10, &cntl);
978 if (result != BP_RESULT_OK) {
979 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
985 /* enables DP PHY output in MST mode */
986 void dcn10_link_encoder_enable_dp_mst_output(
987 struct link_encoder *enc,
988 const struct dc_link_settings *link_settings,
989 enum clock_source_id clock_source)
991 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
992 struct bp_transmitter_control cntl = { 0 };
993 enum bp_result result;
997 /* number_of_lanes is used for pixel clock adjust,
998 * but it's not passed to asic_control.
999 * We need to set number of lanes manually.
1001 enc1_configure_encoder(enc10, link_settings);
1003 cntl.action = TRANSMITTER_CONTROL_ENABLE;
1004 cntl.engine_id = ENGINE_ID_UNKNOWN;
1005 cntl.transmitter = enc10->base.transmitter;
1006 cntl.pll_id = clock_source;
1007 cntl.signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
1008 cntl.lanes_number = link_settings->lane_count;
1009 cntl.hpd_sel = enc10->base.hpd_source;
1010 cntl.pixel_clock = link_settings->link_rate
1011 * LINK_RATE_REF_FREQ_IN_KHZ;
1012 /* TODO: check if undefined works */
1013 cntl.color_depth = COLOR_DEPTH_UNDEFINED;
1015 result = link_transmitter_control(enc10, &cntl);
1017 if (result != BP_RESULT_OK) {
1018 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
1020 BREAK_TO_DEBUGGER();
1025 * Disable transmitter and its encoder
1027 void dcn10_link_encoder_disable_output(
1028 struct link_encoder *enc,
1029 enum signal_type signal)
1031 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1032 struct bp_transmitter_control cntl = { 0 };
1033 enum bp_result result;
1035 if (!dcn10_is_dig_enabled(enc)) {
1036 /* OF_SKIP_POWER_DOWN_INACTIVE_ENCODER */
1037 /*in DP_Alt_No_Connect case, we turn off the dig already,
1038 after excuation the PHY w/a sequence, not allow touch PHY any more*/
1041 /* Power-down RX and disable GPU PHY should be paired.
1042 * Disabling PHY without powering down RX may cause
1043 * symbol lock loss, on which we will get DP Sink interrupt.
1046 /* There is a case for the DP active dongles
1047 * where we want to disable the PHY but keep RX powered,
1048 * for those we need to ignore DP Sink interrupt
1049 * by checking lane count that has been set
1050 * on the last do_enable_output().
1053 /* disable transmitter */
1054 cntl.action = TRANSMITTER_CONTROL_DISABLE;
1055 cntl.transmitter = enc10->base.transmitter;
1056 cntl.hpd_sel = enc10->base.hpd_source;
1057 cntl.signal = signal;
1058 cntl.connector_obj_id = enc10->base.connector;
1060 result = link_transmitter_control(enc10, &cntl);
1062 if (result != BP_RESULT_OK) {
1063 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
1065 BREAK_TO_DEBUGGER();
1069 /* disable encoder */
1070 if (dc_is_dp_signal(signal))
1071 link_encoder_disable(enc10);
1074 void dcn10_link_encoder_dp_set_lane_settings(
1075 struct link_encoder *enc,
1076 const struct link_training_settings *link_settings)
1078 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1079 union dpcd_training_lane_set training_lane_set = { { 0 } };
1081 struct bp_transmitter_control cntl = { 0 };
1083 if (!link_settings) {
1084 BREAK_TO_DEBUGGER();
1088 cntl.action = TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS;
1089 cntl.transmitter = enc10->base.transmitter;
1090 cntl.connector_obj_id = enc10->base.connector;
1091 cntl.lanes_number = link_settings->link_settings.lane_count;
1092 cntl.hpd_sel = enc10->base.hpd_source;
1093 cntl.pixel_clock = link_settings->link_settings.link_rate *
1094 LINK_RATE_REF_FREQ_IN_KHZ;
1096 for (lane = 0; lane < link_settings->link_settings.lane_count; lane++) {
1097 /* translate lane settings */
1099 training_lane_set.bits.VOLTAGE_SWING_SET =
1100 link_settings->lane_settings[lane].VOLTAGE_SWING;
1101 training_lane_set.bits.PRE_EMPHASIS_SET =
1102 link_settings->lane_settings[lane].PRE_EMPHASIS;
1104 /* post cursor 2 setting only applies to HBR2 link rate */
1105 if (link_settings->link_settings.link_rate == LINK_RATE_HIGH2) {
1106 /* this is passed to VBIOS
1107 * to program post cursor 2 level
1109 training_lane_set.bits.POST_CURSOR2_SET =
1110 link_settings->lane_settings[lane].POST_CURSOR2;
1113 cntl.lane_select = lane;
1114 cntl.lane_settings = training_lane_set.raw;
1116 /* call VBIOS table to set voltage swing and pre-emphasis */
1117 link_transmitter_control(enc10, &cntl);
1121 /* set DP PHY test and training patterns */
1122 void dcn10_link_encoder_dp_set_phy_pattern(
1123 struct link_encoder *enc,
1124 const struct encoder_set_dp_phy_pattern_param *param)
1126 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1128 switch (param->dp_phy_pattern) {
1129 case DP_TEST_PATTERN_TRAINING_PATTERN1:
1130 dcn10_link_encoder_set_dp_phy_pattern_training_pattern(enc, 0);
1132 case DP_TEST_PATTERN_TRAINING_PATTERN2:
1133 dcn10_link_encoder_set_dp_phy_pattern_training_pattern(enc, 1);
1135 case DP_TEST_PATTERN_TRAINING_PATTERN3:
1136 dcn10_link_encoder_set_dp_phy_pattern_training_pattern(enc, 2);
1138 case DP_TEST_PATTERN_TRAINING_PATTERN4:
1139 dcn10_link_encoder_set_dp_phy_pattern_training_pattern(enc, 3);
1141 case DP_TEST_PATTERN_D102:
1142 set_dp_phy_pattern_d102(enc10);
1144 case DP_TEST_PATTERN_SYMBOL_ERROR:
1145 set_dp_phy_pattern_symbol_error(enc10);
1147 case DP_TEST_PATTERN_PRBS7:
1148 set_dp_phy_pattern_prbs7(enc10);
1150 case DP_TEST_PATTERN_80BIT_CUSTOM:
1151 set_dp_phy_pattern_80bit_custom(
1152 enc10, param->custom_pattern);
1154 case DP_TEST_PATTERN_CP2520_1:
1155 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc10, 1);
1157 case DP_TEST_PATTERN_CP2520_2:
1158 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc10, 2);
1160 case DP_TEST_PATTERN_CP2520_3:
1161 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc10, 3);
1163 case DP_TEST_PATTERN_VIDEO_MODE: {
1164 set_dp_phy_pattern_passthrough_mode(
1165 enc10, param->dp_panel_mode);
1170 /* invalid phy pattern */
1171 ASSERT_CRITICAL(false);
1176 static void fill_stream_allocation_row_info(
1177 const struct link_mst_stream_allocation *stream_allocation,
1181 const struct stream_encoder *stream_enc = stream_allocation->stream_enc;
1184 *src = stream_enc->id;
1185 *slots = stream_allocation->slot_count;
1192 /* programs DP MST VC payload allocation */
1193 void dcn10_link_encoder_update_mst_stream_allocation_table(
1194 struct link_encoder *enc,
1195 const struct link_mst_stream_allocation_table *table)
1197 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1198 uint32_t value0 = 0;
1199 uint32_t value1 = 0;
1200 uint32_t value2 = 0;
1203 uint32_t retries = 0;
1205 /* For CZ, there are only 3 pipes. So Virtual channel is up 3.*/
1207 /* --- Set MSE Stream Attribute -
1208 * Setup VC Payload Table on Tx Side,
1209 * Issue allocation change trigger
1210 * to commit payload on both tx and rx side
1213 /* we should clean-up table each time */
1215 if (table->stream_count >= 1) {
1216 fill_stream_allocation_row_info(
1217 &table->stream_allocations[0],
1225 REG_UPDATE_2(DP_MSE_SAT0,
1226 DP_MSE_SAT_SRC0, src,
1227 DP_MSE_SAT_SLOT_COUNT0, slots);
1229 if (table->stream_count >= 2) {
1230 fill_stream_allocation_row_info(
1231 &table->stream_allocations[1],
1239 REG_UPDATE_2(DP_MSE_SAT0,
1240 DP_MSE_SAT_SRC1, src,
1241 DP_MSE_SAT_SLOT_COUNT1, slots);
1243 if (table->stream_count >= 3) {
1244 fill_stream_allocation_row_info(
1245 &table->stream_allocations[2],
1253 REG_UPDATE_2(DP_MSE_SAT1,
1254 DP_MSE_SAT_SRC2, src,
1255 DP_MSE_SAT_SLOT_COUNT2, slots);
1257 if (table->stream_count >= 4) {
1258 fill_stream_allocation_row_info(
1259 &table->stream_allocations[3],
1267 REG_UPDATE_2(DP_MSE_SAT1,
1268 DP_MSE_SAT_SRC3, src,
1269 DP_MSE_SAT_SLOT_COUNT3, slots);
1271 /* --- wait for transaction finish */
1273 /* send allocation change trigger (ACT) ?
1274 * this step first sends the ACT,
1275 * then double buffers the SAT into the hardware
1276 * making the new allocation active on the DP MST mode link
1279 /* DP_MSE_SAT_UPDATE:
1281 * 1 - Update SAT with trigger
1282 * 2 - Update SAT without trigger
1284 REG_UPDATE(DP_MSE_SAT_UPDATE,
1285 DP_MSE_SAT_UPDATE, 1);
1287 /* wait for update to complete
1288 * (i.e. DP_MSE_SAT_UPDATE field is reset to 0)
1289 * then wait for the transmission
1290 * of at least 16 MTP headers on immediate local link.
1291 * i.e. DP_MSE_16_MTP_KEEPOUT field (read only) is reset to 0
1292 * a value of 1 indicates that DP MST mode
1293 * is in the 16 MTP keepout region after a VC has been added.
1294 * MST stream bandwidth (VC rate) can be configured
1295 * after this bit is cleared
1300 value0 = REG_READ(DP_MSE_SAT_UPDATE);
1302 REG_GET(DP_MSE_SAT_UPDATE,
1303 DP_MSE_SAT_UPDATE, &value1);
1305 REG_GET(DP_MSE_SAT_UPDATE,
1306 DP_MSE_16_MTP_KEEPOUT, &value2);
1308 /* bit field DP_MSE_SAT_UPDATE is set to 1 already */
1309 if (!value1 && !value2)
1312 } while (retries < DP_MST_UPDATE_MAX_RETRY);
1315 void dcn10_link_encoder_connect_dig_be_to_fe(
1316 struct link_encoder *enc,
1317 enum engine_id engine,
1320 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1323 if (engine != ENGINE_ID_UNKNOWN) {
1325 REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &field);
1328 field |= get_frontend_source(engine);
1330 field &= ~get_frontend_source(engine);
1332 REG_UPDATE(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, field);
1337 #define HPD_REG(reg)\
1338 (enc10->hpd_regs->reg)
1340 #define HPD_REG_READ(reg_name) \
1341 dm_read_reg(CTX, HPD_REG(reg_name))
1343 #define HPD_REG_UPDATE_N(reg_name, n, ...) \
1344 generic_reg_update_ex(CTX, \
1345 HPD_REG(reg_name), \
1348 #define HPD_REG_UPDATE(reg_name, field, val) \
1349 HPD_REG_UPDATE_N(reg_name, 1, \
1350 FN(reg_name, field), val)
1352 void dcn10_link_encoder_enable_hpd(struct link_encoder *enc)
1354 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1356 HPD_REG_UPDATE(DC_HPD_CONTROL,
1360 void dcn10_link_encoder_disable_hpd(struct link_encoder *enc)
1362 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1364 HPD_REG_UPDATE(DC_HPD_CONTROL,
1369 #define AUX_REG(reg)\
1370 (enc10->aux_regs->reg)
1372 #define AUX_REG_READ(reg_name) \
1373 dm_read_reg(CTX, AUX_REG(reg_name))
1375 #define AUX_REG_UPDATE_N(reg_name, n, ...) \
1376 generic_reg_update_ex(CTX, \
1377 AUX_REG(reg_name), \
1380 #define AUX_REG_UPDATE(reg_name, field, val) \
1381 AUX_REG_UPDATE_N(reg_name, 1, \
1382 FN(reg_name, field), val)
1384 #define AUX_REG_UPDATE_2(reg, f1, v1, f2, v2) \
1385 AUX_REG_UPDATE_N(reg, 2,\
1389 void dcn10_aux_initialize(struct dcn10_link_encoder *enc10)
1391 enum hpd_source_id hpd_source = enc10->base.hpd_source;
1393 AUX_REG_UPDATE_2(AUX_CONTROL,
1394 AUX_HPD_SEL, hpd_source,
1397 /* 1/4 window (the maximum allowed) */
1398 AUX_REG_UPDATE(AUX_DPHY_RX_CONTROL0,
1399 AUX_RX_RECEIVE_WINDOW, 0);
1402 enum signal_type dcn10_get_dig_mode(
1403 struct link_encoder *enc)
1405 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1407 REG_GET(DIG_BE_CNTL, DIG_MODE, &value);
1410 return SIGNAL_TYPE_DISPLAY_PORT;
1412 return SIGNAL_TYPE_DVI_SINGLE_LINK;
1414 return SIGNAL_TYPE_HDMI_TYPE_A;
1416 return SIGNAL_TYPE_DISPLAY_PORT_MST;
1418 return SIGNAL_TYPE_NONE;
1420 return SIGNAL_TYPE_NONE;