drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h

   1 /*
   2 * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #ifndef __DC_HWSS_DCN10_H__
  27 #define __DC_HWSS_DCN10_H__
  28
  29 #include "core_types.h"
  30
  31 struct dc;
  32
  33 void dcn10_hw_sequencer_construct(struct dc *dc);
  34
  35 int dcn10_get_vupdate_offset_from_vsync(struct pipe_ctx *pipe_ctx);
  36 void dcn10_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx);
  37 enum dc_status dcn10_enable_stream_timing(
  38                 struct pipe_ctx *pipe_ctx,
  39                 struct dc_state *context,
  40                 struct dc *dc);
  41 void dcn10_optimize_bandwidth(
  42                 struct dc *dc,
  43                 struct dc_state *context);
  44 void dcn10_prepare_bandwidth(
  45                 struct dc *dc,
  46                 struct dc_state *context);
  47 void dcn10_pipe_control_lock(
  48         struct dc *dc,
  49         struct pipe_ctx *pipe,
  50         bool lock);
  51 void dcn10_blank_pixel_data(
  52                 struct dc *dc,
  53                 struct pipe_ctx *pipe_ctx,
  54                 bool blank);
  55 void dcn10_unblank_stream(struct pipe_ctx *pipe_ctx,
  56                 struct dc_link_settings *link_settings);
  57 void dcn10_program_output_csc(struct dc *dc,
  58                 struct pipe_ctx *pipe_ctx,
  59                 enum dc_color_space colorspace,
  60                 uint16_t *matrix,
  61                 int opp_id);
  62 bool dcn10_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
  63                                 const struct dc_stream_state *stream);
  64 bool dcn10_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
  65                         const struct dc_plane_state *plane_state);
  66 void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx);
  67 void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);
  68 void dcn10_reset_hw_ctx_wrap(
  69                 struct dc *dc,
  70                 struct dc_state *context);
  71 void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx);
  72 void dcn10_apply_ctx_for_surface(
  73                 struct dc *dc,
  74                 const struct dc_stream_state *stream,
  75                 int num_planes,
  76                 struct dc_state *context);
  77 void dcn10_hubp_pg_control(
  78                 struct dce_hwseq *hws,
  79                 unsigned int hubp_inst,
  80                 bool power_on);
  81 void dcn10_dpp_pg_control(
  82                 struct dce_hwseq *hws,
  83                 unsigned int dpp_inst,
  84                 bool power_on);
  85 void dcn10_enable_power_gating_plane(
  86         struct dce_hwseq *hws,
  87         bool enable);
  88 void dcn10_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx);
  89 void dcn10_disable_vga(
  90         struct dce_hwseq *hws);
  91 void dcn10_program_pipe(
  92                 struct dc *dc,
  93                 struct pipe_ctx *pipe_ctx,
  94                 struct dc_state *context);
  95 void dcn10_program_gamut_remap(struct pipe_ctx *pipe_ctx);
  96 void dcn10_init_hw(struct dc *dc);
  97 void dcn10_init_pipes(struct dc *dc, struct dc_state *context);
  98 enum dc_status dce110_apply_ctx_to_hw(
  99                 struct dc *dc,
 100                 struct dc_state *context);
 101 void dcn10_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx);
 102 void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data);
 103 void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx);
 104 void dce110_power_down(struct dc *dc);
 105 void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context);
 106 void dcn10_enable_timing_synchronization(
 107                 struct dc *dc,
 108                 int group_index,
 109                 int group_size,
 110                 struct pipe_ctx *grouped_pipes[]);
 111 void dcn10_enable_per_frame_crtc_position_reset(
 112                 struct dc *dc,
 113                 int group_size,
 114                 struct pipe_ctx *grouped_pipes[]);
 115 void dce110_update_info_frame(struct pipe_ctx *pipe_ctx);
 116 void dcn10_send_immediate_sdp_message(struct pipe_ctx *pipe_ctx,
 117                 const uint8_t *custom_sdp_message,
 118                 unsigned int sdp_message_size);
 119 void dce110_blank_stream(struct pipe_ctx *pipe_ctx);
 120 void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx);
 121 void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx);
 122 bool dcn10_dummy_display_power_gating(
 123                 struct dc *dc,
 124                 uint8_t controller_id,
 125                 struct dc_bios *dcb,
 126                 enum pipe_gating_control power_gating);
 127 void dcn10_set_drr(struct pipe_ctx **pipe_ctx,
 128                 int num_pipes, unsigned int vmin, unsigned int vmax,
 129                 unsigned int vmid, unsigned int vmid_frame_number);
 130 void dcn10_get_position(struct pipe_ctx **pipe_ctx,
 131                 int num_pipes,
 132                 struct crtc_position *position);
 133 void dcn10_set_static_screen_control(struct pipe_ctx **pipe_ctx,
 134                 int num_pipes, const struct dc_static_screen_events *events);
 135 void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc);
 136 void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);
 137 void dcn10_log_hw_state(struct dc *dc,
 138                 struct dc_log_buffer_ctx *log_ctx);
 139 void dcn10_get_hw_state(struct dc *dc,
 140                 char *pBuf,
 141                 unsigned int bufSize,
 142                 unsigned int mask);
 143 void dcn10_clear_status_bits(struct dc *dc, unsigned int mask);
 144 void dcn10_wait_for_mpcc_disconnect(
 145                 struct dc *dc,
 146                 struct resource_pool *res_pool,
 147                 struct pipe_ctx *pipe_ctx);
 148 void dce110_edp_backlight_control(
 149                 struct dc_link *link,
 150                 bool enable);
 151 void dce110_edp_power_control(
 152                 struct dc_link *link,
 153                 bool power_up);
 154 void dce110_edp_wait_for_hpd_ready(
 155                 struct dc_link *link,
 156                 bool power_up);
 157 void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx);
 158 void dcn10_set_cursor_attribute(struct pipe_ctx *pipe_ctx);
 159 void dcn10_set_cursor_sdr_white_level(struct pipe_ctx *pipe_ctx);
 160 void dcn10_setup_periodic_interrupt(
 161                 struct dc *dc,
 162                 struct pipe_ctx *pipe_ctx,
 163                 enum vline_select vline);
 164 enum dc_status dcn10_set_clock(struct dc *dc,
 165                 enum dc_clock_type clock_type,
 166                 uint32_t clk_khz,
 167                 uint32_t stepping);
 168 void dcn10_get_clock(struct dc *dc,
 169                 enum dc_clock_type clock_type,
 170                 struct dc_clock_config *clock_cfg);
 171 bool dcn10_did_underflow_occur(struct dc *dc, struct pipe_ctx *pipe_ctx);
 172 void dcn10_bios_golden_init(struct dc *dc);
 173 void dcn10_plane_atomic_power_down(struct dc *dc,
 174                 struct dpp *dpp,
 175                 struct hubp *hubp);
 176 void dcn10_get_surface_visual_confirm_color(
 177                 const struct pipe_ctx *pipe_ctx,
 178                 struct tg_color *color);
 179 void dcn10_get_hdr_visual_confirm_color(
 180                 struct pipe_ctx *pipe_ctx,
 181                 struct tg_color *color);
 182 void dcn10_set_hdr_multiplier(struct pipe_ctx *pipe_ctx);
 183 void dcn10_verify_allow_pstate_change_high(struct dc *dc);
 184
 185 #endif /* __DC_HWSS_DCN10_H__ */