drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/delay.h>
  27 #include "dm_services.h"
  28 #include "basics/dc_common.h"
  29 #include "core_types.h"
  30 #include "resource.h"
  31 #include "custom_float.h"
  32 #include "dcn10_hw_sequencer.h"
  33 #include "dcn10_hw_sequencer_debug.h"
  34 #include "dce/dce_hwseq.h"
  35 #include "abm.h"
  36 #include "dmcu.h"
  37 #include "dcn10_optc.h"
  38 #include "dcn10_dpp.h"
  39 #include "dcn10_mpc.h"
  40 #include "timing_generator.h"
  41 #include "opp.h"
  42 #include "ipp.h"
  43 #include "mpc.h"
  44 #include "reg_helper.h"
  45 #include "dcn10_hubp.h"
  46 #include "dcn10_hubbub.h"
  47 #include "dcn10_cm_common.h"
  48 #include "dc_link_dp.h"
  49 #include "dccg.h"
  50 #include "clk_mgr.h"
  51
  52
  53 #include "dsc.h"
  54
  55 #define DC_LOGGER_INIT(logger)
  56
  57 #define CTX \
  58         hws->ctx
  59 #define REG(reg)\
  60         hws->regs->reg
  61
  62 #undef FN
  63 #define FN(reg_name, field_name) \
  64         hws->shifts->field_name, hws->masks->field_name
  65
  66 /*print is 17 wide, first two characters are spaces*/
  67 #define DTN_INFO_MICRO_SEC(ref_cycle) \
  68         print_microsec(dc_ctx, log_ctx, ref_cycle)
  69
  70 #define GAMMA_HW_POINTS_NUM 256
  71
  72 void print_microsec(struct dc_context *dc_ctx,
  73         struct dc_log_buffer_ctx *log_ctx,
  74         uint32_t ref_cycle)
  75 {
  76         const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000;
  77         static const unsigned int frac = 1000;
  78         uint32_t us_x10 = (ref_cycle * frac) / ref_clk_mhz;
  79
  80         DTN_INFO("  %11d.%03d",
  81                         us_x10 / frac,
  82                         us_x10 % frac);
  83 }
  84
  85 void dcn10_lock_all_pipes(struct dc *dc,
  86         struct dc_state *context,
  87         bool lock)
  88 {
  89         struct pipe_ctx *pipe_ctx;
  90         struct timing_generator *tg;
  91         int i;
  92
  93         for (i = 0; i < dc->res_pool->pipe_count; i++) {
  94                 pipe_ctx = &context->res_ctx.pipe_ctx[i];
  95                 tg = pipe_ctx->stream_res.tg;
  96
  97                 /*
  98                  * Only lock the top pipe's tg to prevent redundant
  99                  * (un)locking. Also skip if pipe is disabled.
 100                  */
 101                 if (pipe_ctx->top_pipe ||
 102                     !pipe_ctx->stream || !pipe_ctx->plane_state ||
 103                     !tg->funcs->is_tg_enabled(tg))
 104                         continue;
 105
 106                 if (lock)
 107                         dc->hwss.pipe_control_lock(dc, pipe_ctx, true);
 108                 else
 109                         dc->hwss.pipe_control_lock(dc, pipe_ctx, false);
 110         }
 111 }
 112
 113 static void log_mpc_crc(struct dc *dc,
 114         struct dc_log_buffer_ctx *log_ctx)
 115 {
 116         struct dc_context *dc_ctx = dc->ctx;
 117         struct dce_hwseq *hws = dc->hwseq;
 118
 119         if (REG(MPC_CRC_RESULT_GB))
 120                 DTN_INFO("MPC_CRC_RESULT_GB:%d MPC_CRC_RESULT_C:%d MPC_CRC_RESULT_AR:%d\n",
 121                 REG_READ(MPC_CRC_RESULT_GB), REG_READ(MPC_CRC_RESULT_C), REG_READ(MPC_CRC_RESULT_AR));
 122         if (REG(DPP_TOP0_DPP_CRC_VAL_B_A))
 123                 DTN_INFO("DPP_TOP0_DPP_CRC_VAL_B_A:%d DPP_TOP0_DPP_CRC_VAL_R_G:%d\n",
 124                 REG_READ(DPP_TOP0_DPP_CRC_VAL_B_A), REG_READ(DPP_TOP0_DPP_CRC_VAL_R_G));
 125 }
 126
 127 void dcn10_log_hubbub_state(struct dc *dc, struct dc_log_buffer_ctx *log_ctx)
 128 {
 129         struct dc_context *dc_ctx = dc->ctx;
 130         struct dcn_hubbub_wm wm;
 131         int i;
 132
 133         memset(&wm, 0, sizeof(struct dcn_hubbub_wm));
 134         dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm);
 135
 136         DTN_INFO("HUBBUB WM:      data_urgent  pte_meta_urgent"
 137                         "         sr_enter          sr_exit  dram_clk_change\n");
 138
 139         for (i = 0; i < 4; i++) {
 140                 struct dcn_hubbub_wm_set *s;
 141
 142                 s = &wm.sets[i];
 143                 DTN_INFO("WM_Set[%d]:", s->wm_set);
 144                 DTN_INFO_MICRO_SEC(s->data_urgent);
 145                 DTN_INFO_MICRO_SEC(s->pte_meta_urgent);
 146                 DTN_INFO_MICRO_SEC(s->sr_enter);
 147                 DTN_INFO_MICRO_SEC(s->sr_exit);
 148                 DTN_INFO_MICRO_SEC(s->dram_clk_chanage);
 149                 DTN_INFO("\n");
 150         }
 151
 152         DTN_INFO("\n");
 153 }
 154
 155 static void dcn10_log_hubp_states(struct dc *dc, void *log_ctx)
 156 {
 157         struct dc_context *dc_ctx = dc->ctx;
 158         struct resource_pool *pool = dc->res_pool;
 159         int i;
 160
 161         DTN_INFO(
 162                 "HUBP:  format  addr_hi  width  height  rot  mir  sw_mode  dcc_en  blank_en  clock_en  ttu_dis  underflow   min_ttu_vblank       qos_low_wm      qos_high_wm\n");
 163         for (i = 0; i < pool->pipe_count; i++) {
 164                 struct hubp *hubp = pool->hubps[i];
 165                 struct dcn_hubp_state *s = &(TO_DCN10_HUBP(hubp)->state);
 166
 167                 hubp->funcs->hubp_read_state(hubp);
 168
 169                 if (!s->blank_en) {
 170                         DTN_INFO("[%2d]:  %5xh  %6xh  %5d  %6d  %2xh  %2xh  %6xh  %6d  %8d  %8d  %7d  %8xh",
 171                                         hubp->inst,
 172                                         s->pixel_format,
 173                                         s->inuse_addr_hi,
 174                                         s->viewport_width,
 175                                         s->viewport_height,
 176                                         s->rotation_angle,
 177                                         s->h_mirror_en,
 178                                         s->sw_mode,
 179                                         s->dcc_en,
 180                                         s->blank_en,
 181                                         s->clock_en,
 182                                         s->ttu_disable,
 183                                         s->underflow_status);
 184                         DTN_INFO_MICRO_SEC(s->min_ttu_vblank);
 185                         DTN_INFO_MICRO_SEC(s->qos_level_low_wm);
 186                         DTN_INFO_MICRO_SEC(s->qos_level_high_wm);
 187                         DTN_INFO("\n");
 188                 }
 189         }
 190
 191         DTN_INFO("\n=========RQ========\n");
 192         DTN_INFO("HUBP:  drq_exp_m  prq_exp_m  mrq_exp_m  crq_exp_m  plane1_ba  L:chunk_s  min_chu_s  meta_ch_s"
 193                 "  min_m_c_s  dpte_gr_s  mpte_gr_s  swath_hei  pte_row_h  C:chunk_s  min_chu_s  meta_ch_s"
 194                 "  min_m_c_s  dpte_gr_s  mpte_gr_s  swath_hei  pte_row_h\n");
 195         for (i = 0; i < pool->pipe_count; i++) {
 196                 struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);
 197                 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;
 198
 199                 if (!s->blank_en)
 200                         DTN_INFO("[%2d]:  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh\n",
 201                                 pool->hubps[i]->inst, rq_regs->drq_expansion_mode, rq_regs->prq_expansion_mode, rq_regs->mrq_expansion_mode,
 202                                 rq_regs->crq_expansion_mode, rq_regs->plane1_base_address, rq_regs->rq_regs_l.chunk_size,
 203                                 rq_regs->rq_regs_l.min_chunk_size, rq_regs->rq_regs_l.meta_chunk_size,
 204                                 rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs->rq_regs_l.dpte_group_size,
 205                                 rq_regs->rq_regs_l.mpte_group_size, rq_regs->rq_regs_l.swath_height,
 206                                 rq_regs->rq_regs_l.pte_row_height_linear, rq_regs->rq_regs_c.chunk_size, rq_regs->rq_regs_c.min_chunk_size,
 207                                 rq_regs->rq_regs_c.meta_chunk_size, rq_regs->rq_regs_c.min_meta_chunk_size,
 208                                 rq_regs->rq_regs_c.dpte_group_size, rq_regs->rq_regs_c.mpte_group_size,
 209                                 rq_regs->rq_regs_c.swath_height, rq_regs->rq_regs_c.pte_row_height_linear);
 210         }
 211
 212         DTN_INFO("========DLG========\n");
 213         DTN_INFO("HUBP:  rc_hbe     dlg_vbe    min_d_y_n  rc_per_ht  rc_x_a_s "
 214                         "  dst_y_a_s  dst_y_pf   dst_y_vvb  dst_y_rvb  dst_y_vfl  dst_y_rfl  rf_pix_fq"
 215                         "  vratio_pf  vrat_pf_c  rc_pg_vbl  rc_pg_vbc  rc_mc_vbl  rc_mc_vbc  rc_pg_fll"
 216                         "  rc_pg_flc  rc_mc_fll  rc_mc_flc  pr_nom_l   pr_nom_c   rc_pg_nl   rc_pg_nc "
 217                         "  mr_nom_l   mr_nom_c   rc_mc_nl   rc_mc_nc   rc_ld_pl   rc_ld_pc   rc_ld_l  "
 218                         "  rc_ld_c    cha_cur0   ofst_cur1  cha_cur1   vr_af_vc0  ddrq_limt  x_rt_dlay"
 219                         "  x_rp_dlay  x_rr_sfl\n");
 220         for (i = 0; i < pool->pipe_count; i++) {
 221                 struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);
 222                 struct _vcs_dpi_display_dlg_regs_st *dlg_regs = &s->dlg_attr;
 223
 224                 if (!s->blank_en)
 225                         DTN_INFO("[%2d]:  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh"
 226                                 "%  8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh"
 227                                 "  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh\n",
 228                                 pool->hubps[i]->inst, dlg_regs->refcyc_h_blank_end, dlg_regs->dlg_vblank_end, dlg_regs->min_dst_y_next_start,
 229                                 dlg_regs->refcyc_per_htotal, dlg_regs->refcyc_x_after_scaler, dlg_regs->dst_y_after_scaler,
 230                                 dlg_regs->dst_y_prefetch, dlg_regs->dst_y_per_vm_vblank, dlg_regs->dst_y_per_row_vblank,
 231                                 dlg_regs->dst_y_per_vm_flip, dlg_regs->dst_y_per_row_flip, dlg_regs->ref_freq_to_pix_freq,
 232                                 dlg_regs->vratio_prefetch, dlg_regs->vratio_prefetch_c, dlg_regs->refcyc_per_pte_group_vblank_l,
 233                                 dlg_regs->refcyc_per_pte_group_vblank_c, dlg_regs->refcyc_per_meta_chunk_vblank_l,
 234                                 dlg_regs->refcyc_per_meta_chunk_vblank_c, dlg_regs->refcyc_per_pte_group_flip_l,
 235                                 dlg_regs->refcyc_per_pte_group_flip_c, dlg_regs->refcyc_per_meta_chunk_flip_l,
 236                                 dlg_regs->refcyc_per_meta_chunk_flip_c, dlg_regs->dst_y_per_pte_row_nom_l,
 237                                 dlg_regs->dst_y_per_pte_row_nom_c, dlg_regs->refcyc_per_pte_group_nom_l,
 238                                 dlg_regs->refcyc_per_pte_group_nom_c, dlg_regs->dst_y_per_meta_row_nom_l,
 239                                 dlg_regs->dst_y_per_meta_row_nom_c, dlg_regs->refcyc_per_meta_chunk_nom_l,
 240                                 dlg_regs->refcyc_per_meta_chunk_nom_c, dlg_regs->refcyc_per_line_delivery_pre_l,
 241                                 dlg_regs->refcyc_per_line_delivery_pre_c, dlg_regs->refcyc_per_line_delivery_l,
 242                                 dlg_regs->refcyc_per_line_delivery_c, dlg_regs->chunk_hdl_adjust_cur0, dlg_regs->dst_y_offset_cur1,
 243                                 dlg_regs->chunk_hdl_adjust_cur1, dlg_regs->vready_after_vcount0, dlg_regs->dst_y_delta_drq_limit,
 244                                 dlg_regs->xfc_reg_transfer_delay, dlg_regs->xfc_reg_precharge_delay,
 245                                 dlg_regs->xfc_reg_remote_surface_flip_latency);
 246         }
 247
 248         DTN_INFO("========TTU========\n");
 249         DTN_INFO("HUBP:  qos_ll_wm  qos_lh_wm  mn_ttu_vb  qos_l_flp  rc_rd_p_l  rc_rd_l    rc_rd_p_c"
 250                         "  rc_rd_c    rc_rd_c0   rc_rd_pc0  rc_rd_c1   rc_rd_pc1  qos_lf_l   qos_rds_l"
 251                         "  qos_lf_c   qos_rds_c  qos_lf_c0  qos_rds_c0 qos_lf_c1  qos_rds_c1\n");
 252         for (i = 0; i < pool->pipe_count; i++) {
 253                 struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);
 254                 struct _vcs_dpi_display_ttu_regs_st *ttu_regs = &s->ttu_attr;
 255
 256                 if (!s->blank_en)
 257                         DTN_INFO("[%2d]:  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh\n",
 258                                 pool->hubps[i]->inst, ttu_regs->qos_level_low_wm, ttu_regs->qos_level_high_wm, ttu_regs->min_ttu_vblank,
 259                                 ttu_regs->qos_level_flip, ttu_regs->refcyc_per_req_delivery_pre_l, ttu_regs->refcyc_per_req_delivery_l,
 260                                 ttu_regs->refcyc_per_req_delivery_pre_c, ttu_regs->refcyc_per_req_delivery_c, ttu_regs->refcyc_per_req_delivery_cur0,
 261                                 ttu_regs->refcyc_per_req_delivery_pre_cur0, ttu_regs->refcyc_per_req_delivery_cur1,
 262                                 ttu_regs->refcyc_per_req_delivery_pre_cur1, ttu_regs->qos_level_fixed_l, ttu_regs->qos_ramp_disable_l,
 263                                 ttu_regs->qos_level_fixed_c, ttu_regs->qos_ramp_disable_c, ttu_regs->qos_level_fixed_cur0,
 264                                 ttu_regs->qos_ramp_disable_cur0, ttu_regs->qos_level_fixed_cur1, ttu_regs->qos_ramp_disable_cur1);
 265         }
 266         DTN_INFO("\n");
 267 }
 268
 269 void dcn10_log_hw_state(struct dc *dc,
 270         struct dc_log_buffer_ctx *log_ctx)
 271 {
 272         struct dc_context *dc_ctx = dc->ctx;
 273         struct resource_pool *pool = dc->res_pool;
 274         int i;
 275
 276         DTN_INFO_BEGIN();
 277
 278         dcn10_log_hubbub_state(dc, log_ctx);
 279
 280         dcn10_log_hubp_states(dc, log_ctx);
 281
 282         DTN_INFO("DPP:    IGAM format  IGAM mode    DGAM mode    RGAM mode"
 283                         "  GAMUT mode  C11 C12   C13 C14   C21 C22   C23 C24   "
 284                         "C31 C32   C33 C34\n");
 285         for (i = 0; i < pool->pipe_count; i++) {
 286                 struct dpp *dpp = pool->dpps[i];
 287                 struct dcn_dpp_state s = {0};
 288
 289                 dpp->funcs->dpp_read_state(dpp, &s);
 290
 291                 if (!s.is_enabled)
 292                         continue;
 293
 294                 DTN_INFO("[%2d]:  %11xh  %-11s  %-11s  %-11s"
 295                                 "%8x    %08xh %08xh %08xh %08xh %08xh %08xh",
 296                                 dpp->inst,
 297                                 s.igam_input_format,
 298                                 (s.igam_lut_mode == 0) ? "BypassFixed" :
 299                                         ((s.igam_lut_mode == 1) ? "BypassFloat" :
 300                                         ((s.igam_lut_mode == 2) ? "RAM" :
 301                                         ((s.igam_lut_mode == 3) ? "RAM" :
 302                                                                  "Unknown"))),
 303                                 (s.dgam_lut_mode == 0) ? "Bypass" :
 304                                         ((s.dgam_lut_mode == 1) ? "sRGB" :
 305                                         ((s.dgam_lut_mode == 2) ? "Ycc" :
 306                                         ((s.dgam_lut_mode == 3) ? "RAM" :
 307                                         ((s.dgam_lut_mode == 4) ? "RAM" :
 308                                                                  "Unknown")))),
 309                                 (s.rgam_lut_mode == 0) ? "Bypass" :
 310                                         ((s.rgam_lut_mode == 1) ? "sRGB" :
 311                                         ((s.rgam_lut_mode == 2) ? "Ycc" :
 312                                         ((s.rgam_lut_mode == 3) ? "RAM" :
 313                                         ((s.rgam_lut_mode == 4) ? "RAM" :
 314                                                                  "Unknown")))),
 315                                 s.gamut_remap_mode,
 316                                 s.gamut_remap_c11_c12,
 317                                 s.gamut_remap_c13_c14,
 318                                 s.gamut_remap_c21_c22,
 319                                 s.gamut_remap_c23_c24,
 320                                 s.gamut_remap_c31_c32,
 321                                 s.gamut_remap_c33_c34);
 322                 DTN_INFO("\n");
 323         }
 324         DTN_INFO("\n");
 325
 326         DTN_INFO("MPCC:  OPP  DPP  MPCCBOT  MODE  ALPHA_MODE  PREMULT  OVERLAP_ONLY  IDLE\n");
 327         for (i = 0; i < pool->pipe_count; i++) {
 328                 struct mpcc_state s = {0};
 329
 330                 pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s);
 331                 if (s.opp_id != 0xf)
 332                         DTN_INFO("[%2d]:  %2xh  %2xh  %6xh  %4d  %10d  %7d  %12d  %4d\n",
 333                                 i, s.opp_id, s.dpp_id, s.bot_mpcc_id,
 334                                 s.mode, s.alpha_mode, s.pre_multiplied_alpha, s.overlap_only,
 335                                 s.idle);
 336         }
 337         DTN_INFO("\n");
 338
 339         DTN_INFO("OTG:  v_bs  v_be  v_ss  v_se  vpol  vmax  vmin  vmax_sel  vmin_sel  h_bs  h_be  h_ss  h_se  hpol  htot  vtot  underflow blank_en\n");
 340
 341         for (i = 0; i < pool->timing_generator_count; i++) {
 342                 struct timing_generator *tg = pool->timing_generators[i];
 343                 struct dcn_otg_state s = {0};
 344                 /* Read shared OTG state registers for all DCNx */
 345                 optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s);
 346
 347                 /*
 348                  * For DCN2 and greater, a register on the OPP is used to
 349                  * determine if the CRTC is blanked instead of the OTG. So use
 350                  * dpg_is_blanked() if exists, otherwise fallback on otg.
 351                  *
 352                  * TODO: Implement DCN-specific read_otg_state hooks.
 353                  */
 354                 if (pool->opps[i]->funcs->dpg_is_blanked)
 355                         s.blank_enabled = pool->opps[i]->funcs->dpg_is_blanked(pool->opps[i]);
 356                 else
 357                         s.blank_enabled = tg->funcs->is_blanked(tg);
 358
 359                 //only print if OTG master is enabled
 360                 if ((s.otg_enabled & 1) == 0)
 361                         continue;
 362
 363                 DTN_INFO("[%d]: %5d %5d %5d %5d %5d %5d %5d %9d %9d %5d %5d %5d %5d %5d %5d %5d  %9d %8d\n",
 364                                 tg->inst,
 365                                 s.v_blank_start,
 366                                 s.v_blank_end,
 367                                 s.v_sync_a_start,
 368                                 s.v_sync_a_end,
 369                                 s.v_sync_a_pol,
 370                                 s.v_total_max,
 371                                 s.v_total_min,
 372                                 s.v_total_max_sel,
 373                                 s.v_total_min_sel,
 374                                 s.h_blank_start,
 375                                 s.h_blank_end,
 376                                 s.h_sync_a_start,
 377                                 s.h_sync_a_end,
 378                                 s.h_sync_a_pol,
 379                                 s.h_total,
 380                                 s.v_total,
 381                                 s.underflow_occurred_status,
 382                                 s.blank_enabled);
 383
 384                 // Clear underflow for debug purposes
 385                 // We want to keep underflow sticky bit on for the longevity tests outside of test environment.
 386                 // This function is called only from Windows or Diags test environment, hence it's safe to clear
 387                 // it from here without affecting the original intent.
 388                 tg->funcs->clear_optc_underflow(tg);
 389         }
 390         DTN_INFO("\n");
 391
 392         DTN_INFO("DSC: CLOCK_EN  SLICE_WIDTH  Bytes_pp\n");
 393         for (i = 0; i < pool->res_cap->num_dsc; i++) {
 394                 struct display_stream_compressor *dsc = pool->dscs[i];
 395                 struct dcn_dsc_state s = {0};
 396
 397                 dsc->funcs->dsc_read_state(dsc, &s);
 398                 DTN_INFO("[%d]: %-9d %-12d %-10d\n",
 399                 dsc->inst,
 400                         s.dsc_clock_en,
 401                         s.dsc_slice_width,
 402                         s.dsc_bytes_per_pixel);
 403                 DTN_INFO("\n");
 404         }
 405         DTN_INFO("\n");
 406
 407         DTN_INFO("S_ENC: DSC_MODE  SEC_GSP7_LINE_NUM"
 408                         "  VBID6_LINE_REFERENCE  VBID6_LINE_NUM  SEC_GSP7_ENABLE  SEC_STREAM_ENABLE\n");
 409         for (i = 0; i < pool->stream_enc_count; i++) {
 410                 struct stream_encoder *enc = pool->stream_enc[i];
 411                 struct enc_state s = {0};
 412
 413                 if (enc->funcs->enc_read_state) {
 414                         enc->funcs->enc_read_state(enc, &s);
 415                         DTN_INFO("[%-3d]: %-9d %-18d %-21d %-15d %-16d %-17d\n",
 416                                 enc->id,
 417                                 s.dsc_mode,
 418                                 s.sec_gsp_pps_line_num,
 419                                 s.vbid6_line_reference,
 420                                 s.vbid6_line_num,
 421                                 s.sec_gsp_pps_enable,
 422                                 s.sec_stream_enable);
 423                         DTN_INFO("\n");
 424                 }
 425         }
 426         DTN_INFO("\n");
 427
 428         DTN_INFO("L_ENC: DPHY_FEC_EN  DPHY_FEC_READY_SHADOW  DPHY_FEC_ACTIVE_STATUS  DP_LINK_TRAINING_COMPLETE\n");
 429         for (i = 0; i < dc->link_count; i++) {
 430                 struct link_encoder *lenc = dc->links[i]->link_enc;
 431
 432                 struct link_enc_state s = {0};
 433
 434                 if (lenc->funcs->read_state) {
 435                         lenc->funcs->read_state(lenc, &s);
 436                         DTN_INFO("[%-3d]: %-12d %-22d %-22d %-25d\n",
 437                                 i,
 438                                 s.dphy_fec_en,
 439                                 s.dphy_fec_ready_shadow,
 440                                 s.dphy_fec_active_status,
 441                                 s.dp_link_training_complete);
 442                         DTN_INFO("\n");
 443                 }
 444         }
 445         DTN_INFO("\n");
 446
 447         DTN_INFO("\nCALCULATED Clocks: dcfclk_khz:%d  dcfclk_deep_sleep_khz:%d  dispclk_khz:%d\n"
 448                 "dppclk_khz:%d  max_supported_dppclk_khz:%d  fclk_khz:%d  socclk_khz:%d\n\n",
 449                         dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_khz,
 450                         dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz,
 451                         dc->current_state->bw_ctx.bw.dcn.clk.dispclk_khz,
 452                         dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz,
 453                         dc->current_state->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz,
 454                         dc->current_state->bw_ctx.bw.dcn.clk.fclk_khz,
 455                         dc->current_state->bw_ctx.bw.dcn.clk.socclk_khz);
 456
 457         log_mpc_crc(dc, log_ctx);
 458
 459         DTN_INFO_END();
 460 }
 461
 462 bool dcn10_did_underflow_occur(struct dc *dc, struct pipe_ctx *pipe_ctx)
 463 {
 464         struct hubp *hubp = pipe_ctx->plane_res.hubp;
 465         struct timing_generator *tg = pipe_ctx->stream_res.tg;
 466
 467         if (tg->funcs->is_optc_underflow_occurred(tg)) {
 468                 tg->funcs->clear_optc_underflow(tg);
 469                 return true;
 470         }
 471
 472         if (hubp->funcs->hubp_get_underflow_status(hubp)) {
 473                 hubp->funcs->hubp_clear_underflow(hubp);
 474                 return true;
 475         }
 476         return false;
 477 }
 478
 479 void dcn10_enable_power_gating_plane(
 480         struct dce_hwseq *hws,
 481         bool enable)
 482 {
 483         bool force_on = true; /* disable power gating */
 484
 485         if (enable)
 486                 force_on = false;
 487
 488         /* DCHUBP0/1/2/3 */
 489         REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on);
 490         REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on);
 491         REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on);
 492         REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on);
 493
 494         /* DPP0/1/2/3 */
 495         REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on);
 496         REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on);
 497         REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on);
 498         REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);
 499 }
 500
 501 void dcn10_disable_vga(
 502         struct dce_hwseq *hws)
 503 {
 504         unsigned int in_vga1_mode = 0;
 505         unsigned int in_vga2_mode = 0;
 506         unsigned int in_vga3_mode = 0;
 507         unsigned int in_vga4_mode = 0;
 508
 509         REG_GET(D1VGA_CONTROL, D1VGA_MODE_ENABLE, &in_vga1_mode);
 510         REG_GET(D2VGA_CONTROL, D2VGA_MODE_ENABLE, &in_vga2_mode);
 511         REG_GET(D3VGA_CONTROL, D3VGA_MODE_ENABLE, &in_vga3_mode);
 512         REG_GET(D4VGA_CONTROL, D4VGA_MODE_ENABLE, &in_vga4_mode);
 513
 514         if (in_vga1_mode == 0 && in_vga2_mode == 0 &&
 515                         in_vga3_mode == 0 && in_vga4_mode == 0)
 516                 return;
 517
 518         REG_WRITE(D1VGA_CONTROL, 0);
 519         REG_WRITE(D2VGA_CONTROL, 0);
 520         REG_WRITE(D3VGA_CONTROL, 0);
 521         REG_WRITE(D4VGA_CONTROL, 0);
 522
 523         /* HW Engineer's Notes:
 524          *  During switch from vga->extended, if we set the VGA_TEST_ENABLE and
 525          *  then hit the VGA_TEST_RENDER_START, then the DCHUBP timing gets updated correctly.
 526          *
 527          *  Then vBIOS will have it poll for the VGA_TEST_RENDER_DONE and unset
 528          *  VGA_TEST_ENABLE, to leave it in the same state as before.
 529          */
 530         REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_ENABLE, 1);
 531         REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_RENDER_START, 1);
 532 }
 533
 534 void dcn10_dpp_pg_control(
 535                 struct dce_hwseq *hws,
 536                 unsigned int dpp_inst,
 537                 bool power_on)
 538 {
 539         uint32_t power_gate = power_on ? 0 : 1;
 540         uint32_t pwr_status = power_on ? 0 : 2;
 541
 542         if (hws->ctx->dc->debug.disable_dpp_power_gate)
 543                 return;
 544         if (REG(DOMAIN1_PG_CONFIG) == 0)
 545                 return;
 546
 547         switch (dpp_inst) {
 548         case 0: /* DPP0 */
 549                 REG_UPDATE(DOMAIN1_PG_CONFIG,
 550                                 DOMAIN1_POWER_GATE, power_gate);
 551
 552                 REG_WAIT(DOMAIN1_PG_STATUS,
 553                                 DOMAIN1_PGFSM_PWR_STATUS, pwr_status,
 554                                 1, 1000);
 555                 break;
 556         case 1: /* DPP1 */
 557                 REG_UPDATE(DOMAIN3_PG_CONFIG,
 558                                 DOMAIN3_POWER_GATE, power_gate);
 559
 560                 REG_WAIT(DOMAIN3_PG_STATUS,
 561                                 DOMAIN3_PGFSM_PWR_STATUS, pwr_status,
 562                                 1, 1000);
 563                 break;
 564         case 2: /* DPP2 */
 565                 REG_UPDATE(DOMAIN5_PG_CONFIG,
 566                                 DOMAIN5_POWER_GATE, power_gate);
 567
 568                 REG_WAIT(DOMAIN5_PG_STATUS,
 569                                 DOMAIN5_PGFSM_PWR_STATUS, pwr_status,
 570                                 1, 1000);
 571                 break;
 572         case 3: /* DPP3 */
 573                 REG_UPDATE(DOMAIN7_PG_CONFIG,
 574                                 DOMAIN7_POWER_GATE, power_gate);
 575
 576                 REG_WAIT(DOMAIN7_PG_STATUS,
 577                                 DOMAIN7_PGFSM_PWR_STATUS, pwr_status,
 578                                 1, 1000);
 579                 break;
 580         default:
 581                 BREAK_TO_DEBUGGER();
 582                 break;
 583         }
 584 }
 585
 586 void dcn10_hubp_pg_control(
 587                 struct dce_hwseq *hws,
 588                 unsigned int hubp_inst,
 589                 bool power_on)
 590 {
 591         uint32_t power_gate = power_on ? 0 : 1;
 592         uint32_t pwr_status = power_on ? 0 : 2;
 593
 594         if (hws->ctx->dc->debug.disable_hubp_power_gate)
 595                 return;
 596         if (REG(DOMAIN0_PG_CONFIG) == 0)
 597                 return;
 598
 599         switch (hubp_inst) {
 600         case 0: /* DCHUBP0 */
 601                 REG_UPDATE(DOMAIN0_PG_CONFIG,
 602                                 DOMAIN0_POWER_GATE, power_gate);
 603
 604                 REG_WAIT(DOMAIN0_PG_STATUS,
 605                                 DOMAIN0_PGFSM_PWR_STATUS, pwr_status,
 606                                 1, 1000);
 607                 break;
 608         case 1: /* DCHUBP1 */
 609                 REG_UPDATE(DOMAIN2_PG_CONFIG,
 610                                 DOMAIN2_POWER_GATE, power_gate);
 611
 612                 REG_WAIT(DOMAIN2_PG_STATUS,
 613                                 DOMAIN2_PGFSM_PWR_STATUS, pwr_status,
 614                                 1, 1000);
 615                 break;
 616         case 2: /* DCHUBP2 */
 617                 REG_UPDATE(DOMAIN4_PG_CONFIG,
 618                                 DOMAIN4_POWER_GATE, power_gate);
 619
 620                 REG_WAIT(DOMAIN4_PG_STATUS,
 621                                 DOMAIN4_PGFSM_PWR_STATUS, pwr_status,
 622                                 1, 1000);
 623                 break;
 624         case 3: /* DCHUBP3 */
 625                 REG_UPDATE(DOMAIN6_PG_CONFIG,
 626                                 DOMAIN6_POWER_GATE, power_gate);
 627
 628                 REG_WAIT(DOMAIN6_PG_STATUS,
 629                                 DOMAIN6_PGFSM_PWR_STATUS, pwr_status,
 630                                 1, 1000);
 631                 break;
 632         default:
 633                 BREAK_TO_DEBUGGER();
 634                 break;
 635         }
 636 }
 637
 638 static void power_on_plane(
 639         struct dce_hwseq *hws,
 640         int plane_id)
 641 {
 642         DC_LOGGER_INIT(hws->ctx->logger);
 643         if (REG(DC_IP_REQUEST_CNTL)) {
 644                 REG_SET(DC_IP_REQUEST_CNTL, 0,
 645                                 IP_REQUEST_EN, 1);
 646                 hws->funcs.dpp_pg_control(hws, plane_id, true);
 647                 hws->funcs.hubp_pg_control(hws, plane_id, true);
 648                 REG_SET(DC_IP_REQUEST_CNTL, 0,
 649                                 IP_REQUEST_EN, 0);
 650                 DC_LOG_DEBUG(
 651                                 "Un-gated front end for pipe %d\n", plane_id);
 652         }
 653 }
 654
 655 static void undo_DEGVIDCN10_253_wa(struct dc *dc)
 656 {
 657         struct dce_hwseq *hws = dc->hwseq;
 658         struct hubp *hubp = dc->res_pool->hubps[0];
 659
 660         if (!hws->wa_state.DEGVIDCN10_253_applied)
 661                 return;
 662
 663         hubp->funcs->set_blank(hubp, true);
 664
 665         REG_SET(DC_IP_REQUEST_CNTL, 0,
 666                         IP_REQUEST_EN, 1);
 667
 668         hws->funcs.hubp_pg_control(hws, 0, false);
 669         REG_SET(DC_IP_REQUEST_CNTL, 0,
 670                         IP_REQUEST_EN, 0);
 671
 672         hws->wa_state.DEGVIDCN10_253_applied = false;
 673 }
 674
 675 static void apply_DEGVIDCN10_253_wa(struct dc *dc)
 676 {
 677         struct dce_hwseq *hws = dc->hwseq;
 678         struct hubp *hubp = dc->res_pool->hubps[0];
 679         int i;
 680
 681         if (dc->debug.disable_stutter)
 682                 return;
 683
 684         if (!hws->wa.DEGVIDCN10_253)
 685                 return;
 686
 687         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 688                 if (!dc->res_pool->hubps[i]->power_gated)
 689                         return;
 690         }
 691
 692         /* all pipe power gated, apply work around to enable stutter. */
 693
 694         REG_SET(DC_IP_REQUEST_CNTL, 0,
 695                         IP_REQUEST_EN, 1);
 696
 697         hws->funcs.hubp_pg_control(hws, 0, true);
 698         REG_SET(DC_IP_REQUEST_CNTL, 0,
 699                         IP_REQUEST_EN, 0);
 700
 701         hubp->funcs->set_hubp_blank_en(hubp, false);
 702         hws->wa_state.DEGVIDCN10_253_applied = true;
 703 }
 704
 705 void dcn10_bios_golden_init(struct dc *dc)
 706 {
 707         struct dce_hwseq *hws = dc->hwseq;
 708         struct dc_bios *bp = dc->ctx->dc_bios;
 709         int i;
 710         bool allow_self_fresh_force_enable = true;
 711
 712         if (hws->funcs.s0i3_golden_init_wa && hws->funcs.s0i3_golden_init_wa(dc))
 713                 return;
 714
 715         if (dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled)
 716                 allow_self_fresh_force_enable =
 717                                 dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled(dc->res_pool->hubbub);
 718
 719
 720         /* WA for making DF sleep when idle after resume from S0i3.
 721          * DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE is set to 1 by
 722          * command table, if DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE = 0
 723          * before calling command table and it changed to 1 after,
 724          * it should be set back to 0.
 725          */
 726
 727         /* initialize dcn global */
 728         bp->funcs->enable_disp_power_gating(bp,
 729                         CONTROLLER_ID_D0, ASIC_PIPE_INIT);
 730
 731         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 732                 /* initialize dcn per pipe */
 733                 bp->funcs->enable_disp_power_gating(bp,
 734                                 CONTROLLER_ID_D0 + i, ASIC_PIPE_DISABLE);
 735         }
 736
 737         if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)
 738                 if (allow_self_fresh_force_enable == false &&
 739                                 dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled(dc->res_pool->hubbub))
 740                         dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, true);
 741
 742 }
 743
 744 static void false_optc_underflow_wa(
 745                 struct dc *dc,
 746                 const struct dc_stream_state *stream,
 747                 struct timing_generator *tg)
 748 {
 749         int i;
 750         bool underflow;
 751
 752         if (!dc->hwseq->wa.false_optc_underflow)
 753                 return;
 754
 755         underflow = tg->funcs->is_optc_underflow_occurred(tg);
 756
 757         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 758                 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
 759
 760                 if (old_pipe_ctx->stream != stream)
 761                         continue;
 762
 763                 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, old_pipe_ctx);
 764         }
 765
 766         if (tg->funcs->set_blank_data_double_buffer)
 767                 tg->funcs->set_blank_data_double_buffer(tg, true);
 768
 769         if (tg->funcs->is_optc_underflow_occurred(tg) && !underflow)
 770                 tg->funcs->clear_optc_underflow(tg);
 771 }
 772
 773 enum dc_status dcn10_enable_stream_timing(
 774                 struct pipe_ctx *pipe_ctx,
 775                 struct dc_state *context,
 776                 struct dc *dc)
 777 {
 778         struct dc_stream_state *stream = pipe_ctx->stream;
 779         enum dc_color_space color_space;
 780         struct tg_color black_color = {0};
 781
 782         /* by upper caller loop, pipe0 is parent pipe and be called first.
 783          * back end is set up by for pipe0. Other children pipe share back end
 784          * with pipe 0. No program is needed.
 785          */
 786         if (pipe_ctx->top_pipe != NULL)
 787                 return DC_OK;
 788
 789         /* TODO check if timing_changed, disable stream if timing changed */
 790
 791         /* HW program guide assume display already disable
 792          * by unplug sequence. OTG assume stop.
 793          */
 794         pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true);
 795
 796         if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
 797                         pipe_ctx->clock_source,
 798                         &pipe_ctx->stream_res.pix_clk_params,
 799                         &pipe_ctx->pll_settings)) {
 800                 BREAK_TO_DEBUGGER();
 801                 return DC_ERROR_UNEXPECTED;
 802         }
 803
 804         pipe_ctx->stream_res.tg->funcs->program_timing(
 805                         pipe_ctx->stream_res.tg,
 806                         &stream->timing,
 807                         pipe_ctx->pipe_dlg_param.vready_offset,
 808                         pipe_ctx->pipe_dlg_param.vstartup_start,
 809                         pipe_ctx->pipe_dlg_param.vupdate_offset,
 810                         pipe_ctx->pipe_dlg_param.vupdate_width,
 811                         pipe_ctx->stream->signal,
 812                         true);
 813
 814 #if 0 /* move to after enable_crtc */
 815         /* TODO: OPP FMT, ABM. etc. should be done here. */
 816         /* or FPGA now. instance 0 only. TODO: move to opp.c */
 817
 818         inst_offset = reg_offsets[pipe_ctx->stream_res.tg->inst].fmt;
 819
 820         pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
 821                                 pipe_ctx->stream_res.opp,
 822                                 &stream->bit_depth_params,
 823                                 &stream->clamping);
 824 #endif
 825         /* program otg blank color */
 826         color_space = stream->output_color_space;
 827         color_space_to_black_color(dc, color_space, &black_color);
 828
 829         if (pipe_ctx->stream_res.tg->funcs->set_blank_color)
 830                 pipe_ctx->stream_res.tg->funcs->set_blank_color(
 831                                 pipe_ctx->stream_res.tg,
 832                                 &black_color);
 833
 834         if (pipe_ctx->stream_res.tg->funcs->is_blanked &&
 835                         !pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg)) {
 836                 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);
 837                 hwss_wait_for_blank_complete(pipe_ctx->stream_res.tg);
 838                 false_optc_underflow_wa(dc, pipe_ctx->stream, pipe_ctx->stream_res.tg);
 839         }
 840
 841         /* VTG is  within DCHUB command block. DCFCLK is always on */
 842         if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {
 843                 BREAK_TO_DEBUGGER();
 844                 return DC_ERROR_UNEXPECTED;
 845         }
 846
 847         /* TODO program crtc source select for non-virtual signal*/
 848         /* TODO program FMT */
 849         /* TODO setup link_enc */
 850         /* TODO set stream attributes */
 851         /* TODO program audio */
 852         /* TODO enable stream if timing changed */
 853         /* TODO unblank stream if DP */
 854
 855         return DC_OK;
 856 }
 857
 858 static void dcn10_reset_back_end_for_pipe(
 859                 struct dc *dc,
 860                 struct pipe_ctx *pipe_ctx,
 861                 struct dc_state *context)
 862 {
 863         int i;
 864         struct dc_link *link;
 865         DC_LOGGER_INIT(dc->ctx->logger);
 866         if (pipe_ctx->stream_res.stream_enc == NULL) {
 867                 pipe_ctx->stream = NULL;
 868                 return;
 869         }
 870
 871         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
 872                 link = pipe_ctx->stream->link;
 873                 /* DPMS may already disable or */
 874                 /* dpms_off status is incorrect due to fastboot
 875                  * feature. When system resume from S4 with second
 876                  * screen only, the dpms_off would be true but
 877                  * VBIOS lit up eDP, so check link status too.
 878                  */
 879                 if (!pipe_ctx->stream->dpms_off || link->link_status.link_active)
 880                         core_link_disable_stream(pipe_ctx);
 881                 else if (pipe_ctx->stream_res.audio)
 882                         dc->hwss.disable_audio_stream(pipe_ctx);
 883
 884                 if (pipe_ctx->stream_res.audio) {
 885                         /*disable az_endpoint*/
 886                         pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
 887
 888                         /*free audio*/
 889                         if (dc->caps.dynamic_audio == true) {
 890                                 /*we have to dynamic arbitrate the audio endpoints*/
 891                                 /*we free the resource, need reset is_audio_acquired*/
 892                                 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
 893                                                 pipe_ctx->stream_res.audio, false);
 894                                 pipe_ctx->stream_res.audio = NULL;
 895                         }
 896                 }
 897         }
 898
 899         /* by upper caller loop, parent pipe: pipe0, will be reset last.
 900          * back end share by all pipes and will be disable only when disable
 901          * parent pipe.
 902          */
 903         if (pipe_ctx->top_pipe == NULL) {
 904
 905                 if (pipe_ctx->stream_res.abm)
 906                         pipe_ctx->stream_res.abm->funcs->set_abm_immediate_disable(pipe_ctx->stream_res.abm);
 907
 908                 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
 909
 910                 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
 911                 if (pipe_ctx->stream_res.tg->funcs->set_drr)
 912                         pipe_ctx->stream_res.tg->funcs->set_drr(
 913                                         pipe_ctx->stream_res.tg, NULL);
 914         }
 915
 916         for (i = 0; i < dc->res_pool->pipe_count; i++)
 917                 if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx)
 918                         break;
 919
 920         if (i == dc->res_pool->pipe_count)
 921                 return;
 922
 923         pipe_ctx->stream = NULL;
 924         DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n",
 925                                         pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
 926 }
 927
 928 static bool dcn10_hw_wa_force_recovery(struct dc *dc)
 929 {
 930         struct hubp *hubp ;
 931         unsigned int i;
 932         bool need_recover = true;
 933
 934         if (!dc->debug.recovery_enabled)
 935                 return false;
 936
 937         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 938                 struct pipe_ctx *pipe_ctx =
 939                         &dc->current_state->res_ctx.pipe_ctx[i];
 940                 if (pipe_ctx != NULL) {
 941                         hubp = pipe_ctx->plane_res.hubp;
 942                         if (hubp != NULL && hubp->funcs->hubp_get_underflow_status) {
 943                                 if (hubp->funcs->hubp_get_underflow_status(hubp) != 0) {
 944                                         /* one pipe underflow, we will reset all the pipes*/
 945                                         need_recover = true;
 946                                 }
 947                         }
 948                 }
 949         }
 950         if (!need_recover)
 951                 return false;
 952         /*
 953         DCHUBP_CNTL:HUBP_BLANK_EN=1
 954         DCHUBBUB_SOFT_RESET:DCHUBBUB_GLOBAL_SOFT_RESET=1
 955         DCHUBP_CNTL:HUBP_DISABLE=1
 956         DCHUBP_CNTL:HUBP_DISABLE=0
 957         DCHUBBUB_SOFT_RESET:DCHUBBUB_GLOBAL_SOFT_RESET=0
 958         DCSURF_PRIMARY_SURFACE_ADDRESS
 959         DCHUBP_CNTL:HUBP_BLANK_EN=0
 960         */
 961
 962         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 963                 struct pipe_ctx *pipe_ctx =
 964                         &dc->current_state->res_ctx.pipe_ctx[i];
 965                 if (pipe_ctx != NULL) {
 966                         hubp = pipe_ctx->plane_res.hubp;
 967                         /*DCHUBP_CNTL:HUBP_BLANK_EN=1*/
 968                         if (hubp != NULL && hubp->funcs->set_hubp_blank_en)
 969                                 hubp->funcs->set_hubp_blank_en(hubp, true);
 970                 }
 971         }
 972         /*DCHUBBUB_SOFT_RESET:DCHUBBUB_GLOBAL_SOFT_RESET=1*/
 973         hubbub1_soft_reset(dc->res_pool->hubbub, true);
 974
 975         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 976                 struct pipe_ctx *pipe_ctx =
 977                         &dc->current_state->res_ctx.pipe_ctx[i];
 978                 if (pipe_ctx != NULL) {
 979                         hubp = pipe_ctx->plane_res.hubp;
 980                         /*DCHUBP_CNTL:HUBP_DISABLE=1*/
 981                         if (hubp != NULL && hubp->funcs->hubp_disable_control)
 982                                 hubp->funcs->hubp_disable_control(hubp, true);
 983                 }
 984         }
 985         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 986                 struct pipe_ctx *pipe_ctx =
 987                         &dc->current_state->res_ctx.pipe_ctx[i];
 988                 if (pipe_ctx != NULL) {
 989                         hubp = pipe_ctx->plane_res.hubp;
 990                         /*DCHUBP_CNTL:HUBP_DISABLE=0*/
 991                         if (hubp != NULL && hubp->funcs->hubp_disable_control)
 992                                 hubp->funcs->hubp_disable_control(hubp, true);
 993                 }
 994         }
 995         /*DCHUBBUB_SOFT_RESET:DCHUBBUB_GLOBAL_SOFT_RESET=0*/
 996         hubbub1_soft_reset(dc->res_pool->hubbub, false);
 997         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 998                 struct pipe_ctx *pipe_ctx =
 999                         &dc->current_state->res_ctx.pipe_ctx[i];
1000                 if (pipe_ctx != NULL) {
1001                         hubp = pipe_ctx->plane_res.hubp;
1002                         /*DCHUBP_CNTL:HUBP_BLANK_EN=0*/
1003                         if (hubp != NULL && hubp->funcs->set_hubp_blank_en)
1004                                 hubp->funcs->set_hubp_blank_en(hubp, true);
1005                 }
1006         }
1007         return true;
1008
1009 }
1010
1011
1012 void dcn10_verify_allow_pstate_change_high(struct dc *dc)
1013 {
1014         static bool should_log_hw_state; /* prevent hw state log by default */
1015
1016         if (!hubbub1_verify_allow_pstate_change_high(dc->res_pool->hubbub)) {
1017                 if (should_log_hw_state) {
1018                         dcn10_log_hw_state(dc, NULL);
1019                 }
1020                 BREAK_TO_DEBUGGER();
1021                 if (dcn10_hw_wa_force_recovery(dc)) {
1022                 /*check again*/
1023                         if (!hubbub1_verify_allow_pstate_change_high(dc->res_pool->hubbub))
1024                                 BREAK_TO_DEBUGGER();
1025                 }
1026         }
1027 }
1028
1029 /* trigger HW to start disconnect plane from stream on the next vsync */
1030 void dcn10_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx)
1031 {
1032         struct dce_hwseq *hws = dc->hwseq;
1033         struct hubp *hubp = pipe_ctx->plane_res.hubp;
1034         int dpp_id = pipe_ctx->plane_res.dpp->inst;
1035         struct mpc *mpc = dc->res_pool->mpc;
1036         struct mpc_tree *mpc_tree_params;
1037         struct mpcc *mpcc_to_remove = NULL;
1038         struct output_pixel_processor *opp = pipe_ctx->stream_res.opp;
1039
1040         mpc_tree_params = &(opp->mpc_tree_params);
1041         mpcc_to_remove = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, dpp_id);
1042
1043         /*Already reset*/
1044         if (mpcc_to_remove == NULL)
1045                 return;
1046
1047         mpc->funcs->remove_mpcc(mpc, mpc_tree_params, mpcc_to_remove);
1048         if (opp != NULL)
1049                 opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
1050
1051         dc->optimized_required = true;
1052
1053         if (hubp->funcs->hubp_disconnect)
1054                 hubp->funcs->hubp_disconnect(hubp);
1055
1056         if (dc->debug.sanity_checks)
1057                 hws->funcs.verify_allow_pstate_change_high(dc);
1058 }
1059
1060 void dcn10_plane_atomic_power_down(struct dc *dc,
1061                 struct dpp *dpp,
1062                 struct hubp *hubp)
1063 {
1064         struct dce_hwseq *hws = dc->hwseq;
1065         DC_LOGGER_INIT(dc->ctx->logger);
1066
1067         if (REG(DC_IP_REQUEST_CNTL)) {
1068                 REG_SET(DC_IP_REQUEST_CNTL, 0,
1069                                 IP_REQUEST_EN, 1);
1070                 hws->funcs.dpp_pg_control(hws, dpp->inst, false);
1071                 hws->funcs.hubp_pg_control(hws, hubp->inst, false);
1072                 dpp->funcs->dpp_reset(dpp);
1073                 REG_SET(DC_IP_REQUEST_CNTL, 0,
1074                                 IP_REQUEST_EN, 0);
1075                 DC_LOG_DEBUG(
1076                                 "Power gated front end %d\n", hubp->inst);
1077         }
1078 }
1079
1080 /* disable HW used by plane.
1081  * note:  cannot disable until disconnect is complete
1082  */
1083 void dcn10_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
1084 {
1085         struct dce_hwseq *hws = dc->hwseq;
1086         struct hubp *hubp = pipe_ctx->plane_res.hubp;
1087         struct dpp *dpp = pipe_ctx->plane_res.dpp;
1088         int opp_id = hubp->opp_id;
1089
1090         dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);
1091
1092         hubp->funcs->hubp_clk_cntl(hubp, false);
1093
1094         dpp->funcs->dpp_dppclk_control(dpp, false, false);
1095
1096         if (opp_id != 0xf && pipe_ctx->stream_res.opp->mpc_tree_params.opp_list == NULL)
1097                 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
1098                                 pipe_ctx->stream_res.opp,
1099                                 false);
1100
1101         hubp->power_gated = true;
1102         dc->optimized_required = false; /* We're powering off, no need to optimize */
1103
1104         hws->funcs.plane_atomic_power_down(dc,
1105                         pipe_ctx->plane_res.dpp,
1106                         pipe_ctx->plane_res.hubp);
1107
1108         pipe_ctx->stream = NULL;
1109         memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res));
1110         memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res));
1111         pipe_ctx->top_pipe = NULL;
1112         pipe_ctx->bottom_pipe = NULL;
1113         pipe_ctx->plane_state = NULL;
1114 }
1115
1116 void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
1117 {
1118         struct dce_hwseq *hws = dc->hwseq;
1119         DC_LOGGER_INIT(dc->ctx->logger);
1120
1121         if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)
1122                 return;
1123
1124         hws->funcs.plane_atomic_disable(dc, pipe_ctx);
1125
1126         apply_DEGVIDCN10_253_wa(dc);
1127
1128         DC_LOG_DC("Power down front end %d\n",
1129                                         pipe_ctx->pipe_idx);
1130 }
1131
1132 void dcn10_init_pipes(struct dc *dc, struct dc_state *context)
1133 {
1134         int i;
1135         struct dce_hwseq *hws = dc->hwseq;
1136         bool can_apply_seamless_boot = false;
1137
1138         for (i = 0; i < context->stream_count; i++) {
1139                 if (context->streams[i]->apply_seamless_boot_optimization) {
1140                         can_apply_seamless_boot = true;
1141                         break;
1142                 }
1143         }
1144
1145         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1146                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
1147                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1148
1149                 /* There is assumption that pipe_ctx is not mapping irregularly
1150                  * to non-preferred front end. If pipe_ctx->stream is not NULL,
1151                  * we will use the pipe, so don't disable
1152                  */
1153                 if (pipe_ctx->stream != NULL && can_apply_seamless_boot)
1154                         continue;
1155
1156                 /* Blank controller using driver code instead of
1157                  * command table.
1158                  */
1159                 if (tg->funcs->is_tg_enabled(tg)) {
1160                         if (hws->funcs.init_blank != NULL) {
1161                                 hws->funcs.init_blank(dc, tg);
1162                                 tg->funcs->lock(tg);
1163                         } else {
1164                                 tg->funcs->lock(tg);
1165                                 tg->funcs->set_blank(tg, true);
1166                                 hwss_wait_for_blank_complete(tg);
1167                         }
1168                 }
1169         }
1170
1171         /* num_opp will be equal to number of mpcc */
1172         for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {
1173                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1174
1175                 /* Cannot reset the MPC mux if seamless boot */
1176                 if (pipe_ctx->stream != NULL && can_apply_seamless_boot)
1177                         continue;
1178
1179                 dc->res_pool->mpc->funcs->mpc_init_single_inst(
1180                                 dc->res_pool->mpc, i);
1181         }
1182
1183         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1184                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
1185                 struct hubp *hubp = dc->res_pool->hubps[i];
1186                 struct dpp *dpp = dc->res_pool->dpps[i];
1187                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1188
1189                 /* There is assumption that pipe_ctx is not mapping irregularly
1190                  * to non-preferred front end. If pipe_ctx->stream is not NULL,
1191                  * we will use the pipe, so don't disable
1192                  */
1193                 if (can_apply_seamless_boot &&
1194                         pipe_ctx->stream != NULL &&
1195                         pipe_ctx->stream_res.tg->funcs->is_tg_enabled(
1196                                 pipe_ctx->stream_res.tg)) {
1197                         // Enable double buffering for OTG_BLANK no matter if
1198                         // seamless boot is enabled or not to suppress global sync
1199                         // signals when OTG blanked. This is to prevent pipe from
1200                         // requesting data while in PSR.
1201                         tg->funcs->tg_init(tg);
1202                         continue;
1203                 }
1204
1205                 /* Disable on the current state so the new one isn't cleared. */
1206                 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
1207
1208                 dpp->funcs->dpp_reset(dpp);
1209
1210                 pipe_ctx->stream_res.tg = tg;
1211                 pipe_ctx->pipe_idx = i;
1212
1213                 pipe_ctx->plane_res.hubp = hubp;
1214                 pipe_ctx->plane_res.dpp = dpp;
1215                 pipe_ctx->plane_res.mpcc_inst = dpp->inst;
1216                 hubp->mpcc_id = dpp->inst;
1217                 hubp->opp_id = OPP_ID_INVALID;
1218                 hubp->power_gated = false;
1219
1220                 dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
1221                 dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
1222                 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
1223                 pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
1224
1225                 hws->funcs.plane_atomic_disconnect(dc, pipe_ctx);
1226
1227                 if (tg->funcs->is_tg_enabled(tg))
1228                         tg->funcs->unlock(tg);
1229
1230                 dc->hwss.disable_plane(dc, pipe_ctx);
1231
1232                 pipe_ctx->stream_res.tg = NULL;
1233                 pipe_ctx->plane_res.hubp = NULL;
1234
1235                 tg->funcs->tg_init(tg);
1236         }
1237 }
1238
1239 void dcn10_init_hw(struct dc *dc)
1240 {
1241         int i;
1242         struct abm *abm = dc->res_pool->abm;
1243         struct dmcu *dmcu = dc->res_pool->dmcu;
1244         struct dce_hwseq *hws = dc->hwseq;
1245         struct dc_bios *dcb = dc->ctx->dc_bios;
1246         struct resource_pool *res_pool = dc->res_pool;
1247
1248         if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
1249                 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
1250
1251         // Initialize the dccg
1252         if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->dccg_init)
1253                 dc->res_pool->dccg->funcs->dccg_init(res_pool->dccg);
1254
1255         if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
1256
1257                 REG_WRITE(REFCLK_CNTL, 0);
1258                 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
1259                 REG_WRITE(DIO_MEM_PWR_CTRL, 0);
1260
1261                 if (!dc->debug.disable_clock_gate) {
1262                         /* enable all DCN clock gating */
1263                         REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
1264
1265                         REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
1266
1267                         REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
1268                 }
1269
1270                 //Enable ability to power gate / don't force power on permanently
1271                 hws->funcs.enable_power_gating_plane(hws, true);
1272
1273                 return;
1274         }
1275
1276         if (!dcb->funcs->is_accelerated_mode(dcb))
1277                 hws->funcs.disable_vga(dc->hwseq);
1278
1279         hws->funcs.bios_golden_init(dc);
1280         if (dc->ctx->dc_bios->fw_info_valid) {
1281                 res_pool->ref_clocks.xtalin_clock_inKhz =
1282                                 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
1283
1284                 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
1285                         if (res_pool->dccg && res_pool->hubbub) {
1286
1287                                 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
1288                                                 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
1289                                                 &res_pool->ref_clocks.dccg_ref_clock_inKhz);
1290
1291                                 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
1292                                                 res_pool->ref_clocks.dccg_ref_clock_inKhz,
1293                                                 &res_pool->ref_clocks.dchub_ref_clock_inKhz);
1294                         } else {
1295                                 // Not all ASICs have DCCG sw component
1296                                 res_pool->ref_clocks.dccg_ref_clock_inKhz =
1297                                                 res_pool->ref_clocks.xtalin_clock_inKhz;
1298                                 res_pool->ref_clocks.dchub_ref_clock_inKhz =
1299                                                 res_pool->ref_clocks.xtalin_clock_inKhz;
1300                         }
1301                 }
1302         } else
1303                 ASSERT_CRITICAL(false);
1304
1305         for (i = 0; i < dc->link_count; i++) {
1306                 /* Power up AND update implementation according to the
1307                  * required signal (which may be different from the
1308                  * default signal on connector).
1309                  */
1310                 struct dc_link *link = dc->links[i];
1311
1312                 link->link_enc->funcs->hw_init(link->link_enc);
1313
1314                 /* Check for enabled DIG to identify enabled display */
1315                 if (link->link_enc->funcs->is_dig_enabled &&
1316                         link->link_enc->funcs->is_dig_enabled(link->link_enc))
1317                         link->link_status.link_active = true;
1318         }
1319
1320         /* Power gate DSCs */
1321         for (i = 0; i < res_pool->res_cap->num_dsc; i++)
1322                 if (hws->funcs.dsc_pg_control != NULL)
1323                         hws->funcs.dsc_pg_control(hws, res_pool->dscs[i]->inst, false);
1324
1325         /* If taking control over from VBIOS, we may want to optimize our first
1326          * mode set, so we need to skip powering down pipes until we know which
1327          * pipes we want to use.
1328          * Otherwise, if taking control is not possible, we need to power
1329          * everything down.
1330          */
1331         if (dcb->funcs->is_accelerated_mode(dcb) || dc->config.power_down_display_on_boot) {
1332                 hws->funcs.init_pipes(dc, dc->current_state);
1333         }
1334
1335         for (i = 0; i < res_pool->audio_count; i++) {
1336                 struct audio *audio = res_pool->audios[i];
1337
1338                 audio->funcs->hw_init(audio);
1339         }
1340
1341         if (abm != NULL) {
1342                 abm->funcs->init_backlight(abm);
1343                 abm->funcs->abm_init(abm);
1344         }
1345
1346         if (dmcu != NULL && !dmcu->auto_load_dmcu)
1347                 dmcu->funcs->dmcu_init(dmcu);
1348
1349         if (abm != NULL && dmcu != NULL)
1350                 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
1351
1352         /* power AFMT HDMI memory TODO: may move to dis/en output save power*/
1353         REG_WRITE(DIO_MEM_PWR_CTRL, 0);
1354
1355         if (!dc->debug.disable_clock_gate) {
1356                 /* enable all DCN clock gating */
1357                 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
1358
1359                 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
1360
1361                 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
1362         }
1363
1364         hws->funcs.enable_power_gating_plane(dc->hwseq, true);
1365
1366         if (dc->clk_mgr->funcs->notify_wm_ranges)
1367                 dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);
1368
1369 }
1370
1371 void dcn10_reset_hw_ctx_wrap(
1372                 struct dc *dc,
1373                 struct dc_state *context)
1374 {
1375         int i;
1376         struct dce_hwseq *hws = dc->hwseq;
1377
1378         /* Reset Back End*/
1379         for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
1380                 struct pipe_ctx *pipe_ctx_old =
1381                         &dc->current_state->res_ctx.pipe_ctx[i];
1382                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1383
1384                 if (!pipe_ctx_old->stream)
1385                         continue;
1386
1387                 if (pipe_ctx_old->top_pipe)
1388                         continue;
1389
1390                 if (!pipe_ctx->stream ||
1391                                 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
1392                         struct clock_source *old_clk = pipe_ctx_old->clock_source;
1393
1394                         dcn10_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
1395                         if (hws->funcs.enable_stream_gating)
1396                                 hws->funcs.enable_stream_gating(dc, pipe_ctx);
1397                         if (old_clk)
1398                                 old_clk->funcs->cs_power_down(old_clk);
1399                 }
1400         }
1401 }
1402
1403 static bool patch_address_for_sbs_tb_stereo(
1404                 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr)
1405 {
1406         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1407         bool sec_split = pipe_ctx->top_pipe &&
1408                         pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
1409         if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
1410                 (pipe_ctx->stream->timing.timing_3d_format ==
1411                  TIMING_3D_FORMAT_SIDE_BY_SIDE ||
1412                  pipe_ctx->stream->timing.timing_3d_format ==
1413                  TIMING_3D_FORMAT_TOP_AND_BOTTOM)) {
1414                 *addr = plane_state->address.grph_stereo.left_addr;
1415                 plane_state->address.grph_stereo.left_addr =
1416                 plane_state->address.grph_stereo.right_addr;
1417                 return true;
1418         } else {
1419                 if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE &&
1420                         plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) {
1421                         plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO;
1422                         plane_state->address.grph_stereo.right_addr =
1423                         plane_state->address.grph_stereo.left_addr;
1424                 }
1425         }
1426         return false;
1427 }
1428
1429 void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)
1430 {
1431         bool addr_patched = false;
1432         PHYSICAL_ADDRESS_LOC addr;
1433         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1434
1435         if (plane_state == NULL)
1436                 return;
1437
1438         addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);
1439
1440         pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(
1441                         pipe_ctx->plane_res.hubp,
1442                         &plane_state->address,
1443                         plane_state->flip_immediate);
1444
1445         plane_state->status.requested_address = plane_state->address;
1446
1447         if (plane_state->flip_immediate)
1448                 plane_state->status.current_address = plane_state->address;
1449
1450         if (addr_patched)
1451                 pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;
1452 }
1453
1454 bool dcn10_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
1455                         const struct dc_plane_state *plane_state)
1456 {
1457         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
1458         const struct dc_transfer_func *tf = NULL;
1459         bool result = true;
1460
1461         if (dpp_base == NULL)
1462                 return false;
1463
1464         if (plane_state->in_transfer_func)
1465                 tf = plane_state->in_transfer_func;
1466
1467         if (plane_state->gamma_correction &&
1468                 !dpp_base->ctx->dc->debug.always_use_regamma
1469                 && !plane_state->gamma_correction->is_identity
1470                         && dce_use_lut(plane_state->format))
1471                 dpp_base->funcs->dpp_program_input_lut(dpp_base, plane_state->gamma_correction);
1472
1473         if (tf == NULL)
1474                 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
1475         else if (tf->type == TF_TYPE_PREDEFINED) {
1476                 switch (tf->tf) {
1477                 case TRANSFER_FUNCTION_SRGB:
1478                         dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_sRGB);
1479                         break;
1480                 case TRANSFER_FUNCTION_BT709:
1481                         dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_xvYCC);
1482                         break;
1483                 case TRANSFER_FUNCTION_LINEAR:
1484                         dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
1485                         break;
1486                 case TRANSFER_FUNCTION_PQ:
1487                         dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_USER_PWL);
1488                         cm_helper_translate_curve_to_degamma_hw_format(tf, &dpp_base->degamma_params);
1489                         dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, &dpp_base->degamma_params);
1490                         result = true;
1491                         break;
1492                 default:
1493                         result = false;
1494                         break;
1495                 }
1496         } else if (tf->type == TF_TYPE_BYPASS) {
1497                 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
1498         } else {
1499                 cm_helper_translate_curve_to_degamma_hw_format(tf,
1500                                         &dpp_base->degamma_params);
1501                 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base,
1502                                 &dpp_base->degamma_params);
1503                 result = true;
1504         }
1505
1506         return result;
1507 }
1508
1509 #define MAX_NUM_HW_POINTS 0x200
1510
1511 static void log_tf(struct dc_context *ctx,
1512                                 struct dc_transfer_func *tf, uint32_t hw_points_num)
1513 {
1514         // DC_LOG_GAMMA is default logging of all hw points
1515         // DC_LOG_ALL_GAMMA logs all points, not only hw points
1516         // DC_LOG_ALL_TF_POINTS logs all channels of the tf
1517         int i = 0;
1518
1519         DC_LOGGER_INIT(ctx->logger);
1520         DC_LOG_GAMMA("Gamma Correction TF");
1521         DC_LOG_ALL_GAMMA("Logging all tf points...");
1522         DC_LOG_ALL_TF_CHANNELS("Logging all channels...");
1523
1524         for (i = 0; i < hw_points_num; i++) {
1525                 DC_LOG_GAMMA("R\t%d\t%llu", i, tf->tf_pts.red[i].value);
1526                 DC_LOG_ALL_TF_CHANNELS("G\t%d\t%llu", i, tf->tf_pts.green[i].value);
1527                 DC_LOG_ALL_TF_CHANNELS("B\t%d\t%llu", i, tf->tf_pts.blue[i].value);
1528         }
1529
1530         for (i = hw_points_num; i < MAX_NUM_HW_POINTS; i++) {
1531                 DC_LOG_ALL_GAMMA("R\t%d\t%llu", i, tf->tf_pts.red[i].value);
1532                 DC_LOG_ALL_TF_CHANNELS("G\t%d\t%llu", i, tf->tf_pts.green[i].value);
1533                 DC_LOG_ALL_TF_CHANNELS("B\t%d\t%llu", i, tf->tf_pts.blue[i].value);
1534         }
1535 }
1536
1537 bool dcn10_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
1538                                 const struct dc_stream_state *stream)
1539 {
1540         struct dpp *dpp = pipe_ctx->plane_res.dpp;
1541
1542         if (dpp == NULL)
1543                 return false;
1544
1545         dpp->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
1546
1547         if (stream->out_transfer_func &&
1548             stream->out_transfer_func->type == TF_TYPE_PREDEFINED &&
1549             stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB)
1550                 dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_SRGB);
1551
1552         /* dcn10_translate_regamma_to_hw_format takes 750us, only do it when full
1553          * update.
1554          */
1555         else if (cm_helper_translate_curve_to_hw_format(
1556                         stream->out_transfer_func,
1557                         &dpp->regamma_params, false)) {
1558                 dpp->funcs->dpp_program_regamma_pwl(
1559                                 dpp,
1560                                 &dpp->regamma_params, OPP_REGAMMA_USER);
1561         } else
1562                 dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_BYPASS);
1563
1564         if (stream != NULL && stream->ctx != NULL &&
1565                         stream->out_transfer_func != NULL) {
1566                 log_tf(stream->ctx,
1567                                 stream->out_transfer_func,
1568                                 dpp->regamma_params.hw_points_num);
1569         }
1570
1571         return true;
1572 }
1573
1574 void dcn10_pipe_control_lock(
1575         struct dc *dc,
1576         struct pipe_ctx *pipe,
1577         bool lock)
1578 {
1579         struct dce_hwseq *hws = dc->hwseq;
1580
1581         /* use TG master update lock to lock everything on the TG
1582          * therefore only top pipe need to lock
1583          */
1584         if (!pipe || pipe->top_pipe)
1585                 return;
1586
1587         if (dc->debug.sanity_checks)
1588                 hws->funcs.verify_allow_pstate_change_high(dc);
1589
1590         if (lock)
1591                 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);
1592         else
1593                 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);
1594
1595         if (dc->debug.sanity_checks)
1596                 hws->funcs.verify_allow_pstate_change_high(dc);
1597 }
1598
1599 static bool wait_for_reset_trigger_to_occur(
1600         struct dc_context *dc_ctx,
1601         struct timing_generator *tg)
1602 {
1603         bool rc = false;
1604
1605         /* To avoid endless loop we wait at most
1606          * frames_to_wait_on_triggered_reset frames for the reset to occur. */
1607         const uint32_t frames_to_wait_on_triggered_reset = 10;
1608         int i;
1609
1610         for (i = 0; i < frames_to_wait_on_triggered_reset; i++) {
1611
1612                 if (!tg->funcs->is_counter_moving(tg)) {
1613                         DC_ERROR("TG counter is not moving!\n");
1614                         break;
1615                 }
1616
1617                 if (tg->funcs->did_triggered_reset_occur(tg)) {
1618                         rc = true;
1619                         /* usually occurs at i=1 */
1620                         DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",
1621                                         i);
1622                         break;
1623                 }
1624
1625                 /* Wait for one frame. */
1626                 tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);
1627                 tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
1628         }
1629
1630         if (false == rc)
1631                 DC_ERROR("GSL: Timeout on reset trigger!\n");
1632
1633         return rc;
1634 }
1635
1636 void dcn10_enable_timing_synchronization(
1637         struct dc *dc,
1638         int group_index,
1639         int group_size,
1640         struct pipe_ctx *grouped_pipes[])
1641 {
1642         struct dc_context *dc_ctx = dc->ctx;
1643         int i;
1644
1645         DC_SYNC_INFO("Setting up OTG reset trigger\n");
1646
1647         for (i = 1; i < group_size; i++)
1648                 grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger(
1649                                 grouped_pipes[i]->stream_res.tg,
1650                                 grouped_pipes[0]->stream_res.tg->inst);
1651
1652         DC_SYNC_INFO("Waiting for trigger\n");
1653
1654         /* Need to get only check 1 pipe for having reset as all the others are
1655          * synchronized. Look at last pipe programmed to reset.
1656          */
1657
1658         wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[1]->stream_res.tg);
1659         for (i = 1; i < group_size; i++)
1660                 grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(
1661                                 grouped_pipes[i]->stream_res.tg);
1662
1663         DC_SYNC_INFO("Sync complete\n");
1664 }
1665
1666 void dcn10_enable_per_frame_crtc_position_reset(
1667         struct dc *dc,
1668         int group_size,
1669         struct pipe_ctx *grouped_pipes[])
1670 {
1671         struct dc_context *dc_ctx = dc->ctx;
1672         int i;
1673
1674         DC_SYNC_INFO("Setting up\n");
1675         for (i = 0; i < group_size; i++)
1676                 if (grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset)
1677                         grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset(
1678                                         grouped_pipes[i]->stream_res.tg,
1679                                         0,
1680                                         &grouped_pipes[i]->stream->triggered_crtc_reset);
1681
1682         DC_SYNC_INFO("Waiting for trigger\n");
1683
1684         for (i = 0; i < group_size; i++)
1685                 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
1686
1687         DC_SYNC_INFO("Multi-display sync is complete\n");
1688 }
1689
1690 /*static void print_rq_dlg_ttu(
1691                 struct dc *dc,
1692                 struct pipe_ctx *pipe_ctx)
1693 {
1694         DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger,
1695                         "\n============== DML TTU Output parameters [%d] ==============\n"
1696                         "qos_level_low_wm: %d, \n"
1697                         "qos_level_high_wm: %d, \n"
1698                         "min_ttu_vblank: %d, \n"
1699                         "qos_level_flip: %d, \n"
1700                         "refcyc_per_req_delivery_l: %d, \n"
1701                         "qos_level_fixed_l: %d, \n"
1702                         "qos_ramp_disable_l: %d, \n"
1703                         "refcyc_per_req_delivery_pre_l: %d, \n"
1704                         "refcyc_per_req_delivery_c: %d, \n"
1705                         "qos_level_fixed_c: %d, \n"
1706                         "qos_ramp_disable_c: %d, \n"
1707                         "refcyc_per_req_delivery_pre_c: %d\n"
1708                         "=============================================================\n",
1709                         pipe_ctx->pipe_idx,
1710                         pipe_ctx->ttu_regs.qos_level_low_wm,
1711                         pipe_ctx->ttu_regs.qos_level_high_wm,
1712                         pipe_ctx->ttu_regs.min_ttu_vblank,
1713                         pipe_ctx->ttu_regs.qos_level_flip,
1714                         pipe_ctx->ttu_regs.refcyc_per_req_delivery_l,
1715                         pipe_ctx->ttu_regs.qos_level_fixed_l,
1716                         pipe_ctx->ttu_regs.qos_ramp_disable_l,
1717                         pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_l,
1718                         pipe_ctx->ttu_regs.refcyc_per_req_delivery_c,
1719                         pipe_ctx->ttu_regs.qos_level_fixed_c,
1720                         pipe_ctx->ttu_regs.qos_ramp_disable_c,
1721                         pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_c
1722                         );
1723
1724         DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger,
1725                         "\n============== DML DLG Output parameters [%d] ==============\n"
1726                         "refcyc_h_blank_end: %d, \n"
1727                         "dlg_vblank_end: %d, \n"
1728                         "min_dst_y_next_start: %d, \n"
1729                         "refcyc_per_htotal: %d, \n"
1730                         "refcyc_x_after_scaler: %d, \n"
1731                         "dst_y_after_scaler: %d, \n"
1732                         "dst_y_prefetch: %d, \n"
1733                         "dst_y_per_vm_vblank: %d, \n"
1734                         "dst_y_per_row_vblank: %d, \n"
1735                         "ref_freq_to_pix_freq: %d, \n"
1736                         "vratio_prefetch: %d, \n"
1737                         "refcyc_per_pte_group_vblank_l: %d, \n"
1738                         "refcyc_per_meta_chunk_vblank_l: %d, \n"
1739                         "dst_y_per_pte_row_nom_l: %d, \n"
1740                         "refcyc_per_pte_group_nom_l: %d, \n",
1741                         pipe_ctx->pipe_idx,
1742                         pipe_ctx->dlg_regs.refcyc_h_blank_end,
1743                         pipe_ctx->dlg_regs.dlg_vblank_end,
1744                         pipe_ctx->dlg_regs.min_dst_y_next_start,
1745                         pipe_ctx->dlg_regs.refcyc_per_htotal,
1746                         pipe_ctx->dlg_regs.refcyc_x_after_scaler,
1747                         pipe_ctx->dlg_regs.dst_y_after_scaler,
1748                         pipe_ctx->dlg_regs.dst_y_prefetch,
1749                         pipe_ctx->dlg_regs.dst_y_per_vm_vblank,
1750                         pipe_ctx->dlg_regs.dst_y_per_row_vblank,
1751                         pipe_ctx->dlg_regs.ref_freq_to_pix_freq,
1752                         pipe_ctx->dlg_regs.vratio_prefetch,
1753                         pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_l,
1754                         pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_l,
1755                         pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_l,
1756                         pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_l
1757                         );
1758
1759         DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger,
1760                         "\ndst_y_per_meta_row_nom_l: %d, \n"
1761                         "refcyc_per_meta_chunk_nom_l: %d, \n"
1762                         "refcyc_per_line_delivery_pre_l: %d, \n"
1763                         "refcyc_per_line_delivery_l: %d, \n"
1764                         "vratio_prefetch_c: %d, \n"
1765                         "refcyc_per_pte_group_vblank_c: %d, \n"
1766                         "refcyc_per_meta_chunk_vblank_c: %d, \n"
1767                         "dst_y_per_pte_row_nom_c: %d, \n"
1768                         "refcyc_per_pte_group_nom_c: %d, \n"
1769                         "dst_y_per_meta_row_nom_c: %d, \n"
1770                         "refcyc_per_meta_chunk_nom_c: %d, \n"
1771                         "refcyc_per_line_delivery_pre_c: %d, \n"
1772                         "refcyc_per_line_delivery_c: %d \n"
1773                         "========================================================\n",
1774                         pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_l,
1775                         pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_l,
1776                         pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_l,
1777                         pipe_ctx->dlg_regs.refcyc_per_line_delivery_l,
1778                         pipe_ctx->dlg_regs.vratio_prefetch_c,
1779                         pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_c,
1780                         pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_c,
1781                         pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_c,
1782                         pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_c,
1783                         pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_c,
1784                         pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_c,
1785                         pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_c,
1786                         pipe_ctx->dlg_regs.refcyc_per_line_delivery_c
1787                         );
1788
1789         DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger,
1790                         "\n============== DML RQ Output parameters [%d] ==============\n"
1791                         "chunk_size: %d \n"
1792                         "min_chunk_size: %d \n"
1793                         "meta_chunk_size: %d \n"
1794                         "min_meta_chunk_size: %d \n"
1795                         "dpte_group_size: %d \n"
1796                         "mpte_group_size: %d \n"
1797                         "swath_height: %d \n"
1798                         "pte_row_height_linear: %d \n"
1799                         "========================================================\n",
1800                         pipe_ctx->pipe_idx,
1801                         pipe_ctx->rq_regs.rq_regs_l.chunk_size,
1802                         pipe_ctx->rq_regs.rq_regs_l.min_chunk_size,
1803                         pipe_ctx->rq_regs.rq_regs_l.meta_chunk_size,
1804                         pipe_ctx->rq_regs.rq_regs_l.min_meta_chunk_size,
1805                         pipe_ctx->rq_regs.rq_regs_l.dpte_group_size,
1806                         pipe_ctx->rq_regs.rq_regs_l.mpte_group_size,
1807                         pipe_ctx->rq_regs.rq_regs_l.swath_height,
1808                         pipe_ctx->rq_regs.rq_regs_l.pte_row_height_linear
1809                         );
1810 }
1811 */
1812
1813 static void mmhub_read_vm_system_aperture_settings(struct dcn10_hubp *hubp1,
1814                 struct vm_system_aperture_param *apt,
1815                 struct dce_hwseq *hws)
1816 {
1817         PHYSICAL_ADDRESS_LOC physical_page_number;
1818         uint32_t logical_addr_low;
1819         uint32_t logical_addr_high;
1820
1821         REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
1822                         PHYSICAL_PAGE_NUMBER_MSB, &physical_page_number.high_part);
1823         REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
1824                         PHYSICAL_PAGE_NUMBER_LSB, &physical_page_number.low_part);
1825
1826         REG_GET(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1827                         LOGICAL_ADDR, &logical_addr_low);
1828
1829         REG_GET(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1830                         LOGICAL_ADDR, &logical_addr_high);
1831
1832         apt->sys_default.quad_part =  physical_page_number.quad_part << 12;
1833         apt->sys_low.quad_part =  (int64_t)logical_addr_low << 18;
1834         apt->sys_high.quad_part =  (int64_t)logical_addr_high << 18;
1835 }
1836
1837 /* Temporary read settings, future will get values from kmd directly */
1838 static void mmhub_read_vm_context0_settings(struct dcn10_hubp *hubp1,
1839                 struct vm_context0_param *vm0,
1840                 struct dce_hwseq *hws)
1841 {
1842         PHYSICAL_ADDRESS_LOC fb_base;
1843         PHYSICAL_ADDRESS_LOC fb_offset;
1844         uint32_t fb_base_value;
1845         uint32_t fb_offset_value;
1846
1847         REG_GET(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, &fb_base_value);
1848         REG_GET(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, &fb_offset_value);
1849
1850         REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
1851                         PAGE_DIRECTORY_ENTRY_HI32, &vm0->pte_base.high_part);
1852         REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
1853                         PAGE_DIRECTORY_ENTRY_LO32, &vm0->pte_base.low_part);
1854
1855         REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
1856                         LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_start.high_part);
1857         REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
1858                         LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_start.low_part);
1859
1860         REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
1861                         LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_end.high_part);
1862         REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
1863                         LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_end.low_part);
1864
1865         REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
1866                         PHYSICAL_PAGE_ADDR_HI4, &vm0->fault_default.high_part);
1867         REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
1868                         PHYSICAL_PAGE_ADDR_LO32, &vm0->fault_default.low_part);
1869
1870         /*
1871          * The values in VM_CONTEXT0_PAGE_TABLE_BASE_ADDR is in UMA space.
1872          * Therefore we need to do
1873          * DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
1874          * - DCHUBBUB_SDPIF_FB_OFFSET + DCHUBBUB_SDPIF_FB_BASE
1875          */
1876         fb_base.quad_part = (uint64_t)fb_base_value << 24;
1877         fb_offset.quad_part = (uint64_t)fb_offset_value << 24;
1878         vm0->pte_base.quad_part += fb_base.quad_part;
1879         vm0->pte_base.quad_part -= fb_offset.quad_part;
1880 }
1881
1882
1883 void dcn10_program_pte_vm(struct dce_hwseq *hws, struct hubp *hubp)
1884 {
1885         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
1886         struct vm_system_aperture_param apt = { {{ 0 } } };
1887         struct vm_context0_param vm0 = { { { 0 } } };
1888
1889         mmhub_read_vm_system_aperture_settings(hubp1, &apt, hws);
1890         mmhub_read_vm_context0_settings(hubp1, &vm0, hws);
1891
1892         hubp->funcs->hubp_set_vm_system_aperture_settings(hubp, &apt);
1893         hubp->funcs->hubp_set_vm_context0_settings(hubp, &vm0);
1894 }
1895
1896 static void dcn10_enable_plane(
1897         struct dc *dc,
1898         struct pipe_ctx *pipe_ctx,
1899         struct dc_state *context)
1900 {
1901         struct dce_hwseq *hws = dc->hwseq;
1902
1903         if (dc->debug.sanity_checks) {
1904                 hws->funcs.verify_allow_pstate_change_high(dc);
1905         }
1906
1907         undo_DEGVIDCN10_253_wa(dc);
1908
1909         power_on_plane(dc->hwseq,
1910                 pipe_ctx->plane_res.hubp->inst);
1911
1912         /* enable DCFCLK current DCHUB */
1913         pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);
1914
1915         /* make sure OPP_PIPE_CLOCK_EN = 1 */
1916         pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
1917                         pipe_ctx->stream_res.opp,
1918                         true);
1919
1920 /* TODO: enable/disable in dm as per update type.
1921         if (plane_state) {
1922                 DC_LOG_DC(dc->ctx->logger,
1923                                 "Pipe:%d 0x%x: addr hi:0x%x, "
1924                                 "addr low:0x%x, "
1925                                 "src: %d, %d, %d,"
1926                                 " %d; dst: %d, %d, %d, %d;\n",
1927                                 pipe_ctx->pipe_idx,
1928                                 plane_state,
1929                                 plane_state->address.grph.addr.high_part,
1930                                 plane_state->address.grph.addr.low_part,
1931                                 plane_state->src_rect.x,
1932                                 plane_state->src_rect.y,
1933                                 plane_state->src_rect.width,
1934                                 plane_state->src_rect.height,
1935                                 plane_state->dst_rect.x,
1936                                 plane_state->dst_rect.y,
1937                                 plane_state->dst_rect.width,
1938                                 plane_state->dst_rect.height);
1939
1940                 DC_LOG_DC(dc->ctx->logger,
1941                                 "Pipe %d: width, height, x, y         format:%d\n"
1942                                 "viewport:%d, %d, %d, %d\n"
1943                                 "recout:  %d, %d, %d, %d\n",
1944                                 pipe_ctx->pipe_idx,
1945                                 plane_state->format,
1946                                 pipe_ctx->plane_res.scl_data.viewport.width,
1947                                 pipe_ctx->plane_res.scl_data.viewport.height,
1948                                 pipe_ctx->plane_res.scl_data.viewport.x,
1949                                 pipe_ctx->plane_res.scl_data.viewport.y,
1950                                 pipe_ctx->plane_res.scl_data.recout.width,
1951                                 pipe_ctx->plane_res.scl_data.recout.height,
1952                                 pipe_ctx->plane_res.scl_data.recout.x,
1953                                 pipe_ctx->plane_res.scl_data.recout.y);
1954                 print_rq_dlg_ttu(dc, pipe_ctx);
1955         }
1956 */
1957         if (dc->config.gpu_vm_support)
1958                 dcn10_program_pte_vm(hws, pipe_ctx->plane_res.hubp);
1959
1960         if (dc->debug.sanity_checks) {
1961                 hws->funcs.verify_allow_pstate_change_high(dc);
1962         }
1963 }
1964
1965 void dcn10_program_gamut_remap(struct pipe_ctx *pipe_ctx)
1966 {
1967         int i = 0;
1968         struct dpp_grph_csc_adjustment adjust;
1969         memset(&adjust, 0, sizeof(adjust));
1970         adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
1971
1972
1973         if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
1974                 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
1975                 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
1976                         adjust.temperature_matrix[i] =
1977                                 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
1978         }
1979
1980         pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp, &adjust);
1981 }
1982
1983
1984 static bool dcn10_is_rear_mpo_fix_required(struct pipe_ctx *pipe_ctx, enum dc_color_space colorspace)
1985 {
1986         if (pipe_ctx->plane_state && pipe_ctx->plane_state->layer_index > 0 && is_rgb_cspace(colorspace)) {
1987                 if (pipe_ctx->top_pipe) {
1988                         struct pipe_ctx *top = pipe_ctx->top_pipe;
1989
1990                         while (top->top_pipe)
1991                                 top = top->top_pipe; // Traverse to top pipe_ctx
1992                         if (top->plane_state && top->plane_state->layer_index == 0)
1993                                 return true; // Front MPO plane not hidden
1994                 }
1995         }
1996         return false;
1997 }
1998
1999 static void dcn10_set_csc_adjustment_rgb_mpo_fix(struct pipe_ctx *pipe_ctx, uint16_t *matrix)
2000 {
2001         // Override rear plane RGB bias to fix MPO brightness
2002         uint16_t rgb_bias = matrix[3];
2003
2004         matrix[3] = 0;
2005         matrix[7] = 0;
2006         matrix[11] = 0;
2007         pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, matrix);
2008         matrix[3] = rgb_bias;
2009         matrix[7] = rgb_bias;
2010         matrix[11] = rgb_bias;
2011 }
2012
2013 void dcn10_program_output_csc(struct dc *dc,
2014                 struct pipe_ctx *pipe_ctx,
2015                 enum dc_color_space colorspace,
2016                 uint16_t *matrix,
2017                 int opp_id)
2018 {
2019         if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
2020                 if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment != NULL) {
2021
2022                         /* MPO is broken with RGB colorspaces when OCSC matrix
2023                          * brightness offset >= 0 on DCN1 due to OCSC before MPC
2024                          * Blending adds offsets from front + rear to rear plane
2025                          *
2026                          * Fix is to set RGB bias to 0 on rear plane, top plane
2027                          * black value pixels add offset instead of rear + front
2028                          */
2029
2030                         int16_t rgb_bias = matrix[3];
2031                         // matrix[3/7/11] are all the same offset value
2032
2033                         if (rgb_bias > 0 && dcn10_is_rear_mpo_fix_required(pipe_ctx, colorspace)) {
2034                                 dcn10_set_csc_adjustment_rgb_mpo_fix(pipe_ctx, matrix);
2035                         } else {
2036                                 pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, matrix);
2037                         }
2038                 }
2039         } else {
2040                 if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default != NULL)
2041                         pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default(pipe_ctx->plane_res.dpp, colorspace);
2042         }
2043 }
2044
2045 void dcn10_get_surface_visual_confirm_color(
2046                 const struct pipe_ctx *pipe_ctx,
2047                 struct tg_color *color)
2048 {
2049         uint32_t color_value = MAX_TG_COLOR_VALUE;
2050
2051         switch (pipe_ctx->plane_res.scl_data.format) {
2052         case PIXEL_FORMAT_ARGB8888:
2053                 /* set boarder color to red */
2054                 color->color_r_cr = color_value;
2055                 break;
2056
2057         case PIXEL_FORMAT_ARGB2101010:
2058                 /* set boarder color to blue */
2059                 color->color_b_cb = color_value;
2060                 break;
2061         case PIXEL_FORMAT_420BPP8:
2062                 /* set boarder color to green */
2063                 color->color_g_y = color_value;
2064                 break;
2065         case PIXEL_FORMAT_420BPP10:
2066                 /* set boarder color to yellow */
2067                 color->color_g_y = color_value;
2068                 color->color_r_cr = color_value;
2069                 break;
2070         case PIXEL_FORMAT_FP16:
2071                 /* set boarder color to white */
2072                 color->color_r_cr = color_value;
2073                 color->color_b_cb = color_value;
2074                 color->color_g_y = color_value;
2075                 break;
2076         default:
2077                 break;
2078         }
2079 }
2080
2081 void dcn10_get_hdr_visual_confirm_color(
2082                 struct pipe_ctx *pipe_ctx,
2083                 struct tg_color *color)
2084 {
2085         uint32_t color_value = MAX_TG_COLOR_VALUE;
2086
2087         // Determine the overscan color based on the top-most (desktop) plane's context
2088         struct pipe_ctx *top_pipe_ctx  = pipe_ctx;
2089
2090         while (top_pipe_ctx->top_pipe != NULL)
2091                 top_pipe_ctx = top_pipe_ctx->top_pipe;
2092
2093         switch (top_pipe_ctx->plane_res.scl_data.format) {
2094         case PIXEL_FORMAT_ARGB2101010:
2095                 if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_PQ) {
2096                         /* HDR10, ARGB2101010 - set boarder color to red */
2097                         color->color_r_cr = color_value;
2098                 }
2099                 break;
2100         case PIXEL_FORMAT_FP16:
2101                 if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_PQ) {
2102                         /* HDR10, FP16 - set boarder color to blue */
2103                         color->color_b_cb = color_value;
2104                 } else if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22) {
2105                         /* FreeSync 2 HDR - set boarder color to green */
2106                         color->color_g_y = color_value;
2107                 }
2108                 break;
2109         default:
2110                 /* SDR - set boarder color to Gray */
2111                 color->color_r_cr = color_value/2;
2112                 color->color_b_cb = color_value/2;
2113                 color->color_g_y = color_value/2;
2114                 break;
2115         }
2116 }
2117
2118 static void dcn10_update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state)
2119 {
2120         struct dc_bias_and_scale bns_params = {0};
2121
2122         // program the input csc
2123         dpp->funcs->dpp_setup(dpp,
2124                         plane_state->format,
2125                         EXPANSION_MODE_ZERO,
2126                         plane_state->input_csc_color_matrix,
2127                         plane_state->color_space,
2128                         NULL);
2129
2130         //set scale and bias registers
2131         build_prescale_params(&bns_params, plane_state);
2132         if (dpp->funcs->dpp_program_bias_and_scale)
2133                 dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
2134 }
2135
2136 void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
2137 {
2138         struct dce_hwseq *hws = dc->hwseq;
2139         struct hubp *hubp = pipe_ctx->plane_res.hubp;
2140         struct mpcc_blnd_cfg blnd_cfg = {{0}};
2141         bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
2142         int mpcc_id;
2143         struct mpcc *new_mpcc;
2144         struct mpc *mpc = dc->res_pool->mpc;
2145         struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);
2146
2147         if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) {
2148                 hws->funcs.get_hdr_visual_confirm_color(
2149                                 pipe_ctx, &blnd_cfg.black_color);
2150         } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) {
2151                 hws->funcs.get_surface_visual_confirm_color(
2152                                 pipe_ctx, &blnd_cfg.black_color);
2153         } else {
2154                 color_space_to_black_color(
2155                                 dc, pipe_ctx->stream->output_color_space,
2156                                 &blnd_cfg.black_color);
2157         }
2158
2159         if (per_pixel_alpha)
2160                 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;
2161         else
2162                 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA;
2163
2164         blnd_cfg.overlap_only = false;
2165         blnd_cfg.global_gain = 0xff;
2166
2167         if (pipe_ctx->plane_state->global_alpha)
2168                 blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value;
2169         else
2170                 blnd_cfg.global_alpha = 0xff;
2171
2172         /* DCN1.0 has output CM before MPC which seems to screw with
2173          * pre-multiplied alpha.
2174          */
2175         blnd_cfg.pre_multiplied_alpha = is_rgb_cspace(
2176                         pipe_ctx->stream->output_color_space)
2177                                         && per_pixel_alpha;
2178
2179
2180         /*
2181          * TODO: remove hack
2182          * Note: currently there is a bug in init_hw such that
2183          * on resume from hibernate, BIOS sets up MPCC0, and
2184          * we do mpcc_remove but the mpcc cannot go to idle
2185          * after remove. This cause us to pick mpcc1 here,
2186          * which causes a pstate hang for yet unknown reason.
2187          */
2188         mpcc_id = hubp->inst;
2189
2190         /* If there is no full update, don't need to touch MPC tree*/
2191         if (!pipe_ctx->plane_state->update_flags.bits.full_update) {
2192                 mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id);
2193                 return;
2194         }
2195
2196         /* check if this MPCC is already being used */
2197         new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id);
2198         /* remove MPCC if being used */
2199         if (new_mpcc != NULL)
2200                 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc);
2201         else
2202                 if (dc->debug.sanity_checks)
2203                         mpc->funcs->assert_mpcc_idle_before_connect(
2204                                         dc->res_pool->mpc, mpcc_id);
2205
2206         /* Call MPC to insert new plane */
2207         new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,
2208                         mpc_tree_params,
2209                         &blnd_cfg,
2210                         NULL,
2211                         NULL,
2212                         hubp->inst,
2213                         mpcc_id);
2214
2215         ASSERT(new_mpcc != NULL);
2216
2217         hubp->opp_id = pipe_ctx->stream_res.opp->inst;
2218         hubp->mpcc_id = mpcc_id;
2219 }
2220
2221 static void update_scaler(struct pipe_ctx *pipe_ctx)
2222 {
2223         bool per_pixel_alpha =
2224                         pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
2225
2226         pipe_ctx->plane_res.scl_data.lb_params.alpha_en = per_pixel_alpha;
2227         pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
2228         /* scaler configuration */
2229         pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(
2230                         pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);
2231 }
2232
2233 static void dcn10_update_dchubp_dpp(
2234         struct dc *dc,
2235         struct pipe_ctx *pipe_ctx,
2236         struct dc_state *context)
2237 {
2238         struct dce_hwseq *hws = dc->hwseq;
2239         struct hubp *hubp = pipe_ctx->plane_res.hubp;
2240         struct dpp *dpp = pipe_ctx->plane_res.dpp;
2241         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2242         struct plane_size size = plane_state->plane_size;
2243         unsigned int compat_level = 0;
2244
2245         /* depends on DML calculation, DPP clock value may change dynamically */
2246         /* If request max dpp clk is lower than current dispclk, no need to
2247          * divided by 2
2248          */
2249         if (plane_state->update_flags.bits.full_update) {
2250                 bool should_divided_by_2 = context->bw_ctx.bw.dcn.clk.dppclk_khz <=
2251                                 dc->clk_mgr->clks.dispclk_khz / 2;
2252
2253                 dpp->funcs->dpp_dppclk_control(
2254                                 dpp,
2255                                 should_divided_by_2,
2256                                 true);
2257
2258                 if (dc->res_pool->dccg)
2259                         dc->res_pool->dccg->funcs->update_dpp_dto(
2260                                         dc->res_pool->dccg,
2261                                         dpp->inst,
2262                                         pipe_ctx->plane_res.bw.dppclk_khz);
2263                 else
2264                         dc->clk_mgr->clks.dppclk_khz = should_divided_by_2 ?
2265                                                 dc->clk_mgr->clks.dispclk_khz / 2 :
2266                                                         dc->clk_mgr->clks.dispclk_khz;
2267         }
2268
2269         /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG
2270          * VTG is within DCHUBBUB which is commond block share by each pipe HUBP.
2271          * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG
2272          */
2273         if (plane_state->update_flags.bits.full_update) {
2274                 hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst);
2275
2276                 hubp->funcs->hubp_setup(
2277                         hubp,
2278                         &pipe_ctx->dlg_regs,
2279                         &pipe_ctx->ttu_regs,
2280                         &pipe_ctx->rq_regs,
2281                         &pipe_ctx->pipe_dlg_param);
2282                 hubp->funcs->hubp_setup_interdependent(
2283                         hubp,
2284                         &pipe_ctx->dlg_regs,
2285                         &pipe_ctx->ttu_regs);
2286         }
2287
2288         size.surface_size = pipe_ctx->plane_res.scl_data.viewport;
2289
2290         if (plane_state->update_flags.bits.full_update ||
2291                 plane_state->update_flags.bits.bpp_change)
2292                 dcn10_update_dpp(dpp, plane_state);
2293
2294         if (plane_state->update_flags.bits.full_update ||
2295                 plane_state->update_flags.bits.per_pixel_alpha_change ||
2296                 plane_state->update_flags.bits.global_alpha_change)
2297                 hws->funcs.update_mpcc(dc, pipe_ctx);
2298
2299         if (plane_state->update_flags.bits.full_update ||
2300                 plane_state->update_flags.bits.per_pixel_alpha_change ||
2301                 plane_state->update_flags.bits.global_alpha_change ||
2302                 plane_state->update_flags.bits.scaling_change ||
2303                 plane_state->update_flags.bits.position_change) {
2304                 update_scaler(pipe_ctx);
2305         }
2306
2307         if (plane_state->update_flags.bits.full_update ||
2308                 plane_state->update_flags.bits.scaling_change ||
2309                 plane_state->update_flags.bits.position_change) {
2310                 hubp->funcs->mem_program_viewport(
2311                         hubp,
2312                         &pipe_ctx->plane_res.scl_data.viewport,
2313                         &pipe_ctx->plane_res.scl_data.viewport_c);
2314         }
2315
2316         if (pipe_ctx->stream->cursor_attributes.address.quad_part != 0) {
2317                 dc->hwss.set_cursor_position(pipe_ctx);
2318                 dc->hwss.set_cursor_attribute(pipe_ctx);
2319
2320                 if (dc->hwss.set_cursor_sdr_white_level)
2321                         dc->hwss.set_cursor_sdr_white_level(pipe_ctx);
2322         }
2323
2324         if (plane_state->update_flags.bits.full_update) {
2325                 /*gamut remap*/
2326                 dc->hwss.program_gamut_remap(pipe_ctx);
2327
2328                 dc->hwss.program_output_csc(dc,
2329                                 pipe_ctx,
2330                                 pipe_ctx->stream->output_color_space,
2331                                 pipe_ctx->stream->csc_color_matrix.matrix,
2332                                 pipe_ctx->stream_res.opp->inst);
2333         }
2334
2335         if (plane_state->update_flags.bits.full_update ||
2336                 plane_state->update_flags.bits.pixel_format_change ||
2337                 plane_state->update_flags.bits.horizontal_mirror_change ||
2338                 plane_state->update_flags.bits.rotation_change ||
2339                 plane_state->update_flags.bits.swizzle_change ||
2340                 plane_state->update_flags.bits.dcc_change ||
2341                 plane_state->update_flags.bits.bpp_change ||
2342                 plane_state->update_flags.bits.scaling_change ||
2343                 plane_state->update_flags.bits.plane_size_change) {
2344                 hubp->funcs->hubp_program_surface_config(
2345                         hubp,
2346                         plane_state->format,
2347                         &plane_state->tiling_info,
2348                         &size,
2349                         plane_state->rotation,
2350                         &plane_state->dcc,
2351                         plane_state->horizontal_mirror,
2352                         compat_level);
2353         }
2354
2355         hubp->power_gated = false;
2356
2357         hws->funcs.update_plane_addr(dc, pipe_ctx);
2358
2359         if (is_pipe_tree_visible(pipe_ctx))
2360                 hubp->funcs->set_blank(hubp, false);
2361 }
2362
2363 void dcn10_blank_pixel_data(
2364                 struct dc *dc,
2365                 struct pipe_ctx *pipe_ctx,
2366                 bool blank)
2367 {
2368         enum dc_color_space color_space;
2369         struct tg_color black_color = {0};
2370         struct stream_resource *stream_res = &pipe_ctx->stream_res;
2371         struct dc_stream_state *stream = pipe_ctx->stream;
2372
2373         /* program otg blank color */
2374         color_space = stream->output_color_space;
2375         color_space_to_black_color(dc, color_space, &black_color);
2376
2377         /*
2378          * The way 420 is packed, 2 channels carry Y component, 1 channel
2379          * alternate between Cb and Cr, so both channels need the pixel
2380          * value for Y
2381          */
2382         if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
2383                 black_color.color_r_cr = black_color.color_g_y;
2384
2385
2386         if (stream_res->tg->funcs->set_blank_color)
2387                 stream_res->tg->funcs->set_blank_color(
2388                                 stream_res->tg,
2389                                 &black_color);
2390
2391         if (!blank) {
2392                 if (stream_res->tg->funcs->set_blank)
2393                         stream_res->tg->funcs->set_blank(stream_res->tg, blank);
2394                 if (stream_res->abm) {
2395                         stream_res->abm->funcs->set_pipe(stream_res->abm, stream_res->tg->inst + 1);
2396                         stream_res->abm->funcs->set_abm_level(stream_res->abm, stream->abm_level);
2397                 }
2398         } else if (blank) {
2399                 if (stream_res->abm)
2400                         stream_res->abm->funcs->set_abm_immediate_disable(stream_res->abm);
2401                 if (stream_res->tg->funcs->set_blank)
2402                         stream_res->tg->funcs->set_blank(stream_res->tg, blank);
2403         }
2404 }
2405
2406 void dcn10_set_hdr_multiplier(struct pipe_ctx *pipe_ctx)
2407 {
2408         struct fixed31_32 multiplier = pipe_ctx->plane_state->hdr_mult;
2409         uint32_t hw_mult = 0x1f000; // 1.0 default multiplier
2410         struct custom_float_format fmt;
2411
2412         fmt.exponenta_bits = 6;
2413         fmt.mantissa_bits = 12;
2414         fmt.sign = true;
2415
2416
2417         if (!dc_fixpt_eq(multiplier, dc_fixpt_from_int(0))) // check != 0
2418                 convert_to_custom_float_format(multiplier, &fmt, &hw_mult);
2419
2420         pipe_ctx->plane_res.dpp->funcs->dpp_set_hdr_multiplier(
2421                         pipe_ctx->plane_res.dpp, hw_mult);
2422 }
2423
2424 void dcn10_program_pipe(
2425                 struct dc *dc,
2426                 struct pipe_ctx *pipe_ctx,
2427                 struct dc_state *context)
2428 {
2429         struct dce_hwseq *hws = dc->hwseq;
2430
2431         if (pipe_ctx->plane_state->update_flags.bits.full_update)
2432                 dcn10_enable_plane(dc, pipe_ctx, context);
2433
2434         dcn10_update_dchubp_dpp(dc, pipe_ctx, context);
2435
2436         hws->funcs.set_hdr_multiplier(pipe_ctx);
2437
2438         if (pipe_ctx->plane_state->update_flags.bits.full_update ||
2439                         pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
2440                         pipe_ctx->plane_state->update_flags.bits.gamma_change)
2441                 hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);
2442
2443         /* dcn10_translate_regamma_to_hw_format takes 750us to finish
2444          * only do gamma programming for full update.
2445          * TODO: This can be further optimized/cleaned up
2446          * Always call this for now since it does memcmp inside before
2447          * doing heavy calculation and programming
2448          */
2449         if (pipe_ctx->plane_state->update_flags.bits.full_update)
2450                 hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
2451 }
2452
2453 static void dcn10_program_all_pipe_in_tree(
2454                 struct dc *dc,
2455                 struct pipe_ctx *pipe_ctx,
2456                 struct dc_state *context)
2457 {
2458         struct dce_hwseq *hws = dc->hwseq;
2459
2460         if (pipe_ctx->top_pipe == NULL) {
2461                 bool blank = !is_pipe_tree_visible(pipe_ctx);
2462
2463                 pipe_ctx->stream_res.tg->funcs->program_global_sync(
2464                                 pipe_ctx->stream_res.tg,
2465                                 pipe_ctx->pipe_dlg_param.vready_offset,
2466                                 pipe_ctx->pipe_dlg_param.vstartup_start,
2467                                 pipe_ctx->pipe_dlg_param.vupdate_offset,
2468                                 pipe_ctx->pipe_dlg_param.vupdate_width);
2469
2470                 pipe_ctx->stream_res.tg->funcs->set_vtg_params(
2471                                 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
2472
2473                 if (hws->funcs.setup_vupdate_interrupt)
2474                         hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
2475
2476                 hws->funcs.blank_pixel_data(dc, pipe_ctx, blank);
2477         }
2478
2479         if (pipe_ctx->plane_state != NULL)
2480                 hws->funcs.program_pipe(dc, pipe_ctx, context);
2481
2482         if (pipe_ctx->bottom_pipe != NULL && pipe_ctx->bottom_pipe != pipe_ctx)
2483                 dcn10_program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context);
2484 }
2485
2486 static struct pipe_ctx *dcn10_find_top_pipe_for_stream(
2487                 struct dc *dc,
2488                 struct dc_state *context,
2489                 const struct dc_stream_state *stream)
2490 {
2491         int i;
2492
2493         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2494                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2495                 struct pipe_ctx *old_pipe_ctx =
2496                                 &dc->current_state->res_ctx.pipe_ctx[i];
2497
2498                 if (!pipe_ctx->plane_state && !old_pipe_ctx->plane_state)
2499                         continue;
2500
2501                 if (pipe_ctx->stream != stream)
2502                         continue;
2503
2504                 if (!pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe)
2505                         return pipe_ctx;
2506         }
2507         return NULL;
2508 }
2509
2510 void dcn10_apply_ctx_for_surface(
2511                 struct dc *dc,
2512                 const struct dc_stream_state *stream,
2513                 int num_planes,
2514                 struct dc_state *context)
2515 {
2516         struct dce_hwseq *hws = dc->hwseq;
2517         int i;
2518         struct timing_generator *tg;
2519         uint32_t underflow_check_delay_us;
2520         bool interdependent_update = false;
2521         struct pipe_ctx *top_pipe_to_program =
2522                         dcn10_find_top_pipe_for_stream(dc, context, stream);
2523         DC_LOGGER_INIT(dc->ctx->logger);
2524
2525         if (!top_pipe_to_program)
2526                 return;
2527
2528         tg = top_pipe_to_program->stream_res.tg;
2529
2530         interdependent_update = top_pipe_to_program->plane_state &&
2531                 top_pipe_to_program->plane_state->update_flags.bits.full_update;
2532
2533         underflow_check_delay_us = dc->debug.underflow_assert_delay_us;
2534
2535         if (underflow_check_delay_us != 0xFFFFFFFF && hws->funcs.did_underflow_occur)
2536                 ASSERT(hws->funcs.did_underflow_occur(dc, top_pipe_to_program));
2537
2538         if (underflow_check_delay_us != 0xFFFFFFFF)
2539                 udelay(underflow_check_delay_us);
2540
2541         if (underflow_check_delay_us != 0xFFFFFFFF && hws->funcs.did_underflow_occur)
2542                 ASSERT(hws->funcs.did_underflow_occur(dc, top_pipe_to_program));
2543
2544         if (num_planes == 0) {
2545                 /* OTG blank before remove all front end */
2546                 hws->funcs.blank_pixel_data(dc, top_pipe_to_program, true);
2547         }
2548
2549         /* Disconnect unused mpcc */
2550         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2551                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2552                 struct pipe_ctx *old_pipe_ctx =
2553                                 &dc->current_state->res_ctx.pipe_ctx[i];
2554
2555                 pipe_ctx->update_flags.raw = 0;
2556
2557                 if ((!pipe_ctx->plane_state ||
2558                      pipe_ctx->stream_res.tg != old_pipe_ctx->stream_res.tg) &&
2559                     old_pipe_ctx->plane_state &&
2560                     old_pipe_ctx->stream_res.tg == tg) {
2561
2562                         hws->funcs.plane_atomic_disconnect(dc, old_pipe_ctx);
2563                         pipe_ctx->update_flags.bits.disable = 1;
2564
2565                         DC_LOG_DC("Reset mpcc for pipe %d\n",
2566                                         old_pipe_ctx->pipe_idx);
2567                 }
2568         }
2569
2570         if (num_planes > 0)
2571                 dcn10_program_all_pipe_in_tree(dc, top_pipe_to_program, context);
2572
2573         /* Program secondary blending tree and writeback pipes */
2574         if ((stream->num_wb_info > 0) && (hws->funcs.program_all_writeback_pipes_in_tree))
2575                 hws->funcs.program_all_writeback_pipes_in_tree(dc, stream, context);
2576         if (interdependent_update)
2577                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2578                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2579                         /* Skip inactive pipes and ones already updated */
2580                         if (!pipe_ctx->stream || pipe_ctx->stream == stream ||
2581                             !pipe_ctx->plane_state || !tg->funcs->is_tg_enabled(tg))
2582                                 continue;
2583
2584                         pipe_ctx->plane_res.hubp->funcs->hubp_setup_interdependent(
2585                                 pipe_ctx->plane_res.hubp,
2586                                 &pipe_ctx->dlg_regs,
2587                                 &pipe_ctx->ttu_regs);
2588                 }
2589 }
2590
2591 void dcn10_post_unlock_program_front_end(
2592                 struct dc *dc,
2593                 struct dc_state *context)
2594 {
2595         int i, j;
2596
2597         DC_LOGGER_INIT(dc->ctx->logger);
2598
2599         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2600                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2601
2602                 if (!pipe_ctx->top_pipe &&
2603                         !pipe_ctx->prev_odm_pipe &&
2604                         pipe_ctx->stream) {
2605                         struct dc_stream_status *stream_status = NULL;
2606                         struct timing_generator *tg = pipe_ctx->stream_res.tg;
2607
2608                         for (j = 0; j < context->stream_count; j++) {
2609                                 if (pipe_ctx->stream == context->streams[j])
2610                                         stream_status = &context->stream_status[j];
2611                         }
2612
2613                         if (context->stream_status[i].plane_count == 0)
2614                                 false_optc_underflow_wa(dc, pipe_ctx->stream, tg);
2615                 }
2616         }
2617
2618         for (i = 0; i < dc->res_pool->pipe_count; i++)
2619                 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable)
2620                         dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
2621
2622         for (i = 0; i < dc->res_pool->pipe_count; i++)
2623                 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable) {
2624                         dc->hwss.optimize_bandwidth(dc, context);
2625                         break;
2626                 }
2627
2628         if (dc->hwseq->wa.DEGVIDCN10_254)
2629                 hubbub1_wm_change_req_wa(dc->res_pool->hubbub);
2630 }
2631
2632 static void dcn10_stereo_hw_frame_pack_wa(struct dc *dc, struct dc_state *context)
2633 {
2634         uint8_t i;
2635
2636         for (i = 0; i < context->stream_count; i++) {
2637                 if (context->streams[i]->timing.timing_3d_format
2638                                 == TIMING_3D_FORMAT_HW_FRAME_PACKING) {
2639                         /*
2640                          * Disable stutter
2641                          */
2642                         hubbub1_allow_self_refresh_control(dc->res_pool->hubbub, false);
2643                         break;
2644                 }
2645         }
2646 }
2647
2648 void dcn10_prepare_bandwidth(
2649                 struct dc *dc,
2650                 struct dc_state *context)
2651 {
2652         struct dce_hwseq *hws = dc->hwseq;
2653         struct hubbub *hubbub = dc->res_pool->hubbub;
2654
2655         if (dc->debug.sanity_checks)
2656                 hws->funcs.verify_allow_pstate_change_high(dc);
2657
2658         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
2659                 if (context->stream_count == 0)
2660                         context->bw_ctx.bw.dcn.clk.phyclk_khz = 0;
2661
2662                 dc->clk_mgr->funcs->update_clocks(
2663                                 dc->clk_mgr,
2664                                 context,
2665                                 false);
2666         }
2667
2668         hubbub->funcs->program_watermarks(hubbub,
2669                         &context->bw_ctx.bw.dcn.watermarks,
2670                         dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
2671                         true);
2672         dcn10_stereo_hw_frame_pack_wa(dc, context);
2673
2674         if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE)
2675                 dcn_bw_notify_pplib_of_wm_ranges(dc);
2676
2677         if (dc->debug.sanity_checks)
2678                 hws->funcs.verify_allow_pstate_change_high(dc);
2679 }
2680
2681 void dcn10_optimize_bandwidth(
2682                 struct dc *dc,
2683                 struct dc_state *context)
2684 {
2685         struct dce_hwseq *hws = dc->hwseq;
2686         struct hubbub *hubbub = dc->res_pool->hubbub;
2687
2688         if (dc->debug.sanity_checks)
2689                 hws->funcs.verify_allow_pstate_change_high(dc);
2690
2691         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
2692                 if (context->stream_count == 0)
2693                         context->bw_ctx.bw.dcn.clk.phyclk_khz = 0;
2694
2695                 dc->clk_mgr->funcs->update_clocks(
2696                                 dc->clk_mgr,
2697                                 context,
2698                                 true);
2699         }
2700
2701         hubbub->funcs->program_watermarks(hubbub,
2702                         &context->bw_ctx.bw.dcn.watermarks,
2703                         dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
2704                         true);
2705         dcn10_stereo_hw_frame_pack_wa(dc, context);
2706
2707         if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE)
2708                 dcn_bw_notify_pplib_of_wm_ranges(dc);
2709
2710         if (dc->debug.sanity_checks)
2711                 hws->funcs.verify_allow_pstate_change_high(dc);
2712 }
2713
2714 void dcn10_set_drr(struct pipe_ctx **pipe_ctx,
2715                 int num_pipes, unsigned int vmin, unsigned int vmax,
2716                 unsigned int vmid, unsigned int vmid_frame_number)
2717 {
2718         int i = 0;
2719         struct drr_params params = {0};
2720         // DRR set trigger event mapped to OTG_TRIG_A (bit 11) for manual control flow
2721         unsigned int event_triggers = 0x800;
2722         // Note DRR trigger events are generated regardless of whether num frames met.
2723         unsigned int num_frames = 2;
2724
2725         params.vertical_total_max = vmax;
2726         params.vertical_total_min = vmin;
2727         params.vertical_total_mid = vmid;
2728         params.vertical_total_mid_frame_num = vmid_frame_number;
2729
2730         /* TODO: If multiple pipes are to be supported, you need
2731          * some GSL stuff. Static screen triggers may be programmed differently
2732          * as well.
2733          */
2734         for (i = 0; i < num_pipes; i++) {
2735                 pipe_ctx[i]->stream_res.tg->funcs->set_drr(
2736                         pipe_ctx[i]->stream_res.tg, &params);
2737                 if (vmax != 0 && vmin != 0)
2738                         pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control(
2739                                         pipe_ctx[i]->stream_res.tg,
2740                                         event_triggers, num_frames);
2741         }
2742 }
2743
2744 void dcn10_get_position(struct pipe_ctx **pipe_ctx,
2745                 int num_pipes,
2746                 struct crtc_position *position)
2747 {
2748         int i = 0;
2749
2750         /* TODO: handle pipes > 1
2751          */
2752         for (i = 0; i < num_pipes; i++)
2753                 pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);
2754 }
2755
2756 void dcn10_set_static_screen_control(struct pipe_ctx **pipe_ctx,
2757                 int num_pipes, const struct dc_static_screen_params *params)
2758 {
2759         unsigned int i;
2760         unsigned int triggers = 0;
2761
2762         if (params->triggers.surface_update)
2763                 triggers |= 0x80;
2764         if (params->triggers.cursor_update)
2765                 triggers |= 0x2;
2766         if (params->triggers.force_trigger)
2767                 triggers |= 0x1;
2768
2769         for (i = 0; i < num_pipes; i++)
2770                 pipe_ctx[i]->stream_res.tg->funcs->
2771                         set_static_screen_control(pipe_ctx[i]->stream_res.tg,
2772                                         triggers, params->num_frames);
2773 }
2774
2775 static void dcn10_config_stereo_parameters(
2776                 struct dc_stream_state *stream, struct crtc_stereo_flags *flags)
2777 {
2778         enum view_3d_format view_format = stream->view_format;
2779         enum dc_timing_3d_format timing_3d_format =\
2780                         stream->timing.timing_3d_format;
2781         bool non_stereo_timing = false;
2782
2783         if (timing_3d_format == TIMING_3D_FORMAT_NONE ||
2784                 timing_3d_format == TIMING_3D_FORMAT_SIDE_BY_SIDE ||
2785                 timing_3d_format == TIMING_3D_FORMAT_TOP_AND_BOTTOM)
2786                 non_stereo_timing = true;
2787
2788         if (non_stereo_timing == false &&
2789                 view_format == VIEW_3D_FORMAT_FRAME_SEQUENTIAL) {
2790
2791                 flags->PROGRAM_STEREO         = 1;
2792                 flags->PROGRAM_POLARITY       = 1;
2793                 if (timing_3d_format == TIMING_3D_FORMAT_INBAND_FA ||
2794                         timing_3d_format == TIMING_3D_FORMAT_DP_HDMI_INBAND_FA ||
2795                         timing_3d_format == TIMING_3D_FORMAT_SIDEBAND_FA) {
2796                         enum display_dongle_type dongle = \
2797                                         stream->link->ddc->dongle_type;
2798                         if (dongle == DISPLAY_DONGLE_DP_VGA_CONVERTER ||
2799                                 dongle == DISPLAY_DONGLE_DP_DVI_CONVERTER ||
2800                                 dongle == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
2801                                 flags->DISABLE_STEREO_DP_SYNC = 1;
2802                 }
2803                 flags->RIGHT_EYE_POLARITY =\
2804                                 stream->timing.flags.RIGHT_EYE_3D_POLARITY;
2805                 if (timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
2806                         flags->FRAME_PACKED = 1;
2807         }
2808
2809         return;
2810 }
2811
2812 void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc)
2813 {
2814         struct crtc_stereo_flags flags = { 0 };
2815         struct dc_stream_state *stream = pipe_ctx->stream;
2816
2817         dcn10_config_stereo_parameters(stream, &flags);
2818
2819         if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_SIDEBAND_FA) {
2820                 if (!dc_set_generic_gpio_for_stereo(true, dc->ctx->gpio_service))
2821                         dc_set_generic_gpio_for_stereo(false, dc->ctx->gpio_service);
2822         } else {
2823                 dc_set_generic_gpio_for_stereo(false, dc->ctx->gpio_service);
2824         }
2825
2826         pipe_ctx->stream_res.opp->funcs->opp_program_stereo(
2827                 pipe_ctx->stream_res.opp,
2828                 flags.PROGRAM_STEREO == 1 ? true:false,
2829                 &stream->timing);
2830
2831         pipe_ctx->stream_res.tg->funcs->program_stereo(
2832                 pipe_ctx->stream_res.tg,
2833                 &stream->timing,
2834                 &flags);
2835
2836         return;
2837 }
2838
2839 static struct hubp *get_hubp_by_inst(struct resource_pool *res_pool, int mpcc_inst)
2840 {
2841         int i;
2842
2843         for (i = 0; i < res_pool->pipe_count; i++) {
2844                 if (res_pool->hubps[i]->inst == mpcc_inst)
2845                         return res_pool->hubps[i];
2846         }
2847         ASSERT(false);
2848         return NULL;
2849 }
2850
2851 void dcn10_wait_for_mpcc_disconnect(
2852                 struct dc *dc,
2853                 struct resource_pool *res_pool,
2854                 struct pipe_ctx *pipe_ctx)
2855 {
2856         struct dce_hwseq *hws = dc->hwseq;
2857         int mpcc_inst;
2858
2859         if (dc->debug.sanity_checks) {
2860                 hws->funcs.verify_allow_pstate_change_high(dc);
2861         }
2862
2863         if (!pipe_ctx->stream_res.opp)
2864                 return;
2865
2866         for (mpcc_inst = 0; mpcc_inst < MAX_PIPES; mpcc_inst++) {
2867                 if (pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst]) {
2868                         struct hubp *hubp = get_hubp_by_inst(res_pool, mpcc_inst);
2869
2870                         res_pool->mpc->funcs->wait_for_idle(res_pool->mpc, mpcc_inst);
2871                         pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst] = false;
2872                         hubp->funcs->set_blank(hubp, true);
2873                 }
2874         }
2875
2876         if (dc->debug.sanity_checks) {
2877                 hws->funcs.verify_allow_pstate_change_high(dc);
2878         }
2879
2880 }
2881
2882 bool dcn10_dummy_display_power_gating(
2883         struct dc *dc,
2884         uint8_t controller_id,
2885         struct dc_bios *dcb,
2886         enum pipe_gating_control power_gating)
2887 {
2888         return true;
2889 }
2890
2891 void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx)
2892 {
2893         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2894         struct timing_generator *tg = pipe_ctx->stream_res.tg;
2895         bool flip_pending;
2896
2897         if (plane_state == NULL)
2898                 return;
2899
2900         flip_pending = pipe_ctx->plane_res.hubp->funcs->hubp_is_flip_pending(
2901                                         pipe_ctx->plane_res.hubp);
2902
2903         plane_state->status.is_flip_pending = plane_state->status.is_flip_pending || flip_pending;
2904
2905         if (!flip_pending)
2906                 plane_state->status.current_address = plane_state->status.requested_address;
2907
2908         if (plane_state->status.current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2909                         tg->funcs->is_stereo_left_eye) {
2910                 plane_state->status.is_right_eye =
2911                                 !tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);
2912         }
2913 }
2914
2915 void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data)
2916 {
2917         struct hubbub *hubbub = hws->ctx->dc->res_pool->hubbub;
2918
2919         /* In DCN, this programming sequence is owned by the hubbub */
2920         hubbub->funcs->update_dchub(hubbub, dh_data);
2921 }
2922
2923 static bool dcn10_can_pipe_disable_cursor(struct pipe_ctx *pipe_ctx)
2924 {
2925         struct pipe_ctx *test_pipe;
2926         const struct rect *r1 = &pipe_ctx->plane_res.scl_data.recout, *r2;
2927         int r1_r = r1->x + r1->width, r1_b = r1->y + r1->height, r2_r, r2_b;
2928
2929         /**
2930          * Disable the cursor if there's another pipe above this with a
2931          * plane that contains this pipe's viewport to prevent double cursor
2932          * and incorrect scaling artifacts.
2933          */
2934         for (test_pipe = pipe_ctx->top_pipe; test_pipe;
2935              test_pipe = test_pipe->top_pipe) {
2936                 if (!test_pipe->plane_state->visible)
2937                         continue;
2938
2939                 r2 = &test_pipe->plane_res.scl_data.recout;
2940                 r2_r = r2->x + r2->width;
2941                 r2_b = r2->y + r2->height;
2942
2943                 if (r1->x >= r2->x && r1->y >= r2->y && r1_r <= r2_r && r1_b <= r2_b)
2944                         return true;
2945         }
2946
2947         return false;
2948 }
2949
2950 void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)
2951 {
2952         struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;
2953         struct hubp *hubp = pipe_ctx->plane_res.hubp;
2954         struct dpp *dpp = pipe_ctx->plane_res.dpp;
2955         struct dc_cursor_mi_param param = {
2956                 .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10,
2957                 .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz,
2958                 .viewport = pipe_ctx->plane_res.scl_data.viewport,
2959                 .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz,
2960                 .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert,
2961                 .rotation = pipe_ctx->plane_state->rotation,
2962                 .mirror = pipe_ctx->plane_state->horizontal_mirror
2963         };
2964         bool pipe_split_on = (pipe_ctx->top_pipe != NULL) ||
2965                 (pipe_ctx->bottom_pipe != NULL);
2966
2967         int x_plane = pipe_ctx->plane_state->dst_rect.x;
2968         int y_plane = pipe_ctx->plane_state->dst_rect.y;
2969         int x_pos = pos_cpy.x;
2970         int y_pos = pos_cpy.y;
2971
2972         // translate cursor from stream space to plane space
2973         x_pos = (x_pos - x_plane) * pipe_ctx->plane_state->src_rect.width /
2974                         pipe_ctx->plane_state->dst_rect.width;
2975         y_pos = (y_pos - y_plane) * pipe_ctx->plane_state->src_rect.height /
2976                         pipe_ctx->plane_state->dst_rect.height;
2977
2978         if (x_pos < 0) {
2979                 pos_cpy.x_hotspot -= x_pos;
2980                 x_pos = 0;
2981         }
2982
2983         if (y_pos < 0) {
2984                 pos_cpy.y_hotspot -= y_pos;
2985                 y_pos = 0;
2986         }
2987
2988         pos_cpy.x = (uint32_t)x_pos;
2989         pos_cpy.y = (uint32_t)y_pos;
2990
2991         if (pipe_ctx->plane_state->address.type
2992                         == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
2993                 pos_cpy.enable = false;
2994
2995         if (pos_cpy.enable && dcn10_can_pipe_disable_cursor(pipe_ctx))
2996                 pos_cpy.enable = false;
2997
2998         // Swap axis and mirror horizontally
2999         if (param.rotation == ROTATION_ANGLE_90) {
3000                 uint32_t temp_x = pos_cpy.x;
3001
3002                 pos_cpy.x = pipe_ctx->plane_res.scl_data.viewport.width -
3003                                 (pos_cpy.y - pipe_ctx->plane_res.scl_data.viewport.x) + pipe_ctx->plane_res.scl_data.viewport.x;
3004                 pos_cpy.y = temp_x;
3005         }
3006         // Swap axis and mirror vertically
3007         else if (param.rotation == ROTATION_ANGLE_270) {
3008                 uint32_t temp_y = pos_cpy.y;
3009                 int viewport_height =
3010                         pipe_ctx->plane_res.scl_data.viewport.height;
3011
3012                 if (pipe_split_on) {
3013                         if (pos_cpy.x > viewport_height) {
3014                                 pos_cpy.x = pos_cpy.x - viewport_height;
3015                                 pos_cpy.y = viewport_height - pos_cpy.x;
3016                         } else {
3017                                 pos_cpy.y = 2 * viewport_height - pos_cpy.x;
3018                         }
3019                 } else
3020                         pos_cpy.y = viewport_height - pos_cpy.x;
3021                 pos_cpy.x = temp_y;
3022         }
3023         // Mirror horizontally and vertically
3024         else if (param.rotation == ROTATION_ANGLE_180) {
3025                 int viewport_width =
3026                         pipe_ctx->plane_res.scl_data.viewport.width;
3027                 int viewport_x =
3028                         pipe_ctx->plane_res.scl_data.viewport.x;
3029
3030                 if (pipe_split_on) {
3031                         if (pos_cpy.x >= viewport_width + viewport_x) {
3032                                 pos_cpy.x = 2 * viewport_width
3033                                                 - pos_cpy.x + 2 * viewport_x;
3034                         } else {
3035                                 uint32_t temp_x = pos_cpy.x;
3036
3037                                 pos_cpy.x = 2 * viewport_x - pos_cpy.x;
3038                                 if (temp_x >= viewport_x +
3039                                         (int)hubp->curs_attr.width || pos_cpy.x
3040                                         <= (int)hubp->curs_attr.width +
3041                                         pipe_ctx->plane_state->src_rect.x) {
3042                                         pos_cpy.x = temp_x + viewport_width;
3043                                 }
3044                         }
3045                 } else {
3046                         pos_cpy.x = viewport_width - pos_cpy.x + 2 * viewport_x;
3047                 }
3048                 pos_cpy.y = pipe_ctx->plane_res.scl_data.viewport.height - pos_cpy.y;
3049         }
3050
3051         hubp->funcs->set_cursor_position(hubp, &pos_cpy, &param);
3052         dpp->funcs->set_cursor_position(dpp, &pos_cpy, &param, hubp->curs_attr.width, hubp->curs_attr.height);
3053 }
3054
3055 void dcn10_set_cursor_attribute(struct pipe_ctx *pipe_ctx)
3056 {
3057         struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;
3058
3059         pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes(
3060                         pipe_ctx->plane_res.hubp, attributes);
3061         pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes(
3062                 pipe_ctx->plane_res.dpp, attributes);
3063 }
3064
3065 void dcn10_set_cursor_sdr_white_level(struct pipe_ctx *pipe_ctx)
3066 {
3067         uint32_t sdr_white_level = pipe_ctx->stream->cursor_attributes.sdr_white_level;
3068         struct fixed31_32 multiplier;
3069         struct dpp_cursor_attributes opt_attr = { 0 };
3070         uint32_t hw_scale = 0x3c00; // 1.0 default multiplier
3071         struct custom_float_format fmt;
3072
3073         if (!pipe_ctx->plane_res.dpp->funcs->set_optional_cursor_attributes)
3074                 return;
3075
3076         fmt.exponenta_bits = 5;
3077         fmt.mantissa_bits = 10;
3078         fmt.sign = true;
3079
3080         if (sdr_white_level > 80) {
3081                 multiplier = dc_fixpt_from_fraction(sdr_white_level, 80);
3082                 convert_to_custom_float_format(multiplier, &fmt, &hw_scale);
3083         }
3084
3085         opt_attr.scale = hw_scale;
3086         opt_attr.bias = 0;
3087
3088         pipe_ctx->plane_res.dpp->funcs->set_optional_cursor_attributes(
3089                         pipe_ctx->plane_res.dpp, &opt_attr);
3090 }
3091
3092 /*
3093  * apply_front_porch_workaround  TODO FPGA still need?
3094  *
3095  * This is a workaround for a bug that has existed since R5xx and has not been
3096  * fixed keep Front porch at minimum 2 for Interlaced mode or 1 for progressive.
3097  */
3098 static void apply_front_porch_workaround(
3099         struct dc_crtc_timing *timing)
3100 {
3101         if (timing->flags.INTERLACE == 1) {
3102                 if (timing->v_front_porch < 2)
3103                         timing->v_front_porch = 2;
3104         } else {
3105                 if (timing->v_front_porch < 1)
3106                         timing->v_front_porch = 1;
3107         }
3108 }
3109
3110 int dcn10_get_vupdate_offset_from_vsync(struct pipe_ctx *pipe_ctx)
3111 {
3112         const struct dc_crtc_timing *dc_crtc_timing = &pipe_ctx->stream->timing;
3113         struct dc_crtc_timing patched_crtc_timing;
3114         int vesa_sync_start;
3115         int asic_blank_end;
3116         int interlace_factor;
3117         int vertical_line_start;
3118
3119         patched_crtc_timing = *dc_crtc_timing;
3120         apply_front_porch_workaround(&patched_crtc_timing);
3121
3122         interlace_factor = patched_crtc_timing.flags.INTERLACE ? 2 : 1;
3123
3124         vesa_sync_start = patched_crtc_timing.v_addressable +
3125                         patched_crtc_timing.v_border_bottom +
3126                         patched_crtc_timing.v_front_porch;
3127
3128         asic_blank_end = (patched_crtc_timing.v_total -
3129                         vesa_sync_start -
3130                         patched_crtc_timing.v_border_top)
3131                         * interlace_factor;
3132
3133         vertical_line_start = asic_blank_end -
3134                         pipe_ctx->pipe_dlg_param.vstartup_start + 1;
3135
3136         return vertical_line_start;
3137 }
3138
3139 static void dcn10_calc_vupdate_position(
3140                 struct dc *dc,
3141                 struct pipe_ctx *pipe_ctx,
3142                 uint32_t *start_line,
3143                 uint32_t *end_line)
3144 {
3145         const struct dc_crtc_timing *dc_crtc_timing = &pipe_ctx->stream->timing;
3146         int vline_int_offset_from_vupdate =
3147                         pipe_ctx->stream->periodic_interrupt0.lines_offset;
3148         int vupdate_offset_from_vsync = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);
3149         int start_position;
3150
3151         if (vline_int_offset_from_vupdate > 0)
3152                 vline_int_offset_from_vupdate--;
3153         else if (vline_int_offset_from_vupdate < 0)
3154                 vline_int_offset_from_vupdate++;
3155
3156         start_position = vline_int_offset_from_vupdate + vupdate_offset_from_vsync;
3157
3158         if (start_position >= 0)
3159                 *start_line = start_position;
3160         else
3161                 *start_line = dc_crtc_timing->v_total + start_position - 1;
3162
3163         *end_line = *start_line + 2;
3164
3165         if (*end_line >= dc_crtc_timing->v_total)
3166                 *end_line = 2;
3167 }
3168
3169 static void dcn10_cal_vline_position(
3170                 struct dc *dc,
3171                 struct pipe_ctx *pipe_ctx,
3172                 enum vline_select vline,
3173                 uint32_t *start_line,
3174                 uint32_t *end_line)
3175 {
3176         enum vertical_interrupt_ref_point ref_point = INVALID_POINT;
3177
3178         if (vline == VLINE0)
3179                 ref_point = pipe_ctx->stream->periodic_interrupt0.ref_point;
3180         else if (vline == VLINE1)
3181                 ref_point = pipe_ctx->stream->periodic_interrupt1.ref_point;
3182
3183         switch (ref_point) {
3184         case START_V_UPDATE:
3185                 dcn10_calc_vupdate_position(
3186                                 dc,
3187                                 pipe_ctx,
3188                                 start_line,
3189                                 end_line);
3190                 break;
3191         case START_V_SYNC:
3192                 // Suppose to do nothing because vsync is 0;
3193                 break;
3194         default:
3195                 ASSERT(0);
3196                 break;
3197         }
3198 }
3199
3200 void dcn10_setup_periodic_interrupt(
3201                 struct dc *dc,
3202                 struct pipe_ctx *pipe_ctx,
3203                 enum vline_select vline)
3204 {
3205         struct timing_generator *tg = pipe_ctx->stream_res.tg;
3206
3207         if (vline == VLINE0) {
3208                 uint32_t start_line = 0;
3209                 uint32_t end_line = 0;
3210
3211                 dcn10_cal_vline_position(dc, pipe_ctx, vline, &start_line, &end_line);
3212
3213                 tg->funcs->setup_vertical_interrupt0(tg, start_line, end_line);
3214
3215         } else if (vline == VLINE1) {
3216                 pipe_ctx->stream_res.tg->funcs->setup_vertical_interrupt1(
3217                                 tg,
3218                                 pipe_ctx->stream->periodic_interrupt1.lines_offset);
3219         }
3220 }
3221
3222 void dcn10_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx)
3223 {
3224         struct timing_generator *tg = pipe_ctx->stream_res.tg;
3225         int start_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);
3226
3227         if (start_line < 0) {
3228                 ASSERT(0);
3229                 start_line = 0;
3230         }
3231
3232         if (tg->funcs->setup_vertical_interrupt2)
3233                 tg->funcs->setup_vertical_interrupt2(tg, start_line);
3234 }
3235
3236 void dcn10_unblank_stream(struct pipe_ctx *pipe_ctx,
3237                 struct dc_link_settings *link_settings)
3238 {
3239         struct encoder_unblank_param params = { { 0 } };
3240         struct dc_stream_state *stream = pipe_ctx->stream;
3241         struct dc_link *link = stream->link;
3242         struct dce_hwseq *hws = link->dc->hwseq;
3243
3244         /* only 3 items below are used by unblank */
3245         params.timing = pipe_ctx->stream->timing;
3246
3247         params.link_settings.link_rate = link_settings->link_rate;
3248
3249         if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
3250                 if (params.timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
3251                         params.timing.pix_clk_100hz /= 2;
3252                 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, &params);
3253         }
3254
3255         if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
3256                 hws->funcs.edp_backlight_control(link, true);
3257         }
3258 }
3259
3260 void dcn10_send_immediate_sdp_message(struct pipe_ctx *pipe_ctx,
3261                                 const uint8_t *custom_sdp_message,
3262                                 unsigned int sdp_message_size)
3263 {
3264         if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
3265                 pipe_ctx->stream_res.stream_enc->funcs->send_immediate_sdp_message(
3266                                 pipe_ctx->stream_res.stream_enc,
3267                                 custom_sdp_message,
3268                                 sdp_message_size);
3269         }
3270 }
3271 enum dc_status dcn10_set_clock(struct dc *dc,
3272                         enum dc_clock_type clock_type,
3273                         uint32_t clk_khz,
3274                         uint32_t stepping)
3275 {
3276         struct dc_state *context = dc->current_state;
3277         struct dc_clock_config clock_cfg = {0};
3278         struct dc_clocks *current_clocks = &context->bw_ctx.bw.dcn.clk;
3279
3280         if (dc->clk_mgr && dc->clk_mgr->funcs->get_clock)
3281                                 dc->clk_mgr->funcs->get_clock(dc->clk_mgr,
3282                                                 context, clock_type, &clock_cfg);
3283
3284         if (!dc->clk_mgr->funcs->get_clock)
3285                 return DC_FAIL_UNSUPPORTED_1;
3286
3287         if (clk_khz > clock_cfg.max_clock_khz)
3288                 return DC_FAIL_CLK_EXCEED_MAX;
3289
3290         if (clk_khz < clock_cfg.min_clock_khz)
3291                 return DC_FAIL_CLK_BELOW_MIN;
3292
3293         if (clk_khz < clock_cfg.bw_requirequired_clock_khz)
3294                 return DC_FAIL_CLK_BELOW_CFG_REQUIRED;
3295
3296         /*update internal request clock for update clock use*/
3297         if (clock_type == DC_CLOCK_TYPE_DISPCLK)
3298                 current_clocks->dispclk_khz = clk_khz;
3299         else if (clock_type == DC_CLOCK_TYPE_DPPCLK)
3300                 current_clocks->dppclk_khz = clk_khz;
3301         else
3302                 return DC_ERROR_UNEXPECTED;
3303
3304         if (dc->clk_mgr && dc->clk_mgr->funcs->update_clocks)
3305                                 dc->clk_mgr->funcs->update_clocks(dc->clk_mgr,
3306                                 context, true);
3307         return DC_OK;
3308
3309 }
3310
3311 void dcn10_get_clock(struct dc *dc,
3312                         enum dc_clock_type clock_type,
3313                         struct dc_clock_config *clock_cfg)
3314 {
3315         struct dc_state *context = dc->current_state;
3316
3317         if (dc->clk_mgr && dc->clk_mgr->funcs->get_clock)
3318                                 dc->clk_mgr->funcs->get_clock(dc->clk_mgr, context, clock_type, clock_cfg);
3319
3320 }