2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include "dm_services.h"
27 #include "core_types.h"
29 #include "custom_float.h"
30 #include "dcn10_hw_sequencer.h"
31 #include "dce110/dce110_hw_sequencer.h"
32 #include "dce/dce_hwseq.h"
35 #include "dcn10_optc.h"
36 #include "dcn10/dcn10_dpp.h"
37 #include "dcn10/dcn10_mpc.h"
38 #include "timing_generator.h"
42 #include "reg_helper.h"
43 #include "dcn10_hubp.h"
44 #include "dcn10_hubbub.h"
45 #include "dcn10_cm_common.h"
46 #include "dc_link_dp.h"
49 #define DC_LOGGER_INIT(logger)
57 #define FN(reg_name, field_name) \
58 hws->shifts->field_name, hws->masks->field_name
60 /*print is 17 wide, first two characters are spaces*/
61 #define DTN_INFO_MICRO_SEC(ref_cycle) \
62 print_microsec(dc_ctx, log_ctx, ref_cycle)
64 void print_microsec(struct dc_context *dc_ctx,
65 struct dc_log_buffer_ctx *log_ctx,
68 const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000;
69 static const unsigned int frac = 1000;
70 uint32_t us_x10 = (ref_cycle * frac) / ref_clk_mhz;
72 DTN_INFO(" %11d.%03d",
77 static void log_mpc_crc(struct dc *dc,
78 struct dc_log_buffer_ctx *log_ctx)
80 struct dc_context *dc_ctx = dc->ctx;
81 struct dce_hwseq *hws = dc->hwseq;
83 if (REG(MPC_CRC_RESULT_GB))
84 DTN_INFO("MPC_CRC_RESULT_GB:%d MPC_CRC_RESULT_C:%d MPC_CRC_RESULT_AR:%d\n",
85 REG_READ(MPC_CRC_RESULT_GB), REG_READ(MPC_CRC_RESULT_C), REG_READ(MPC_CRC_RESULT_AR));
86 if (REG(DPP_TOP0_DPP_CRC_VAL_B_A))
87 DTN_INFO("DPP_TOP0_DPP_CRC_VAL_B_A:%d DPP_TOP0_DPP_CRC_VAL_R_G:%d\n",
88 REG_READ(DPP_TOP0_DPP_CRC_VAL_B_A), REG_READ(DPP_TOP0_DPP_CRC_VAL_R_G));
91 void dcn10_log_hubbub_state(struct dc *dc, struct dc_log_buffer_ctx *log_ctx)
93 struct dc_context *dc_ctx = dc->ctx;
94 struct dcn_hubbub_wm wm;
97 memset(&wm, 0, sizeof(struct dcn_hubbub_wm));
98 dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm);
100 DTN_INFO("HUBBUB WM: data_urgent pte_meta_urgent"
101 " sr_enter sr_exit dram_clk_change\n");
103 for (i = 0; i < 4; i++) {
104 struct dcn_hubbub_wm_set *s;
107 DTN_INFO("WM_Set[%d]:", s->wm_set);
108 DTN_INFO_MICRO_SEC(s->data_urgent);
109 DTN_INFO_MICRO_SEC(s->pte_meta_urgent);
110 DTN_INFO_MICRO_SEC(s->sr_enter);
111 DTN_INFO_MICRO_SEC(s->sr_exit);
112 DTN_INFO_MICRO_SEC(s->dram_clk_chanage);
119 static void dcn10_log_hubp_states(struct dc *dc, void *log_ctx)
121 struct dc_context *dc_ctx = dc->ctx;
122 struct resource_pool *pool = dc->res_pool;
125 DTN_INFO("HUBP: format addr_hi width height"
126 " rot mir sw_mode dcc_en blank_en ttu_dis underflow"
127 " min_ttu_vblank qos_low_wm qos_high_wm\n");
128 for (i = 0; i < pool->pipe_count; i++) {
129 struct hubp *hubp = pool->hubps[i];
130 struct dcn_hubp_state *s = &(TO_DCN10_HUBP(hubp)->state);
132 hubp->funcs->hubp_read_state(hubp);
135 DTN_INFO("[%2d]: %5xh %6xh %5d %6d %2xh %2xh %6xh"
148 s->underflow_status);
149 DTN_INFO_MICRO_SEC(s->min_ttu_vblank);
150 DTN_INFO_MICRO_SEC(s->qos_level_low_wm);
151 DTN_INFO_MICRO_SEC(s->qos_level_high_wm);
156 DTN_INFO("\n=========RQ========\n");
157 DTN_INFO("HUBP: drq_exp_m prq_exp_m mrq_exp_m crq_exp_m plane1_ba L:chunk_s min_chu_s meta_ch_s"
158 " min_m_c_s dpte_gr_s mpte_gr_s swath_hei pte_row_h C:chunk_s min_chu_s meta_ch_s"
159 " min_m_c_s dpte_gr_s mpte_gr_s swath_hei pte_row_h\n");
160 for (i = 0; i < pool->pipe_count; i++) {
161 struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);
162 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;
165 DTN_INFO("[%2d]: %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh\n",
166 pool->hubps[i]->inst, rq_regs->drq_expansion_mode, rq_regs->prq_expansion_mode, rq_regs->mrq_expansion_mode,
167 rq_regs->crq_expansion_mode, rq_regs->plane1_base_address, rq_regs->rq_regs_l.chunk_size,
168 rq_regs->rq_regs_l.min_chunk_size, rq_regs->rq_regs_l.meta_chunk_size,
169 rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs->rq_regs_l.dpte_group_size,
170 rq_regs->rq_regs_l.mpte_group_size, rq_regs->rq_regs_l.swath_height,
171 rq_regs->rq_regs_l.pte_row_height_linear, rq_regs->rq_regs_c.chunk_size, rq_regs->rq_regs_c.min_chunk_size,
172 rq_regs->rq_regs_c.meta_chunk_size, rq_regs->rq_regs_c.min_meta_chunk_size,
173 rq_regs->rq_regs_c.dpte_group_size, rq_regs->rq_regs_c.mpte_group_size,
174 rq_regs->rq_regs_c.swath_height, rq_regs->rq_regs_c.pte_row_height_linear);
177 DTN_INFO("========DLG========\n");
178 DTN_INFO("HUBP: rc_hbe dlg_vbe min_d_y_n rc_per_ht rc_x_a_s "
179 " dst_y_a_s dst_y_pf dst_y_vvb dst_y_rvb dst_y_vfl dst_y_rfl rf_pix_fq"
180 " vratio_pf vrat_pf_c rc_pg_vbl rc_pg_vbc rc_mc_vbl rc_mc_vbc rc_pg_fll"
181 " rc_pg_flc rc_mc_fll rc_mc_flc pr_nom_l pr_nom_c rc_pg_nl rc_pg_nc "
182 " mr_nom_l mr_nom_c rc_mc_nl rc_mc_nc rc_ld_pl rc_ld_pc rc_ld_l "
183 " rc_ld_c cha_cur0 ofst_cur1 cha_cur1 vr_af_vc0 ddrq_limt x_rt_dlay"
184 " x_rp_dlay x_rr_sfl\n");
185 for (i = 0; i < pool->pipe_count; i++) {
186 struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);
187 struct _vcs_dpi_display_dlg_regs_st *dlg_regs = &s->dlg_attr;
190 DTN_INFO("[%2d]: %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh"
191 "% 8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh"
192 " %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh\n",
193 pool->hubps[i]->inst, dlg_regs->refcyc_h_blank_end, dlg_regs->dlg_vblank_end, dlg_regs->min_dst_y_next_start,
194 dlg_regs->refcyc_per_htotal, dlg_regs->refcyc_x_after_scaler, dlg_regs->dst_y_after_scaler,
195 dlg_regs->dst_y_prefetch, dlg_regs->dst_y_per_vm_vblank, dlg_regs->dst_y_per_row_vblank,
196 dlg_regs->dst_y_per_vm_flip, dlg_regs->dst_y_per_row_flip, dlg_regs->ref_freq_to_pix_freq,
197 dlg_regs->vratio_prefetch, dlg_regs->vratio_prefetch_c, dlg_regs->refcyc_per_pte_group_vblank_l,
198 dlg_regs->refcyc_per_pte_group_vblank_c, dlg_regs->refcyc_per_meta_chunk_vblank_l,
199 dlg_regs->refcyc_per_meta_chunk_vblank_c, dlg_regs->refcyc_per_pte_group_flip_l,
200 dlg_regs->refcyc_per_pte_group_flip_c, dlg_regs->refcyc_per_meta_chunk_flip_l,
201 dlg_regs->refcyc_per_meta_chunk_flip_c, dlg_regs->dst_y_per_pte_row_nom_l,
202 dlg_regs->dst_y_per_pte_row_nom_c, dlg_regs->refcyc_per_pte_group_nom_l,
203 dlg_regs->refcyc_per_pte_group_nom_c, dlg_regs->dst_y_per_meta_row_nom_l,
204 dlg_regs->dst_y_per_meta_row_nom_c, dlg_regs->refcyc_per_meta_chunk_nom_l,
205 dlg_regs->refcyc_per_meta_chunk_nom_c, dlg_regs->refcyc_per_line_delivery_pre_l,
206 dlg_regs->refcyc_per_line_delivery_pre_c, dlg_regs->refcyc_per_line_delivery_l,
207 dlg_regs->refcyc_per_line_delivery_c, dlg_regs->chunk_hdl_adjust_cur0, dlg_regs->dst_y_offset_cur1,
208 dlg_regs->chunk_hdl_adjust_cur1, dlg_regs->vready_after_vcount0, dlg_regs->dst_y_delta_drq_limit,
209 dlg_regs->xfc_reg_transfer_delay, dlg_regs->xfc_reg_precharge_delay,
210 dlg_regs->xfc_reg_remote_surface_flip_latency);
213 DTN_INFO("========TTU========\n");
214 DTN_INFO("HUBP: qos_ll_wm qos_lh_wm mn_ttu_vb qos_l_flp rc_rd_p_l rc_rd_l rc_rd_p_c"
215 " rc_rd_c rc_rd_c0 rc_rd_pc0 rc_rd_c1 rc_rd_pc1 qos_lf_l qos_rds_l"
216 " qos_lf_c qos_rds_c qos_lf_c0 qos_rds_c0 qos_lf_c1 qos_rds_c1\n");
217 for (i = 0; i < pool->pipe_count; i++) {
218 struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);
219 struct _vcs_dpi_display_ttu_regs_st *ttu_regs = &s->ttu_attr;
222 DTN_INFO("[%2d]: %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh\n",
223 pool->hubps[i]->inst, ttu_regs->qos_level_low_wm, ttu_regs->qos_level_high_wm, ttu_regs->min_ttu_vblank,
224 ttu_regs->qos_level_flip, ttu_regs->refcyc_per_req_delivery_pre_l, ttu_regs->refcyc_per_req_delivery_l,
225 ttu_regs->refcyc_per_req_delivery_pre_c, ttu_regs->refcyc_per_req_delivery_c, ttu_regs->refcyc_per_req_delivery_cur0,
226 ttu_regs->refcyc_per_req_delivery_pre_cur0, ttu_regs->refcyc_per_req_delivery_cur1,
227 ttu_regs->refcyc_per_req_delivery_pre_cur1, ttu_regs->qos_level_fixed_l, ttu_regs->qos_ramp_disable_l,
228 ttu_regs->qos_level_fixed_c, ttu_regs->qos_ramp_disable_c, ttu_regs->qos_level_fixed_cur0,
229 ttu_regs->qos_ramp_disable_cur0, ttu_regs->qos_level_fixed_cur1, ttu_regs->qos_ramp_disable_cur1);
234 void dcn10_log_hw_state(struct dc *dc,
235 struct dc_log_buffer_ctx *log_ctx)
237 struct dc_context *dc_ctx = dc->ctx;
238 struct resource_pool *pool = dc->res_pool;
243 dcn10_log_hubbub_state(dc, log_ctx);
245 dcn10_log_hubp_states(dc, log_ctx);
247 DTN_INFO("DPP: IGAM format IGAM mode DGAM mode RGAM mode"
248 " GAMUT mode C11 C12 C13 C14 C21 C22 C23 C24 "
249 "C31 C32 C33 C34\n");
250 for (i = 0; i < pool->pipe_count; i++) {
251 struct dpp *dpp = pool->dpps[i];
252 struct dcn_dpp_state s = {0};
254 dpp->funcs->dpp_read_state(dpp, &s);
259 DTN_INFO("[%2d]: %11xh %-11s %-11s %-11s"
260 "%8x %08xh %08xh %08xh %08xh %08xh %08xh",
263 (s.igam_lut_mode == 0) ? "BypassFixed" :
264 ((s.igam_lut_mode == 1) ? "BypassFloat" :
265 ((s.igam_lut_mode == 2) ? "RAM" :
266 ((s.igam_lut_mode == 3) ? "RAM" :
268 (s.dgam_lut_mode == 0) ? "Bypass" :
269 ((s.dgam_lut_mode == 1) ? "sRGB" :
270 ((s.dgam_lut_mode == 2) ? "Ycc" :
271 ((s.dgam_lut_mode == 3) ? "RAM" :
272 ((s.dgam_lut_mode == 4) ? "RAM" :
274 (s.rgam_lut_mode == 0) ? "Bypass" :
275 ((s.rgam_lut_mode == 1) ? "sRGB" :
276 ((s.rgam_lut_mode == 2) ? "Ycc" :
277 ((s.rgam_lut_mode == 3) ? "RAM" :
278 ((s.rgam_lut_mode == 4) ? "RAM" :
281 s.gamut_remap_c11_c12,
282 s.gamut_remap_c13_c14,
283 s.gamut_remap_c21_c22,
284 s.gamut_remap_c23_c24,
285 s.gamut_remap_c31_c32,
286 s.gamut_remap_c33_c34);
291 DTN_INFO("MPCC: OPP DPP MPCCBOT MODE ALPHA_MODE PREMULT OVERLAP_ONLY IDLE\n");
292 for (i = 0; i < pool->pipe_count; i++) {
293 struct mpcc_state s = {0};
295 pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s);
297 DTN_INFO("[%2d]: %2xh %2xh %6xh %4d %10d %7d %12d %4d\n",
298 i, s.opp_id, s.dpp_id, s.bot_mpcc_id,
299 s.mode, s.alpha_mode, s.pre_multiplied_alpha, s.overlap_only,
304 DTN_INFO("OTG: v_bs v_be v_ss v_se vpol vmax vmin vmax_sel vmin_sel"
305 " h_bs h_be h_ss h_se hpol htot vtot underflow\n");
307 for (i = 0; i < pool->timing_generator_count; i++) {
308 struct timing_generator *tg = pool->timing_generators[i];
309 struct dcn_otg_state s = {0};
311 optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s);
313 //only print if OTG master is enabled
314 if ((s.otg_enabled & 1) == 0)
317 DTN_INFO("[%d]: %5d %5d %5d %5d %5d %5d %5d %9d %9d %5d %5d %5d"
318 " %5d %5d %5d %5d %9d\n",
336 s.underflow_occurred_status);
338 // Clear underflow for debug purposes
339 // We want to keep underflow sticky bit on for the longevity tests outside of test environment.
340 // This function is called only from Windows or Diags test environment, hence it's safe to clear
341 // it from here without affecting the original intent.
342 tg->funcs->clear_optc_underflow(tg);
346 DTN_INFO("\nCALCULATED Clocks: dcfclk_khz:%d dcfclk_deep_sleep_khz:%d dispclk_khz:%d\n"
347 "dppclk_khz:%d max_supported_dppclk_khz:%d fclk_khz:%d socclk_khz:%d\n\n",
348 dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_khz,
349 dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz,
350 dc->current_state->bw_ctx.bw.dcn.clk.dispclk_khz,
351 dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz,
352 dc->current_state->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz,
353 dc->current_state->bw_ctx.bw.dcn.clk.fclk_khz,
354 dc->current_state->bw_ctx.bw.dcn.clk.socclk_khz);
356 log_mpc_crc(dc, log_ctx);
361 static void enable_power_gating_plane(
362 struct dce_hwseq *hws,
365 bool force_on = 1; /* disable power gating */
371 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on);
372 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on);
373 REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on);
374 REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on);
377 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on);
378 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on);
379 REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on);
380 REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);
383 static void disable_vga(
384 struct dce_hwseq *hws)
386 unsigned int in_vga1_mode = 0;
387 unsigned int in_vga2_mode = 0;
388 unsigned int in_vga3_mode = 0;
389 unsigned int in_vga4_mode = 0;
391 REG_GET(D1VGA_CONTROL, D1VGA_MODE_ENABLE, &in_vga1_mode);
392 REG_GET(D2VGA_CONTROL, D2VGA_MODE_ENABLE, &in_vga2_mode);
393 REG_GET(D3VGA_CONTROL, D3VGA_MODE_ENABLE, &in_vga3_mode);
394 REG_GET(D4VGA_CONTROL, D4VGA_MODE_ENABLE, &in_vga4_mode);
396 if (in_vga1_mode == 0 && in_vga2_mode == 0 &&
397 in_vga3_mode == 0 && in_vga4_mode == 0)
400 REG_WRITE(D1VGA_CONTROL, 0);
401 REG_WRITE(D2VGA_CONTROL, 0);
402 REG_WRITE(D3VGA_CONTROL, 0);
403 REG_WRITE(D4VGA_CONTROL, 0);
405 /* HW Engineer's Notes:
406 * During switch from vga->extended, if we set the VGA_TEST_ENABLE and
407 * then hit the VGA_TEST_RENDER_START, then the DCHUBP timing gets updated correctly.
409 * Then vBIOS will have it poll for the VGA_TEST_RENDER_DONE and unset
410 * VGA_TEST_ENABLE, to leave it in the same state as before.
412 REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_ENABLE, 1);
413 REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_RENDER_START, 1);
416 static void dpp_pg_control(
417 struct dce_hwseq *hws,
418 unsigned int dpp_inst,
421 uint32_t power_gate = power_on ? 0 : 1;
422 uint32_t pwr_status = power_on ? 0 : 2;
424 if (hws->ctx->dc->debug.disable_dpp_power_gate)
426 if (REG(DOMAIN1_PG_CONFIG) == 0)
431 REG_UPDATE(DOMAIN1_PG_CONFIG,
432 DOMAIN1_POWER_GATE, power_gate);
434 REG_WAIT(DOMAIN1_PG_STATUS,
435 DOMAIN1_PGFSM_PWR_STATUS, pwr_status,
439 REG_UPDATE(DOMAIN3_PG_CONFIG,
440 DOMAIN3_POWER_GATE, power_gate);
442 REG_WAIT(DOMAIN3_PG_STATUS,
443 DOMAIN3_PGFSM_PWR_STATUS, pwr_status,
447 REG_UPDATE(DOMAIN5_PG_CONFIG,
448 DOMAIN5_POWER_GATE, power_gate);
450 REG_WAIT(DOMAIN5_PG_STATUS,
451 DOMAIN5_PGFSM_PWR_STATUS, pwr_status,
455 REG_UPDATE(DOMAIN7_PG_CONFIG,
456 DOMAIN7_POWER_GATE, power_gate);
458 REG_WAIT(DOMAIN7_PG_STATUS,
459 DOMAIN7_PGFSM_PWR_STATUS, pwr_status,
468 static void hubp_pg_control(
469 struct dce_hwseq *hws,
470 unsigned int hubp_inst,
473 uint32_t power_gate = power_on ? 0 : 1;
474 uint32_t pwr_status = power_on ? 0 : 2;
476 if (hws->ctx->dc->debug.disable_hubp_power_gate)
478 if (REG(DOMAIN0_PG_CONFIG) == 0)
482 case 0: /* DCHUBP0 */
483 REG_UPDATE(DOMAIN0_PG_CONFIG,
484 DOMAIN0_POWER_GATE, power_gate);
486 REG_WAIT(DOMAIN0_PG_STATUS,
487 DOMAIN0_PGFSM_PWR_STATUS, pwr_status,
490 case 1: /* DCHUBP1 */
491 REG_UPDATE(DOMAIN2_PG_CONFIG,
492 DOMAIN2_POWER_GATE, power_gate);
494 REG_WAIT(DOMAIN2_PG_STATUS,
495 DOMAIN2_PGFSM_PWR_STATUS, pwr_status,
498 case 2: /* DCHUBP2 */
499 REG_UPDATE(DOMAIN4_PG_CONFIG,
500 DOMAIN4_POWER_GATE, power_gate);
502 REG_WAIT(DOMAIN4_PG_STATUS,
503 DOMAIN4_PGFSM_PWR_STATUS, pwr_status,
506 case 3: /* DCHUBP3 */
507 REG_UPDATE(DOMAIN6_PG_CONFIG,
508 DOMAIN6_POWER_GATE, power_gate);
510 REG_WAIT(DOMAIN6_PG_STATUS,
511 DOMAIN6_PGFSM_PWR_STATUS, pwr_status,
520 static void power_on_plane(
521 struct dce_hwseq *hws,
524 DC_LOGGER_INIT(hws->ctx->logger);
525 if (REG(DC_IP_REQUEST_CNTL)) {
526 REG_SET(DC_IP_REQUEST_CNTL, 0,
528 dpp_pg_control(hws, plane_id, true);
529 hubp_pg_control(hws, plane_id, true);
530 REG_SET(DC_IP_REQUEST_CNTL, 0,
533 "Un-gated front end for pipe %d\n", plane_id);
537 static void undo_DEGVIDCN10_253_wa(struct dc *dc)
539 struct dce_hwseq *hws = dc->hwseq;
540 struct hubp *hubp = dc->res_pool->hubps[0];
542 if (!hws->wa_state.DEGVIDCN10_253_applied)
545 hubp->funcs->set_blank(hubp, true);
547 REG_SET(DC_IP_REQUEST_CNTL, 0,
550 hubp_pg_control(hws, 0, false);
551 REG_SET(DC_IP_REQUEST_CNTL, 0,
554 hws->wa_state.DEGVIDCN10_253_applied = false;
557 static void apply_DEGVIDCN10_253_wa(struct dc *dc)
559 struct dce_hwseq *hws = dc->hwseq;
560 struct hubp *hubp = dc->res_pool->hubps[0];
563 if (dc->debug.disable_stutter)
566 if (!hws->wa.DEGVIDCN10_253)
569 for (i = 0; i < dc->res_pool->pipe_count; i++) {
570 if (!dc->res_pool->hubps[i]->power_gated)
574 /* all pipe power gated, apply work around to enable stutter. */
576 REG_SET(DC_IP_REQUEST_CNTL, 0,
579 hubp_pg_control(hws, 0, true);
580 REG_SET(DC_IP_REQUEST_CNTL, 0,
583 hubp->funcs->set_hubp_blank_en(hubp, false);
584 hws->wa_state.DEGVIDCN10_253_applied = true;
587 static void bios_golden_init(struct dc *dc)
589 struct dc_bios *bp = dc->ctx->dc_bios;
592 /* initialize dcn global */
593 bp->funcs->enable_disp_power_gating(bp,
594 CONTROLLER_ID_D0, ASIC_PIPE_INIT);
596 for (i = 0; i < dc->res_pool->pipe_count; i++) {
597 /* initialize dcn per pipe */
598 bp->funcs->enable_disp_power_gating(bp,
599 CONTROLLER_ID_D0 + i, ASIC_PIPE_DISABLE);
603 static void false_optc_underflow_wa(
605 const struct dc_stream_state *stream,
606 struct timing_generator *tg)
611 if (!dc->hwseq->wa.false_optc_underflow)
614 underflow = tg->funcs->is_optc_underflow_occurred(tg);
616 for (i = 0; i < dc->res_pool->pipe_count; i++) {
617 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
619 if (old_pipe_ctx->stream != stream)
622 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, old_pipe_ctx);
625 tg->funcs->set_blank_data_double_buffer(tg, true);
627 if (tg->funcs->is_optc_underflow_occurred(tg) && !underflow)
628 tg->funcs->clear_optc_underflow(tg);
631 static enum dc_status dcn10_enable_stream_timing(
632 struct pipe_ctx *pipe_ctx,
633 struct dc_state *context,
636 struct dc_stream_state *stream = pipe_ctx->stream;
637 enum dc_color_space color_space;
638 struct tg_color black_color = {0};
640 /* by upper caller loop, pipe0 is parent pipe and be called first.
641 * back end is set up by for pipe0. Other children pipe share back end
642 * with pipe 0. No program is needed.
644 if (pipe_ctx->top_pipe != NULL)
647 /* TODO check if timing_changed, disable stream if timing changed */
649 /* HW program guide assume display already disable
650 * by unplug sequence. OTG assume stop.
652 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true);
654 if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
655 pipe_ctx->clock_source,
656 &pipe_ctx->stream_res.pix_clk_params,
657 &pipe_ctx->pll_settings)) {
659 return DC_ERROR_UNEXPECTED;
662 pipe_ctx->stream_res.tg->funcs->program_timing(
663 pipe_ctx->stream_res.tg,
665 pipe_ctx->pipe_dlg_param.vready_offset,
666 pipe_ctx->pipe_dlg_param.vstartup_start,
667 pipe_ctx->pipe_dlg_param.vupdate_offset,
668 pipe_ctx->pipe_dlg_param.vupdate_width,
669 pipe_ctx->stream->signal,
672 #if 0 /* move to after enable_crtc */
673 /* TODO: OPP FMT, ABM. etc. should be done here. */
674 /* or FPGA now. instance 0 only. TODO: move to opp.c */
676 inst_offset = reg_offsets[pipe_ctx->stream_res.tg->inst].fmt;
678 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
679 pipe_ctx->stream_res.opp,
680 &stream->bit_depth_params,
683 /* program otg blank color */
684 color_space = stream->output_color_space;
685 color_space_to_black_color(dc, color_space, &black_color);
687 if (pipe_ctx->stream_res.tg->funcs->set_blank_color)
688 pipe_ctx->stream_res.tg->funcs->set_blank_color(
689 pipe_ctx->stream_res.tg,
692 if (pipe_ctx->stream_res.tg->funcs->is_blanked &&
693 !pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg)) {
694 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);
695 hwss_wait_for_blank_complete(pipe_ctx->stream_res.tg);
696 false_optc_underflow_wa(dc, pipe_ctx->stream, pipe_ctx->stream_res.tg);
699 /* VTG is within DCHUB command block. DCFCLK is always on */
700 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {
702 return DC_ERROR_UNEXPECTED;
705 /* TODO program crtc source select for non-virtual signal*/
706 /* TODO program FMT */
707 /* TODO setup link_enc */
708 /* TODO set stream attributes */
709 /* TODO program audio */
710 /* TODO enable stream if timing changed */
711 /* TODO unblank stream if DP */
716 static void dcn10_reset_back_end_for_pipe(
718 struct pipe_ctx *pipe_ctx,
719 struct dc_state *context)
722 DC_LOGGER_INIT(dc->ctx->logger);
723 if (pipe_ctx->stream_res.stream_enc == NULL) {
724 pipe_ctx->stream = NULL;
728 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
729 /* DPMS may already disable */
730 if (!pipe_ctx->stream->dpms_off)
731 core_link_disable_stream(pipe_ctx, FREE_ACQUIRED_RESOURCE);
732 else if (pipe_ctx->stream_res.audio) {
733 dc->hwss.disable_audio_stream(pipe_ctx, FREE_ACQUIRED_RESOURCE);
738 /* by upper caller loop, parent pipe: pipe0, will be reset last.
739 * back end share by all pipes and will be disable only when disable
742 if (pipe_ctx->top_pipe == NULL) {
743 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
745 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
748 for (i = 0; i < dc->res_pool->pipe_count; i++)
749 if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx)
752 if (i == dc->res_pool->pipe_count)
755 pipe_ctx->stream = NULL;
756 DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n",
757 pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
760 static bool dcn10_hw_wa_force_recovery(struct dc *dc)
764 bool need_recover = true;
766 if (!dc->debug.recovery_enabled)
769 for (i = 0; i < dc->res_pool->pipe_count; i++) {
770 struct pipe_ctx *pipe_ctx =
771 &dc->current_state->res_ctx.pipe_ctx[i];
772 if (pipe_ctx != NULL) {
773 hubp = pipe_ctx->plane_res.hubp;
774 if (hubp != NULL && hubp->funcs->hubp_get_underflow_status) {
775 if (hubp->funcs->hubp_get_underflow_status(hubp) != 0) {
776 /* one pipe underflow, we will reset all the pipes*/
785 DCHUBP_CNTL:HUBP_BLANK_EN=1
786 DCHUBBUB_SOFT_RESET:DCHUBBUB_GLOBAL_SOFT_RESET=1
787 DCHUBP_CNTL:HUBP_DISABLE=1
788 DCHUBP_CNTL:HUBP_DISABLE=0
789 DCHUBBUB_SOFT_RESET:DCHUBBUB_GLOBAL_SOFT_RESET=0
790 DCSURF_PRIMARY_SURFACE_ADDRESS
791 DCHUBP_CNTL:HUBP_BLANK_EN=0
794 for (i = 0; i < dc->res_pool->pipe_count; i++) {
795 struct pipe_ctx *pipe_ctx =
796 &dc->current_state->res_ctx.pipe_ctx[i];
797 if (pipe_ctx != NULL) {
798 hubp = pipe_ctx->plane_res.hubp;
799 /*DCHUBP_CNTL:HUBP_BLANK_EN=1*/
800 if (hubp != NULL && hubp->funcs->set_hubp_blank_en)
801 hubp->funcs->set_hubp_blank_en(hubp, true);
804 /*DCHUBBUB_SOFT_RESET:DCHUBBUB_GLOBAL_SOFT_RESET=1*/
805 hubbub1_soft_reset(dc->res_pool->hubbub, true);
807 for (i = 0; i < dc->res_pool->pipe_count; i++) {
808 struct pipe_ctx *pipe_ctx =
809 &dc->current_state->res_ctx.pipe_ctx[i];
810 if (pipe_ctx != NULL) {
811 hubp = pipe_ctx->plane_res.hubp;
812 /*DCHUBP_CNTL:HUBP_DISABLE=1*/
813 if (hubp != NULL && hubp->funcs->hubp_disable_control)
814 hubp->funcs->hubp_disable_control(hubp, true);
817 for (i = 0; i < dc->res_pool->pipe_count; i++) {
818 struct pipe_ctx *pipe_ctx =
819 &dc->current_state->res_ctx.pipe_ctx[i];
820 if (pipe_ctx != NULL) {
821 hubp = pipe_ctx->plane_res.hubp;
822 /*DCHUBP_CNTL:HUBP_DISABLE=0*/
823 if (hubp != NULL && hubp->funcs->hubp_disable_control)
824 hubp->funcs->hubp_disable_control(hubp, true);
827 /*DCHUBBUB_SOFT_RESET:DCHUBBUB_GLOBAL_SOFT_RESET=0*/
828 hubbub1_soft_reset(dc->res_pool->hubbub, false);
829 for (i = 0; i < dc->res_pool->pipe_count; i++) {
830 struct pipe_ctx *pipe_ctx =
831 &dc->current_state->res_ctx.pipe_ctx[i];
832 if (pipe_ctx != NULL) {
833 hubp = pipe_ctx->plane_res.hubp;
834 /*DCHUBP_CNTL:HUBP_BLANK_EN=0*/
835 if (hubp != NULL && hubp->funcs->set_hubp_blank_en)
836 hubp->funcs->set_hubp_blank_en(hubp, true);
844 void dcn10_verify_allow_pstate_change_high(struct dc *dc)
846 static bool should_log_hw_state; /* prevent hw state log by default */
848 if (!hubbub1_verify_allow_pstate_change_high(dc->res_pool->hubbub)) {
849 if (should_log_hw_state) {
850 dcn10_log_hw_state(dc, NULL);
853 if (dcn10_hw_wa_force_recovery(dc)) {
855 if (!hubbub1_verify_allow_pstate_change_high(dc->res_pool->hubbub))
861 /* trigger HW to start disconnect plane from stream on the next vsync */
862 void hwss1_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx)
864 struct hubp *hubp = pipe_ctx->plane_res.hubp;
865 int dpp_id = pipe_ctx->plane_res.dpp->inst;
866 struct mpc *mpc = dc->res_pool->mpc;
867 struct mpc_tree *mpc_tree_params;
868 struct mpcc *mpcc_to_remove = NULL;
869 struct output_pixel_processor *opp = pipe_ctx->stream_res.opp;
871 mpc_tree_params = &(opp->mpc_tree_params);
872 mpcc_to_remove = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, dpp_id);
875 if (mpcc_to_remove == NULL)
878 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, mpcc_to_remove);
880 opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
882 dc->optimized_required = true;
884 if (hubp->funcs->hubp_disconnect)
885 hubp->funcs->hubp_disconnect(hubp);
887 if (dc->debug.sanity_checks)
888 dcn10_verify_allow_pstate_change_high(dc);
891 static void plane_atomic_power_down(struct dc *dc,
895 struct dce_hwseq *hws = dc->hwseq;
896 DC_LOGGER_INIT(dc->ctx->logger);
898 if (REG(DC_IP_REQUEST_CNTL)) {
899 REG_SET(DC_IP_REQUEST_CNTL, 0,
901 dpp_pg_control(hws, dpp->inst, false);
902 hubp_pg_control(hws, hubp->inst, false);
903 dpp->funcs->dpp_reset(dpp);
904 REG_SET(DC_IP_REQUEST_CNTL, 0,
907 "Power gated front end %d\n", hubp->inst);
911 /* disable HW used by plane.
912 * note: cannot disable until disconnect is complete
914 static void plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
916 struct hubp *hubp = pipe_ctx->plane_res.hubp;
917 struct dpp *dpp = pipe_ctx->plane_res.dpp;
918 int opp_id = hubp->opp_id;
920 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);
922 hubp->funcs->hubp_clk_cntl(hubp, false);
924 dpp->funcs->dpp_dppclk_control(dpp, false, false);
926 if (opp_id != 0xf && pipe_ctx->stream_res.opp->mpc_tree_params.opp_list == NULL)
927 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
928 pipe_ctx->stream_res.opp,
931 hubp->power_gated = true;
932 dc->optimized_required = false; /* We're powering off, no need to optimize */
934 plane_atomic_power_down(dc,
935 pipe_ctx->plane_res.dpp,
936 pipe_ctx->plane_res.hubp);
938 pipe_ctx->stream = NULL;
939 memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res));
940 memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res));
941 pipe_ctx->top_pipe = NULL;
942 pipe_ctx->bottom_pipe = NULL;
943 pipe_ctx->plane_state = NULL;
946 static void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
948 DC_LOGGER_INIT(dc->ctx->logger);
950 if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)
953 plane_atomic_disable(dc, pipe_ctx);
955 apply_DEGVIDCN10_253_wa(dc);
957 DC_LOG_DC("Power down front end %d\n",
961 static void dcn10_init_pipes(struct dc *dc, struct dc_state *context)
964 bool can_apply_seamless_boot = false;
966 for (i = 0; i < context->stream_count; i++) {
967 if (context->streams[i]->apply_seamless_boot_optimization) {
968 can_apply_seamless_boot = true;
973 for (i = 0; i < dc->res_pool->pipe_count; i++) {
974 struct timing_generator *tg = dc->res_pool->timing_generators[i];
975 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
977 /* There is assumption that pipe_ctx is not mapping irregularly
978 * to non-preferred front end. If pipe_ctx->stream is not NULL,
979 * we will use the pipe, so don't disable
981 if (pipe_ctx->stream != NULL && can_apply_seamless_boot)
984 /* Blank controller using driver code instead of
987 if (tg->funcs->is_tg_enabled(tg)) {
989 tg->funcs->set_blank(tg, true);
990 hwss_wait_for_blank_complete(tg);
994 /* Cannot reset the MPC mux if seamless boot */
995 if (!can_apply_seamless_boot)
996 dc->res_pool->mpc->funcs->mpc_init(dc->res_pool->mpc);
998 for (i = 0; i < dc->res_pool->pipe_count; i++) {
999 struct timing_generator *tg = dc->res_pool->timing_generators[i];
1000 struct hubp *hubp = dc->res_pool->hubps[i];
1001 struct dpp *dpp = dc->res_pool->dpps[i];
1002 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1004 /* There is assumption that pipe_ctx is not mapping irregularly
1005 * to non-preferred front end. If pipe_ctx->stream is not NULL,
1006 * we will use the pipe, so don't disable
1008 if (can_apply_seamless_boot &&
1009 pipe_ctx->stream != NULL &&
1010 pipe_ctx->stream_res.tg->funcs->is_tg_enabled(
1011 pipe_ctx->stream_res.tg))
1014 /* Disable on the current state so the new one isn't cleared. */
1015 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
1017 dpp->funcs->dpp_reset(dpp);
1019 pipe_ctx->stream_res.tg = tg;
1020 pipe_ctx->pipe_idx = i;
1022 pipe_ctx->plane_res.hubp = hubp;
1023 pipe_ctx->plane_res.dpp = dpp;
1024 pipe_ctx->plane_res.mpcc_inst = dpp->inst;
1025 hubp->mpcc_id = dpp->inst;
1027 hubp->power_gated = false;
1029 dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
1030 dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
1031 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
1032 pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
1034 hwss1_plane_atomic_disconnect(dc, pipe_ctx);
1036 if (tg->funcs->is_tg_enabled(tg))
1037 tg->funcs->unlock(tg);
1039 dcn10_disable_plane(dc, pipe_ctx);
1041 pipe_ctx->stream_res.tg = NULL;
1042 pipe_ctx->plane_res.hubp = NULL;
1044 tg->funcs->tg_init(tg);
1048 static void dcn10_init_hw(struct dc *dc)
1051 struct abm *abm = dc->res_pool->abm;
1052 struct dmcu *dmcu = dc->res_pool->dmcu;
1053 struct dce_hwseq *hws = dc->hwseq;
1054 struct dc_bios *dcb = dc->ctx->dc_bios;
1056 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
1057 REG_WRITE(REFCLK_CNTL, 0);
1058 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
1059 REG_WRITE(DIO_MEM_PWR_CTRL, 0);
1061 if (!dc->debug.disable_clock_gate) {
1062 /* enable all DCN clock gating */
1063 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
1065 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
1067 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
1070 enable_power_gating_plane(dc->hwseq, true);
1072 /* end of FPGA. Below if real ASIC */
1076 if (!dcb->funcs->is_accelerated_mode(dcb)) {
1077 bool allow_self_fresh_force_enable =
1078 hububu1_is_allow_self_refresh_enabled(
1079 dc->res_pool->hubbub);
1081 bios_golden_init(dc);
1083 /* WA for making DF sleep when idle after resume from S0i3.
1084 * DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE is set to 1 by
1085 * command table, if DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE = 0
1086 * before calling command table and it changed to 1 after,
1087 * it should be set back to 0.
1089 if (allow_self_fresh_force_enable == false &&
1090 hububu1_is_allow_self_refresh_enabled(dc->res_pool->hubbub))
1091 hubbub1_allow_self_refresh_control(dc->res_pool->hubbub, true);
1093 disable_vga(dc->hwseq);
1096 for (i = 0; i < dc->link_count; i++) {
1097 /* Power up AND update implementation according to the
1098 * required signal (which may be different from the
1099 * default signal on connector).
1101 struct dc_link *link = dc->links[i];
1103 if (link->link_enc->connector.id == CONNECTOR_ID_EDP)
1104 dc->hwss.edp_power_control(link, true);
1106 link->link_enc->funcs->hw_init(link->link_enc);
1108 /* Check for enabled DIG to identify enabled display */
1109 if (link->link_enc->funcs->is_dig_enabled &&
1110 link->link_enc->funcs->is_dig_enabled(link->link_enc))
1111 link->link_status.link_active = true;
1114 /* If taking control over from VBIOS, we may want to optimize our first
1115 * mode set, so we need to skip powering down pipes until we know which
1116 * pipes we want to use.
1117 * Otherwise, if taking control is not possible, we need to power
1120 if (dcb->funcs->is_accelerated_mode(dcb) || dc->config.power_down_display_on_boot) {
1121 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1122 struct hubp *hubp = dc->res_pool->hubps[i];
1123 struct dpp *dpp = dc->res_pool->dpps[i];
1125 hubp->funcs->hubp_init(hubp);
1126 dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
1127 plane_atomic_power_down(dc, dpp, hubp);
1130 apply_DEGVIDCN10_253_wa(dc);
1133 for (i = 0; i < dc->res_pool->audio_count; i++) {
1134 struct audio *audio = dc->res_pool->audios[i];
1136 audio->funcs->hw_init(audio);
1140 abm->funcs->init_backlight(abm);
1141 abm->funcs->abm_init(abm);
1145 dmcu->funcs->dmcu_init(dmcu);
1147 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/
1148 REG_WRITE(DIO_MEM_PWR_CTRL, 0);
1150 if (!dc->debug.disable_clock_gate) {
1151 /* enable all DCN clock gating */
1152 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
1154 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
1156 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
1159 enable_power_gating_plane(dc->hwseq, true);
1161 memset(&dc->res_pool->clk_mgr->clks, 0, sizeof(dc->res_pool->clk_mgr->clks));
1164 static void dcn10_reset_hw_ctx_wrap(
1166 struct dc_state *context)
1171 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
1172 struct pipe_ctx *pipe_ctx_old =
1173 &dc->current_state->res_ctx.pipe_ctx[i];
1174 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1176 if (!pipe_ctx_old->stream)
1179 if (pipe_ctx_old->top_pipe)
1182 if (!pipe_ctx->stream ||
1183 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
1184 struct clock_source *old_clk = pipe_ctx_old->clock_source;
1186 dcn10_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
1187 if (dc->hwss.enable_stream_gating)
1188 dc->hwss.enable_stream_gating(dc, pipe_ctx);
1190 old_clk->funcs->cs_power_down(old_clk);
1195 static bool patch_address_for_sbs_tb_stereo(
1196 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr)
1198 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1199 bool sec_split = pipe_ctx->top_pipe &&
1200 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
1201 if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
1202 (pipe_ctx->stream->timing.timing_3d_format ==
1203 TIMING_3D_FORMAT_SIDE_BY_SIDE ||
1204 pipe_ctx->stream->timing.timing_3d_format ==
1205 TIMING_3D_FORMAT_TOP_AND_BOTTOM)) {
1206 *addr = plane_state->address.grph_stereo.left_addr;
1207 plane_state->address.grph_stereo.left_addr =
1208 plane_state->address.grph_stereo.right_addr;
1211 if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE &&
1212 plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) {
1213 plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO;
1214 plane_state->address.grph_stereo.right_addr =
1215 plane_state->address.grph_stereo.left_addr;
1223 static void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)
1225 bool addr_patched = false;
1226 PHYSICAL_ADDRESS_LOC addr;
1227 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1229 if (plane_state == NULL)
1232 addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);
1234 pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(
1235 pipe_ctx->plane_res.hubp,
1236 &plane_state->address,
1237 plane_state->flip_immediate,
1240 plane_state->status.requested_address = plane_state->address;
1242 if (plane_state->flip_immediate)
1243 plane_state->status.current_address = plane_state->address;
1246 pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;
1249 static bool dcn10_set_input_transfer_func(struct pipe_ctx *pipe_ctx,
1250 const struct dc_plane_state *plane_state)
1252 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
1253 const struct dc_transfer_func *tf = NULL;
1256 if (dpp_base == NULL)
1259 if (plane_state->in_transfer_func)
1260 tf = plane_state->in_transfer_func;
1262 if (plane_state->gamma_correction &&
1263 !dpp_base->ctx->dc->debug.always_use_regamma
1264 && !plane_state->gamma_correction->is_identity
1265 && dce_use_lut(plane_state->format))
1266 dpp_base->funcs->dpp_program_input_lut(dpp_base, plane_state->gamma_correction);
1269 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
1270 else if (tf->type == TF_TYPE_PREDEFINED) {
1272 case TRANSFER_FUNCTION_SRGB:
1273 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_sRGB);
1275 case TRANSFER_FUNCTION_BT709:
1276 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_xvYCC);
1278 case TRANSFER_FUNCTION_LINEAR:
1279 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
1281 case TRANSFER_FUNCTION_PQ:
1286 } else if (tf->type == TF_TYPE_BYPASS) {
1287 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
1289 cm_helper_translate_curve_to_degamma_hw_format(tf,
1290 &dpp_base->degamma_params);
1291 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base,
1292 &dpp_base->degamma_params);
1304 dcn10_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
1305 const struct dc_stream_state *stream)
1307 struct dpp *dpp = pipe_ctx->plane_res.dpp;
1312 dpp->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
1314 if (stream->out_transfer_func &&
1315 stream->out_transfer_func->type == TF_TYPE_PREDEFINED &&
1316 stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB)
1317 dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_SRGB);
1319 /* dcn10_translate_regamma_to_hw_format takes 750us, only do it when full
1322 else if (cm_helper_translate_curve_to_hw_format(
1323 stream->out_transfer_func,
1324 &dpp->regamma_params, false)) {
1325 dpp->funcs->dpp_program_regamma_pwl(
1327 &dpp->regamma_params, OPP_REGAMMA_USER);
1329 dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_BYPASS);
1334 static void dcn10_pipe_control_lock(
1336 struct pipe_ctx *pipe,
1339 /* use TG master update lock to lock everything on the TG
1340 * therefore only top pipe need to lock
1345 if (dc->debug.sanity_checks)
1346 dcn10_verify_allow_pstate_change_high(dc);
1349 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);
1351 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);
1353 if (dc->debug.sanity_checks)
1354 dcn10_verify_allow_pstate_change_high(dc);
1357 static bool wait_for_reset_trigger_to_occur(
1358 struct dc_context *dc_ctx,
1359 struct timing_generator *tg)
1363 /* To avoid endless loop we wait at most
1364 * frames_to_wait_on_triggered_reset frames for the reset to occur. */
1365 const uint32_t frames_to_wait_on_triggered_reset = 10;
1368 for (i = 0; i < frames_to_wait_on_triggered_reset; i++) {
1370 if (!tg->funcs->is_counter_moving(tg)) {
1371 DC_ERROR("TG counter is not moving!\n");
1375 if (tg->funcs->did_triggered_reset_occur(tg)) {
1377 /* usually occurs at i=1 */
1378 DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",
1383 /* Wait for one frame. */
1384 tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);
1385 tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
1389 DC_ERROR("GSL: Timeout on reset trigger!\n");
1394 static void dcn10_enable_timing_synchronization(
1398 struct pipe_ctx *grouped_pipes[])
1400 struct dc_context *dc_ctx = dc->ctx;
1403 DC_SYNC_INFO("Setting up OTG reset trigger\n");
1405 for (i = 1; i < group_size; i++)
1406 grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger(
1407 grouped_pipes[i]->stream_res.tg,
1408 grouped_pipes[0]->stream_res.tg->inst);
1410 DC_SYNC_INFO("Waiting for trigger\n");
1412 /* Need to get only check 1 pipe for having reset as all the others are
1413 * synchronized. Look at last pipe programmed to reset.
1416 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[1]->stream_res.tg);
1417 for (i = 1; i < group_size; i++)
1418 grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(
1419 grouped_pipes[i]->stream_res.tg);
1421 DC_SYNC_INFO("Sync complete\n");
1424 static void dcn10_enable_per_frame_crtc_position_reset(
1427 struct pipe_ctx *grouped_pipes[])
1429 struct dc_context *dc_ctx = dc->ctx;
1432 DC_SYNC_INFO("Setting up\n");
1433 for (i = 0; i < group_size; i++)
1434 if (grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset)
1435 grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset(
1436 grouped_pipes[i]->stream_res.tg,
1438 &grouped_pipes[i]->stream->triggered_crtc_reset);
1440 DC_SYNC_INFO("Waiting for trigger\n");
1442 for (i = 0; i < group_size; i++)
1443 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
1445 DC_SYNC_INFO("Multi-display sync is complete\n");
1448 /*static void print_rq_dlg_ttu(
1450 struct pipe_ctx *pipe_ctx)
1452 DC_LOG_BANDWIDTH_CALCS(core_dc->ctx->logger,
1453 "\n============== DML TTU Output parameters [%d] ==============\n"
1454 "qos_level_low_wm: %d, \n"
1455 "qos_level_high_wm: %d, \n"
1456 "min_ttu_vblank: %d, \n"
1457 "qos_level_flip: %d, \n"
1458 "refcyc_per_req_delivery_l: %d, \n"
1459 "qos_level_fixed_l: %d, \n"
1460 "qos_ramp_disable_l: %d, \n"
1461 "refcyc_per_req_delivery_pre_l: %d, \n"
1462 "refcyc_per_req_delivery_c: %d, \n"
1463 "qos_level_fixed_c: %d, \n"
1464 "qos_ramp_disable_c: %d, \n"
1465 "refcyc_per_req_delivery_pre_c: %d\n"
1466 "=============================================================\n",
1468 pipe_ctx->ttu_regs.qos_level_low_wm,
1469 pipe_ctx->ttu_regs.qos_level_high_wm,
1470 pipe_ctx->ttu_regs.min_ttu_vblank,
1471 pipe_ctx->ttu_regs.qos_level_flip,
1472 pipe_ctx->ttu_regs.refcyc_per_req_delivery_l,
1473 pipe_ctx->ttu_regs.qos_level_fixed_l,
1474 pipe_ctx->ttu_regs.qos_ramp_disable_l,
1475 pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_l,
1476 pipe_ctx->ttu_regs.refcyc_per_req_delivery_c,
1477 pipe_ctx->ttu_regs.qos_level_fixed_c,
1478 pipe_ctx->ttu_regs.qos_ramp_disable_c,
1479 pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_c
1482 DC_LOG_BANDWIDTH_CALCS(core_dc->ctx->logger,
1483 "\n============== DML DLG Output parameters [%d] ==============\n"
1484 "refcyc_h_blank_end: %d, \n"
1485 "dlg_vblank_end: %d, \n"
1486 "min_dst_y_next_start: %d, \n"
1487 "refcyc_per_htotal: %d, \n"
1488 "refcyc_x_after_scaler: %d, \n"
1489 "dst_y_after_scaler: %d, \n"
1490 "dst_y_prefetch: %d, \n"
1491 "dst_y_per_vm_vblank: %d, \n"
1492 "dst_y_per_row_vblank: %d, \n"
1493 "ref_freq_to_pix_freq: %d, \n"
1494 "vratio_prefetch: %d, \n"
1495 "refcyc_per_pte_group_vblank_l: %d, \n"
1496 "refcyc_per_meta_chunk_vblank_l: %d, \n"
1497 "dst_y_per_pte_row_nom_l: %d, \n"
1498 "refcyc_per_pte_group_nom_l: %d, \n",
1500 pipe_ctx->dlg_regs.refcyc_h_blank_end,
1501 pipe_ctx->dlg_regs.dlg_vblank_end,
1502 pipe_ctx->dlg_regs.min_dst_y_next_start,
1503 pipe_ctx->dlg_regs.refcyc_per_htotal,
1504 pipe_ctx->dlg_regs.refcyc_x_after_scaler,
1505 pipe_ctx->dlg_regs.dst_y_after_scaler,
1506 pipe_ctx->dlg_regs.dst_y_prefetch,
1507 pipe_ctx->dlg_regs.dst_y_per_vm_vblank,
1508 pipe_ctx->dlg_regs.dst_y_per_row_vblank,
1509 pipe_ctx->dlg_regs.ref_freq_to_pix_freq,
1510 pipe_ctx->dlg_regs.vratio_prefetch,
1511 pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_l,
1512 pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_l,
1513 pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_l,
1514 pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_l
1517 DC_LOG_BANDWIDTH_CALCS(core_dc->ctx->logger,
1518 "\ndst_y_per_meta_row_nom_l: %d, \n"
1519 "refcyc_per_meta_chunk_nom_l: %d, \n"
1520 "refcyc_per_line_delivery_pre_l: %d, \n"
1521 "refcyc_per_line_delivery_l: %d, \n"
1522 "vratio_prefetch_c: %d, \n"
1523 "refcyc_per_pte_group_vblank_c: %d, \n"
1524 "refcyc_per_meta_chunk_vblank_c: %d, \n"
1525 "dst_y_per_pte_row_nom_c: %d, \n"
1526 "refcyc_per_pte_group_nom_c: %d, \n"
1527 "dst_y_per_meta_row_nom_c: %d, \n"
1528 "refcyc_per_meta_chunk_nom_c: %d, \n"
1529 "refcyc_per_line_delivery_pre_c: %d, \n"
1530 "refcyc_per_line_delivery_c: %d \n"
1531 "========================================================\n",
1532 pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_l,
1533 pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_l,
1534 pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_l,
1535 pipe_ctx->dlg_regs.refcyc_per_line_delivery_l,
1536 pipe_ctx->dlg_regs.vratio_prefetch_c,
1537 pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_c,
1538 pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_c,
1539 pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_c,
1540 pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_c,
1541 pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_c,
1542 pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_c,
1543 pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_c,
1544 pipe_ctx->dlg_regs.refcyc_per_line_delivery_c
1547 DC_LOG_BANDWIDTH_CALCS(core_dc->ctx->logger,
1548 "\n============== DML RQ Output parameters [%d] ==============\n"
1550 "min_chunk_size: %d \n"
1551 "meta_chunk_size: %d \n"
1552 "min_meta_chunk_size: %d \n"
1553 "dpte_group_size: %d \n"
1554 "mpte_group_size: %d \n"
1555 "swath_height: %d \n"
1556 "pte_row_height_linear: %d \n"
1557 "========================================================\n",
1559 pipe_ctx->rq_regs.rq_regs_l.chunk_size,
1560 pipe_ctx->rq_regs.rq_regs_l.min_chunk_size,
1561 pipe_ctx->rq_regs.rq_regs_l.meta_chunk_size,
1562 pipe_ctx->rq_regs.rq_regs_l.min_meta_chunk_size,
1563 pipe_ctx->rq_regs.rq_regs_l.dpte_group_size,
1564 pipe_ctx->rq_regs.rq_regs_l.mpte_group_size,
1565 pipe_ctx->rq_regs.rq_regs_l.swath_height,
1566 pipe_ctx->rq_regs.rq_regs_l.pte_row_height_linear
1571 static void mmhub_read_vm_system_aperture_settings(struct dcn10_hubp *hubp1,
1572 struct vm_system_aperture_param *apt,
1573 struct dce_hwseq *hws)
1575 PHYSICAL_ADDRESS_LOC physical_page_number;
1576 uint32_t logical_addr_low;
1577 uint32_t logical_addr_high;
1579 REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
1580 PHYSICAL_PAGE_NUMBER_MSB, &physical_page_number.high_part);
1581 REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
1582 PHYSICAL_PAGE_NUMBER_LSB, &physical_page_number.low_part);
1584 REG_GET(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1585 LOGICAL_ADDR, &logical_addr_low);
1587 REG_GET(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1588 LOGICAL_ADDR, &logical_addr_high);
1590 apt->sys_default.quad_part = physical_page_number.quad_part << 12;
1591 apt->sys_low.quad_part = (int64_t)logical_addr_low << 18;
1592 apt->sys_high.quad_part = (int64_t)logical_addr_high << 18;
1595 /* Temporary read settings, future will get values from kmd directly */
1596 static void mmhub_read_vm_context0_settings(struct dcn10_hubp *hubp1,
1597 struct vm_context0_param *vm0,
1598 struct dce_hwseq *hws)
1600 PHYSICAL_ADDRESS_LOC fb_base;
1601 PHYSICAL_ADDRESS_LOC fb_offset;
1602 uint32_t fb_base_value;
1603 uint32_t fb_offset_value;
1605 REG_GET(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, &fb_base_value);
1606 REG_GET(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, &fb_offset_value);
1608 REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
1609 PAGE_DIRECTORY_ENTRY_HI32, &vm0->pte_base.high_part);
1610 REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
1611 PAGE_DIRECTORY_ENTRY_LO32, &vm0->pte_base.low_part);
1613 REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
1614 LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_start.high_part);
1615 REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
1616 LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_start.low_part);
1618 REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
1619 LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_end.high_part);
1620 REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
1621 LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_end.low_part);
1623 REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
1624 PHYSICAL_PAGE_ADDR_HI4, &vm0->fault_default.high_part);
1625 REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
1626 PHYSICAL_PAGE_ADDR_LO32, &vm0->fault_default.low_part);
1629 * The values in VM_CONTEXT0_PAGE_TABLE_BASE_ADDR is in UMA space.
1630 * Therefore we need to do
1631 * DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
1632 * - DCHUBBUB_SDPIF_FB_OFFSET + DCHUBBUB_SDPIF_FB_BASE
1634 fb_base.quad_part = (uint64_t)fb_base_value << 24;
1635 fb_offset.quad_part = (uint64_t)fb_offset_value << 24;
1636 vm0->pte_base.quad_part += fb_base.quad_part;
1637 vm0->pte_base.quad_part -= fb_offset.quad_part;
1641 void dcn10_program_pte_vm(struct dce_hwseq *hws, struct hubp *hubp)
1643 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
1644 struct vm_system_aperture_param apt = { {{ 0 } } };
1645 struct vm_context0_param vm0 = { { { 0 } } };
1647 mmhub_read_vm_system_aperture_settings(hubp1, &apt, hws);
1648 mmhub_read_vm_context0_settings(hubp1, &vm0, hws);
1650 hubp->funcs->hubp_set_vm_system_aperture_settings(hubp, &apt);
1651 hubp->funcs->hubp_set_vm_context0_settings(hubp, &vm0);
1654 static void dcn10_enable_plane(
1656 struct pipe_ctx *pipe_ctx,
1657 struct dc_state *context)
1659 struct dce_hwseq *hws = dc->hwseq;
1661 if (dc->debug.sanity_checks) {
1662 dcn10_verify_allow_pstate_change_high(dc);
1665 undo_DEGVIDCN10_253_wa(dc);
1667 power_on_plane(dc->hwseq,
1668 pipe_ctx->plane_res.hubp->inst);
1670 /* enable DCFCLK current DCHUB */
1671 pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);
1673 /* make sure OPP_PIPE_CLOCK_EN = 1 */
1674 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
1675 pipe_ctx->stream_res.opp,
1678 /* TODO: enable/disable in dm as per update type.
1680 DC_LOG_DC(dc->ctx->logger,
1681 "Pipe:%d 0x%x: addr hi:0x%x, "
1684 " %d; dst: %d, %d, %d, %d;\n",
1687 plane_state->address.grph.addr.high_part,
1688 plane_state->address.grph.addr.low_part,
1689 plane_state->src_rect.x,
1690 plane_state->src_rect.y,
1691 plane_state->src_rect.width,
1692 plane_state->src_rect.height,
1693 plane_state->dst_rect.x,
1694 plane_state->dst_rect.y,
1695 plane_state->dst_rect.width,
1696 plane_state->dst_rect.height);
1698 DC_LOG_DC(dc->ctx->logger,
1699 "Pipe %d: width, height, x, y format:%d\n"
1700 "viewport:%d, %d, %d, %d\n"
1701 "recout: %d, %d, %d, %d\n",
1703 plane_state->format,
1704 pipe_ctx->plane_res.scl_data.viewport.width,
1705 pipe_ctx->plane_res.scl_data.viewport.height,
1706 pipe_ctx->plane_res.scl_data.viewport.x,
1707 pipe_ctx->plane_res.scl_data.viewport.y,
1708 pipe_ctx->plane_res.scl_data.recout.width,
1709 pipe_ctx->plane_res.scl_data.recout.height,
1710 pipe_ctx->plane_res.scl_data.recout.x,
1711 pipe_ctx->plane_res.scl_data.recout.y);
1712 print_rq_dlg_ttu(dc, pipe_ctx);
1715 if (dc->config.gpu_vm_support)
1716 dcn10_program_pte_vm(hws, pipe_ctx->plane_res.hubp);
1718 if (dc->debug.sanity_checks) {
1719 dcn10_verify_allow_pstate_change_high(dc);
1723 static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
1726 struct dpp_grph_csc_adjustment adjust;
1727 memset(&adjust, 0, sizeof(adjust));
1728 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
1731 if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
1732 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
1733 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
1734 adjust.temperature_matrix[i] =
1735 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
1738 pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp, &adjust);
1741 static void dcn10_program_output_csc(struct dc *dc,
1742 struct pipe_ctx *pipe_ctx,
1743 enum dc_color_space colorspace,
1747 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
1748 if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment != NULL)
1749 pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, matrix);
1751 if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default != NULL)
1752 pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default(pipe_ctx->plane_res.dpp, colorspace);
1756 bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
1758 if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible)
1760 if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
1765 bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
1767 if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible)
1769 if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
1774 bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
1776 if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible)
1778 if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
1780 if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
1785 bool is_rgb_cspace(enum dc_color_space output_color_space)
1787 switch (output_color_space) {
1788 case COLOR_SPACE_SRGB:
1789 case COLOR_SPACE_SRGB_LIMITED:
1790 case COLOR_SPACE_2020_RGB_FULLRANGE:
1791 case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
1792 case COLOR_SPACE_ADOBERGB:
1794 case COLOR_SPACE_YCBCR601:
1795 case COLOR_SPACE_YCBCR709:
1796 case COLOR_SPACE_YCBCR601_LIMITED:
1797 case COLOR_SPACE_YCBCR709_LIMITED:
1798 case COLOR_SPACE_2020_YCBCR:
1801 /* Add a case to switch */
1802 BREAK_TO_DEBUGGER();
1807 void dcn10_get_surface_visual_confirm_color(
1808 const struct pipe_ctx *pipe_ctx,
1809 struct tg_color *color)
1811 uint32_t color_value = MAX_TG_COLOR_VALUE;
1813 switch (pipe_ctx->plane_res.scl_data.format) {
1814 case PIXEL_FORMAT_ARGB8888:
1815 /* set boarder color to red */
1816 color->color_r_cr = color_value;
1819 case PIXEL_FORMAT_ARGB2101010:
1820 /* set boarder color to blue */
1821 color->color_b_cb = color_value;
1823 case PIXEL_FORMAT_420BPP8:
1824 /* set boarder color to green */
1825 color->color_g_y = color_value;
1827 case PIXEL_FORMAT_420BPP10:
1828 /* set boarder color to yellow */
1829 color->color_g_y = color_value;
1830 color->color_r_cr = color_value;
1832 case PIXEL_FORMAT_FP16:
1833 /* set boarder color to white */
1834 color->color_r_cr = color_value;
1835 color->color_b_cb = color_value;
1836 color->color_g_y = color_value;
1843 void dcn10_get_hdr_visual_confirm_color(
1844 struct pipe_ctx *pipe_ctx,
1845 struct tg_color *color)
1847 uint32_t color_value = MAX_TG_COLOR_VALUE;
1849 // Determine the overscan color based on the top-most (desktop) plane's context
1850 struct pipe_ctx *top_pipe_ctx = pipe_ctx;
1852 while (top_pipe_ctx->top_pipe != NULL)
1853 top_pipe_ctx = top_pipe_ctx->top_pipe;
1855 switch (top_pipe_ctx->plane_res.scl_data.format) {
1856 case PIXEL_FORMAT_ARGB2101010:
1857 if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_PQ) {
1858 /* HDR10, ARGB2101010 - set boarder color to red */
1859 color->color_r_cr = color_value;
1862 case PIXEL_FORMAT_FP16:
1863 if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_PQ) {
1864 /* HDR10, FP16 - set boarder color to blue */
1865 color->color_b_cb = color_value;
1866 } else if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22) {
1867 /* FreeSync 2 HDR - set boarder color to green */
1868 color->color_g_y = color_value;
1872 /* SDR - set boarder color to Gray */
1873 color->color_r_cr = color_value/2;
1874 color->color_b_cb = color_value/2;
1875 color->color_g_y = color_value/2;
1880 static uint16_t fixed_point_to_int_frac(
1881 struct fixed31_32 arg,
1882 uint8_t integer_bits,
1883 uint8_t fractional_bits)
1886 int32_t divisor = 1 << fractional_bits;
1890 uint16_t d = (uint16_t)dc_fixpt_floor(
1894 if (d <= (uint16_t)(1 << integer_bits) - (1 / (uint16_t)divisor))
1895 numerator = (uint16_t)dc_fixpt_floor(
1900 numerator = dc_fixpt_floor(
1903 1LL << integer_bits),
1910 result = (uint16_t)numerator;
1912 result = (uint16_t)(
1913 (1 << (integer_bits + fractional_bits + 1)) + numerator);
1915 if ((result != 0) && dc_fixpt_lt(
1916 arg, dc_fixpt_zero))
1917 result |= 1 << (integer_bits + fractional_bits);
1922 void dcn10_build_prescale_params(struct dc_bias_and_scale *bias_and_scale,
1923 const struct dc_plane_state *plane_state)
1925 if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
1926 && plane_state->format != SURFACE_PIXEL_FORMAT_INVALID
1927 && plane_state->input_csc_color_matrix.enable_adjustment
1928 && plane_state->coeff_reduction_factor.value != 0) {
1929 bias_and_scale->scale_blue = fixed_point_to_int_frac(
1930 dc_fixpt_mul(plane_state->coeff_reduction_factor,
1931 dc_fixpt_from_fraction(256, 255)),
1934 bias_and_scale->scale_red = bias_and_scale->scale_blue;
1935 bias_and_scale->scale_green = bias_and_scale->scale_blue;
1937 bias_and_scale->scale_blue = 0x2000;
1938 bias_and_scale->scale_red = 0x2000;
1939 bias_and_scale->scale_green = 0x2000;
1943 static void update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state)
1945 struct dc_bias_and_scale bns_params = {0};
1947 // program the input csc
1948 dpp->funcs->dpp_setup(dpp,
1949 plane_state->format,
1950 EXPANSION_MODE_ZERO,
1951 plane_state->input_csc_color_matrix,
1952 plane_state->color_space);
1954 //set scale and bias registers
1955 dcn10_build_prescale_params(&bns_params, plane_state);
1956 if (dpp->funcs->dpp_program_bias_and_scale)
1957 dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
1960 static void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
1962 struct hubp *hubp = pipe_ctx->plane_res.hubp;
1963 struct mpcc_blnd_cfg blnd_cfg = {{0}};
1964 bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
1966 struct mpcc *new_mpcc;
1967 struct mpc *mpc = dc->res_pool->mpc;
1968 struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);
1970 if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) {
1971 dcn10_get_hdr_visual_confirm_color(
1972 pipe_ctx, &blnd_cfg.black_color);
1973 } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) {
1974 dcn10_get_surface_visual_confirm_color(
1975 pipe_ctx, &blnd_cfg.black_color);
1977 color_space_to_black_color(
1978 dc, pipe_ctx->stream->output_color_space,
1979 &blnd_cfg.black_color);
1982 if (per_pixel_alpha)
1983 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;
1985 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA;
1987 blnd_cfg.overlap_only = false;
1988 blnd_cfg.global_gain = 0xff;
1990 if (pipe_ctx->plane_state->global_alpha)
1991 blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value;
1993 blnd_cfg.global_alpha = 0xff;
1995 /* DCN1.0 has output CM before MPC which seems to screw with
1996 * pre-multiplied alpha.
1998 blnd_cfg.pre_multiplied_alpha = is_rgb_cspace(
1999 pipe_ctx->stream->output_color_space)
2005 * Note: currently there is a bug in init_hw such that
2006 * on resume from hibernate, BIOS sets up MPCC0, and
2007 * we do mpcc_remove but the mpcc cannot go to idle
2008 * after remove. This cause us to pick mpcc1 here,
2009 * which causes a pstate hang for yet unknown reason.
2011 mpcc_id = hubp->inst;
2013 /* If there is no full update, don't need to touch MPC tree*/
2014 if (!pipe_ctx->plane_state->update_flags.bits.full_update) {
2015 mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id);
2019 /* check if this MPCC is already being used */
2020 new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id);
2021 /* remove MPCC if being used */
2022 if (new_mpcc != NULL)
2023 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc);
2025 if (dc->debug.sanity_checks)
2026 mpc->funcs->assert_mpcc_idle_before_connect(
2027 dc->res_pool->mpc, mpcc_id);
2029 /* Call MPC to insert new plane */
2030 new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,
2038 ASSERT(new_mpcc != NULL);
2040 hubp->opp_id = pipe_ctx->stream_res.opp->inst;
2041 hubp->mpcc_id = mpcc_id;
2044 static void update_scaler(struct pipe_ctx *pipe_ctx)
2046 bool per_pixel_alpha =
2047 pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
2049 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = per_pixel_alpha;
2050 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
2051 /* scaler configuration */
2052 pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(
2053 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);
2056 void update_dchubp_dpp(
2058 struct pipe_ctx *pipe_ctx,
2059 struct dc_state *context)
2061 struct hubp *hubp = pipe_ctx->plane_res.hubp;
2062 struct dpp *dpp = pipe_ctx->plane_res.dpp;
2063 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2064 union plane_size size = plane_state->plane_size;
2065 unsigned int compat_level = 0;
2067 /* depends on DML calculation, DPP clock value may change dynamically */
2068 /* If request max dpp clk is lower than current dispclk, no need to
2071 if (plane_state->update_flags.bits.full_update) {
2072 bool should_divided_by_2 = context->bw_ctx.bw.dcn.clk.dppclk_khz <=
2073 dc->res_pool->clk_mgr->clks.dispclk_khz / 2;
2075 dpp->funcs->dpp_dppclk_control(
2077 should_divided_by_2,
2080 if (dc->res_pool->dccg)
2081 dc->res_pool->dccg->funcs->update_dpp_dto(
2084 pipe_ctx->plane_res.bw.dppclk_khz);
2086 dc->res_pool->clk_mgr->clks.dppclk_khz = should_divided_by_2 ?
2087 dc->res_pool->clk_mgr->clks.dispclk_khz / 2 :
2088 dc->res_pool->clk_mgr->clks.dispclk_khz;
2091 /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG
2092 * VTG is within DCHUBBUB which is commond block share by each pipe HUBP.
2093 * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG
2095 if (plane_state->update_flags.bits.full_update) {
2096 hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst);
2098 hubp->funcs->hubp_setup(
2100 &pipe_ctx->dlg_regs,
2101 &pipe_ctx->ttu_regs,
2103 &pipe_ctx->pipe_dlg_param);
2104 hubp->funcs->hubp_setup_interdependent(
2106 &pipe_ctx->dlg_regs,
2107 &pipe_ctx->ttu_regs);
2110 size.grph.surface_size = pipe_ctx->plane_res.scl_data.viewport;
2112 if (plane_state->update_flags.bits.full_update ||
2113 plane_state->update_flags.bits.bpp_change)
2114 update_dpp(dpp, plane_state);
2116 if (plane_state->update_flags.bits.full_update ||
2117 plane_state->update_flags.bits.per_pixel_alpha_change ||
2118 plane_state->update_flags.bits.global_alpha_change)
2119 dc->hwss.update_mpcc(dc, pipe_ctx);
2121 if (plane_state->update_flags.bits.full_update ||
2122 plane_state->update_flags.bits.per_pixel_alpha_change ||
2123 plane_state->update_flags.bits.global_alpha_change ||
2124 plane_state->update_flags.bits.scaling_change ||
2125 plane_state->update_flags.bits.position_change) {
2126 update_scaler(pipe_ctx);
2129 if (plane_state->update_flags.bits.full_update ||
2130 plane_state->update_flags.bits.scaling_change ||
2131 plane_state->update_flags.bits.position_change) {
2132 hubp->funcs->mem_program_viewport(
2134 &pipe_ctx->plane_res.scl_data.viewport,
2135 &pipe_ctx->plane_res.scl_data.viewport_c);
2138 if (pipe_ctx->stream->cursor_attributes.address.quad_part != 0) {
2139 dc->hwss.set_cursor_position(pipe_ctx);
2140 dc->hwss.set_cursor_attribute(pipe_ctx);
2142 if (dc->hwss.set_cursor_sdr_white_level)
2143 dc->hwss.set_cursor_sdr_white_level(pipe_ctx);
2146 if (plane_state->update_flags.bits.full_update) {
2148 program_gamut_remap(pipe_ctx);
2150 dc->hwss.program_output_csc(dc,
2152 pipe_ctx->stream->output_color_space,
2153 pipe_ctx->stream->csc_color_matrix.matrix,
2157 if (plane_state->update_flags.bits.full_update ||
2158 plane_state->update_flags.bits.pixel_format_change ||
2159 plane_state->update_flags.bits.horizontal_mirror_change ||
2160 plane_state->update_flags.bits.rotation_change ||
2161 plane_state->update_flags.bits.swizzle_change ||
2162 plane_state->update_flags.bits.dcc_change ||
2163 plane_state->update_flags.bits.bpp_change ||
2164 plane_state->update_flags.bits.scaling_change ||
2165 plane_state->update_flags.bits.plane_size_change) {
2166 hubp->funcs->hubp_program_surface_config(
2168 plane_state->format,
2169 &plane_state->tiling_info,
2171 plane_state->rotation,
2173 plane_state->horizontal_mirror,
2177 hubp->power_gated = false;
2179 dc->hwss.update_plane_addr(dc, pipe_ctx);
2181 if (is_pipe_tree_visible(pipe_ctx))
2182 hubp->funcs->set_blank(hubp, false);
2185 static void dcn10_blank_pixel_data(
2187 struct pipe_ctx *pipe_ctx,
2190 enum dc_color_space color_space;
2191 struct tg_color black_color = {0};
2192 struct stream_resource *stream_res = &pipe_ctx->stream_res;
2193 struct dc_stream_state *stream = pipe_ctx->stream;
2195 /* program otg blank color */
2196 color_space = stream->output_color_space;
2197 color_space_to_black_color(dc, color_space, &black_color);
2200 * The way 420 is packed, 2 channels carry Y component, 1 channel
2201 * alternate between Cb and Cr, so both channels need the pixel
2204 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
2205 black_color.color_r_cr = black_color.color_g_y;
2208 if (stream_res->tg->funcs->set_blank_color)
2209 stream_res->tg->funcs->set_blank_color(
2214 if (stream_res->tg->funcs->set_blank)
2215 stream_res->tg->funcs->set_blank(stream_res->tg, blank);
2216 if (stream_res->abm) {
2217 stream_res->abm->funcs->set_pipe(stream_res->abm, stream_res->tg->inst + 1);
2218 stream_res->abm->funcs->set_abm_level(stream_res->abm, stream->abm_level);
2221 if (stream_res->abm)
2222 stream_res->abm->funcs->set_abm_immediate_disable(stream_res->abm);
2223 if (stream_res->tg->funcs->set_blank)
2224 stream_res->tg->funcs->set_blank(stream_res->tg, blank);
2228 void set_hdr_multiplier(struct pipe_ctx *pipe_ctx)
2230 struct fixed31_32 multiplier = dc_fixpt_from_fraction(
2231 pipe_ctx->plane_state->sdr_white_level, 80);
2232 uint32_t hw_mult = 0x1f000; // 1.0 default multiplier
2233 struct custom_float_format fmt;
2235 fmt.exponenta_bits = 6;
2236 fmt.mantissa_bits = 12;
2239 if (pipe_ctx->plane_state->sdr_white_level > 80)
2240 convert_to_custom_float_format(multiplier, &fmt, &hw_mult);
2242 pipe_ctx->plane_res.dpp->funcs->dpp_set_hdr_multiplier(
2243 pipe_ctx->plane_res.dpp, hw_mult);
2246 void dcn10_program_pipe(
2248 struct pipe_ctx *pipe_ctx,
2249 struct dc_state *context)
2251 if (pipe_ctx->plane_state->update_flags.bits.full_update)
2252 dcn10_enable_plane(dc, pipe_ctx, context);
2254 update_dchubp_dpp(dc, pipe_ctx, context);
2256 set_hdr_multiplier(pipe_ctx);
2258 if (pipe_ctx->plane_state->update_flags.bits.full_update ||
2259 pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
2260 pipe_ctx->plane_state->update_flags.bits.gamma_change)
2261 dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state);
2263 /* dcn10_translate_regamma_to_hw_format takes 750us to finish
2264 * only do gamma programming for full update.
2265 * TODO: This can be further optimized/cleaned up
2266 * Always call this for now since it does memcmp inside before
2267 * doing heavy calculation and programming
2269 if (pipe_ctx->plane_state->update_flags.bits.full_update)
2270 dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);
2273 static void program_all_pipe_in_tree(
2275 struct pipe_ctx *pipe_ctx,
2276 struct dc_state *context)
2278 if (pipe_ctx->top_pipe == NULL) {
2279 bool blank = !is_pipe_tree_visible(pipe_ctx);
2281 pipe_ctx->stream_res.tg->funcs->program_global_sync(
2282 pipe_ctx->stream_res.tg,
2283 pipe_ctx->pipe_dlg_param.vready_offset,
2284 pipe_ctx->pipe_dlg_param.vstartup_start,
2285 pipe_ctx->pipe_dlg_param.vupdate_offset,
2286 pipe_ctx->pipe_dlg_param.vupdate_width);
2288 pipe_ctx->stream_res.tg->funcs->set_vtg_params(
2289 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
2291 dc->hwss.blank_pixel_data(dc, pipe_ctx, blank);
2295 if (pipe_ctx->plane_state != NULL)
2296 dcn10_program_pipe(dc, pipe_ctx, context);
2298 if (pipe_ctx->bottom_pipe != NULL && pipe_ctx->bottom_pipe != pipe_ctx)
2299 program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context);
2302 struct pipe_ctx *find_top_pipe_for_stream(
2304 struct dc_state *context,
2305 const struct dc_stream_state *stream)
2309 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2310 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2311 struct pipe_ctx *old_pipe_ctx =
2312 &dc->current_state->res_ctx.pipe_ctx[i];
2314 if (!pipe_ctx->plane_state && !old_pipe_ctx->plane_state)
2317 if (pipe_ctx->stream != stream)
2320 if (!pipe_ctx->top_pipe)
2326 static void dcn10_apply_ctx_for_surface(
2328 const struct dc_stream_state *stream,
2330 struct dc_state *context)
2333 struct timing_generator *tg;
2334 bool removed_pipe[4] = { false };
2335 bool interdependent_update = false;
2336 struct pipe_ctx *top_pipe_to_program =
2337 find_top_pipe_for_stream(dc, context, stream);
2338 DC_LOGGER_INIT(dc->ctx->logger);
2340 if (!top_pipe_to_program)
2343 tg = top_pipe_to_program->stream_res.tg;
2345 interdependent_update = top_pipe_to_program->plane_state &&
2346 top_pipe_to_program->plane_state->update_flags.bits.full_update;
2348 if (interdependent_update)
2349 lock_all_pipes(dc, context, true);
2351 dcn10_pipe_control_lock(dc, top_pipe_to_program, true);
2353 if (num_planes == 0) {
2354 /* OTG blank before remove all front end */
2355 dc->hwss.blank_pixel_data(dc, top_pipe_to_program, true);
2358 /* Disconnect unused mpcc */
2359 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2360 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2361 struct pipe_ctx *old_pipe_ctx =
2362 &dc->current_state->res_ctx.pipe_ctx[i];
2364 * Powergate reused pipes that are not powergated
2365 * fairly hacky right now, using opp_id as indicator
2366 * TODO: After move dc_post to dc_update, this will
2369 if (pipe_ctx->plane_state && !old_pipe_ctx->plane_state) {
2370 if (old_pipe_ctx->stream_res.tg == tg &&
2371 old_pipe_ctx->plane_res.hubp &&
2372 old_pipe_ctx->plane_res.hubp->opp_id != 0xf)
2373 dcn10_disable_plane(dc, old_pipe_ctx);
2376 if ((!pipe_ctx->plane_state ||
2377 pipe_ctx->stream_res.tg != old_pipe_ctx->stream_res.tg) &&
2378 old_pipe_ctx->plane_state &&
2379 old_pipe_ctx->stream_res.tg == tg) {
2381 dc->hwss.plane_atomic_disconnect(dc, old_pipe_ctx);
2382 removed_pipe[i] = true;
2384 DC_LOG_DC("Reset mpcc for pipe %d\n",
2385 old_pipe_ctx->pipe_idx);
2390 program_all_pipe_in_tree(dc, top_pipe_to_program, context);
2392 if (interdependent_update)
2393 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2394 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2395 /* Skip inactive pipes and ones already updated */
2396 if (!pipe_ctx->stream || pipe_ctx->stream == stream ||
2397 !pipe_ctx->plane_state || !tg->funcs->is_tg_enabled(tg))
2400 pipe_ctx->plane_res.hubp->funcs->hubp_setup_interdependent(
2401 pipe_ctx->plane_res.hubp,
2402 &pipe_ctx->dlg_regs,
2403 &pipe_ctx->ttu_regs);
2406 if (interdependent_update)
2407 lock_all_pipes(dc, context, false);
2409 dcn10_pipe_control_lock(dc, top_pipe_to_program, false);
2411 if (num_planes == 0)
2412 false_optc_underflow_wa(dc, stream, tg);
2414 for (i = 0; i < dc->res_pool->pipe_count; i++)
2415 if (removed_pipe[i])
2416 dcn10_disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
2418 if (dc->hwseq->wa.DEGVIDCN10_254)
2419 hubbub1_wm_change_req_wa(dc->res_pool->hubbub);
2422 static void dcn10_stereo_hw_frame_pack_wa(struct dc *dc, struct dc_state *context)
2426 for (i = 0; i < context->stream_count; i++) {
2427 if (context->streams[i]->timing.timing_3d_format
2428 == TIMING_3D_FORMAT_HW_FRAME_PACKING) {
2432 hubbub1_allow_self_refresh_control(dc->res_pool->hubbub, false);
2438 static void dcn10_prepare_bandwidth(
2440 struct dc_state *context)
2442 struct hubbub *hubbub = dc->res_pool->hubbub;
2444 if (dc->debug.sanity_checks)
2445 dcn10_verify_allow_pstate_change_high(dc);
2447 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
2448 if (context->stream_count == 0)
2449 context->bw_ctx.bw.dcn.clk.phyclk_khz = 0;
2451 dc->res_pool->clk_mgr->funcs->update_clocks(
2452 dc->res_pool->clk_mgr,
2457 hubbub->funcs->program_watermarks(hubbub,
2458 &context->bw_ctx.bw.dcn.watermarks,
2459 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
2461 dcn10_stereo_hw_frame_pack_wa(dc, context);
2463 if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE)
2464 dcn_bw_notify_pplib_of_wm_ranges(dc);
2466 if (dc->debug.sanity_checks)
2467 dcn10_verify_allow_pstate_change_high(dc);
2470 static void dcn10_optimize_bandwidth(
2472 struct dc_state *context)
2474 struct hubbub *hubbub = dc->res_pool->hubbub;
2476 if (dc->debug.sanity_checks)
2477 dcn10_verify_allow_pstate_change_high(dc);
2479 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
2480 if (context->stream_count == 0)
2481 context->bw_ctx.bw.dcn.clk.phyclk_khz = 0;
2483 dc->res_pool->clk_mgr->funcs->update_clocks(
2484 dc->res_pool->clk_mgr,
2489 hubbub->funcs->program_watermarks(hubbub,
2490 &context->bw_ctx.bw.dcn.watermarks,
2491 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
2493 dcn10_stereo_hw_frame_pack_wa(dc, context);
2495 if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE)
2496 dcn_bw_notify_pplib_of_wm_ranges(dc);
2498 if (dc->debug.sanity_checks)
2499 dcn10_verify_allow_pstate_change_high(dc);
2502 static void set_drr(struct pipe_ctx **pipe_ctx,
2503 int num_pipes, int vmin, int vmax)
2506 struct drr_params params = {0};
2507 // DRR should set trigger event to monitor surface update event
2508 unsigned int event_triggers = 0x80;
2510 params.vertical_total_max = vmax;
2511 params.vertical_total_min = vmin;
2513 /* TODO: If multiple pipes are to be supported, you need
2514 * some GSL stuff. Static screen triggers may be programmed differently
2517 for (i = 0; i < num_pipes; i++) {
2518 pipe_ctx[i]->stream_res.tg->funcs->set_drr(
2519 pipe_ctx[i]->stream_res.tg, ¶ms);
2520 if (vmax != 0 && vmin != 0)
2521 pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control(
2522 pipe_ctx[i]->stream_res.tg,
2527 static void get_position(struct pipe_ctx **pipe_ctx,
2529 struct crtc_position *position)
2533 /* TODO: handle pipes > 1
2535 for (i = 0; i < num_pipes; i++)
2536 pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);
2539 static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
2540 int num_pipes, const struct dc_static_screen_events *events)
2543 unsigned int value = 0;
2545 if (events->surface_update)
2547 if (events->cursor_update)
2549 if (events->force_trigger)
2552 for (i = 0; i < num_pipes; i++)
2553 pipe_ctx[i]->stream_res.tg->funcs->
2554 set_static_screen_control(pipe_ctx[i]->stream_res.tg, value);
2557 static void dcn10_config_stereo_parameters(
2558 struct dc_stream_state *stream, struct crtc_stereo_flags *flags)
2560 enum view_3d_format view_format = stream->view_format;
2561 enum dc_timing_3d_format timing_3d_format =\
2562 stream->timing.timing_3d_format;
2563 bool non_stereo_timing = false;
2565 if (timing_3d_format == TIMING_3D_FORMAT_NONE ||
2566 timing_3d_format == TIMING_3D_FORMAT_SIDE_BY_SIDE ||
2567 timing_3d_format == TIMING_3D_FORMAT_TOP_AND_BOTTOM)
2568 non_stereo_timing = true;
2570 if (non_stereo_timing == false &&
2571 view_format == VIEW_3D_FORMAT_FRAME_SEQUENTIAL) {
2573 flags->PROGRAM_STEREO = 1;
2574 flags->PROGRAM_POLARITY = 1;
2575 if (timing_3d_format == TIMING_3D_FORMAT_INBAND_FA ||
2576 timing_3d_format == TIMING_3D_FORMAT_DP_HDMI_INBAND_FA ||
2577 timing_3d_format == TIMING_3D_FORMAT_SIDEBAND_FA) {
2578 enum display_dongle_type dongle = \
2579 stream->link->ddc->dongle_type;
2580 if (dongle == DISPLAY_DONGLE_DP_VGA_CONVERTER ||
2581 dongle == DISPLAY_DONGLE_DP_DVI_CONVERTER ||
2582 dongle == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
2583 flags->DISABLE_STEREO_DP_SYNC = 1;
2585 flags->RIGHT_EYE_POLARITY =\
2586 stream->timing.flags.RIGHT_EYE_3D_POLARITY;
2587 if (timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
2588 flags->FRAME_PACKED = 1;
2594 static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc)
2596 struct crtc_stereo_flags flags = { 0 };
2597 struct dc_stream_state *stream = pipe_ctx->stream;
2599 dcn10_config_stereo_parameters(stream, &flags);
2601 pipe_ctx->stream_res.opp->funcs->opp_program_stereo(
2602 pipe_ctx->stream_res.opp,
2603 flags.PROGRAM_STEREO == 1 ? true:false,
2606 pipe_ctx->stream_res.tg->funcs->program_stereo(
2607 pipe_ctx->stream_res.tg,
2614 static struct hubp *get_hubp_by_inst(struct resource_pool *res_pool, int mpcc_inst)
2618 for (i = 0; i < res_pool->pipe_count; i++) {
2619 if (res_pool->hubps[i]->inst == mpcc_inst)
2620 return res_pool->hubps[i];
2626 static void dcn10_wait_for_mpcc_disconnect(
2628 struct resource_pool *res_pool,
2629 struct pipe_ctx *pipe_ctx)
2633 if (dc->debug.sanity_checks) {
2634 dcn10_verify_allow_pstate_change_high(dc);
2637 if (!pipe_ctx->stream_res.opp)
2640 for (mpcc_inst = 0; mpcc_inst < MAX_PIPES; mpcc_inst++) {
2641 if (pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst]) {
2642 struct hubp *hubp = get_hubp_by_inst(res_pool, mpcc_inst);
2644 res_pool->mpc->funcs->wait_for_idle(res_pool->mpc, mpcc_inst);
2645 pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst] = false;
2646 hubp->funcs->set_blank(hubp, true);
2650 if (dc->debug.sanity_checks) {
2651 dcn10_verify_allow_pstate_change_high(dc);
2656 static bool dcn10_dummy_display_power_gating(
2658 uint8_t controller_id,
2659 struct dc_bios *dcb,
2660 enum pipe_gating_control power_gating)
2665 static void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx)
2667 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2668 struct timing_generator *tg = pipe_ctx->stream_res.tg;
2671 if (plane_state == NULL)
2674 flip_pending = pipe_ctx->plane_res.hubp->funcs->hubp_is_flip_pending(
2675 pipe_ctx->plane_res.hubp);
2677 plane_state->status.is_flip_pending = plane_state->status.is_flip_pending || flip_pending;
2680 plane_state->status.current_address = plane_state->status.requested_address;
2682 if (plane_state->status.current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2683 tg->funcs->is_stereo_left_eye) {
2684 plane_state->status.is_right_eye =
2685 !tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);
2689 static void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data)
2691 if (hws->ctx->dc->res_pool->hubbub != NULL) {
2692 struct hubp *hubp = hws->ctx->dc->res_pool->hubps[0];
2694 if (hubp->funcs->hubp_update_dchub)
2695 hubp->funcs->hubp_update_dchub(hubp, dh_data);
2697 hubbub1_update_dchub(hws->ctx->dc->res_pool->hubbub, dh_data);
2701 static void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)
2703 struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;
2704 struct hubp *hubp = pipe_ctx->plane_res.hubp;
2705 struct dpp *dpp = pipe_ctx->plane_res.dpp;
2706 struct dc_cursor_mi_param param = {
2707 .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10,
2708 .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz,
2709 .viewport = pipe_ctx->plane_res.scl_data.viewport,
2710 .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz,
2711 .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert,
2712 .rotation = pipe_ctx->plane_state->rotation,
2713 .mirror = pipe_ctx->plane_state->horizontal_mirror
2715 uint32_t x_plane = pipe_ctx->plane_state->dst_rect.x;
2716 uint32_t y_plane = pipe_ctx->plane_state->dst_rect.y;
2717 uint32_t x_offset = min(x_plane, pos_cpy.x);
2718 uint32_t y_offset = min(y_plane, pos_cpy.y);
2720 pos_cpy.x -= x_offset;
2721 pos_cpy.y -= y_offset;
2722 pos_cpy.x_hotspot += (x_plane - x_offset);
2723 pos_cpy.y_hotspot += (y_plane - y_offset);
2725 if (pipe_ctx->plane_state->address.type
2726 == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
2727 pos_cpy.enable = false;
2729 hubp->funcs->set_cursor_position(hubp, &pos_cpy, ¶m);
2730 dpp->funcs->set_cursor_position(dpp, &pos_cpy, ¶m, hubp->curs_attr.width, hubp->curs_attr.height);
2733 static void dcn10_set_cursor_attribute(struct pipe_ctx *pipe_ctx)
2735 struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;
2737 pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes(
2738 pipe_ctx->plane_res.hubp, attributes);
2739 pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes(
2740 pipe_ctx->plane_res.dpp, attributes->color_format);
2743 static void dcn10_set_cursor_sdr_white_level(struct pipe_ctx *pipe_ctx)
2745 uint32_t sdr_white_level = pipe_ctx->stream->cursor_attributes.sdr_white_level;
2746 struct fixed31_32 multiplier;
2747 struct dpp_cursor_attributes opt_attr = { 0 };
2748 uint32_t hw_scale = 0x3c00; // 1.0 default multiplier
2749 struct custom_float_format fmt;
2751 if (!pipe_ctx->plane_res.dpp->funcs->set_optional_cursor_attributes)
2754 fmt.exponenta_bits = 5;
2755 fmt.mantissa_bits = 10;
2758 if (sdr_white_level > 80) {
2759 multiplier = dc_fixpt_from_fraction(sdr_white_level, 80);
2760 convert_to_custom_float_format(multiplier, &fmt, &hw_scale);
2763 opt_attr.scale = hw_scale;
2766 pipe_ctx->plane_res.dpp->funcs->set_optional_cursor_attributes(
2767 pipe_ctx->plane_res.dpp, &opt_attr);
2771 * apply_front_porch_workaround TODO FPGA still need?
2773 * This is a workaround for a bug that has existed since R5xx and has not been
2774 * fixed keep Front porch at minimum 2 for Interlaced mode or 1 for progressive.
2776 static void apply_front_porch_workaround(
2777 struct dc_crtc_timing *timing)
2779 if (timing->flags.INTERLACE == 1) {
2780 if (timing->v_front_porch < 2)
2781 timing->v_front_porch = 2;
2783 if (timing->v_front_porch < 1)
2784 timing->v_front_porch = 1;
2788 int get_vupdate_offset_from_vsync(struct pipe_ctx *pipe_ctx)
2790 const struct dc_crtc_timing *dc_crtc_timing = &pipe_ctx->stream->timing;
2791 struct dc_crtc_timing patched_crtc_timing;
2792 int vesa_sync_start;
2794 int interlace_factor;
2795 int vertical_line_start;
2797 patched_crtc_timing = *dc_crtc_timing;
2798 apply_front_porch_workaround(&patched_crtc_timing);
2800 interlace_factor = patched_crtc_timing.flags.INTERLACE ? 2 : 1;
2802 vesa_sync_start = patched_crtc_timing.v_addressable +
2803 patched_crtc_timing.v_border_bottom +
2804 patched_crtc_timing.v_front_porch;
2806 asic_blank_end = (patched_crtc_timing.v_total -
2808 patched_crtc_timing.v_border_top)
2811 vertical_line_start = asic_blank_end -
2812 pipe_ctx->pipe_dlg_param.vstartup_start + 1;
2814 return vertical_line_start;
2817 void lock_all_pipes(struct dc *dc,
2818 struct dc_state *context,
2821 struct pipe_ctx *pipe_ctx;
2822 struct timing_generator *tg;
2825 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2826 pipe_ctx = &context->res_ctx.pipe_ctx[i];
2827 tg = pipe_ctx->stream_res.tg;
2829 * Only lock the top pipe's tg to prevent redundant
2830 * (un)locking. Also skip if pipe is disabled.
2832 if (pipe_ctx->top_pipe ||
2833 !pipe_ctx->stream || !pipe_ctx->plane_state ||
2834 !tg->funcs->is_tg_enabled(tg))
2838 tg->funcs->lock(tg);
2840 tg->funcs->unlock(tg);
2844 static void calc_vupdate_position(
2845 struct pipe_ctx *pipe_ctx,
2846 uint32_t *start_line,
2849 const struct dc_crtc_timing *dc_crtc_timing = &pipe_ctx->stream->timing;
2850 int vline_int_offset_from_vupdate =
2851 pipe_ctx->stream->periodic_interrupt0.lines_offset;
2852 int vupdate_offset_from_vsync = get_vupdate_offset_from_vsync(pipe_ctx);
2855 if (vline_int_offset_from_vupdate > 0)
2856 vline_int_offset_from_vupdate--;
2857 else if (vline_int_offset_from_vupdate < 0)
2858 vline_int_offset_from_vupdate++;
2860 start_position = vline_int_offset_from_vupdate + vupdate_offset_from_vsync;
2862 if (start_position >= 0)
2863 *start_line = start_position;
2865 *start_line = dc_crtc_timing->v_total + start_position - 1;
2867 *end_line = *start_line + 2;
2869 if (*end_line >= dc_crtc_timing->v_total)
2873 static void cal_vline_position(
2874 struct pipe_ctx *pipe_ctx,
2875 enum vline_select vline,
2876 uint32_t *start_line,
2879 enum vertical_interrupt_ref_point ref_point = INVALID_POINT;
2881 if (vline == VLINE0)
2882 ref_point = pipe_ctx->stream->periodic_interrupt0.ref_point;
2883 else if (vline == VLINE1)
2884 ref_point = pipe_ctx->stream->periodic_interrupt1.ref_point;
2886 switch (ref_point) {
2887 case START_V_UPDATE:
2888 calc_vupdate_position(
2894 // Suppose to do nothing because vsync is 0;
2902 static void dcn10_setup_periodic_interrupt(
2903 struct pipe_ctx *pipe_ctx,
2904 enum vline_select vline)
2906 struct timing_generator *tg = pipe_ctx->stream_res.tg;
2908 if (vline == VLINE0) {
2909 uint32_t start_line = 0;
2910 uint32_t end_line = 0;
2912 cal_vline_position(pipe_ctx, vline, &start_line, &end_line);
2914 tg->funcs->setup_vertical_interrupt0(tg, start_line, end_line);
2916 } else if (vline == VLINE1) {
2917 pipe_ctx->stream_res.tg->funcs->setup_vertical_interrupt1(
2919 pipe_ctx->stream->periodic_interrupt1.lines_offset);
2923 static void dcn10_setup_vupdate_interrupt(struct pipe_ctx *pipe_ctx)
2925 struct timing_generator *tg = pipe_ctx->stream_res.tg;
2926 int start_line = get_vupdate_offset_from_vsync(pipe_ctx);
2928 if (start_line < 0) {
2933 if (tg->funcs->setup_vertical_interrupt2)
2934 tg->funcs->setup_vertical_interrupt2(tg, start_line);
2937 static void dcn10_unblank_stream(struct pipe_ctx *pipe_ctx,
2938 struct dc_link_settings *link_settings)
2940 struct encoder_unblank_param params = { { 0 } };
2941 struct dc_stream_state *stream = pipe_ctx->stream;
2942 struct dc_link *link = stream->link;
2944 /* only 3 items below are used by unblank */
2945 params.timing = pipe_ctx->stream->timing;
2947 params.link_settings.link_rate = link_settings->link_rate;
2949 if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
2950 if (params.timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
2951 params.timing.pix_clk_100hz /= 2;
2952 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, ¶ms);
2955 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
2956 link->dc->hwss.edp_backlight_control(link, true);
2960 static void dcn10_send_immediate_sdp_message(struct pipe_ctx *pipe_ctx,
2961 const uint8_t *custom_sdp_message,
2962 unsigned int sdp_message_size)
2964 if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
2965 pipe_ctx->stream_res.stream_enc->funcs->send_immediate_sdp_message(
2966 pipe_ctx->stream_res.stream_enc,
2972 static const struct hw_sequencer_funcs dcn10_funcs = {
2973 .program_gamut_remap = program_gamut_remap,
2974 .init_hw = dcn10_init_hw,
2975 .init_pipes = dcn10_init_pipes,
2976 .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
2977 .apply_ctx_for_surface = dcn10_apply_ctx_for_surface,
2978 .update_plane_addr = dcn10_update_plane_addr,
2979 .plane_atomic_disconnect = hwss1_plane_atomic_disconnect,
2980 .update_dchub = dcn10_update_dchub,
2981 .update_mpcc = dcn10_update_mpcc,
2982 .update_pending_status = dcn10_update_pending_status,
2983 .set_input_transfer_func = dcn10_set_input_transfer_func,
2984 .set_output_transfer_func = dcn10_set_output_transfer_func,
2985 .program_output_csc = dcn10_program_output_csc,
2986 .power_down = dce110_power_down,
2987 .enable_accelerated_mode = dce110_enable_accelerated_mode,
2988 .enable_timing_synchronization = dcn10_enable_timing_synchronization,
2989 .enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,
2990 .update_info_frame = dce110_update_info_frame,
2991 .send_immediate_sdp_message = dcn10_send_immediate_sdp_message,
2992 .enable_stream = dce110_enable_stream,
2993 .disable_stream = dce110_disable_stream,
2994 .unblank_stream = dcn10_unblank_stream,
2995 .blank_stream = dce110_blank_stream,
2996 .enable_audio_stream = dce110_enable_audio_stream,
2997 .disable_audio_stream = dce110_disable_audio_stream,
2998 .enable_display_power_gating = dcn10_dummy_display_power_gating,
2999 .disable_plane = dcn10_disable_plane,
3000 .blank_pixel_data = dcn10_blank_pixel_data,
3001 .pipe_control_lock = dcn10_pipe_control_lock,
3002 .prepare_bandwidth = dcn10_prepare_bandwidth,
3003 .optimize_bandwidth = dcn10_optimize_bandwidth,
3004 .reset_hw_ctx_wrap = dcn10_reset_hw_ctx_wrap,
3005 .enable_stream_timing = dcn10_enable_stream_timing,
3007 .get_position = get_position,
3008 .set_static_screen_control = set_static_screen_control,
3009 .setup_stereo = dcn10_setup_stereo,
3010 .set_avmute = dce110_set_avmute,
3011 .log_hw_state = dcn10_log_hw_state,
3012 .get_hw_state = dcn10_get_hw_state,
3013 .clear_status_bits = dcn10_clear_status_bits,
3014 .wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
3015 .edp_backlight_control = hwss_edp_backlight_control,
3016 .edp_power_control = hwss_edp_power_control,
3017 .edp_wait_for_hpd_ready = hwss_edp_wait_for_hpd_ready,
3018 .set_cursor_position = dcn10_set_cursor_position,
3019 .set_cursor_attribute = dcn10_set_cursor_attribute,
3020 .set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,
3021 .disable_stream_gating = NULL,
3022 .enable_stream_gating = NULL,
3023 .setup_periodic_interrupt = dcn10_setup_periodic_interrupt,
3024 .setup_vupdate_interrupt = dcn10_setup_vupdate_interrupt
3028 void dcn10_hw_sequencer_construct(struct dc *dc)
3030 dc->hwss = dcn10_funcs;