drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/delay.h>
  27 #include "dm_services.h"
  28 #include "basics/dc_common.h"
  29 #include "core_types.h"
  30 #include "resource.h"
  31 #include "custom_float.h"
  32 #include "dcn10_hw_sequencer.h"
  33 #include "dcn10_hw_sequencer_debug.h"
  34 #include "dce/dce_hwseq.h"
  35 #include "abm.h"
  36 #include "dmcu.h"
  37 #include "dcn10_optc.h"
  38 #include "dcn10_dpp.h"
  39 #include "dcn10_mpc.h"
  40 #include "timing_generator.h"
  41 #include "opp.h"
  42 #include "ipp.h"
  43 #include "mpc.h"
  44 #include "reg_helper.h"
  45 #include "dcn10_hubp.h"
  46 #include "dcn10_hubbub.h"
  47 #include "dcn10_cm_common.h"
  48 #include "dc_link_dp.h"
  49 #include "dccg.h"
  50 #include "clk_mgr.h"
  51
  52
  53 #include "dsc.h"
  54
  55 #define DC_LOGGER_INIT(logger)
  56
  57 #define CTX \
  58         hws->ctx
  59 #define REG(reg)\
  60         hws->regs->reg
  61
  62 #undef FN
  63 #define FN(reg_name, field_name) \
  64         hws->shifts->field_name, hws->masks->field_name
  65
  66 /*print is 17 wide, first two characters are spaces*/
  67 #define DTN_INFO_MICRO_SEC(ref_cycle) \
  68         print_microsec(dc_ctx, log_ctx, ref_cycle)
  69
  70 #define GAMMA_HW_POINTS_NUM 256
  71
  72 void print_microsec(struct dc_context *dc_ctx,
  73         struct dc_log_buffer_ctx *log_ctx,
  74         uint32_t ref_cycle)
  75 {
  76         const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000;
  77         static const unsigned int frac = 1000;
  78         uint32_t us_x10 = (ref_cycle * frac) / ref_clk_mhz;
  79
  80         DTN_INFO("  %11d.%03d",
  81                         us_x10 / frac,
  82                         us_x10 % frac);
  83 }
  84
  85 static void dcn10_lock_all_pipes(struct dc *dc,
  86         struct dc_state *context,
  87         bool lock)
  88 {
  89         struct pipe_ctx *pipe_ctx;
  90         struct timing_generator *tg;
  91         int i;
  92
  93         for (i = 0; i < dc->res_pool->pipe_count; i++) {
  94                 pipe_ctx = &context->res_ctx.pipe_ctx[i];
  95                 tg = pipe_ctx->stream_res.tg;
  96                 /*
  97                  * Only lock the top pipe's tg to prevent redundant
  98                  * (un)locking. Also skip if pipe is disabled.
  99                  */
 100                 if (pipe_ctx->top_pipe ||
 101                     !pipe_ctx->stream || !pipe_ctx->plane_state ||
 102                     !tg->funcs->is_tg_enabled(tg))
 103                         continue;
 104
 105                 if (lock)
 106                         tg->funcs->lock(tg);
 107                 else
 108                         tg->funcs->unlock(tg);
 109         }
 110 }
 111
 112 static void log_mpc_crc(struct dc *dc,
 113         struct dc_log_buffer_ctx *log_ctx)
 114 {
 115         struct dc_context *dc_ctx = dc->ctx;
 116         struct dce_hwseq *hws = dc->hwseq;
 117
 118         if (REG(MPC_CRC_RESULT_GB))
 119                 DTN_INFO("MPC_CRC_RESULT_GB:%d MPC_CRC_RESULT_C:%d MPC_CRC_RESULT_AR:%d\n",
 120                 REG_READ(MPC_CRC_RESULT_GB), REG_READ(MPC_CRC_RESULT_C), REG_READ(MPC_CRC_RESULT_AR));
 121         if (REG(DPP_TOP0_DPP_CRC_VAL_B_A))
 122                 DTN_INFO("DPP_TOP0_DPP_CRC_VAL_B_A:%d DPP_TOP0_DPP_CRC_VAL_R_G:%d\n",
 123                 REG_READ(DPP_TOP0_DPP_CRC_VAL_B_A), REG_READ(DPP_TOP0_DPP_CRC_VAL_R_G));
 124 }
 125
 126 void dcn10_log_hubbub_state(struct dc *dc, struct dc_log_buffer_ctx *log_ctx)
 127 {
 128         struct dc_context *dc_ctx = dc->ctx;
 129         struct dcn_hubbub_wm wm;
 130         int i;
 131
 132         memset(&wm, 0, sizeof(struct dcn_hubbub_wm));
 133         dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm);
 134
 135         DTN_INFO("HUBBUB WM:      data_urgent  pte_meta_urgent"
 136                         "         sr_enter          sr_exit  dram_clk_change\n");
 137
 138         for (i = 0; i < 4; i++) {
 139                 struct dcn_hubbub_wm_set *s;
 140
 141                 s = &wm.sets[i];
 142                 DTN_INFO("WM_Set[%d]:", s->wm_set);
 143                 DTN_INFO_MICRO_SEC(s->data_urgent);
 144                 DTN_INFO_MICRO_SEC(s->pte_meta_urgent);
 145                 DTN_INFO_MICRO_SEC(s->sr_enter);
 146                 DTN_INFO_MICRO_SEC(s->sr_exit);
 147                 DTN_INFO_MICRO_SEC(s->dram_clk_chanage);
 148                 DTN_INFO("\n");
 149         }
 150
 151         DTN_INFO("\n");
 152 }
 153
 154 static void dcn10_log_hubp_states(struct dc *dc, void *log_ctx)
 155 {
 156         struct dc_context *dc_ctx = dc->ctx;
 157         struct resource_pool *pool = dc->res_pool;
 158         int i;
 159
 160         DTN_INFO(
 161                 "HUBP:  format  addr_hi  width  height  rot  mir  sw_mode  dcc_en  blank_en  clock_en  ttu_dis  underflow   min_ttu_vblank       qos_low_wm      qos_high_wm\n");
 162         for (i = 0; i < pool->pipe_count; i++) {
 163                 struct hubp *hubp = pool->hubps[i];
 164                 struct dcn_hubp_state *s = &(TO_DCN10_HUBP(hubp)->state);
 165
 166                 hubp->funcs->hubp_read_state(hubp);
 167
 168                 if (!s->blank_en) {
 169                         DTN_INFO("[%2d]:  %5xh  %6xh  %5d  %6d  %2xh  %2xh  %6xh  %6d  %8d  %8d  %7d  %8xh",
 170                                         hubp->inst,
 171                                         s->pixel_format,
 172                                         s->inuse_addr_hi,
 173                                         s->viewport_width,
 174                                         s->viewport_height,
 175                                         s->rotation_angle,
 176                                         s->h_mirror_en,
 177                                         s->sw_mode,
 178                                         s->dcc_en,
 179                                         s->blank_en,
 180                                         s->clock_en,
 181                                         s->ttu_disable,
 182                                         s->underflow_status);
 183                         DTN_INFO_MICRO_SEC(s->min_ttu_vblank);
 184                         DTN_INFO_MICRO_SEC(s->qos_level_low_wm);
 185                         DTN_INFO_MICRO_SEC(s->qos_level_high_wm);
 186                         DTN_INFO("\n");
 187                 }
 188         }
 189
 190         DTN_INFO("\n=========RQ========\n");
 191         DTN_INFO("HUBP:  drq_exp_m  prq_exp_m  mrq_exp_m  crq_exp_m  plane1_ba  L:chunk_s  min_chu_s  meta_ch_s"
 192                 "  min_m_c_s  dpte_gr_s  mpte_gr_s  swath_hei  pte_row_h  C:chunk_s  min_chu_s  meta_ch_s"
 193                 "  min_m_c_s  dpte_gr_s  mpte_gr_s  swath_hei  pte_row_h\n");
 194         for (i = 0; i < pool->pipe_count; i++) {
 195                 struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);
 196                 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;
 197
 198                 if (!s->blank_en)
 199                         DTN_INFO("[%2d]:  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh\n",
 200                                 pool->hubps[i]->inst, rq_regs->drq_expansion_mode, rq_regs->prq_expansion_mode, rq_regs->mrq_expansion_mode,
 201                                 rq_regs->crq_expansion_mode, rq_regs->plane1_base_address, rq_regs->rq_regs_l.chunk_size,
 202                                 rq_regs->rq_regs_l.min_chunk_size, rq_regs->rq_regs_l.meta_chunk_size,
 203                                 rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs->rq_regs_l.dpte_group_size,
 204                                 rq_regs->rq_regs_l.mpte_group_size, rq_regs->rq_regs_l.swath_height,
 205                                 rq_regs->rq_regs_l.pte_row_height_linear, rq_regs->rq_regs_c.chunk_size, rq_regs->rq_regs_c.min_chunk_size,
 206                                 rq_regs->rq_regs_c.meta_chunk_size, rq_regs->rq_regs_c.min_meta_chunk_size,
 207                                 rq_regs->rq_regs_c.dpte_group_size, rq_regs->rq_regs_c.mpte_group_size,
 208                                 rq_regs->rq_regs_c.swath_height, rq_regs->rq_regs_c.pte_row_height_linear);
 209         }
 210
 211         DTN_INFO("========DLG========\n");
 212         DTN_INFO("HUBP:  rc_hbe     dlg_vbe    min_d_y_n  rc_per_ht  rc_x_a_s "
 213                         "  dst_y_a_s  dst_y_pf   dst_y_vvb  dst_y_rvb  dst_y_vfl  dst_y_rfl  rf_pix_fq"
 214                         "  vratio_pf  vrat_pf_c  rc_pg_vbl  rc_pg_vbc  rc_mc_vbl  rc_mc_vbc  rc_pg_fll"
 215                         "  rc_pg_flc  rc_mc_fll  rc_mc_flc  pr_nom_l   pr_nom_c   rc_pg_nl   rc_pg_nc "
 216                         "  mr_nom_l   mr_nom_c   rc_mc_nl   rc_mc_nc   rc_ld_pl   rc_ld_pc   rc_ld_l  "
 217                         "  rc_ld_c    cha_cur0   ofst_cur1  cha_cur1   vr_af_vc0  ddrq_limt  x_rt_dlay"
 218                         "  x_rp_dlay  x_rr_sfl\n");
 219         for (i = 0; i < pool->pipe_count; i++) {
 220                 struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);
 221                 struct _vcs_dpi_display_dlg_regs_st *dlg_regs = &s->dlg_attr;
 222
 223                 if (!s->blank_en)
 224                         DTN_INFO("[%2d]:  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh"
 225                                 "%  8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh"
 226                                 "  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh\n",
 227                                 pool->hubps[i]->inst, dlg_regs->refcyc_h_blank_end, dlg_regs->dlg_vblank_end, dlg_regs->min_dst_y_next_start,
 228                                 dlg_regs->refcyc_per_htotal, dlg_regs->refcyc_x_after_scaler, dlg_regs->dst_y_after_scaler,
 229                                 dlg_regs->dst_y_prefetch, dlg_regs->dst_y_per_vm_vblank, dlg_regs->dst_y_per_row_vblank,
 230                                 dlg_regs->dst_y_per_vm_flip, dlg_regs->dst_y_per_row_flip, dlg_regs->ref_freq_to_pix_freq,
 231                                 dlg_regs->vratio_prefetch, dlg_regs->vratio_prefetch_c, dlg_regs->refcyc_per_pte_group_vblank_l,
 232                                 dlg_regs->refcyc_per_pte_group_vblank_c, dlg_regs->refcyc_per_meta_chunk_vblank_l,
 233                                 dlg_regs->refcyc_per_meta_chunk_vblank_c, dlg_regs->refcyc_per_pte_group_flip_l,
 234                                 dlg_regs->refcyc_per_pte_group_flip_c, dlg_regs->refcyc_per_meta_chunk_flip_l,
 235                                 dlg_regs->refcyc_per_meta_chunk_flip_c, dlg_regs->dst_y_per_pte_row_nom_l,
 236                                 dlg_regs->dst_y_per_pte_row_nom_c, dlg_regs->refcyc_per_pte_group_nom_l,
 237                                 dlg_regs->refcyc_per_pte_group_nom_c, dlg_regs->dst_y_per_meta_row_nom_l,
 238                                 dlg_regs->dst_y_per_meta_row_nom_c, dlg_regs->refcyc_per_meta_chunk_nom_l,
 239                                 dlg_regs->refcyc_per_meta_chunk_nom_c, dlg_regs->refcyc_per_line_delivery_pre_l,
 240                                 dlg_regs->refcyc_per_line_delivery_pre_c, dlg_regs->refcyc_per_line_delivery_l,
 241                                 dlg_regs->refcyc_per_line_delivery_c, dlg_regs->chunk_hdl_adjust_cur0, dlg_regs->dst_y_offset_cur1,
 242                                 dlg_regs->chunk_hdl_adjust_cur1, dlg_regs->vready_after_vcount0, dlg_regs->dst_y_delta_drq_limit,
 243                                 dlg_regs->xfc_reg_transfer_delay, dlg_regs->xfc_reg_precharge_delay,
 244                                 dlg_regs->xfc_reg_remote_surface_flip_latency);
 245         }
 246
 247         DTN_INFO("========TTU========\n");
 248         DTN_INFO("HUBP:  qos_ll_wm  qos_lh_wm  mn_ttu_vb  qos_l_flp  rc_rd_p_l  rc_rd_l    rc_rd_p_c"
 249                         "  rc_rd_c    rc_rd_c0   rc_rd_pc0  rc_rd_c1   rc_rd_pc1  qos_lf_l   qos_rds_l"
 250                         "  qos_lf_c   qos_rds_c  qos_lf_c0  qos_rds_c0 qos_lf_c1  qos_rds_c1\n");
 251         for (i = 0; i < pool->pipe_count; i++) {
 252                 struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);
 253                 struct _vcs_dpi_display_ttu_regs_st *ttu_regs = &s->ttu_attr;
 254
 255                 if (!s->blank_en)
 256                         DTN_INFO("[%2d]:  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh\n",
 257                                 pool->hubps[i]->inst, ttu_regs->qos_level_low_wm, ttu_regs->qos_level_high_wm, ttu_regs->min_ttu_vblank,
 258                                 ttu_regs->qos_level_flip, ttu_regs->refcyc_per_req_delivery_pre_l, ttu_regs->refcyc_per_req_delivery_l,
 259                                 ttu_regs->refcyc_per_req_delivery_pre_c, ttu_regs->refcyc_per_req_delivery_c, ttu_regs->refcyc_per_req_delivery_cur0,
 260                                 ttu_regs->refcyc_per_req_delivery_pre_cur0, ttu_regs->refcyc_per_req_delivery_cur1,
 261                                 ttu_regs->refcyc_per_req_delivery_pre_cur1, ttu_regs->qos_level_fixed_l, ttu_regs->qos_ramp_disable_l,
 262                                 ttu_regs->qos_level_fixed_c, ttu_regs->qos_ramp_disable_c, ttu_regs->qos_level_fixed_cur0,
 263                                 ttu_regs->qos_ramp_disable_cur0, ttu_regs->qos_level_fixed_cur1, ttu_regs->qos_ramp_disable_cur1);
 264         }
 265         DTN_INFO("\n");
 266 }
 267
 268 void dcn10_log_hw_state(struct dc *dc,
 269         struct dc_log_buffer_ctx *log_ctx)
 270 {
 271         struct dc_context *dc_ctx = dc->ctx;
 272         struct resource_pool *pool = dc->res_pool;
 273         int i;
 274
 275         DTN_INFO_BEGIN();
 276
 277         dcn10_log_hubbub_state(dc, log_ctx);
 278
 279         dcn10_log_hubp_states(dc, log_ctx);
 280
 281         DTN_INFO("DPP:    IGAM format  IGAM mode    DGAM mode    RGAM mode"
 282                         "  GAMUT mode  C11 C12   C13 C14   C21 C22   C23 C24   "
 283                         "C31 C32   C33 C34\n");
 284         for (i = 0; i < pool->pipe_count; i++) {
 285                 struct dpp *dpp = pool->dpps[i];
 286                 struct dcn_dpp_state s = {0};
 287
 288                 dpp->funcs->dpp_read_state(dpp, &s);
 289
 290                 if (!s.is_enabled)
 291                         continue;
 292
 293                 DTN_INFO("[%2d]:  %11xh  %-11s  %-11s  %-11s"
 294                                 "%8x    %08xh %08xh %08xh %08xh %08xh %08xh",
 295                                 dpp->inst,
 296                                 s.igam_input_format,
 297                                 (s.igam_lut_mode == 0) ? "BypassFixed" :
 298                                         ((s.igam_lut_mode == 1) ? "BypassFloat" :
 299                                         ((s.igam_lut_mode == 2) ? "RAM" :
 300                                         ((s.igam_lut_mode == 3) ? "RAM" :
 301                                                                  "Unknown"))),
 302                                 (s.dgam_lut_mode == 0) ? "Bypass" :
 303                                         ((s.dgam_lut_mode == 1) ? "sRGB" :
 304                                         ((s.dgam_lut_mode == 2) ? "Ycc" :
 305                                         ((s.dgam_lut_mode == 3) ? "RAM" :
 306                                         ((s.dgam_lut_mode == 4) ? "RAM" :
 307                                                                  "Unknown")))),
 308                                 (s.rgam_lut_mode == 0) ? "Bypass" :
 309                                         ((s.rgam_lut_mode == 1) ? "sRGB" :
 310                                         ((s.rgam_lut_mode == 2) ? "Ycc" :
 311                                         ((s.rgam_lut_mode == 3) ? "RAM" :
 312                                         ((s.rgam_lut_mode == 4) ? "RAM" :
 313                                                                  "Unknown")))),
 314                                 s.gamut_remap_mode,
 315                                 s.gamut_remap_c11_c12,
 316                                 s.gamut_remap_c13_c14,
 317                                 s.gamut_remap_c21_c22,
 318                                 s.gamut_remap_c23_c24,
 319                                 s.gamut_remap_c31_c32,
 320                                 s.gamut_remap_c33_c34);
 321                 DTN_INFO("\n");
 322         }
 323         DTN_INFO("\n");
 324
 325         DTN_INFO("MPCC:  OPP  DPP  MPCCBOT  MODE  ALPHA_MODE  PREMULT  OVERLAP_ONLY  IDLE\n");
 326         for (i = 0; i < pool->pipe_count; i++) {
 327                 struct mpcc_state s = {0};
 328
 329                 pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s);
 330                 if (s.opp_id != 0xf)
 331                         DTN_INFO("[%2d]:  %2xh  %2xh  %6xh  %4d  %10d  %7d  %12d  %4d\n",
 332                                 i, s.opp_id, s.dpp_id, s.bot_mpcc_id,
 333                                 s.mode, s.alpha_mode, s.pre_multiplied_alpha, s.overlap_only,
 334                                 s.idle);
 335         }
 336         DTN_INFO("\n");
 337
 338         DTN_INFO("OTG:  v_bs  v_be  v_ss  v_se  vpol  vmax  vmin  vmax_sel  vmin_sel  h_bs  h_be  h_ss  h_se  hpol  htot  vtot  underflow blank_en\n");
 339
 340         for (i = 0; i < pool->timing_generator_count; i++) {
 341                 struct timing_generator *tg = pool->timing_generators[i];
 342                 struct dcn_otg_state s = {0};
 343                 /* Read shared OTG state registers for all DCNx */
 344                 optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s);
 345
 346                 /*
 347                  * For DCN2 and greater, a register on the OPP is used to
 348                  * determine if the CRTC is blanked instead of the OTG. So use
 349                  * dpg_is_blanked() if exists, otherwise fallback on otg.
 350                  *
 351                  * TODO: Implement DCN-specific read_otg_state hooks.
 352                  */
 353                 if (pool->opps[i]->funcs->dpg_is_blanked)
 354                         s.blank_enabled = pool->opps[i]->funcs->dpg_is_blanked(pool->opps[i]);
 355                 else
 356                         s.blank_enabled = tg->funcs->is_blanked(tg);
 357
 358                 //only print if OTG master is enabled
 359                 if ((s.otg_enabled & 1) == 0)
 360                         continue;
 361
 362                 DTN_INFO("[%d]: %5d %5d %5d %5d %5d %5d %5d %9d %9d %5d %5d %5d %5d %5d %5d %5d  %9d %8d\n",
 363                                 tg->inst,
 364                                 s.v_blank_start,
 365                                 s.v_blank_end,
 366                                 s.v_sync_a_start,
 367                                 s.v_sync_a_end,
 368                                 s.v_sync_a_pol,
 369                                 s.v_total_max,
 370                                 s.v_total_min,
 371                                 s.v_total_max_sel,
 372                                 s.v_total_min_sel,
 373                                 s.h_blank_start,
 374                                 s.h_blank_end,
 375                                 s.h_sync_a_start,
 376                                 s.h_sync_a_end,
 377                                 s.h_sync_a_pol,
 378                                 s.h_total,
 379                                 s.v_total,
 380                                 s.underflow_occurred_status,
 381                                 s.blank_enabled);
 382
 383                 // Clear underflow for debug purposes
 384                 // We want to keep underflow sticky bit on for the longevity tests outside of test environment.
 385                 // This function is called only from Windows or Diags test environment, hence it's safe to clear
 386                 // it from here without affecting the original intent.
 387                 tg->funcs->clear_optc_underflow(tg);
 388         }
 389         DTN_INFO("\n");
 390
 391         DTN_INFO("DSC: CLOCK_EN  SLICE_WIDTH  Bytes_pp\n");
 392         for (i = 0; i < pool->res_cap->num_dsc; i++) {
 393                 struct display_stream_compressor *dsc = pool->dscs[i];
 394                 struct dcn_dsc_state s = {0};
 395
 396                 dsc->funcs->dsc_read_state(dsc, &s);
 397                 DTN_INFO("[%d]: %-9d %-12d %-10d\n",
 398                 dsc->inst,
 399                         s.dsc_clock_en,
 400                         s.dsc_slice_width,
 401                         s.dsc_bytes_per_pixel);
 402                 DTN_INFO("\n");
 403         }
 404         DTN_INFO("\n");
 405
 406         DTN_INFO("S_ENC: DSC_MODE  SEC_GSP7_LINE_NUM"
 407                         "  VBID6_LINE_REFERENCE  VBID6_LINE_NUM  SEC_GSP7_ENABLE  SEC_STREAM_ENABLE\n");
 408         for (i = 0; i < pool->stream_enc_count; i++) {
 409                 struct stream_encoder *enc = pool->stream_enc[i];
 410                 struct enc_state s = {0};
 411
 412                 if (enc->funcs->enc_read_state) {
 413                         enc->funcs->enc_read_state(enc, &s);
 414                         DTN_INFO("[%-3d]: %-9d %-18d %-21d %-15d %-16d %-17d\n",
 415                                 enc->id,
 416                                 s.dsc_mode,
 417                                 s.sec_gsp_pps_line_num,
 418                                 s.vbid6_line_reference,
 419                                 s.vbid6_line_num,
 420                                 s.sec_gsp_pps_enable,
 421                                 s.sec_stream_enable);
 422                         DTN_INFO("\n");
 423                 }
 424         }
 425         DTN_INFO("\n");
 426
 427         DTN_INFO("L_ENC: DPHY_FEC_EN  DPHY_FEC_READY_SHADOW  DPHY_FEC_ACTIVE_STATUS  DP_LINK_TRAINING_COMPLETE\n");
 428         for (i = 0; i < dc->link_count; i++) {
 429                 struct link_encoder *lenc = dc->links[i]->link_enc;
 430
 431                 struct link_enc_state s = {0};
 432
 433                 if (lenc->funcs->read_state) {
 434                         lenc->funcs->read_state(lenc, &s);
 435                         DTN_INFO("[%-3d]: %-12d %-22d %-22d %-25d\n",
 436                                 i,
 437                                 s.dphy_fec_en,
 438                                 s.dphy_fec_ready_shadow,
 439                                 s.dphy_fec_active_status,
 440                                 s.dp_link_training_complete);
 441                         DTN_INFO("\n");
 442                 }
 443         }
 444         DTN_INFO("\n");
 445
 446         DTN_INFO("\nCALCULATED Clocks: dcfclk_khz:%d  dcfclk_deep_sleep_khz:%d  dispclk_khz:%d\n"
 447                 "dppclk_khz:%d  max_supported_dppclk_khz:%d  fclk_khz:%d  socclk_khz:%d\n\n",
 448                         dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_khz,
 449                         dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz,
 450                         dc->current_state->bw_ctx.bw.dcn.clk.dispclk_khz,
 451                         dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz,
 452                         dc->current_state->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz,
 453                         dc->current_state->bw_ctx.bw.dcn.clk.fclk_khz,
 454                         dc->current_state->bw_ctx.bw.dcn.clk.socclk_khz);
 455
 456         log_mpc_crc(dc, log_ctx);
 457
 458         DTN_INFO_END();
 459 }
 460
 461 bool dcn10_did_underflow_occur(struct dc *dc, struct pipe_ctx *pipe_ctx)
 462 {
 463         struct hubp *hubp = pipe_ctx->plane_res.hubp;
 464         struct timing_generator *tg = pipe_ctx->stream_res.tg;
 465
 466         if (tg->funcs->is_optc_underflow_occurred(tg)) {
 467                 tg->funcs->clear_optc_underflow(tg);
 468                 return true;
 469         }
 470
 471         if (hubp->funcs->hubp_get_underflow_status(hubp)) {
 472                 hubp->funcs->hubp_clear_underflow(hubp);
 473                 return true;
 474         }
 475         return false;
 476 }
 477
 478 void dcn10_enable_power_gating_plane(
 479         struct dce_hwseq *hws,
 480         bool enable)
 481 {
 482         bool force_on = true; /* disable power gating */
 483
 484         if (enable)
 485                 force_on = false;
 486
 487         /* DCHUBP0/1/2/3 */
 488         REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on);
 489         REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on);
 490         REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on);
 491         REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on);
 492
 493         /* DPP0/1/2/3 */
 494         REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on);
 495         REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on);
 496         REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on);
 497         REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);
 498 }
 499
 500 void dcn10_disable_vga(
 501         struct dce_hwseq *hws)
 502 {
 503         unsigned int in_vga1_mode = 0;
 504         unsigned int in_vga2_mode = 0;
 505         unsigned int in_vga3_mode = 0;
 506         unsigned int in_vga4_mode = 0;
 507
 508         REG_GET(D1VGA_CONTROL, D1VGA_MODE_ENABLE, &in_vga1_mode);
 509         REG_GET(D2VGA_CONTROL, D2VGA_MODE_ENABLE, &in_vga2_mode);
 510         REG_GET(D3VGA_CONTROL, D3VGA_MODE_ENABLE, &in_vga3_mode);
 511         REG_GET(D4VGA_CONTROL, D4VGA_MODE_ENABLE, &in_vga4_mode);
 512
 513         if (in_vga1_mode == 0 && in_vga2_mode == 0 &&
 514                         in_vga3_mode == 0 && in_vga4_mode == 0)
 515                 return;
 516
 517         REG_WRITE(D1VGA_CONTROL, 0);
 518         REG_WRITE(D2VGA_CONTROL, 0);
 519         REG_WRITE(D3VGA_CONTROL, 0);
 520         REG_WRITE(D4VGA_CONTROL, 0);
 521
 522         /* HW Engineer's Notes:
 523          *  During switch from vga->extended, if we set the VGA_TEST_ENABLE and
 524          *  then hit the VGA_TEST_RENDER_START, then the DCHUBP timing gets updated correctly.
 525          *
 526          *  Then vBIOS will have it poll for the VGA_TEST_RENDER_DONE and unset
 527          *  VGA_TEST_ENABLE, to leave it in the same state as before.
 528          */
 529         REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_ENABLE, 1);
 530         REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_RENDER_START, 1);
 531 }
 532
 533 void dcn10_dpp_pg_control(
 534                 struct dce_hwseq *hws,
 535                 unsigned int dpp_inst,
 536                 bool power_on)
 537 {
 538         uint32_t power_gate = power_on ? 0 : 1;
 539         uint32_t pwr_status = power_on ? 0 : 2;
 540
 541         if (hws->ctx->dc->debug.disable_dpp_power_gate)
 542                 return;
 543         if (REG(DOMAIN1_PG_CONFIG) == 0)
 544                 return;
 545
 546         switch (dpp_inst) {
 547         case 0: /* DPP0 */
 548                 REG_UPDATE(DOMAIN1_PG_CONFIG,
 549                                 DOMAIN1_POWER_GATE, power_gate);
 550
 551                 REG_WAIT(DOMAIN1_PG_STATUS,
 552                                 DOMAIN1_PGFSM_PWR_STATUS, pwr_status,
 553                                 1, 1000);
 554                 break;
 555         case 1: /* DPP1 */
 556                 REG_UPDATE(DOMAIN3_PG_CONFIG,
 557                                 DOMAIN3_POWER_GATE, power_gate);
 558
 559                 REG_WAIT(DOMAIN3_PG_STATUS,
 560                                 DOMAIN3_PGFSM_PWR_STATUS, pwr_status,
 561                                 1, 1000);
 562                 break;
 563         case 2: /* DPP2 */
 564                 REG_UPDATE(DOMAIN5_PG_CONFIG,
 565                                 DOMAIN5_POWER_GATE, power_gate);
 566
 567                 REG_WAIT(DOMAIN5_PG_STATUS,
 568                                 DOMAIN5_PGFSM_PWR_STATUS, pwr_status,
 569                                 1, 1000);
 570                 break;
 571         case 3: /* DPP3 */
 572                 REG_UPDATE(DOMAIN7_PG_CONFIG,
 573                                 DOMAIN7_POWER_GATE, power_gate);
 574
 575                 REG_WAIT(DOMAIN7_PG_STATUS,
 576                                 DOMAIN7_PGFSM_PWR_STATUS, pwr_status,
 577                                 1, 1000);
 578                 break;
 579         default:
 580                 BREAK_TO_DEBUGGER();
 581                 break;
 582         }
 583 }
 584
 585 void dcn10_hubp_pg_control(
 586                 struct dce_hwseq *hws,
 587                 unsigned int hubp_inst,
 588                 bool power_on)
 589 {
 590         uint32_t power_gate = power_on ? 0 : 1;
 591         uint32_t pwr_status = power_on ? 0 : 2;
 592
 593         if (hws->ctx->dc->debug.disable_hubp_power_gate)
 594                 return;
 595         if (REG(DOMAIN0_PG_CONFIG) == 0)
 596                 return;
 597
 598         switch (hubp_inst) {
 599         case 0: /* DCHUBP0 */
 600                 REG_UPDATE(DOMAIN0_PG_CONFIG,
 601                                 DOMAIN0_POWER_GATE, power_gate);
 602
 603                 REG_WAIT(DOMAIN0_PG_STATUS,
 604                                 DOMAIN0_PGFSM_PWR_STATUS, pwr_status,
 605                                 1, 1000);
 606                 break;
 607         case 1: /* DCHUBP1 */
 608                 REG_UPDATE(DOMAIN2_PG_CONFIG,
 609                                 DOMAIN2_POWER_GATE, power_gate);
 610
 611                 REG_WAIT(DOMAIN2_PG_STATUS,
 612                                 DOMAIN2_PGFSM_PWR_STATUS, pwr_status,
 613                                 1, 1000);
 614                 break;
 615         case 2: /* DCHUBP2 */
 616                 REG_UPDATE(DOMAIN4_PG_CONFIG,
 617                                 DOMAIN4_POWER_GATE, power_gate);
 618
 619                 REG_WAIT(DOMAIN4_PG_STATUS,
 620                                 DOMAIN4_PGFSM_PWR_STATUS, pwr_status,
 621                                 1, 1000);
 622                 break;
 623         case 3: /* DCHUBP3 */
 624                 REG_UPDATE(DOMAIN6_PG_CONFIG,
 625                                 DOMAIN6_POWER_GATE, power_gate);
 626
 627                 REG_WAIT(DOMAIN6_PG_STATUS,
 628                                 DOMAIN6_PGFSM_PWR_STATUS, pwr_status,
 629                                 1, 1000);
 630                 break;
 631         default:
 632                 BREAK_TO_DEBUGGER();
 633                 break;
 634         }
 635 }
 636
 637 static void power_on_plane(
 638         struct dce_hwseq *hws,
 639         int plane_id)
 640 {
 641         DC_LOGGER_INIT(hws->ctx->logger);
 642         if (REG(DC_IP_REQUEST_CNTL)) {
 643                 REG_SET(DC_IP_REQUEST_CNTL, 0,
 644                                 IP_REQUEST_EN, 1);
 645                 hws->funcs.dpp_pg_control(hws, plane_id, true);
 646                 hws->funcs.hubp_pg_control(hws, plane_id, true);
 647                 REG_SET(DC_IP_REQUEST_CNTL, 0,
 648                                 IP_REQUEST_EN, 0);
 649                 DC_LOG_DEBUG(
 650                                 "Un-gated front end for pipe %d\n", plane_id);
 651         }
 652 }
 653
 654 static void undo_DEGVIDCN10_253_wa(struct dc *dc)
 655 {
 656         struct dce_hwseq *hws = dc->hwseq;
 657         struct hubp *hubp = dc->res_pool->hubps[0];
 658
 659         if (!hws->wa_state.DEGVIDCN10_253_applied)
 660                 return;
 661
 662         hubp->funcs->set_blank(hubp, true);
 663
 664         REG_SET(DC_IP_REQUEST_CNTL, 0,
 665                         IP_REQUEST_EN, 1);
 666
 667         hws->funcs.hubp_pg_control(hws, 0, false);
 668         REG_SET(DC_IP_REQUEST_CNTL, 0,
 669                         IP_REQUEST_EN, 0);
 670
 671         hws->wa_state.DEGVIDCN10_253_applied = false;
 672 }
 673
 674 static void apply_DEGVIDCN10_253_wa(struct dc *dc)
 675 {
 676         struct dce_hwseq *hws = dc->hwseq;
 677         struct hubp *hubp = dc->res_pool->hubps[0];
 678         int i;
 679
 680         if (dc->debug.disable_stutter)
 681                 return;
 682
 683         if (!hws->wa.DEGVIDCN10_253)
 684                 return;
 685
 686         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 687                 if (!dc->res_pool->hubps[i]->power_gated)
 688                         return;
 689         }
 690
 691         /* all pipe power gated, apply work around to enable stutter. */
 692
 693         REG_SET(DC_IP_REQUEST_CNTL, 0,
 694                         IP_REQUEST_EN, 1);
 695
 696         hws->funcs.hubp_pg_control(hws, 0, true);
 697         REG_SET(DC_IP_REQUEST_CNTL, 0,
 698                         IP_REQUEST_EN, 0);
 699
 700         hubp->funcs->set_hubp_blank_en(hubp, false);
 701         hws->wa_state.DEGVIDCN10_253_applied = true;
 702 }
 703
 704 void dcn10_bios_golden_init(struct dc *dc)
 705 {
 706         struct dce_hwseq *hws = dc->hwseq;
 707         struct dc_bios *bp = dc->ctx->dc_bios;
 708         int i;
 709         bool allow_self_fresh_force_enable = true;
 710
 711         if (hws->funcs.s0i3_golden_init_wa && hws->funcs.s0i3_golden_init_wa(dc))
 712                 return;
 713
 714         if (dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled)
 715                 allow_self_fresh_force_enable =
 716                                 dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled(dc->res_pool->hubbub);
 717
 718
 719         /* WA for making DF sleep when idle after resume from S0i3.
 720          * DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE is set to 1 by
 721          * command table, if DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE = 0
 722          * before calling command table and it changed to 1 after,
 723          * it should be set back to 0.
 724          */
 725
 726         /* initialize dcn global */
 727         bp->funcs->enable_disp_power_gating(bp,
 728                         CONTROLLER_ID_D0, ASIC_PIPE_INIT);
 729
 730         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 731                 /* initialize dcn per pipe */
 732                 bp->funcs->enable_disp_power_gating(bp,
 733                                 CONTROLLER_ID_D0 + i, ASIC_PIPE_DISABLE);
 734         }
 735
 736         if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)
 737                 if (allow_self_fresh_force_enable == false &&
 738                                 dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled(dc->res_pool->hubbub))
 739                         dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, true);
 740
 741 }
 742
 743 static void false_optc_underflow_wa(
 744                 struct dc *dc,
 745                 const struct dc_stream_state *stream,
 746                 struct timing_generator *tg)
 747 {
 748         int i;
 749         bool underflow;
 750
 751         if (!dc->hwseq->wa.false_optc_underflow)
 752                 return;
 753
 754         underflow = tg->funcs->is_optc_underflow_occurred(tg);
 755
 756         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 757                 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
 758
 759                 if (old_pipe_ctx->stream != stream)
 760                         continue;
 761
 762                 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, old_pipe_ctx);
 763         }
 764
 765         if (tg->funcs->set_blank_data_double_buffer)
 766                 tg->funcs->set_blank_data_double_buffer(tg, true);
 767
 768         if (tg->funcs->is_optc_underflow_occurred(tg) && !underflow)
 769                 tg->funcs->clear_optc_underflow(tg);
 770 }
 771
 772 enum dc_status dcn10_enable_stream_timing(
 773                 struct pipe_ctx *pipe_ctx,
 774                 struct dc_state *context,
 775                 struct dc *dc)
 776 {
 777         struct dc_stream_state *stream = pipe_ctx->stream;
 778         enum dc_color_space color_space;
 779         struct tg_color black_color = {0};
 780
 781         /* by upper caller loop, pipe0 is parent pipe and be called first.
 782          * back end is set up by for pipe0. Other children pipe share back end
 783          * with pipe 0. No program is needed.
 784          */
 785         if (pipe_ctx->top_pipe != NULL)
 786                 return DC_OK;
 787
 788         /* TODO check if timing_changed, disable stream if timing changed */
 789
 790         /* HW program guide assume display already disable
 791          * by unplug sequence. OTG assume stop.
 792          */
 793         pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true);
 794
 795         if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
 796                         pipe_ctx->clock_source,
 797                         &pipe_ctx->stream_res.pix_clk_params,
 798                         &pipe_ctx->pll_settings)) {
 799                 BREAK_TO_DEBUGGER();
 800                 return DC_ERROR_UNEXPECTED;
 801         }
 802
 803         pipe_ctx->stream_res.tg->funcs->program_timing(
 804                         pipe_ctx->stream_res.tg,
 805                         &stream->timing,
 806                         pipe_ctx->pipe_dlg_param.vready_offset,
 807                         pipe_ctx->pipe_dlg_param.vstartup_start,
 808                         pipe_ctx->pipe_dlg_param.vupdate_offset,
 809                         pipe_ctx->pipe_dlg_param.vupdate_width,
 810                         pipe_ctx->stream->signal,
 811                         true);
 812
 813 #if 0 /* move to after enable_crtc */
 814         /* TODO: OPP FMT, ABM. etc. should be done here. */
 815         /* or FPGA now. instance 0 only. TODO: move to opp.c */
 816
 817         inst_offset = reg_offsets[pipe_ctx->stream_res.tg->inst].fmt;
 818
 819         pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
 820                                 pipe_ctx->stream_res.opp,
 821                                 &stream->bit_depth_params,
 822                                 &stream->clamping);
 823 #endif
 824         /* program otg blank color */
 825         color_space = stream->output_color_space;
 826         color_space_to_black_color(dc, color_space, &black_color);
 827
 828         if (pipe_ctx->stream_res.tg->funcs->set_blank_color)
 829                 pipe_ctx->stream_res.tg->funcs->set_blank_color(
 830                                 pipe_ctx->stream_res.tg,
 831                                 &black_color);
 832
 833         if (pipe_ctx->stream_res.tg->funcs->is_blanked &&
 834                         !pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg)) {
 835                 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);
 836                 hwss_wait_for_blank_complete(pipe_ctx->stream_res.tg);
 837                 false_optc_underflow_wa(dc, pipe_ctx->stream, pipe_ctx->stream_res.tg);
 838         }
 839
 840         /* VTG is  within DCHUB command block. DCFCLK is always on */
 841         if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {
 842                 BREAK_TO_DEBUGGER();
 843                 return DC_ERROR_UNEXPECTED;
 844         }
 845
 846         /* TODO program crtc source select for non-virtual signal*/
 847         /* TODO program FMT */
 848         /* TODO setup link_enc */
 849         /* TODO set stream attributes */
 850         /* TODO program audio */
 851         /* TODO enable stream if timing changed */
 852         /* TODO unblank stream if DP */
 853
 854         return DC_OK;
 855 }
 856
 857 static void dcn10_reset_back_end_for_pipe(
 858                 struct dc *dc,
 859                 struct pipe_ctx *pipe_ctx,
 860                 struct dc_state *context)
 861 {
 862         int i;
 863         struct dc_link *link;
 864         DC_LOGGER_INIT(dc->ctx->logger);
 865         if (pipe_ctx->stream_res.stream_enc == NULL) {
 866                 pipe_ctx->stream = NULL;
 867                 return;
 868         }
 869
 870         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
 871                 link = pipe_ctx->stream->link;
 872                 /* DPMS may already disable or */
 873                 /* dpms_off status is incorrect due to fastboot
 874                  * feature. When system resume from S4 with second
 875                  * screen only, the dpms_off would be true but
 876                  * VBIOS lit up eDP, so check link status too.
 877                  */
 878                 if (!pipe_ctx->stream->dpms_off || link->link_status.link_active)
 879                         core_link_disable_stream(pipe_ctx);
 880                 else if (pipe_ctx->stream_res.audio)
 881                         dc->hwss.disable_audio_stream(pipe_ctx);
 882
 883                 if (pipe_ctx->stream_res.audio) {
 884                         /*disable az_endpoint*/
 885                         pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
 886
 887                         /*free audio*/
 888                         if (dc->caps.dynamic_audio == true) {
 889                                 /*we have to dynamic arbitrate the audio endpoints*/
 890                                 /*we free the resource, need reset is_audio_acquired*/
 891                                 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
 892                                                 pipe_ctx->stream_res.audio, false);
 893                                 pipe_ctx->stream_res.audio = NULL;
 894                         }
 895                 }
 896         }
 897
 898         /* by upper caller loop, parent pipe: pipe0, will be reset last.
 899          * back end share by all pipes and will be disable only when disable
 900          * parent pipe.
 901          */
 902         if (pipe_ctx->top_pipe == NULL) {
 903                 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
 904
 905                 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
 906                 if (pipe_ctx->stream_res.tg->funcs->set_drr)
 907                         pipe_ctx->stream_res.tg->funcs->set_drr(
 908                                         pipe_ctx->stream_res.tg, NULL);
 909         }
 910
 911         for (i = 0; i < dc->res_pool->pipe_count; i++)
 912                 if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx)
 913                         break;
 914
 915         if (i == dc->res_pool->pipe_count)
 916                 return;
 917
 918         pipe_ctx->stream = NULL;
 919         DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n",
 920                                         pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
 921 }
 922
 923 static bool dcn10_hw_wa_force_recovery(struct dc *dc)
 924 {
 925         struct hubp *hubp ;
 926         unsigned int i;
 927         bool need_recover = true;
 928
 929         if (!dc->debug.recovery_enabled)
 930                 return false;
 931
 932         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 933                 struct pipe_ctx *pipe_ctx =
 934                         &dc->current_state->res_ctx.pipe_ctx[i];
 935                 if (pipe_ctx != NULL) {
 936                         hubp = pipe_ctx->plane_res.hubp;
 937                         if (hubp != NULL && hubp->funcs->hubp_get_underflow_status) {
 938                                 if (hubp->funcs->hubp_get_underflow_status(hubp) != 0) {
 939                                         /* one pipe underflow, we will reset all the pipes*/
 940                                         need_recover = true;
 941                                 }
 942                         }
 943                 }
 944         }
 945         if (!need_recover)
 946                 return false;
 947         /*
 948         DCHUBP_CNTL:HUBP_BLANK_EN=1
 949         DCHUBBUB_SOFT_RESET:DCHUBBUB_GLOBAL_SOFT_RESET=1
 950         DCHUBP_CNTL:HUBP_DISABLE=1
 951         DCHUBP_CNTL:HUBP_DISABLE=0
 952         DCHUBBUB_SOFT_RESET:DCHUBBUB_GLOBAL_SOFT_RESET=0
 953         DCSURF_PRIMARY_SURFACE_ADDRESS
 954         DCHUBP_CNTL:HUBP_BLANK_EN=0
 955         */
 956
 957         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 958                 struct pipe_ctx *pipe_ctx =
 959                         &dc->current_state->res_ctx.pipe_ctx[i];
 960                 if (pipe_ctx != NULL) {
 961                         hubp = pipe_ctx->plane_res.hubp;
 962                         /*DCHUBP_CNTL:HUBP_BLANK_EN=1*/
 963                         if (hubp != NULL && hubp->funcs->set_hubp_blank_en)
 964                                 hubp->funcs->set_hubp_blank_en(hubp, true);
 965                 }
 966         }
 967         /*DCHUBBUB_SOFT_RESET:DCHUBBUB_GLOBAL_SOFT_RESET=1*/
 968         hubbub1_soft_reset(dc->res_pool->hubbub, true);
 969
 970         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 971                 struct pipe_ctx *pipe_ctx =
 972                         &dc->current_state->res_ctx.pipe_ctx[i];
 973                 if (pipe_ctx != NULL) {
 974                         hubp = pipe_ctx->plane_res.hubp;
 975                         /*DCHUBP_CNTL:HUBP_DISABLE=1*/
 976                         if (hubp != NULL && hubp->funcs->hubp_disable_control)
 977                                 hubp->funcs->hubp_disable_control(hubp, true);
 978                 }
 979         }
 980         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 981                 struct pipe_ctx *pipe_ctx =
 982                         &dc->current_state->res_ctx.pipe_ctx[i];
 983                 if (pipe_ctx != NULL) {
 984                         hubp = pipe_ctx->plane_res.hubp;
 985                         /*DCHUBP_CNTL:HUBP_DISABLE=0*/
 986                         if (hubp != NULL && hubp->funcs->hubp_disable_control)
 987                                 hubp->funcs->hubp_disable_control(hubp, true);
 988                 }
 989         }
 990         /*DCHUBBUB_SOFT_RESET:DCHUBBUB_GLOBAL_SOFT_RESET=0*/
 991         hubbub1_soft_reset(dc->res_pool->hubbub, false);
 992         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 993                 struct pipe_ctx *pipe_ctx =
 994                         &dc->current_state->res_ctx.pipe_ctx[i];
 995                 if (pipe_ctx != NULL) {
 996                         hubp = pipe_ctx->plane_res.hubp;
 997                         /*DCHUBP_CNTL:HUBP_BLANK_EN=0*/
 998                         if (hubp != NULL && hubp->funcs->set_hubp_blank_en)
 999                                 hubp->funcs->set_hubp_blank_en(hubp, true);
1000                 }
1001         }
1002         return true;
1003
1004 }
1005
1006
1007 void dcn10_verify_allow_pstate_change_high(struct dc *dc)
1008 {
1009         static bool should_log_hw_state; /* prevent hw state log by default */
1010
1011         if (!hubbub1_verify_allow_pstate_change_high(dc->res_pool->hubbub)) {
1012                 if (should_log_hw_state) {
1013                         dcn10_log_hw_state(dc, NULL);
1014                 }
1015                 BREAK_TO_DEBUGGER();
1016                 if (dcn10_hw_wa_force_recovery(dc)) {
1017                 /*check again*/
1018                         if (!hubbub1_verify_allow_pstate_change_high(dc->res_pool->hubbub))
1019                                 BREAK_TO_DEBUGGER();
1020                 }
1021         }
1022 }
1023
1024 /* trigger HW to start disconnect plane from stream on the next vsync */
1025 void dcn10_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx)
1026 {
1027         struct dce_hwseq *hws = dc->hwseq;
1028         struct hubp *hubp = pipe_ctx->plane_res.hubp;
1029         int dpp_id = pipe_ctx->plane_res.dpp->inst;
1030         struct mpc *mpc = dc->res_pool->mpc;
1031         struct mpc_tree *mpc_tree_params;
1032         struct mpcc *mpcc_to_remove = NULL;
1033         struct output_pixel_processor *opp = pipe_ctx->stream_res.opp;
1034
1035         mpc_tree_params = &(opp->mpc_tree_params);
1036         mpcc_to_remove = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, dpp_id);
1037
1038         /*Already reset*/
1039         if (mpcc_to_remove == NULL)
1040                 return;
1041
1042         mpc->funcs->remove_mpcc(mpc, mpc_tree_params, mpcc_to_remove);
1043         if (opp != NULL)
1044                 opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
1045
1046         dc->optimized_required = true;
1047
1048         if (hubp->funcs->hubp_disconnect)
1049                 hubp->funcs->hubp_disconnect(hubp);
1050
1051         if (dc->debug.sanity_checks)
1052                 hws->funcs.verify_allow_pstate_change_high(dc);
1053 }
1054
1055 void dcn10_plane_atomic_power_down(struct dc *dc,
1056                 struct dpp *dpp,
1057                 struct hubp *hubp)
1058 {
1059         struct dce_hwseq *hws = dc->hwseq;
1060         DC_LOGGER_INIT(dc->ctx->logger);
1061
1062         if (REG(DC_IP_REQUEST_CNTL)) {
1063                 REG_SET(DC_IP_REQUEST_CNTL, 0,
1064                                 IP_REQUEST_EN, 1);
1065                 hws->funcs.dpp_pg_control(hws, dpp->inst, false);
1066                 hws->funcs.hubp_pg_control(hws, hubp->inst, false);
1067                 dpp->funcs->dpp_reset(dpp);
1068                 REG_SET(DC_IP_REQUEST_CNTL, 0,
1069                                 IP_REQUEST_EN, 0);
1070                 DC_LOG_DEBUG(
1071                                 "Power gated front end %d\n", hubp->inst);
1072         }
1073 }
1074
1075 /* disable HW used by plane.
1076  * note:  cannot disable until disconnect is complete
1077  */
1078 void dcn10_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
1079 {
1080         struct dce_hwseq *hws = dc->hwseq;
1081         struct hubp *hubp = pipe_ctx->plane_res.hubp;
1082         struct dpp *dpp = pipe_ctx->plane_res.dpp;
1083         int opp_id = hubp->opp_id;
1084
1085         dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);
1086
1087         hubp->funcs->hubp_clk_cntl(hubp, false);
1088
1089         dpp->funcs->dpp_dppclk_control(dpp, false, false);
1090
1091         if (opp_id != 0xf && pipe_ctx->stream_res.opp->mpc_tree_params.opp_list == NULL)
1092                 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
1093                                 pipe_ctx->stream_res.opp,
1094                                 false);
1095
1096         hubp->power_gated = true;
1097         dc->optimized_required = false; /* We're powering off, no need to optimize */
1098
1099         hws->funcs.plane_atomic_power_down(dc,
1100                         pipe_ctx->plane_res.dpp,
1101                         pipe_ctx->plane_res.hubp);
1102
1103         pipe_ctx->stream = NULL;
1104         memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res));
1105         memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res));
1106         pipe_ctx->top_pipe = NULL;
1107         pipe_ctx->bottom_pipe = NULL;
1108         pipe_ctx->plane_state = NULL;
1109 }
1110
1111 void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
1112 {
1113         struct dce_hwseq *hws = dc->hwseq;
1114         DC_LOGGER_INIT(dc->ctx->logger);
1115
1116         if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)
1117                 return;
1118
1119         hws->funcs.plane_atomic_disable(dc, pipe_ctx);
1120
1121         apply_DEGVIDCN10_253_wa(dc);
1122
1123         DC_LOG_DC("Power down front end %d\n",
1124                                         pipe_ctx->pipe_idx);
1125 }
1126
1127 void dcn10_init_pipes(struct dc *dc, struct dc_state *context)
1128 {
1129         int i;
1130         struct dce_hwseq *hws = dc->hwseq;
1131         bool can_apply_seamless_boot = false;
1132
1133         for (i = 0; i < context->stream_count; i++) {
1134                 if (context->streams[i]->apply_seamless_boot_optimization) {
1135                         can_apply_seamless_boot = true;
1136                         break;
1137                 }
1138         }
1139
1140         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1141                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
1142                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1143
1144                 /* There is assumption that pipe_ctx is not mapping irregularly
1145                  * to non-preferred front end. If pipe_ctx->stream is not NULL,
1146                  * we will use the pipe, so don't disable
1147                  */
1148                 if (pipe_ctx->stream != NULL && can_apply_seamless_boot)
1149                         continue;
1150
1151                 /* Blank controller using driver code instead of
1152                  * command table.
1153                  */
1154                 if (tg->funcs->is_tg_enabled(tg)) {
1155                         if (hws->funcs.init_blank != NULL) {
1156                                 hws->funcs.init_blank(dc, tg);
1157                                 tg->funcs->lock(tg);
1158                         } else {
1159                                 tg->funcs->lock(tg);
1160                                 tg->funcs->set_blank(tg, true);
1161                                 hwss_wait_for_blank_complete(tg);
1162                         }
1163                 }
1164         }
1165
1166         /* num_opp will be equal to number of mpcc */
1167         for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {
1168                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1169
1170                 /* Cannot reset the MPC mux if seamless boot */
1171                 if (pipe_ctx->stream != NULL && can_apply_seamless_boot)
1172                         continue;
1173
1174                 dc->res_pool->mpc->funcs->mpc_init_single_inst(
1175                                 dc->res_pool->mpc, i);
1176         }
1177
1178         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1179                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
1180                 struct hubp *hubp = dc->res_pool->hubps[i];
1181                 struct dpp *dpp = dc->res_pool->dpps[i];
1182                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1183
1184                 /* There is assumption that pipe_ctx is not mapping irregularly
1185                  * to non-preferred front end. If pipe_ctx->stream is not NULL,
1186                  * we will use the pipe, so don't disable
1187                  */
1188                 if (can_apply_seamless_boot &&
1189                         pipe_ctx->stream != NULL &&
1190                         pipe_ctx->stream_res.tg->funcs->is_tg_enabled(
1191                                 pipe_ctx->stream_res.tg))
1192                         continue;
1193
1194                 /* Disable on the current state so the new one isn't cleared. */
1195                 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
1196
1197                 dpp->funcs->dpp_reset(dpp);
1198
1199                 pipe_ctx->stream_res.tg = tg;
1200                 pipe_ctx->pipe_idx = i;
1201
1202                 pipe_ctx->plane_res.hubp = hubp;
1203                 pipe_ctx->plane_res.dpp = dpp;
1204                 pipe_ctx->plane_res.mpcc_inst = dpp->inst;
1205                 hubp->mpcc_id = dpp->inst;
1206                 hubp->opp_id = OPP_ID_INVALID;
1207                 hubp->power_gated = false;
1208
1209                 dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
1210                 dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
1211                 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
1212                 pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
1213
1214                 hws->funcs.plane_atomic_disconnect(dc, pipe_ctx);
1215
1216                 if (tg->funcs->is_tg_enabled(tg))
1217                         tg->funcs->unlock(tg);
1218
1219                 dc->hwss.disable_plane(dc, pipe_ctx);
1220
1221                 pipe_ctx->stream_res.tg = NULL;
1222                 pipe_ctx->plane_res.hubp = NULL;
1223
1224                 tg->funcs->tg_init(tg);
1225         }
1226 }
1227
1228 void dcn10_init_hw(struct dc *dc)
1229 {
1230         int i;
1231         struct abm *abm = dc->res_pool->abm;
1232         struct dmcu *dmcu = dc->res_pool->dmcu;
1233         struct dce_hwseq *hws = dc->hwseq;
1234         struct dc_bios *dcb = dc->ctx->dc_bios;
1235         struct resource_pool *res_pool = dc->res_pool;
1236
1237         if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
1238                 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
1239
1240         // Initialize the dccg
1241         if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->dccg_init)
1242                 dc->res_pool->dccg->funcs->dccg_init(res_pool->dccg);
1243
1244         if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
1245
1246                 REG_WRITE(REFCLK_CNTL, 0);
1247                 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
1248                 REG_WRITE(DIO_MEM_PWR_CTRL, 0);
1249
1250                 if (!dc->debug.disable_clock_gate) {
1251                         /* enable all DCN clock gating */
1252                         REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
1253
1254                         REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
1255
1256                         REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
1257                 }
1258
1259                 //Enable ability to power gate / don't force power on permanently
1260                 hws->funcs.enable_power_gating_plane(hws, true);
1261
1262                 return;
1263         }
1264
1265         if (!dcb->funcs->is_accelerated_mode(dcb))
1266                 hws->funcs.disable_vga(dc->hwseq);
1267
1268         hws->funcs.bios_golden_init(dc);
1269         if (dc->ctx->dc_bios->fw_info_valid) {
1270                 res_pool->ref_clocks.xtalin_clock_inKhz =
1271                                 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
1272
1273                 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
1274                         if (res_pool->dccg && res_pool->hubbub) {
1275
1276                                 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
1277                                                 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
1278                                                 &res_pool->ref_clocks.dccg_ref_clock_inKhz);
1279
1280                                 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
1281                                                 res_pool->ref_clocks.dccg_ref_clock_inKhz,
1282                                                 &res_pool->ref_clocks.dchub_ref_clock_inKhz);
1283                         } else {
1284                                 // Not all ASICs have DCCG sw component
1285                                 res_pool->ref_clocks.dccg_ref_clock_inKhz =
1286                                                 res_pool->ref_clocks.xtalin_clock_inKhz;
1287                                 res_pool->ref_clocks.dchub_ref_clock_inKhz =
1288                                                 res_pool->ref_clocks.xtalin_clock_inKhz;
1289                         }
1290                 }
1291         } else
1292                 ASSERT_CRITICAL(false);
1293
1294         for (i = 0; i < dc->link_count; i++) {
1295                 /* Power up AND update implementation according to the
1296                  * required signal (which may be different from the
1297                  * default signal on connector).
1298                  */
1299                 struct dc_link *link = dc->links[i];
1300
1301                 link->link_enc->funcs->hw_init(link->link_enc);
1302
1303                 /* Check for enabled DIG to identify enabled display */
1304                 if (link->link_enc->funcs->is_dig_enabled &&
1305                         link->link_enc->funcs->is_dig_enabled(link->link_enc))
1306                         link->link_status.link_active = true;
1307         }
1308
1309         /* Power gate DSCs */
1310         for (i = 0; i < res_pool->res_cap->num_dsc; i++)
1311                 if (hws->funcs.dsc_pg_control != NULL)
1312                         hws->funcs.dsc_pg_control(hws, res_pool->dscs[i]->inst, false);
1313
1314         /* If taking control over from VBIOS, we may want to optimize our first
1315          * mode set, so we need to skip powering down pipes until we know which
1316          * pipes we want to use.
1317          * Otherwise, if taking control is not possible, we need to power
1318          * everything down.
1319          */
1320         if (dcb->funcs->is_accelerated_mode(dcb) || dc->config.power_down_display_on_boot) {
1321                 hws->funcs.init_pipes(dc, dc->current_state);
1322         }
1323
1324         for (i = 0; i < res_pool->audio_count; i++) {
1325                 struct audio *audio = res_pool->audios[i];
1326
1327                 audio->funcs->hw_init(audio);
1328         }
1329
1330         if (abm != NULL) {
1331                 abm->funcs->init_backlight(abm);
1332                 abm->funcs->abm_init(abm);
1333         }
1334
1335         if (dmcu != NULL && !dmcu->auto_load_dmcu)
1336                 dmcu->funcs->dmcu_init(dmcu);
1337
1338         if (abm != NULL && dmcu != NULL)
1339                 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
1340
1341         /* power AFMT HDMI memory TODO: may move to dis/en output save power*/
1342         REG_WRITE(DIO_MEM_PWR_CTRL, 0);
1343
1344         if (!dc->debug.disable_clock_gate) {
1345                 /* enable all DCN clock gating */
1346                 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
1347
1348                 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
1349
1350                 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
1351         }
1352
1353         hws->funcs.enable_power_gating_plane(dc->hwseq, true);
1354
1355         if (dc->clk_mgr->funcs->notify_wm_ranges)
1356                 dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);
1357
1358 }
1359
1360 void dcn10_reset_hw_ctx_wrap(
1361                 struct dc *dc,
1362                 struct dc_state *context)
1363 {
1364         int i;
1365         struct dce_hwseq *hws = dc->hwseq;
1366
1367         /* Reset Back End*/
1368         for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
1369                 struct pipe_ctx *pipe_ctx_old =
1370                         &dc->current_state->res_ctx.pipe_ctx[i];
1371                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1372
1373                 if (!pipe_ctx_old->stream)
1374                         continue;
1375
1376                 if (pipe_ctx_old->top_pipe)
1377                         continue;
1378
1379                 if (!pipe_ctx->stream ||
1380                                 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
1381                         struct clock_source *old_clk = pipe_ctx_old->clock_source;
1382
1383                         dcn10_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
1384                         if (hws->funcs.enable_stream_gating)
1385                                 hws->funcs.enable_stream_gating(dc, pipe_ctx);
1386                         if (old_clk)
1387                                 old_clk->funcs->cs_power_down(old_clk);
1388                 }
1389         }
1390 }
1391
1392 static bool patch_address_for_sbs_tb_stereo(
1393                 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr)
1394 {
1395         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1396         bool sec_split = pipe_ctx->top_pipe &&
1397                         pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
1398         if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
1399                 (pipe_ctx->stream->timing.timing_3d_format ==
1400                  TIMING_3D_FORMAT_SIDE_BY_SIDE ||
1401                  pipe_ctx->stream->timing.timing_3d_format ==
1402                  TIMING_3D_FORMAT_TOP_AND_BOTTOM)) {
1403                 *addr = plane_state->address.grph_stereo.left_addr;
1404                 plane_state->address.grph_stereo.left_addr =
1405                 plane_state->address.grph_stereo.right_addr;
1406                 return true;
1407         } else {
1408                 if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE &&
1409                         plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) {
1410                         plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO;
1411                         plane_state->address.grph_stereo.right_addr =
1412                         plane_state->address.grph_stereo.left_addr;
1413                 }
1414         }
1415         return false;
1416 }
1417
1418 void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)
1419 {
1420         bool addr_patched = false;
1421         PHYSICAL_ADDRESS_LOC addr;
1422         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1423
1424         if (plane_state == NULL)
1425                 return;
1426
1427         addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);
1428
1429         pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(
1430                         pipe_ctx->plane_res.hubp,
1431                         &plane_state->address,
1432                         plane_state->flip_immediate);
1433
1434         plane_state->status.requested_address = plane_state->address;
1435
1436         if (plane_state->flip_immediate)
1437                 plane_state->status.current_address = plane_state->address;
1438
1439         if (addr_patched)
1440                 pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;
1441 }
1442
1443 bool dcn10_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
1444                         const struct dc_plane_state *plane_state)
1445 {
1446         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
1447         const struct dc_transfer_func *tf = NULL;
1448         bool result = true;
1449
1450         if (dpp_base == NULL)
1451                 return false;
1452
1453         if (plane_state->in_transfer_func)
1454                 tf = plane_state->in_transfer_func;
1455
1456         if (plane_state->gamma_correction &&
1457                 !dpp_base->ctx->dc->debug.always_use_regamma
1458                 && !plane_state->gamma_correction->is_identity
1459                         && dce_use_lut(plane_state->format))
1460                 dpp_base->funcs->dpp_program_input_lut(dpp_base, plane_state->gamma_correction);
1461
1462         if (tf == NULL)
1463                 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
1464         else if (tf->type == TF_TYPE_PREDEFINED) {
1465                 switch (tf->tf) {
1466                 case TRANSFER_FUNCTION_SRGB:
1467                         dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_sRGB);
1468                         break;
1469                 case TRANSFER_FUNCTION_BT709:
1470                         dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_xvYCC);
1471                         break;
1472                 case TRANSFER_FUNCTION_LINEAR:
1473                         dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
1474                         break;
1475                 case TRANSFER_FUNCTION_PQ:
1476                         dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_USER_PWL);
1477                         cm_helper_translate_curve_to_degamma_hw_format(tf, &dpp_base->degamma_params);
1478                         dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, &dpp_base->degamma_params);
1479                         result = true;
1480                         break;
1481                 default:
1482                         result = false;
1483                         break;
1484                 }
1485         } else if (tf->type == TF_TYPE_BYPASS) {
1486                 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
1487         } else {
1488                 cm_helper_translate_curve_to_degamma_hw_format(tf,
1489                                         &dpp_base->degamma_params);
1490                 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base,
1491                                 &dpp_base->degamma_params);
1492                 result = true;
1493         }
1494
1495         return result;
1496 }
1497
1498 #define MAX_NUM_HW_POINTS 0x200
1499
1500 static void log_tf(struct dc_context *ctx,
1501                                 struct dc_transfer_func *tf, uint32_t hw_points_num)
1502 {
1503         // DC_LOG_GAMMA is default logging of all hw points
1504         // DC_LOG_ALL_GAMMA logs all points, not only hw points
1505         // DC_LOG_ALL_TF_POINTS logs all channels of the tf
1506         int i = 0;
1507
1508         DC_LOGGER_INIT(ctx->logger);
1509         DC_LOG_GAMMA("Gamma Correction TF");
1510         DC_LOG_ALL_GAMMA("Logging all tf points...");
1511         DC_LOG_ALL_TF_CHANNELS("Logging all channels...");
1512
1513         for (i = 0; i < hw_points_num; i++) {
1514                 DC_LOG_GAMMA("R\t%d\t%llu", i, tf->tf_pts.red[i].value);
1515                 DC_LOG_ALL_TF_CHANNELS("G\t%d\t%llu", i, tf->tf_pts.green[i].value);
1516                 DC_LOG_ALL_TF_CHANNELS("B\t%d\t%llu", i, tf->tf_pts.blue[i].value);
1517         }
1518
1519         for (i = hw_points_num; i < MAX_NUM_HW_POINTS; i++) {
1520                 DC_LOG_ALL_GAMMA("R\t%d\t%llu", i, tf->tf_pts.red[i].value);
1521                 DC_LOG_ALL_TF_CHANNELS("G\t%d\t%llu", i, tf->tf_pts.green[i].value);
1522                 DC_LOG_ALL_TF_CHANNELS("B\t%d\t%llu", i, tf->tf_pts.blue[i].value);
1523         }
1524 }
1525
1526 bool dcn10_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
1527                                 const struct dc_stream_state *stream)
1528 {
1529         struct dpp *dpp = pipe_ctx->plane_res.dpp;
1530
1531         if (dpp == NULL)
1532                 return false;
1533
1534         dpp->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
1535
1536         if (stream->out_transfer_func &&
1537             stream->out_transfer_func->type == TF_TYPE_PREDEFINED &&
1538             stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB)
1539                 dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_SRGB);
1540
1541         /* dcn10_translate_regamma_to_hw_format takes 750us, only do it when full
1542          * update.
1543          */
1544         else if (cm_helper_translate_curve_to_hw_format(
1545                         stream->out_transfer_func,
1546                         &dpp->regamma_params, false)) {
1547                 dpp->funcs->dpp_program_regamma_pwl(
1548                                 dpp,
1549                                 &dpp->regamma_params, OPP_REGAMMA_USER);
1550         } else
1551                 dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_BYPASS);
1552
1553         if (stream != NULL && stream->ctx != NULL &&
1554                         stream->out_transfer_func != NULL) {
1555                 log_tf(stream->ctx,
1556                                 stream->out_transfer_func,
1557                                 dpp->regamma_params.hw_points_num);
1558         }
1559
1560         return true;
1561 }
1562
1563 void dcn10_pipe_control_lock(
1564         struct dc *dc,
1565         struct pipe_ctx *pipe,
1566         bool lock)
1567 {
1568         struct dce_hwseq *hws = dc->hwseq;
1569
1570         /* use TG master update lock to lock everything on the TG
1571          * therefore only top pipe need to lock
1572          */
1573         if (pipe->top_pipe)
1574                 return;
1575
1576         if (dc->debug.sanity_checks)
1577                 hws->funcs.verify_allow_pstate_change_high(dc);
1578
1579         if (lock)
1580                 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);
1581         else
1582                 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);
1583
1584         if (dc->debug.sanity_checks)
1585                 hws->funcs.verify_allow_pstate_change_high(dc);
1586 }
1587
1588 static bool wait_for_reset_trigger_to_occur(
1589         struct dc_context *dc_ctx,
1590         struct timing_generator *tg)
1591 {
1592         bool rc = false;
1593
1594         /* To avoid endless loop we wait at most
1595          * frames_to_wait_on_triggered_reset frames for the reset to occur. */
1596         const uint32_t frames_to_wait_on_triggered_reset = 10;
1597         int i;
1598
1599         for (i = 0; i < frames_to_wait_on_triggered_reset; i++) {
1600
1601                 if (!tg->funcs->is_counter_moving(tg)) {
1602                         DC_ERROR("TG counter is not moving!\n");
1603                         break;
1604                 }
1605
1606                 if (tg->funcs->did_triggered_reset_occur(tg)) {
1607                         rc = true;
1608                         /* usually occurs at i=1 */
1609                         DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",
1610                                         i);
1611                         break;
1612                 }
1613
1614                 /* Wait for one frame. */
1615                 tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);
1616                 tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
1617         }
1618
1619         if (false == rc)
1620                 DC_ERROR("GSL: Timeout on reset trigger!\n");
1621
1622         return rc;
1623 }
1624
1625 void dcn10_enable_timing_synchronization(
1626         struct dc *dc,
1627         int group_index,
1628         int group_size,
1629         struct pipe_ctx *grouped_pipes[])
1630 {
1631         struct dc_context *dc_ctx = dc->ctx;
1632         int i;
1633
1634         DC_SYNC_INFO("Setting up OTG reset trigger\n");
1635
1636         for (i = 1; i < group_size; i++)
1637                 grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger(
1638                                 grouped_pipes[i]->stream_res.tg,
1639                                 grouped_pipes[0]->stream_res.tg->inst);
1640
1641         DC_SYNC_INFO("Waiting for trigger\n");
1642
1643         /* Need to get only check 1 pipe for having reset as all the others are
1644          * synchronized. Look at last pipe programmed to reset.
1645          */
1646
1647         wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[1]->stream_res.tg);
1648         for (i = 1; i < group_size; i++)
1649                 grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(
1650                                 grouped_pipes[i]->stream_res.tg);
1651
1652         DC_SYNC_INFO("Sync complete\n");
1653 }
1654
1655 void dcn10_enable_per_frame_crtc_position_reset(
1656         struct dc *dc,
1657         int group_size,
1658         struct pipe_ctx *grouped_pipes[])
1659 {
1660         struct dc_context *dc_ctx = dc->ctx;
1661         int i;
1662
1663         DC_SYNC_INFO("Setting up\n");
1664         for (i = 0; i < group_size; i++)
1665                 if (grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset)
1666                         grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset(
1667                                         grouped_pipes[i]->stream_res.tg,
1668                                         0,
1669                                         &grouped_pipes[i]->stream->triggered_crtc_reset);
1670
1671         DC_SYNC_INFO("Waiting for trigger\n");
1672
1673         for (i = 0; i < group_size; i++)
1674                 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
1675
1676         DC_SYNC_INFO("Multi-display sync is complete\n");
1677 }
1678
1679 /*static void print_rq_dlg_ttu(
1680                 struct dc *dc,
1681                 struct pipe_ctx *pipe_ctx)
1682 {
1683         DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger,
1684                         "\n============== DML TTU Output parameters [%d] ==============\n"
1685                         "qos_level_low_wm: %d, \n"
1686                         "qos_level_high_wm: %d, \n"
1687                         "min_ttu_vblank: %d, \n"
1688                         "qos_level_flip: %d, \n"
1689                         "refcyc_per_req_delivery_l: %d, \n"
1690                         "qos_level_fixed_l: %d, \n"
1691                         "qos_ramp_disable_l: %d, \n"
1692                         "refcyc_per_req_delivery_pre_l: %d, \n"
1693                         "refcyc_per_req_delivery_c: %d, \n"
1694                         "qos_level_fixed_c: %d, \n"
1695                         "qos_ramp_disable_c: %d, \n"
1696                         "refcyc_per_req_delivery_pre_c: %d\n"
1697                         "=============================================================\n",
1698                         pipe_ctx->pipe_idx,
1699                         pipe_ctx->ttu_regs.qos_level_low_wm,
1700                         pipe_ctx->ttu_regs.qos_level_high_wm,
1701                         pipe_ctx->ttu_regs.min_ttu_vblank,
1702                         pipe_ctx->ttu_regs.qos_level_flip,
1703                         pipe_ctx->ttu_regs.refcyc_per_req_delivery_l,
1704                         pipe_ctx->ttu_regs.qos_level_fixed_l,
1705                         pipe_ctx->ttu_regs.qos_ramp_disable_l,
1706                         pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_l,
1707                         pipe_ctx->ttu_regs.refcyc_per_req_delivery_c,
1708                         pipe_ctx->ttu_regs.qos_level_fixed_c,
1709                         pipe_ctx->ttu_regs.qos_ramp_disable_c,
1710                         pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_c
1711                         );
1712
1713         DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger,
1714                         "\n============== DML DLG Output parameters [%d] ==============\n"
1715                         "refcyc_h_blank_end: %d, \n"
1716                         "dlg_vblank_end: %d, \n"
1717                         "min_dst_y_next_start: %d, \n"
1718                         "refcyc_per_htotal: %d, \n"
1719                         "refcyc_x_after_scaler: %d, \n"
1720                         "dst_y_after_scaler: %d, \n"
1721                         "dst_y_prefetch: %d, \n"
1722                         "dst_y_per_vm_vblank: %d, \n"
1723                         "dst_y_per_row_vblank: %d, \n"
1724                         "ref_freq_to_pix_freq: %d, \n"
1725                         "vratio_prefetch: %d, \n"
1726                         "refcyc_per_pte_group_vblank_l: %d, \n"
1727                         "refcyc_per_meta_chunk_vblank_l: %d, \n"
1728                         "dst_y_per_pte_row_nom_l: %d, \n"
1729                         "refcyc_per_pte_group_nom_l: %d, \n",
1730                         pipe_ctx->pipe_idx,
1731                         pipe_ctx->dlg_regs.refcyc_h_blank_end,
1732                         pipe_ctx->dlg_regs.dlg_vblank_end,
1733                         pipe_ctx->dlg_regs.min_dst_y_next_start,
1734                         pipe_ctx->dlg_regs.refcyc_per_htotal,
1735                         pipe_ctx->dlg_regs.refcyc_x_after_scaler,
1736                         pipe_ctx->dlg_regs.dst_y_after_scaler,
1737                         pipe_ctx->dlg_regs.dst_y_prefetch,
1738                         pipe_ctx->dlg_regs.dst_y_per_vm_vblank,
1739                         pipe_ctx->dlg_regs.dst_y_per_row_vblank,
1740                         pipe_ctx->dlg_regs.ref_freq_to_pix_freq,
1741                         pipe_ctx->dlg_regs.vratio_prefetch,
1742                         pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_l,
1743                         pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_l,
1744                         pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_l,
1745                         pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_l
1746                         );
1747
1748         DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger,
1749                         "\ndst_y_per_meta_row_nom_l: %d, \n"
1750                         "refcyc_per_meta_chunk_nom_l: %d, \n"
1751                         "refcyc_per_line_delivery_pre_l: %d, \n"
1752                         "refcyc_per_line_delivery_l: %d, \n"
1753                         "vratio_prefetch_c: %d, \n"
1754                         "refcyc_per_pte_group_vblank_c: %d, \n"
1755                         "refcyc_per_meta_chunk_vblank_c: %d, \n"
1756                         "dst_y_per_pte_row_nom_c: %d, \n"
1757                         "refcyc_per_pte_group_nom_c: %d, \n"
1758                         "dst_y_per_meta_row_nom_c: %d, \n"
1759                         "refcyc_per_meta_chunk_nom_c: %d, \n"
1760                         "refcyc_per_line_delivery_pre_c: %d, \n"
1761                         "refcyc_per_line_delivery_c: %d \n"
1762                         "========================================================\n",
1763                         pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_l,
1764                         pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_l,
1765                         pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_l,
1766                         pipe_ctx->dlg_regs.refcyc_per_line_delivery_l,
1767                         pipe_ctx->dlg_regs.vratio_prefetch_c,
1768                         pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_c,
1769                         pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_c,
1770                         pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_c,
1771                         pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_c,
1772                         pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_c,
1773                         pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_c,
1774                         pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_c,
1775                         pipe_ctx->dlg_regs.refcyc_per_line_delivery_c
1776                         );
1777
1778         DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger,
1779                         "\n============== DML RQ Output parameters [%d] ==============\n"
1780                         "chunk_size: %d \n"
1781                         "min_chunk_size: %d \n"
1782                         "meta_chunk_size: %d \n"
1783                         "min_meta_chunk_size: %d \n"
1784                         "dpte_group_size: %d \n"
1785                         "mpte_group_size: %d \n"
1786                         "swath_height: %d \n"
1787                         "pte_row_height_linear: %d \n"
1788                         "========================================================\n",
1789                         pipe_ctx->pipe_idx,
1790                         pipe_ctx->rq_regs.rq_regs_l.chunk_size,
1791                         pipe_ctx->rq_regs.rq_regs_l.min_chunk_size,
1792                         pipe_ctx->rq_regs.rq_regs_l.meta_chunk_size,
1793                         pipe_ctx->rq_regs.rq_regs_l.min_meta_chunk_size,
1794                         pipe_ctx->rq_regs.rq_regs_l.dpte_group_size,
1795                         pipe_ctx->rq_regs.rq_regs_l.mpte_group_size,
1796                         pipe_ctx->rq_regs.rq_regs_l.swath_height,
1797                         pipe_ctx->rq_regs.rq_regs_l.pte_row_height_linear
1798                         );
1799 }
1800 */
1801
1802 static void mmhub_read_vm_system_aperture_settings(struct dcn10_hubp *hubp1,
1803                 struct vm_system_aperture_param *apt,
1804                 struct dce_hwseq *hws)
1805 {
1806         PHYSICAL_ADDRESS_LOC physical_page_number;
1807         uint32_t logical_addr_low;
1808         uint32_t logical_addr_high;
1809
1810         REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
1811                         PHYSICAL_PAGE_NUMBER_MSB, &physical_page_number.high_part);
1812         REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
1813                         PHYSICAL_PAGE_NUMBER_LSB, &physical_page_number.low_part);
1814
1815         REG_GET(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1816                         LOGICAL_ADDR, &logical_addr_low);
1817
1818         REG_GET(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1819                         LOGICAL_ADDR, &logical_addr_high);
1820
1821         apt->sys_default.quad_part =  physical_page_number.quad_part << 12;
1822         apt->sys_low.quad_part =  (int64_t)logical_addr_low << 18;
1823         apt->sys_high.quad_part =  (int64_t)logical_addr_high << 18;
1824 }
1825
1826 /* Temporary read settings, future will get values from kmd directly */
1827 static void mmhub_read_vm_context0_settings(struct dcn10_hubp *hubp1,
1828                 struct vm_context0_param *vm0,
1829                 struct dce_hwseq *hws)
1830 {
1831         PHYSICAL_ADDRESS_LOC fb_base;
1832         PHYSICAL_ADDRESS_LOC fb_offset;
1833         uint32_t fb_base_value;
1834         uint32_t fb_offset_value;
1835
1836         REG_GET(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, &fb_base_value);
1837         REG_GET(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, &fb_offset_value);
1838
1839         REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
1840                         PAGE_DIRECTORY_ENTRY_HI32, &vm0->pte_base.high_part);
1841         REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
1842                         PAGE_DIRECTORY_ENTRY_LO32, &vm0->pte_base.low_part);
1843
1844         REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
1845                         LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_start.high_part);
1846         REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
1847                         LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_start.low_part);
1848
1849         REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
1850                         LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_end.high_part);
1851         REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
1852                         LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_end.low_part);
1853
1854         REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
1855                         PHYSICAL_PAGE_ADDR_HI4, &vm0->fault_default.high_part);
1856         REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
1857                         PHYSICAL_PAGE_ADDR_LO32, &vm0->fault_default.low_part);
1858
1859         /*
1860          * The values in VM_CONTEXT0_PAGE_TABLE_BASE_ADDR is in UMA space.
1861          * Therefore we need to do
1862          * DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
1863          * - DCHUBBUB_SDPIF_FB_OFFSET + DCHUBBUB_SDPIF_FB_BASE
1864          */
1865         fb_base.quad_part = (uint64_t)fb_base_value << 24;
1866         fb_offset.quad_part = (uint64_t)fb_offset_value << 24;
1867         vm0->pte_base.quad_part += fb_base.quad_part;
1868         vm0->pte_base.quad_part -= fb_offset.quad_part;
1869 }
1870
1871
1872 void dcn10_program_pte_vm(struct dce_hwseq *hws, struct hubp *hubp)
1873 {
1874         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
1875         struct vm_system_aperture_param apt = { {{ 0 } } };
1876         struct vm_context0_param vm0 = { { { 0 } } };
1877
1878         mmhub_read_vm_system_aperture_settings(hubp1, &apt, hws);
1879         mmhub_read_vm_context0_settings(hubp1, &vm0, hws);
1880
1881         hubp->funcs->hubp_set_vm_system_aperture_settings(hubp, &apt);
1882         hubp->funcs->hubp_set_vm_context0_settings(hubp, &vm0);
1883 }
1884
1885 static void dcn10_enable_plane(
1886         struct dc *dc,
1887         struct pipe_ctx *pipe_ctx,
1888         struct dc_state *context)
1889 {
1890         struct dce_hwseq *hws = dc->hwseq;
1891
1892         if (dc->debug.sanity_checks) {
1893                 hws->funcs.verify_allow_pstate_change_high(dc);
1894         }
1895
1896         undo_DEGVIDCN10_253_wa(dc);
1897
1898         power_on_plane(dc->hwseq,
1899                 pipe_ctx->plane_res.hubp->inst);
1900
1901         /* enable DCFCLK current DCHUB */
1902         pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);
1903
1904         /* make sure OPP_PIPE_CLOCK_EN = 1 */
1905         pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
1906                         pipe_ctx->stream_res.opp,
1907                         true);
1908
1909 /* TODO: enable/disable in dm as per update type.
1910         if (plane_state) {
1911                 DC_LOG_DC(dc->ctx->logger,
1912                                 "Pipe:%d 0x%x: addr hi:0x%x, "
1913                                 "addr low:0x%x, "
1914                                 "src: %d, %d, %d,"
1915                                 " %d; dst: %d, %d, %d, %d;\n",
1916                                 pipe_ctx->pipe_idx,
1917                                 plane_state,
1918                                 plane_state->address.grph.addr.high_part,
1919                                 plane_state->address.grph.addr.low_part,
1920                                 plane_state->src_rect.x,
1921                                 plane_state->src_rect.y,
1922                                 plane_state->src_rect.width,
1923                                 plane_state->src_rect.height,
1924                                 plane_state->dst_rect.x,
1925                                 plane_state->dst_rect.y,
1926                                 plane_state->dst_rect.width,
1927                                 plane_state->dst_rect.height);
1928
1929                 DC_LOG_DC(dc->ctx->logger,
1930                                 "Pipe %d: width, height, x, y         format:%d\n"
1931                                 "viewport:%d, %d, %d, %d\n"
1932                                 "recout:  %d, %d, %d, %d\n",
1933                                 pipe_ctx->pipe_idx,
1934                                 plane_state->format,
1935                                 pipe_ctx->plane_res.scl_data.viewport.width,
1936                                 pipe_ctx->plane_res.scl_data.viewport.height,
1937                                 pipe_ctx->plane_res.scl_data.viewport.x,
1938                                 pipe_ctx->plane_res.scl_data.viewport.y,
1939                                 pipe_ctx->plane_res.scl_data.recout.width,
1940                                 pipe_ctx->plane_res.scl_data.recout.height,
1941                                 pipe_ctx->plane_res.scl_data.recout.x,
1942                                 pipe_ctx->plane_res.scl_data.recout.y);
1943                 print_rq_dlg_ttu(dc, pipe_ctx);
1944         }
1945 */
1946         if (dc->config.gpu_vm_support)
1947                 dcn10_program_pte_vm(hws, pipe_ctx->plane_res.hubp);
1948
1949         if (dc->debug.sanity_checks) {
1950                 hws->funcs.verify_allow_pstate_change_high(dc);
1951         }
1952 }
1953
1954 void dcn10_program_gamut_remap(struct pipe_ctx *pipe_ctx)
1955 {
1956         int i = 0;
1957         struct dpp_grph_csc_adjustment adjust;
1958         memset(&adjust, 0, sizeof(adjust));
1959         adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
1960
1961
1962         if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
1963                 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
1964                 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
1965                         adjust.temperature_matrix[i] =
1966                                 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
1967         }
1968
1969         pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp, &adjust);
1970 }
1971
1972
1973 static bool dcn10_is_rear_mpo_fix_required(struct pipe_ctx *pipe_ctx, enum dc_color_space colorspace)
1974 {
1975         if (pipe_ctx->plane_state && pipe_ctx->plane_state->layer_index > 0 && is_rgb_cspace(colorspace)) {
1976                 if (pipe_ctx->top_pipe) {
1977                         struct pipe_ctx *top = pipe_ctx->top_pipe;
1978
1979                         while (top->top_pipe)
1980                                 top = top->top_pipe; // Traverse to top pipe_ctx
1981                         if (top->plane_state && top->plane_state->layer_index == 0)
1982                                 return true; // Front MPO plane not hidden
1983                 }
1984         }
1985         return false;
1986 }
1987
1988 static void dcn10_set_csc_adjustment_rgb_mpo_fix(struct pipe_ctx *pipe_ctx, uint16_t *matrix)
1989 {
1990         // Override rear plane RGB bias to fix MPO brightness
1991         uint16_t rgb_bias = matrix[3];
1992
1993         matrix[3] = 0;
1994         matrix[7] = 0;
1995         matrix[11] = 0;
1996         pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, matrix);
1997         matrix[3] = rgb_bias;
1998         matrix[7] = rgb_bias;
1999         matrix[11] = rgb_bias;
2000 }
2001
2002 void dcn10_program_output_csc(struct dc *dc,
2003                 struct pipe_ctx *pipe_ctx,
2004                 enum dc_color_space colorspace,
2005                 uint16_t *matrix,
2006                 int opp_id)
2007 {
2008         if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
2009                 if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment != NULL) {
2010
2011                         /* MPO is broken with RGB colorspaces when OCSC matrix
2012                          * brightness offset >= 0 on DCN1 due to OCSC before MPC
2013                          * Blending adds offsets from front + rear to rear plane
2014                          *
2015                          * Fix is to set RGB bias to 0 on rear plane, top plane
2016                          * black value pixels add offset instead of rear + front
2017                          */
2018
2019                         int16_t rgb_bias = matrix[3];
2020                         // matrix[3/7/11] are all the same offset value
2021
2022                         if (rgb_bias > 0 && dcn10_is_rear_mpo_fix_required(pipe_ctx, colorspace)) {
2023                                 dcn10_set_csc_adjustment_rgb_mpo_fix(pipe_ctx, matrix);
2024                         } else {
2025                                 pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, matrix);
2026                         }
2027                 }
2028         } else {
2029                 if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default != NULL)
2030                         pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default(pipe_ctx->plane_res.dpp, colorspace);
2031         }
2032 }
2033
2034 void dcn10_get_surface_visual_confirm_color(
2035                 const struct pipe_ctx *pipe_ctx,
2036                 struct tg_color *color)
2037 {
2038         uint32_t color_value = MAX_TG_COLOR_VALUE;
2039
2040         switch (pipe_ctx->plane_res.scl_data.format) {
2041         case PIXEL_FORMAT_ARGB8888:
2042                 /* set boarder color to red */
2043                 color->color_r_cr = color_value;
2044                 break;
2045
2046         case PIXEL_FORMAT_ARGB2101010:
2047                 /* set boarder color to blue */
2048                 color->color_b_cb = color_value;
2049                 break;
2050         case PIXEL_FORMAT_420BPP8:
2051                 /* set boarder color to green */
2052                 color->color_g_y = color_value;
2053                 break;
2054         case PIXEL_FORMAT_420BPP10:
2055                 /* set boarder color to yellow */
2056                 color->color_g_y = color_value;
2057                 color->color_r_cr = color_value;
2058                 break;
2059         case PIXEL_FORMAT_FP16:
2060                 /* set boarder color to white */
2061                 color->color_r_cr = color_value;
2062                 color->color_b_cb = color_value;
2063                 color->color_g_y = color_value;
2064                 break;
2065         default:
2066                 break;
2067         }
2068 }
2069
2070 void dcn10_get_hdr_visual_confirm_color(
2071                 struct pipe_ctx *pipe_ctx,
2072                 struct tg_color *color)
2073 {
2074         uint32_t color_value = MAX_TG_COLOR_VALUE;
2075
2076         // Determine the overscan color based on the top-most (desktop) plane's context
2077         struct pipe_ctx *top_pipe_ctx  = pipe_ctx;
2078
2079         while (top_pipe_ctx->top_pipe != NULL)
2080                 top_pipe_ctx = top_pipe_ctx->top_pipe;
2081
2082         switch (top_pipe_ctx->plane_res.scl_data.format) {
2083         case PIXEL_FORMAT_ARGB2101010:
2084                 if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_PQ) {
2085                         /* HDR10, ARGB2101010 - set boarder color to red */
2086                         color->color_r_cr = color_value;
2087                 }
2088                 break;
2089         case PIXEL_FORMAT_FP16:
2090                 if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_PQ) {
2091                         /* HDR10, FP16 - set boarder color to blue */
2092                         color->color_b_cb = color_value;
2093                 } else if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22) {
2094                         /* FreeSync 2 HDR - set boarder color to green */
2095                         color->color_g_y = color_value;
2096                 }
2097                 break;
2098         default:
2099                 /* SDR - set boarder color to Gray */
2100                 color->color_r_cr = color_value/2;
2101                 color->color_b_cb = color_value/2;
2102                 color->color_g_y = color_value/2;
2103                 break;
2104         }
2105 }
2106
2107 static void dcn10_update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state)
2108 {
2109         struct dc_bias_and_scale bns_params = {0};
2110
2111         // program the input csc
2112         dpp->funcs->dpp_setup(dpp,
2113                         plane_state->format,
2114                         EXPANSION_MODE_ZERO,
2115                         plane_state->input_csc_color_matrix,
2116                         plane_state->color_space,
2117                         NULL);
2118
2119         //set scale and bias registers
2120         build_prescale_params(&bns_params, plane_state);
2121         if (dpp->funcs->dpp_program_bias_and_scale)
2122                 dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
2123 }
2124
2125 void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
2126 {
2127         struct dce_hwseq *hws = dc->hwseq;
2128         struct hubp *hubp = pipe_ctx->plane_res.hubp;
2129         struct mpcc_blnd_cfg blnd_cfg = {{0}};
2130         bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
2131         int mpcc_id;
2132         struct mpcc *new_mpcc;
2133         struct mpc *mpc = dc->res_pool->mpc;
2134         struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);
2135
2136         if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) {
2137                 hws->funcs.get_hdr_visual_confirm_color(
2138                                 pipe_ctx, &blnd_cfg.black_color);
2139         } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) {
2140                 hws->funcs.get_surface_visual_confirm_color(
2141                                 pipe_ctx, &blnd_cfg.black_color);
2142         } else {
2143                 color_space_to_black_color(
2144                                 dc, pipe_ctx->stream->output_color_space,
2145                                 &blnd_cfg.black_color);
2146         }
2147
2148         if (per_pixel_alpha)
2149                 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;
2150         else
2151                 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA;
2152
2153         blnd_cfg.overlap_only = false;
2154         blnd_cfg.global_gain = 0xff;
2155
2156         if (pipe_ctx->plane_state->global_alpha)
2157                 blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value;
2158         else
2159                 blnd_cfg.global_alpha = 0xff;
2160
2161         /* DCN1.0 has output CM before MPC which seems to screw with
2162          * pre-multiplied alpha.
2163          */
2164         blnd_cfg.pre_multiplied_alpha = is_rgb_cspace(
2165                         pipe_ctx->stream->output_color_space)
2166                                         && per_pixel_alpha;
2167
2168
2169         /*
2170          * TODO: remove hack
2171          * Note: currently there is a bug in init_hw such that
2172          * on resume from hibernate, BIOS sets up MPCC0, and
2173          * we do mpcc_remove but the mpcc cannot go to idle
2174          * after remove. This cause us to pick mpcc1 here,
2175          * which causes a pstate hang for yet unknown reason.
2176          */
2177         mpcc_id = hubp->inst;
2178
2179         /* If there is no full update, don't need to touch MPC tree*/
2180         if (!pipe_ctx->plane_state->update_flags.bits.full_update) {
2181                 mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id);
2182                 return;
2183         }
2184
2185         /* check if this MPCC is already being used */
2186         new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id);
2187         /* remove MPCC if being used */
2188         if (new_mpcc != NULL)
2189                 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc);
2190         else
2191                 if (dc->debug.sanity_checks)
2192                         mpc->funcs->assert_mpcc_idle_before_connect(
2193                                         dc->res_pool->mpc, mpcc_id);
2194
2195         /* Call MPC to insert new plane */
2196         new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,
2197                         mpc_tree_params,
2198                         &blnd_cfg,
2199                         NULL,
2200                         NULL,
2201                         hubp->inst,
2202                         mpcc_id);
2203
2204         ASSERT(new_mpcc != NULL);
2205
2206         hubp->opp_id = pipe_ctx->stream_res.opp->inst;
2207         hubp->mpcc_id = mpcc_id;
2208 }
2209
2210 static void update_scaler(struct pipe_ctx *pipe_ctx)
2211 {
2212         bool per_pixel_alpha =
2213                         pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
2214
2215         pipe_ctx->plane_res.scl_data.lb_params.alpha_en = per_pixel_alpha;
2216         pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
2217         /* scaler configuration */
2218         pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(
2219                         pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);
2220 }
2221
2222 static void dcn10_update_dchubp_dpp(
2223         struct dc *dc,
2224         struct pipe_ctx *pipe_ctx,
2225         struct dc_state *context)
2226 {
2227         struct dce_hwseq *hws = dc->hwseq;
2228         struct hubp *hubp = pipe_ctx->plane_res.hubp;
2229         struct dpp *dpp = pipe_ctx->plane_res.dpp;
2230         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2231         struct plane_size size = plane_state->plane_size;
2232         unsigned int compat_level = 0;
2233
2234         /* depends on DML calculation, DPP clock value may change dynamically */
2235         /* If request max dpp clk is lower than current dispclk, no need to
2236          * divided by 2
2237          */
2238         if (plane_state->update_flags.bits.full_update) {
2239                 bool should_divided_by_2 = context->bw_ctx.bw.dcn.clk.dppclk_khz <=
2240                                 dc->clk_mgr->clks.dispclk_khz / 2;
2241
2242                 dpp->funcs->dpp_dppclk_control(
2243                                 dpp,
2244                                 should_divided_by_2,
2245                                 true);
2246
2247                 if (dc->res_pool->dccg)
2248                         dc->res_pool->dccg->funcs->update_dpp_dto(
2249                                         dc->res_pool->dccg,
2250                                         dpp->inst,
2251                                         pipe_ctx->plane_res.bw.dppclk_khz);
2252                 else
2253                         dc->clk_mgr->clks.dppclk_khz = should_divided_by_2 ?
2254                                                 dc->clk_mgr->clks.dispclk_khz / 2 :
2255                                                         dc->clk_mgr->clks.dispclk_khz;
2256         }
2257
2258         /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG
2259          * VTG is within DCHUBBUB which is commond block share by each pipe HUBP.
2260          * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG
2261          */
2262         if (plane_state->update_flags.bits.full_update) {
2263                 hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst);
2264
2265                 hubp->funcs->hubp_setup(
2266                         hubp,
2267                         &pipe_ctx->dlg_regs,
2268                         &pipe_ctx->ttu_regs,
2269                         &pipe_ctx->rq_regs,
2270                         &pipe_ctx->pipe_dlg_param);
2271                 hubp->funcs->hubp_setup_interdependent(
2272                         hubp,
2273                         &pipe_ctx->dlg_regs,
2274                         &pipe_ctx->ttu_regs);
2275         }
2276
2277         size.surface_size = pipe_ctx->plane_res.scl_data.viewport;
2278
2279         if (plane_state->update_flags.bits.full_update ||
2280                 plane_state->update_flags.bits.bpp_change)
2281                 dcn10_update_dpp(dpp, plane_state);
2282
2283         if (plane_state->update_flags.bits.full_update ||
2284                 plane_state->update_flags.bits.per_pixel_alpha_change ||
2285                 plane_state->update_flags.bits.global_alpha_change)
2286                 hws->funcs.update_mpcc(dc, pipe_ctx);
2287
2288         if (plane_state->update_flags.bits.full_update ||
2289                 plane_state->update_flags.bits.per_pixel_alpha_change ||
2290                 plane_state->update_flags.bits.global_alpha_change ||
2291                 plane_state->update_flags.bits.scaling_change ||
2292                 plane_state->update_flags.bits.position_change) {
2293                 update_scaler(pipe_ctx);
2294         }
2295
2296         if (plane_state->update_flags.bits.full_update ||
2297                 plane_state->update_flags.bits.scaling_change ||
2298                 plane_state->update_flags.bits.position_change) {
2299                 hubp->funcs->mem_program_viewport(
2300                         hubp,
2301                         &pipe_ctx->plane_res.scl_data.viewport,
2302                         &pipe_ctx->plane_res.scl_data.viewport_c);
2303         }
2304
2305         if (pipe_ctx->stream->cursor_attributes.address.quad_part != 0) {
2306                 dc->hwss.set_cursor_position(pipe_ctx);
2307                 dc->hwss.set_cursor_attribute(pipe_ctx);
2308
2309                 if (dc->hwss.set_cursor_sdr_white_level)
2310                         dc->hwss.set_cursor_sdr_white_level(pipe_ctx);
2311         }
2312
2313         if (plane_state->update_flags.bits.full_update) {
2314                 /*gamut remap*/
2315                 dc->hwss.program_gamut_remap(pipe_ctx);
2316
2317                 dc->hwss.program_output_csc(dc,
2318                                 pipe_ctx,
2319                                 pipe_ctx->stream->output_color_space,
2320                                 pipe_ctx->stream->csc_color_matrix.matrix,
2321                                 pipe_ctx->stream_res.opp->inst);
2322         }
2323
2324         if (plane_state->update_flags.bits.full_update ||
2325                 plane_state->update_flags.bits.pixel_format_change ||
2326                 plane_state->update_flags.bits.horizontal_mirror_change ||
2327                 plane_state->update_flags.bits.rotation_change ||
2328                 plane_state->update_flags.bits.swizzle_change ||
2329                 plane_state->update_flags.bits.dcc_change ||
2330                 plane_state->update_flags.bits.bpp_change ||
2331                 plane_state->update_flags.bits.scaling_change ||
2332                 plane_state->update_flags.bits.plane_size_change) {
2333                 hubp->funcs->hubp_program_surface_config(
2334                         hubp,
2335                         plane_state->format,
2336                         &plane_state->tiling_info,
2337                         &size,
2338                         plane_state->rotation,
2339                         &plane_state->dcc,
2340                         plane_state->horizontal_mirror,
2341                         compat_level);
2342         }
2343
2344         hubp->power_gated = false;
2345
2346         hws->funcs.update_plane_addr(dc, pipe_ctx);
2347
2348         if (is_pipe_tree_visible(pipe_ctx))
2349                 hubp->funcs->set_blank(hubp, false);
2350 }
2351
2352 void dcn10_blank_pixel_data(
2353                 struct dc *dc,
2354                 struct pipe_ctx *pipe_ctx,
2355                 bool blank)
2356 {
2357         enum dc_color_space color_space;
2358         struct tg_color black_color = {0};
2359         struct stream_resource *stream_res = &pipe_ctx->stream_res;
2360         struct dc_stream_state *stream = pipe_ctx->stream;
2361
2362         /* program otg blank color */
2363         color_space = stream->output_color_space;
2364         color_space_to_black_color(dc, color_space, &black_color);
2365
2366         /*
2367          * The way 420 is packed, 2 channels carry Y component, 1 channel
2368          * alternate between Cb and Cr, so both channels need the pixel
2369          * value for Y
2370          */
2371         if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
2372                 black_color.color_r_cr = black_color.color_g_y;
2373
2374
2375         if (stream_res->tg->funcs->set_blank_color)
2376                 stream_res->tg->funcs->set_blank_color(
2377                                 stream_res->tg,
2378                                 &black_color);
2379
2380         if (!blank) {
2381                 if (stream_res->tg->funcs->set_blank)
2382                         stream_res->tg->funcs->set_blank(stream_res->tg, blank);
2383                 if (stream_res->abm) {
2384                         stream_res->abm->funcs->set_pipe(stream_res->abm, stream_res->tg->inst + 1);
2385                         stream_res->abm->funcs->set_abm_level(stream_res->abm, stream->abm_level);
2386                 }
2387         } else if (blank) {
2388                 if (stream_res->abm)
2389                         stream_res->abm->funcs->set_abm_immediate_disable(stream_res->abm);
2390                 if (stream_res->tg->funcs->set_blank)
2391                         stream_res->tg->funcs->set_blank(stream_res->tg, blank);
2392         }
2393 }
2394
2395 void dcn10_set_hdr_multiplier(struct pipe_ctx *pipe_ctx)
2396 {
2397         struct fixed31_32 multiplier = pipe_ctx->plane_state->hdr_mult;
2398         uint32_t hw_mult = 0x1f000; // 1.0 default multiplier
2399         struct custom_float_format fmt;
2400
2401         fmt.exponenta_bits = 6;
2402         fmt.mantissa_bits = 12;
2403         fmt.sign = true;
2404
2405
2406         if (!dc_fixpt_eq(multiplier, dc_fixpt_from_int(0))) // check != 0
2407                 convert_to_custom_float_format(multiplier, &fmt, &hw_mult);
2408
2409         pipe_ctx->plane_res.dpp->funcs->dpp_set_hdr_multiplier(
2410                         pipe_ctx->plane_res.dpp, hw_mult);
2411 }
2412
2413 void dcn10_program_pipe(
2414                 struct dc *dc,
2415                 struct pipe_ctx *pipe_ctx,
2416                 struct dc_state *context)
2417 {
2418         struct dce_hwseq *hws = dc->hwseq;
2419
2420         if (pipe_ctx->plane_state->update_flags.bits.full_update)
2421                 dcn10_enable_plane(dc, pipe_ctx, context);
2422
2423         dcn10_update_dchubp_dpp(dc, pipe_ctx, context);
2424
2425         hws->funcs.set_hdr_multiplier(pipe_ctx);
2426
2427         if (pipe_ctx->plane_state->update_flags.bits.full_update ||
2428                         pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
2429                         pipe_ctx->plane_state->update_flags.bits.gamma_change)
2430                 hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);
2431
2432         /* dcn10_translate_regamma_to_hw_format takes 750us to finish
2433          * only do gamma programming for full update.
2434          * TODO: This can be further optimized/cleaned up
2435          * Always call this for now since it does memcmp inside before
2436          * doing heavy calculation and programming
2437          */
2438         if (pipe_ctx->plane_state->update_flags.bits.full_update)
2439                 hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
2440 }
2441
2442 static void dcn10_program_all_pipe_in_tree(
2443                 struct dc *dc,
2444                 struct pipe_ctx *pipe_ctx,
2445                 struct dc_state *context)
2446 {
2447         struct dce_hwseq *hws = dc->hwseq;
2448
2449         if (pipe_ctx->top_pipe == NULL) {
2450                 bool blank = !is_pipe_tree_visible(pipe_ctx);
2451
2452                 pipe_ctx->stream_res.tg->funcs->program_global_sync(
2453                                 pipe_ctx->stream_res.tg,
2454                                 pipe_ctx->pipe_dlg_param.vready_offset,
2455                                 pipe_ctx->pipe_dlg_param.vstartup_start,
2456                                 pipe_ctx->pipe_dlg_param.vupdate_offset,
2457                                 pipe_ctx->pipe_dlg_param.vupdate_width);
2458
2459                 pipe_ctx->stream_res.tg->funcs->set_vtg_params(
2460                                 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
2461
2462                 if (hws->funcs.setup_vupdate_interrupt)
2463                         hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
2464
2465                 hws->funcs.blank_pixel_data(dc, pipe_ctx, blank);
2466         }
2467
2468         if (pipe_ctx->plane_state != NULL)
2469                 hws->funcs.program_pipe(dc, pipe_ctx, context);
2470
2471         if (pipe_ctx->bottom_pipe != NULL && pipe_ctx->bottom_pipe != pipe_ctx)
2472                 dcn10_program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context);
2473 }
2474
2475 static struct pipe_ctx *dcn10_find_top_pipe_for_stream(
2476                 struct dc *dc,
2477                 struct dc_state *context,
2478                 const struct dc_stream_state *stream)
2479 {
2480         int i;
2481
2482         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2483                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2484                 struct pipe_ctx *old_pipe_ctx =
2485                                 &dc->current_state->res_ctx.pipe_ctx[i];
2486
2487                 if (!pipe_ctx->plane_state && !old_pipe_ctx->plane_state)
2488                         continue;
2489
2490                 if (pipe_ctx->stream != stream)
2491                         continue;
2492
2493                 if (!pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe)
2494                         return pipe_ctx;
2495         }
2496         return NULL;
2497 }
2498
2499 void dcn10_apply_ctx_for_surface(
2500                 struct dc *dc,
2501                 const struct dc_stream_state *stream,
2502                 int num_planes,
2503                 struct dc_state *context)
2504 {
2505         struct dce_hwseq *hws = dc->hwseq;
2506         int i;
2507         struct timing_generator *tg;
2508         uint32_t underflow_check_delay_us;
2509         bool removed_pipe[4] = { false };
2510         bool interdependent_update = false;
2511         struct pipe_ctx *top_pipe_to_program =
2512                         dcn10_find_top_pipe_for_stream(dc, context, stream);
2513         DC_LOGGER_INIT(dc->ctx->logger);
2514
2515         if (!top_pipe_to_program)
2516                 return;
2517
2518         tg = top_pipe_to_program->stream_res.tg;
2519
2520         interdependent_update = top_pipe_to_program->plane_state &&
2521                 top_pipe_to_program->plane_state->update_flags.bits.full_update;
2522
2523         underflow_check_delay_us = dc->debug.underflow_assert_delay_us;
2524
2525         if (underflow_check_delay_us != 0xFFFFFFFF && hws->funcs.did_underflow_occur)
2526                 ASSERT(hws->funcs.did_underflow_occur(dc, top_pipe_to_program));
2527
2528         if (interdependent_update)
2529                 dcn10_lock_all_pipes(dc, context, true);
2530         else
2531                 dcn10_pipe_control_lock(dc, top_pipe_to_program, true);
2532
2533         if (underflow_check_delay_us != 0xFFFFFFFF)
2534                 udelay(underflow_check_delay_us);
2535
2536         if (underflow_check_delay_us != 0xFFFFFFFF && hws->funcs.did_underflow_occur)
2537                 ASSERT(hws->funcs.did_underflow_occur(dc, top_pipe_to_program));
2538
2539         if (num_planes == 0) {
2540                 /* OTG blank before remove all front end */
2541                 hws->funcs.blank_pixel_data(dc, top_pipe_to_program, true);
2542         }
2543
2544         /* Disconnect unused mpcc */
2545         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2546                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2547                 struct pipe_ctx *old_pipe_ctx =
2548                                 &dc->current_state->res_ctx.pipe_ctx[i];
2549                 /*
2550                  * Powergate reused pipes that are not powergated
2551                  * fairly hacky right now, using opp_id as indicator
2552                  * TODO: After move dc_post to dc_update, this will
2553                  * be removed.
2554                  */
2555                 if (pipe_ctx->plane_state && !old_pipe_ctx->plane_state) {
2556                         if (old_pipe_ctx->stream_res.tg == tg &&
2557                             old_pipe_ctx->plane_res.hubp &&
2558                             old_pipe_ctx->plane_res.hubp->opp_id != OPP_ID_INVALID)
2559                                 dc->hwss.disable_plane(dc, old_pipe_ctx);
2560                 }
2561
2562                 if ((!pipe_ctx->plane_state ||
2563                      pipe_ctx->stream_res.tg != old_pipe_ctx->stream_res.tg) &&
2564                     old_pipe_ctx->plane_state &&
2565                     old_pipe_ctx->stream_res.tg == tg) {
2566
2567                         hws->funcs.plane_atomic_disconnect(dc, old_pipe_ctx);
2568                         removed_pipe[i] = true;
2569
2570                         DC_LOG_DC("Reset mpcc for pipe %d\n",
2571                                         old_pipe_ctx->pipe_idx);
2572                 }
2573         }
2574
2575         if (num_planes > 0)
2576                 dcn10_program_all_pipe_in_tree(dc, top_pipe_to_program, context);
2577
2578         /* Program secondary blending tree and writeback pipes */
2579         if ((stream->num_wb_info > 0) && (hws->funcs.program_all_writeback_pipes_in_tree))
2580                 hws->funcs.program_all_writeback_pipes_in_tree(dc, stream, context);
2581         if (interdependent_update)
2582                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2583                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2584                         /* Skip inactive pipes and ones already updated */
2585                         if (!pipe_ctx->stream || pipe_ctx->stream == stream ||
2586                             !pipe_ctx->plane_state || !tg->funcs->is_tg_enabled(tg))
2587                                 continue;
2588
2589                         pipe_ctx->plane_res.hubp->funcs->hubp_setup_interdependent(
2590                                 pipe_ctx->plane_res.hubp,
2591                                 &pipe_ctx->dlg_regs,
2592                                 &pipe_ctx->ttu_regs);
2593                 }
2594
2595         if (interdependent_update)
2596                 dcn10_lock_all_pipes(dc, context, false);
2597         else
2598                 dcn10_pipe_control_lock(dc, top_pipe_to_program, false);
2599
2600         if (num_planes == 0)
2601                 false_optc_underflow_wa(dc, stream, tg);
2602
2603         for (i = 0; i < dc->res_pool->pipe_count; i++)
2604                 if (removed_pipe[i])
2605                         dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
2606
2607         for (i = 0; i < dc->res_pool->pipe_count; i++)
2608                 if (removed_pipe[i]) {
2609                         dc->hwss.optimize_bandwidth(dc, context);
2610                         break;
2611                 }
2612
2613         if (dc->hwseq->wa.DEGVIDCN10_254)
2614                 hubbub1_wm_change_req_wa(dc->res_pool->hubbub);
2615 }
2616
2617 static void dcn10_stereo_hw_frame_pack_wa(struct dc *dc, struct dc_state *context)
2618 {
2619         uint8_t i;
2620
2621         for (i = 0; i < context->stream_count; i++) {
2622                 if (context->streams[i]->timing.timing_3d_format
2623                                 == TIMING_3D_FORMAT_HW_FRAME_PACKING) {
2624                         /*
2625                          * Disable stutter
2626                          */
2627                         hubbub1_allow_self_refresh_control(dc->res_pool->hubbub, false);
2628                         break;
2629                 }
2630         }
2631 }
2632
2633 void dcn10_prepare_bandwidth(
2634                 struct dc *dc,
2635                 struct dc_state *context)
2636 {
2637         struct dce_hwseq *hws = dc->hwseq;
2638         struct hubbub *hubbub = dc->res_pool->hubbub;
2639
2640         if (dc->debug.sanity_checks)
2641                 hws->funcs.verify_allow_pstate_change_high(dc);
2642
2643         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
2644                 if (context->stream_count == 0)
2645                         context->bw_ctx.bw.dcn.clk.phyclk_khz = 0;
2646
2647                 dc->clk_mgr->funcs->update_clocks(
2648                                 dc->clk_mgr,
2649                                 context,
2650                                 false);
2651         }
2652
2653         hubbub->funcs->program_watermarks(hubbub,
2654                         &context->bw_ctx.bw.dcn.watermarks,
2655                         dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
2656                         true);
2657         dcn10_stereo_hw_frame_pack_wa(dc, context);
2658
2659         if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE)
2660                 dcn_bw_notify_pplib_of_wm_ranges(dc);
2661
2662         if (dc->debug.sanity_checks)
2663                 hws->funcs.verify_allow_pstate_change_high(dc);
2664 }
2665
2666 void dcn10_optimize_bandwidth(
2667                 struct dc *dc,
2668                 struct dc_state *context)
2669 {
2670         struct dce_hwseq *hws = dc->hwseq;
2671         struct hubbub *hubbub = dc->res_pool->hubbub;
2672
2673         if (dc->debug.sanity_checks)
2674                 hws->funcs.verify_allow_pstate_change_high(dc);
2675
2676         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
2677                 if (context->stream_count == 0)
2678                         context->bw_ctx.bw.dcn.clk.phyclk_khz = 0;
2679
2680                 dc->clk_mgr->funcs->update_clocks(
2681                                 dc->clk_mgr,
2682                                 context,
2683                                 true);
2684         }
2685
2686         hubbub->funcs->program_watermarks(hubbub,
2687                         &context->bw_ctx.bw.dcn.watermarks,
2688                         dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
2689                         true);
2690         dcn10_stereo_hw_frame_pack_wa(dc, context);
2691
2692         if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE)
2693                 dcn_bw_notify_pplib_of_wm_ranges(dc);
2694
2695         if (dc->debug.sanity_checks)
2696                 hws->funcs.verify_allow_pstate_change_high(dc);
2697 }
2698
2699 void dcn10_set_drr(struct pipe_ctx **pipe_ctx,
2700                 int num_pipes, unsigned int vmin, unsigned int vmax,
2701                 unsigned int vmid, unsigned int vmid_frame_number)
2702 {
2703         int i = 0;
2704         struct drr_params params = {0};
2705         // DRR set trigger event mapped to OTG_TRIG_A (bit 11) for manual control flow
2706         unsigned int event_triggers = 0x800;
2707
2708         params.vertical_total_max = vmax;
2709         params.vertical_total_min = vmin;
2710         params.vertical_total_mid = vmid;
2711         params.vertical_total_mid_frame_num = vmid_frame_number;
2712
2713         /* TODO: If multiple pipes are to be supported, you need
2714          * some GSL stuff. Static screen triggers may be programmed differently
2715          * as well.
2716          */
2717         for (i = 0; i < num_pipes; i++) {
2718                 pipe_ctx[i]->stream_res.tg->funcs->set_drr(
2719                         pipe_ctx[i]->stream_res.tg, &params);
2720                 if (vmax != 0 && vmin != 0)
2721                         pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control(
2722                                         pipe_ctx[i]->stream_res.tg,
2723                                         event_triggers);
2724         }
2725 }
2726
2727 void dcn10_get_position(struct pipe_ctx **pipe_ctx,
2728                 int num_pipes,
2729                 struct crtc_position *position)
2730 {
2731         int i = 0;
2732
2733         /* TODO: handle pipes > 1
2734          */
2735         for (i = 0; i < num_pipes; i++)
2736                 pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);
2737 }
2738
2739 void dcn10_set_static_screen_control(struct pipe_ctx **pipe_ctx,
2740                 int num_pipes, const struct dc_static_screen_events *events)
2741 {
2742         unsigned int i;
2743         unsigned int value = 0;
2744
2745         if (events->surface_update)
2746                 value |= 0x80;
2747         if (events->cursor_update)
2748                 value |= 0x2;
2749         if (events->force_trigger)
2750                 value |= 0x1;
2751
2752         for (i = 0; i < num_pipes; i++)
2753                 pipe_ctx[i]->stream_res.tg->funcs->
2754                         set_static_screen_control(pipe_ctx[i]->stream_res.tg, value);
2755 }
2756
2757 static void dcn10_config_stereo_parameters(
2758                 struct dc_stream_state *stream, struct crtc_stereo_flags *flags)
2759 {
2760         enum view_3d_format view_format = stream->view_format;
2761         enum dc_timing_3d_format timing_3d_format =\
2762                         stream->timing.timing_3d_format;
2763         bool non_stereo_timing = false;
2764
2765         if (timing_3d_format == TIMING_3D_FORMAT_NONE ||
2766                 timing_3d_format == TIMING_3D_FORMAT_SIDE_BY_SIDE ||
2767                 timing_3d_format == TIMING_3D_FORMAT_TOP_AND_BOTTOM)
2768                 non_stereo_timing = true;
2769
2770         if (non_stereo_timing == false &&
2771                 view_format == VIEW_3D_FORMAT_FRAME_SEQUENTIAL) {
2772
2773                 flags->PROGRAM_STEREO         = 1;
2774                 flags->PROGRAM_POLARITY       = 1;
2775                 if (timing_3d_format == TIMING_3D_FORMAT_INBAND_FA ||
2776                         timing_3d_format == TIMING_3D_FORMAT_DP_HDMI_INBAND_FA ||
2777                         timing_3d_format == TIMING_3D_FORMAT_SIDEBAND_FA) {
2778                         enum display_dongle_type dongle = \
2779                                         stream->link->ddc->dongle_type;
2780                         if (dongle == DISPLAY_DONGLE_DP_VGA_CONVERTER ||
2781                                 dongle == DISPLAY_DONGLE_DP_DVI_CONVERTER ||
2782                                 dongle == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
2783                                 flags->DISABLE_STEREO_DP_SYNC = 1;
2784                 }
2785                 flags->RIGHT_EYE_POLARITY =\
2786                                 stream->timing.flags.RIGHT_EYE_3D_POLARITY;
2787                 if (timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
2788                         flags->FRAME_PACKED = 1;
2789         }
2790
2791         return;
2792 }
2793
2794 void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc)
2795 {
2796         struct crtc_stereo_flags flags = { 0 };
2797         struct dc_stream_state *stream = pipe_ctx->stream;
2798
2799         dcn10_config_stereo_parameters(stream, &flags);
2800
2801         if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_SIDEBAND_FA) {
2802                 if (!dc_set_generic_gpio_for_stereo(true, dc->ctx->gpio_service))
2803                         dc_set_generic_gpio_for_stereo(false, dc->ctx->gpio_service);
2804         } else {
2805                 dc_set_generic_gpio_for_stereo(false, dc->ctx->gpio_service);
2806         }
2807
2808         pipe_ctx->stream_res.opp->funcs->opp_program_stereo(
2809                 pipe_ctx->stream_res.opp,
2810                 flags.PROGRAM_STEREO == 1 ? true:false,
2811                 &stream->timing);
2812
2813         pipe_ctx->stream_res.tg->funcs->program_stereo(
2814                 pipe_ctx->stream_res.tg,
2815                 &stream->timing,
2816                 &flags);
2817
2818         return;
2819 }
2820
2821 static struct hubp *get_hubp_by_inst(struct resource_pool *res_pool, int mpcc_inst)
2822 {
2823         int i;
2824
2825         for (i = 0; i < res_pool->pipe_count; i++) {
2826                 if (res_pool->hubps[i]->inst == mpcc_inst)
2827                         return res_pool->hubps[i];
2828         }
2829         ASSERT(false);
2830         return NULL;
2831 }
2832
2833 void dcn10_wait_for_mpcc_disconnect(
2834                 struct dc *dc,
2835                 struct resource_pool *res_pool,
2836                 struct pipe_ctx *pipe_ctx)
2837 {
2838         struct dce_hwseq *hws = dc->hwseq;
2839         int mpcc_inst;
2840
2841         if (dc->debug.sanity_checks) {
2842                 hws->funcs.verify_allow_pstate_change_high(dc);
2843         }
2844
2845         if (!pipe_ctx->stream_res.opp)
2846                 return;
2847
2848         for (mpcc_inst = 0; mpcc_inst < MAX_PIPES; mpcc_inst++) {
2849                 if (pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst]) {
2850                         struct hubp *hubp = get_hubp_by_inst(res_pool, mpcc_inst);
2851
2852                         res_pool->mpc->funcs->wait_for_idle(res_pool->mpc, mpcc_inst);
2853                         pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst] = false;
2854                         hubp->funcs->set_blank(hubp, true);
2855                 }
2856         }
2857
2858         if (dc->debug.sanity_checks) {
2859                 hws->funcs.verify_allow_pstate_change_high(dc);
2860         }
2861
2862 }
2863
2864 bool dcn10_dummy_display_power_gating(
2865         struct dc *dc,
2866         uint8_t controller_id,
2867         struct dc_bios *dcb,
2868         enum pipe_gating_control power_gating)
2869 {
2870         return true;
2871 }
2872
2873 void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx)
2874 {
2875         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2876         struct timing_generator *tg = pipe_ctx->stream_res.tg;
2877         bool flip_pending;
2878
2879         if (plane_state == NULL)
2880                 return;
2881
2882         flip_pending = pipe_ctx->plane_res.hubp->funcs->hubp_is_flip_pending(
2883                                         pipe_ctx->plane_res.hubp);
2884
2885         plane_state->status.is_flip_pending = plane_state->status.is_flip_pending || flip_pending;
2886
2887         if (!flip_pending)
2888                 plane_state->status.current_address = plane_state->status.requested_address;
2889
2890         if (plane_state->status.current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2891                         tg->funcs->is_stereo_left_eye) {
2892                 plane_state->status.is_right_eye =
2893                                 !tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);
2894         }
2895 }
2896
2897 void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data)
2898 {
2899         struct hubbub *hubbub = hws->ctx->dc->res_pool->hubbub;
2900
2901         /* In DCN, this programming sequence is owned by the hubbub */
2902         hubbub->funcs->update_dchub(hubbub, dh_data);
2903 }
2904
2905 void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)
2906 {
2907         struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;
2908         struct hubp *hubp = pipe_ctx->plane_res.hubp;
2909         struct dpp *dpp = pipe_ctx->plane_res.dpp;
2910         struct dc_cursor_mi_param param = {
2911                 .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10,
2912                 .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz,
2913                 .viewport = pipe_ctx->plane_res.scl_data.viewport,
2914                 .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz,
2915                 .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert,
2916                 .rotation = pipe_ctx->plane_state->rotation,
2917                 .mirror = pipe_ctx->plane_state->horizontal_mirror
2918         };
2919         bool pipe_split_on = (pipe_ctx->top_pipe != NULL) ||
2920                 (pipe_ctx->bottom_pipe != NULL);
2921
2922         int x_plane = pipe_ctx->plane_state->dst_rect.x;
2923         int y_plane = pipe_ctx->plane_state->dst_rect.y;
2924         int x_pos = pos_cpy.x;
2925         int y_pos = pos_cpy.y;
2926
2927         // translate cursor from stream space to plane space
2928         x_pos = (x_pos - x_plane) * pipe_ctx->plane_state->src_rect.width /
2929                         pipe_ctx->plane_state->dst_rect.width;
2930         y_pos = (y_pos - y_plane) * pipe_ctx->plane_state->src_rect.height /
2931                         pipe_ctx->plane_state->dst_rect.height;
2932
2933         if (x_pos < 0) {
2934                 pos_cpy.x_hotspot -= x_pos;
2935                 x_pos = 0;
2936         }
2937
2938         if (y_pos < 0) {
2939                 pos_cpy.y_hotspot -= y_pos;
2940                 y_pos = 0;
2941         }
2942
2943         pos_cpy.x = (uint32_t)x_pos;
2944         pos_cpy.y = (uint32_t)y_pos;
2945
2946         if (pipe_ctx->plane_state->address.type
2947                         == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
2948                 pos_cpy.enable = false;
2949
2950         // Swap axis and mirror horizontally
2951         if (param.rotation == ROTATION_ANGLE_90) {
2952                 uint32_t temp_x = pos_cpy.x;
2953
2954                 pos_cpy.x = pipe_ctx->plane_res.scl_data.viewport.width -
2955                                 (pos_cpy.y - pipe_ctx->plane_res.scl_data.viewport.x) + pipe_ctx->plane_res.scl_data.viewport.x;
2956                 pos_cpy.y = temp_x;
2957         }
2958         // Swap axis and mirror vertically
2959         else if (param.rotation == ROTATION_ANGLE_270) {
2960                 uint32_t temp_y = pos_cpy.y;
2961                 int viewport_height =
2962                         pipe_ctx->plane_res.scl_data.viewport.height;
2963
2964                 if (pipe_split_on) {
2965                         if (pos_cpy.x > viewport_height) {
2966                                 pos_cpy.x = pos_cpy.x - viewport_height;
2967                                 pos_cpy.y = viewport_height - pos_cpy.x;
2968                         } else {
2969                                 pos_cpy.y = 2 * viewport_height - pos_cpy.x;
2970                         }
2971                 } else
2972                         pos_cpy.y = viewport_height - pos_cpy.x;
2973                 pos_cpy.x = temp_y;
2974         }
2975         // Mirror horizontally and vertically
2976         else if (param.rotation == ROTATION_ANGLE_180) {
2977                 int viewport_width =
2978                         pipe_ctx->plane_res.scl_data.viewport.width;
2979                 int viewport_x =
2980                         pipe_ctx->plane_res.scl_data.viewport.x;
2981
2982                 if (pipe_split_on) {
2983                         if (pos_cpy.x >= viewport_width + viewport_x) {
2984                                 pos_cpy.x = 2 * viewport_width
2985                                                 - pos_cpy.x + 2 * viewport_x;
2986                         } else {
2987                                 uint32_t temp_x = pos_cpy.x;
2988
2989                                 pos_cpy.x = 2 * viewport_x - pos_cpy.x;
2990                                 if (temp_x >= viewport_x +
2991                                         (int)hubp->curs_attr.width || pos_cpy.x
2992                                         <= (int)hubp->curs_attr.width +
2993                                         pipe_ctx->plane_state->src_rect.x) {
2994                                         pos_cpy.x = temp_x + viewport_width;
2995                                 }
2996                         }
2997                 } else {
2998                         pos_cpy.x = viewport_width - pos_cpy.x + 2 * viewport_x;
2999                 }
3000                 pos_cpy.y = pipe_ctx->plane_res.scl_data.viewport.height - pos_cpy.y;
3001         }
3002
3003         hubp->funcs->set_cursor_position(hubp, &pos_cpy, &param);
3004         dpp->funcs->set_cursor_position(dpp, &pos_cpy, &param, hubp->curs_attr.width, hubp->curs_attr.height);
3005 }
3006
3007 void dcn10_set_cursor_attribute(struct pipe_ctx *pipe_ctx)
3008 {
3009         struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;
3010
3011         pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes(
3012                         pipe_ctx->plane_res.hubp, attributes);
3013         pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes(
3014                 pipe_ctx->plane_res.dpp, attributes);
3015 }
3016
3017 void dcn10_set_cursor_sdr_white_level(struct pipe_ctx *pipe_ctx)
3018 {
3019         uint32_t sdr_white_level = pipe_ctx->stream->cursor_attributes.sdr_white_level;
3020         struct fixed31_32 multiplier;
3021         struct dpp_cursor_attributes opt_attr = { 0 };
3022         uint32_t hw_scale = 0x3c00; // 1.0 default multiplier
3023         struct custom_float_format fmt;
3024
3025         if (!pipe_ctx->plane_res.dpp->funcs->set_optional_cursor_attributes)
3026                 return;
3027
3028         fmt.exponenta_bits = 5;
3029         fmt.mantissa_bits = 10;
3030         fmt.sign = true;
3031
3032         if (sdr_white_level > 80) {
3033                 multiplier = dc_fixpt_from_fraction(sdr_white_level, 80);
3034                 convert_to_custom_float_format(multiplier, &fmt, &hw_scale);
3035         }
3036
3037         opt_attr.scale = hw_scale;
3038         opt_attr.bias = 0;
3039
3040         pipe_ctx->plane_res.dpp->funcs->set_optional_cursor_attributes(
3041                         pipe_ctx->plane_res.dpp, &opt_attr);
3042 }
3043
3044 /*
3045  * apply_front_porch_workaround  TODO FPGA still need?
3046  *
3047  * This is a workaround for a bug that has existed since R5xx and has not been
3048  * fixed keep Front porch at minimum 2 for Interlaced mode or 1 for progressive.
3049  */
3050 static void apply_front_porch_workaround(
3051         struct dc_crtc_timing *timing)
3052 {
3053         if (timing->flags.INTERLACE == 1) {
3054                 if (timing->v_front_porch < 2)
3055                         timing->v_front_porch = 2;
3056         } else {
3057                 if (timing->v_front_porch < 1)
3058                         timing->v_front_porch = 1;
3059         }
3060 }
3061
3062 int dcn10_get_vupdate_offset_from_vsync(struct pipe_ctx *pipe_ctx)
3063 {
3064         const struct dc_crtc_timing *dc_crtc_timing = &pipe_ctx->stream->timing;
3065         struct dc_crtc_timing patched_crtc_timing;
3066         int vesa_sync_start;
3067         int asic_blank_end;
3068         int interlace_factor;
3069         int vertical_line_start;
3070
3071         patched_crtc_timing = *dc_crtc_timing;
3072         apply_front_porch_workaround(&patched_crtc_timing);
3073
3074         interlace_factor = patched_crtc_timing.flags.INTERLACE ? 2 : 1;
3075
3076         vesa_sync_start = patched_crtc_timing.v_addressable +
3077                         patched_crtc_timing.v_border_bottom +
3078                         patched_crtc_timing.v_front_porch;
3079
3080         asic_blank_end = (patched_crtc_timing.v_total -
3081                         vesa_sync_start -
3082                         patched_crtc_timing.v_border_top)
3083                         * interlace_factor;
3084
3085         vertical_line_start = asic_blank_end -
3086                         pipe_ctx->pipe_dlg_param.vstartup_start + 1;
3087
3088         return vertical_line_start;
3089 }
3090
3091 static void dcn10_calc_vupdate_position(
3092                 struct dc *dc,
3093                 struct pipe_ctx *pipe_ctx,
3094                 uint32_t *start_line,
3095                 uint32_t *end_line)
3096 {
3097         const struct dc_crtc_timing *dc_crtc_timing = &pipe_ctx->stream->timing;
3098         int vline_int_offset_from_vupdate =
3099                         pipe_ctx->stream->periodic_interrupt0.lines_offset;
3100         int vupdate_offset_from_vsync = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);
3101         int start_position;
3102
3103         if (vline_int_offset_from_vupdate > 0)
3104                 vline_int_offset_from_vupdate--;
3105         else if (vline_int_offset_from_vupdate < 0)
3106                 vline_int_offset_from_vupdate++;
3107
3108         start_position = vline_int_offset_from_vupdate + vupdate_offset_from_vsync;
3109
3110         if (start_position >= 0)
3111                 *start_line = start_position;
3112         else
3113                 *start_line = dc_crtc_timing->v_total + start_position - 1;
3114
3115         *end_line = *start_line + 2;
3116
3117         if (*end_line >= dc_crtc_timing->v_total)
3118                 *end_line = 2;
3119 }
3120
3121 static void dcn10_cal_vline_position(
3122                 struct dc *dc,
3123                 struct pipe_ctx *pipe_ctx,
3124                 enum vline_select vline,
3125                 uint32_t *start_line,
3126                 uint32_t *end_line)
3127 {
3128         enum vertical_interrupt_ref_point ref_point = INVALID_POINT;
3129
3130         if (vline == VLINE0)
3131                 ref_point = pipe_ctx->stream->periodic_interrupt0.ref_point;
3132         else if (vline == VLINE1)
3133                 ref_point = pipe_ctx->stream->periodic_interrupt1.ref_point;
3134
3135         switch (ref_point) {
3136         case START_V_UPDATE:
3137                 dcn10_calc_vupdate_position(
3138                                 dc,
3139                                 pipe_ctx,
3140                                 start_line,
3141                                 end_line);
3142                 break;
3143         case START_V_SYNC:
3144                 // Suppose to do nothing because vsync is 0;
3145                 break;
3146         default:
3147                 ASSERT(0);
3148                 break;
3149         }
3150 }
3151
3152 void dcn10_setup_periodic_interrupt(
3153                 struct dc *dc,
3154                 struct pipe_ctx *pipe_ctx,
3155                 enum vline_select vline)
3156 {
3157         struct timing_generator *tg = pipe_ctx->stream_res.tg;
3158
3159         if (vline == VLINE0) {
3160                 uint32_t start_line = 0;
3161                 uint32_t end_line = 0;
3162
3163                 dcn10_cal_vline_position(dc, pipe_ctx, vline, &start_line, &end_line);
3164
3165                 tg->funcs->setup_vertical_interrupt0(tg, start_line, end_line);
3166
3167         } else if (vline == VLINE1) {
3168                 pipe_ctx->stream_res.tg->funcs->setup_vertical_interrupt1(
3169                                 tg,
3170                                 pipe_ctx->stream->periodic_interrupt1.lines_offset);
3171         }
3172 }
3173
3174 void dcn10_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx)
3175 {
3176         struct timing_generator *tg = pipe_ctx->stream_res.tg;
3177         int start_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);
3178
3179         if (start_line < 0) {
3180                 ASSERT(0);
3181                 start_line = 0;
3182         }
3183
3184         if (tg->funcs->setup_vertical_interrupt2)
3185                 tg->funcs->setup_vertical_interrupt2(tg, start_line);
3186 }
3187
3188 void dcn10_unblank_stream(struct pipe_ctx *pipe_ctx,
3189                 struct dc_link_settings *link_settings)
3190 {
3191         struct encoder_unblank_param params = { { 0 } };
3192         struct dc_stream_state *stream = pipe_ctx->stream;
3193         struct dc_link *link = stream->link;
3194         struct dce_hwseq *hws = link->dc->hwseq;
3195
3196         /* only 3 items below are used by unblank */
3197         params.timing = pipe_ctx->stream->timing;
3198
3199         params.link_settings.link_rate = link_settings->link_rate;
3200
3201         if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
3202                 if (params.timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
3203                         params.timing.pix_clk_100hz /= 2;
3204                 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, &params);
3205         }
3206
3207         if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
3208                 hws->funcs.edp_backlight_control(link, true);
3209         }
3210 }
3211
3212 void dcn10_send_immediate_sdp_message(struct pipe_ctx *pipe_ctx,
3213                                 const uint8_t *custom_sdp_message,
3214                                 unsigned int sdp_message_size)
3215 {
3216         if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
3217                 pipe_ctx->stream_res.stream_enc->funcs->send_immediate_sdp_message(
3218                                 pipe_ctx->stream_res.stream_enc,
3219                                 custom_sdp_message,
3220                                 sdp_message_size);
3221         }
3222 }
3223 enum dc_status dcn10_set_clock(struct dc *dc,
3224                         enum dc_clock_type clock_type,
3225                         uint32_t clk_khz,
3226                         uint32_t stepping)
3227 {
3228         struct dc_state *context = dc->current_state;
3229         struct dc_clock_config clock_cfg = {0};
3230         struct dc_clocks *current_clocks = &context->bw_ctx.bw.dcn.clk;
3231
3232         if (dc->clk_mgr && dc->clk_mgr->funcs->get_clock)
3233                                 dc->clk_mgr->funcs->get_clock(dc->clk_mgr,
3234                                                 context, clock_type, &clock_cfg);
3235
3236         if (!dc->clk_mgr->funcs->get_clock)
3237                 return DC_FAIL_UNSUPPORTED_1;
3238
3239         if (clk_khz > clock_cfg.max_clock_khz)
3240                 return DC_FAIL_CLK_EXCEED_MAX;
3241
3242         if (clk_khz < clock_cfg.min_clock_khz)
3243                 return DC_FAIL_CLK_BELOW_MIN;
3244
3245         if (clk_khz < clock_cfg.bw_requirequired_clock_khz)
3246                 return DC_FAIL_CLK_BELOW_CFG_REQUIRED;
3247
3248         /*update internal request clock for update clock use*/
3249         if (clock_type == DC_CLOCK_TYPE_DISPCLK)
3250                 current_clocks->dispclk_khz = clk_khz;
3251         else if (clock_type == DC_CLOCK_TYPE_DPPCLK)
3252                 current_clocks->dppclk_khz = clk_khz;
3253         else
3254                 return DC_ERROR_UNEXPECTED;
3255
3256         if (dc->clk_mgr && dc->clk_mgr->funcs->update_clocks)
3257                                 dc->clk_mgr->funcs->update_clocks(dc->clk_mgr,
3258                                 context, true);
3259         return DC_OK;
3260
3261 }
3262
3263 void dcn10_get_clock(struct dc *dc,
3264                         enum dc_clock_type clock_type,
3265                         struct dc_clock_config *clock_cfg)
3266 {
3267         struct dc_state *context = dc->current_state;
3268
3269         if (dc->clk_mgr && dc->clk_mgr->funcs->get_clock)
3270                                 dc->clk_mgr->funcs->get_clock(dc->clk_mgr, context, clock_type, clock_cfg);
3271
3272 }