drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27 #include "core_types.h"
  28 #include "resource.h"
  29 #include "custom_float.h"
  30 #include "dcn10_hw_sequencer.h"
  31 #include "dce110/dce110_hw_sequencer.h"
  32 #include "dce/dce_hwseq.h"
  33 #include "abm.h"
  34 #include "dmcu.h"
  35 #include "dcn10_optc.h"
  36 #include "dcn10/dcn10_dpp.h"
  37 #include "dcn10/dcn10_mpc.h"
  38 #include "timing_generator.h"
  39 #include "opp.h"
  40 #include "ipp.h"
  41 #include "mpc.h"
  42 #include "reg_helper.h"
  43 #include "dcn10_hubp.h"
  44 #include "dcn10_hubbub.h"
  45 #include "dcn10_cm_common.h"
  46 #include "dc_link_dp.h"
  47 #include "dccg.h"
  48
  49 #define DC_LOGGER_INIT(logger)
  50
  51 #define CTX \
  52         hws->ctx
  53 #define REG(reg)\
  54         hws->regs->reg
  55
  56 #undef FN
  57 #define FN(reg_name, field_name) \
  58         hws->shifts->field_name, hws->masks->field_name
  59
  60 /*print is 17 wide, first two characters are spaces*/
  61 #define DTN_INFO_MICRO_SEC(ref_cycle) \
  62         print_microsec(dc_ctx, log_ctx, ref_cycle)
  63
  64 void print_microsec(struct dc_context *dc_ctx,
  65         struct dc_log_buffer_ctx *log_ctx,
  66         uint32_t ref_cycle)
  67 {
  68         const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000;
  69         static const unsigned int frac = 1000;
  70         uint32_t us_x10 = (ref_cycle * frac) / ref_clk_mhz;
  71
  72         DTN_INFO("  %11d.%03d",
  73                         us_x10 / frac,
  74                         us_x10 % frac);
  75 }
  76
  77 static void log_mpc_crc(struct dc *dc,
  78         struct dc_log_buffer_ctx *log_ctx)
  79 {
  80         struct dc_context *dc_ctx = dc->ctx;
  81         struct dce_hwseq *hws = dc->hwseq;
  82
  83         if (REG(MPC_CRC_RESULT_GB))
  84                 DTN_INFO("MPC_CRC_RESULT_GB:%d MPC_CRC_RESULT_C:%d MPC_CRC_RESULT_AR:%d\n",
  85                 REG_READ(MPC_CRC_RESULT_GB), REG_READ(MPC_CRC_RESULT_C), REG_READ(MPC_CRC_RESULT_AR));
  86         if (REG(DPP_TOP0_DPP_CRC_VAL_B_A))
  87                 DTN_INFO("DPP_TOP0_DPP_CRC_VAL_B_A:%d DPP_TOP0_DPP_CRC_VAL_R_G:%d\n",
  88                 REG_READ(DPP_TOP0_DPP_CRC_VAL_B_A), REG_READ(DPP_TOP0_DPP_CRC_VAL_R_G));
  89 }
  90
  91 void dcn10_log_hubbub_state(struct dc *dc, struct dc_log_buffer_ctx *log_ctx)
  92 {
  93         struct dc_context *dc_ctx = dc->ctx;
  94         struct dcn_hubbub_wm wm;
  95         int i;
  96
  97         memset(&wm, 0, sizeof(struct dcn_hubbub_wm));
  98         dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm);
  99
 100         DTN_INFO("HUBBUB WM:      data_urgent  pte_meta_urgent"
 101                         "         sr_enter          sr_exit  dram_clk_change\n");
 102
 103         for (i = 0; i < 4; i++) {
 104                 struct dcn_hubbub_wm_set *s;
 105
 106                 s = &wm.sets[i];
 107                 DTN_INFO("WM_Set[%d]:", s->wm_set);
 108                 DTN_INFO_MICRO_SEC(s->data_urgent);
 109                 DTN_INFO_MICRO_SEC(s->pte_meta_urgent);
 110                 DTN_INFO_MICRO_SEC(s->sr_enter);
 111                 DTN_INFO_MICRO_SEC(s->sr_exit);
 112                 DTN_INFO_MICRO_SEC(s->dram_clk_chanage);
 113                 DTN_INFO("\n");
 114         }
 115
 116         DTN_INFO("\n");
 117 }
 118
 119 static void dcn10_log_hubp_states(struct dc *dc, void *log_ctx)
 120 {
 121         struct dc_context *dc_ctx = dc->ctx;
 122         struct resource_pool *pool = dc->res_pool;
 123         int i;
 124
 125         DTN_INFO("HUBP:  format  addr_hi  width  height"
 126                         "  rot  mir  sw_mode  dcc_en  blank_en  ttu_dis  underflow"
 127                         "   min_ttu_vblank       qos_low_wm      qos_high_wm\n");
 128         for (i = 0; i < pool->pipe_count; i++) {
 129                 struct hubp *hubp = pool->hubps[i];
 130                 struct dcn_hubp_state *s = &(TO_DCN10_HUBP(hubp)->state);
 131
 132                 hubp->funcs->hubp_read_state(hubp);
 133
 134                 if (!s->blank_en) {
 135                         DTN_INFO("[%2d]:  %5xh  %6xh  %5d  %6d  %2xh  %2xh  %6xh"
 136                                         "  %6d  %8d  %7d  %8xh",
 137                                         hubp->inst,
 138                                         s->pixel_format,
 139                                         s->inuse_addr_hi,
 140                                         s->viewport_width,
 141                                         s->viewport_height,
 142                                         s->rotation_angle,
 143                                         s->h_mirror_en,
 144                                         s->sw_mode,
 145                                         s->dcc_en,
 146                                         s->blank_en,
 147                                         s->ttu_disable,
 148                                         s->underflow_status);
 149                         DTN_INFO_MICRO_SEC(s->min_ttu_vblank);
 150                         DTN_INFO_MICRO_SEC(s->qos_level_low_wm);
 151                         DTN_INFO_MICRO_SEC(s->qos_level_high_wm);
 152                         DTN_INFO("\n");
 153                 }
 154         }
 155
 156         DTN_INFO("\n=========RQ========\n");
 157         DTN_INFO("HUBP:  drq_exp_m  prq_exp_m  mrq_exp_m  crq_exp_m  plane1_ba  L:chunk_s  min_chu_s  meta_ch_s"
 158                 "  min_m_c_s  dpte_gr_s  mpte_gr_s  swath_hei  pte_row_h  C:chunk_s  min_chu_s  meta_ch_s"
 159                 "  min_m_c_s  dpte_gr_s  mpte_gr_s  swath_hei  pte_row_h\n");
 160         for (i = 0; i < pool->pipe_count; i++) {
 161                 struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);
 162                 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;
 163
 164                 if (!s->blank_en)
 165                         DTN_INFO("[%2d]:  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh\n",
 166                                 pool->hubps[i]->inst, rq_regs->drq_expansion_mode, rq_regs->prq_expansion_mode, rq_regs->mrq_expansion_mode,
 167                                 rq_regs->crq_expansion_mode, rq_regs->plane1_base_address, rq_regs->rq_regs_l.chunk_size,
 168                                 rq_regs->rq_regs_l.min_chunk_size, rq_regs->rq_regs_l.meta_chunk_size,
 169                                 rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs->rq_regs_l.dpte_group_size,
 170                                 rq_regs->rq_regs_l.mpte_group_size, rq_regs->rq_regs_l.swath_height,
 171                                 rq_regs->rq_regs_l.pte_row_height_linear, rq_regs->rq_regs_c.chunk_size, rq_regs->rq_regs_c.min_chunk_size,
 172                                 rq_regs->rq_regs_c.meta_chunk_size, rq_regs->rq_regs_c.min_meta_chunk_size,
 173                                 rq_regs->rq_regs_c.dpte_group_size, rq_regs->rq_regs_c.mpte_group_size,
 174                                 rq_regs->rq_regs_c.swath_height, rq_regs->rq_regs_c.pte_row_height_linear);
 175         }
 176
 177         DTN_INFO("========DLG========\n");
 178         DTN_INFO("HUBP:  rc_hbe     dlg_vbe    min_d_y_n  rc_per_ht  rc_x_a_s "
 179                         "  dst_y_a_s  dst_y_pf   dst_y_vvb  dst_y_rvb  dst_y_vfl  dst_y_rfl  rf_pix_fq"
 180                         "  vratio_pf  vrat_pf_c  rc_pg_vbl  rc_pg_vbc  rc_mc_vbl  rc_mc_vbc  rc_pg_fll"
 181                         "  rc_pg_flc  rc_mc_fll  rc_mc_flc  pr_nom_l   pr_nom_c   rc_pg_nl   rc_pg_nc "
 182                         "  mr_nom_l   mr_nom_c   rc_mc_nl   rc_mc_nc   rc_ld_pl   rc_ld_pc   rc_ld_l  "
 183                         "  rc_ld_c    cha_cur0   ofst_cur1  cha_cur1   vr_af_vc0  ddrq_limt  x_rt_dlay"
 184                         "  x_rp_dlay  x_rr_sfl\n");
 185         for (i = 0; i < pool->pipe_count; i++) {
 186                 struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);
 187                 struct _vcs_dpi_display_dlg_regs_st *dlg_regs = &s->dlg_attr;
 188
 189                 if (!s->blank_en)
 190                         DTN_INFO("[%2d]:  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh"
 191                                 "%  8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh"
 192                                 "  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh\n",
 193                                 pool->hubps[i]->inst, dlg_regs->refcyc_h_blank_end, dlg_regs->dlg_vblank_end, dlg_regs->min_dst_y_next_start,
 194                                 dlg_regs->refcyc_per_htotal, dlg_regs->refcyc_x_after_scaler, dlg_regs->dst_y_after_scaler,
 195                                 dlg_regs->dst_y_prefetch, dlg_regs->dst_y_per_vm_vblank, dlg_regs->dst_y_per_row_vblank,
 196                                 dlg_regs->dst_y_per_vm_flip, dlg_regs->dst_y_per_row_flip, dlg_regs->ref_freq_to_pix_freq,
 197                                 dlg_regs->vratio_prefetch, dlg_regs->vratio_prefetch_c, dlg_regs->refcyc_per_pte_group_vblank_l,
 198                                 dlg_regs->refcyc_per_pte_group_vblank_c, dlg_regs->refcyc_per_meta_chunk_vblank_l,
 199                                 dlg_regs->refcyc_per_meta_chunk_vblank_c, dlg_regs->refcyc_per_pte_group_flip_l,
 200                                 dlg_regs->refcyc_per_pte_group_flip_c, dlg_regs->refcyc_per_meta_chunk_flip_l,
 201                                 dlg_regs->refcyc_per_meta_chunk_flip_c, dlg_regs->dst_y_per_pte_row_nom_l,
 202                                 dlg_regs->dst_y_per_pte_row_nom_c, dlg_regs->refcyc_per_pte_group_nom_l,
 203                                 dlg_regs->refcyc_per_pte_group_nom_c, dlg_regs->dst_y_per_meta_row_nom_l,
 204                                 dlg_regs->dst_y_per_meta_row_nom_c, dlg_regs->refcyc_per_meta_chunk_nom_l,
 205                                 dlg_regs->refcyc_per_meta_chunk_nom_c, dlg_regs->refcyc_per_line_delivery_pre_l,
 206                                 dlg_regs->refcyc_per_line_delivery_pre_c, dlg_regs->refcyc_per_line_delivery_l,
 207                                 dlg_regs->refcyc_per_line_delivery_c, dlg_regs->chunk_hdl_adjust_cur0, dlg_regs->dst_y_offset_cur1,
 208                                 dlg_regs->chunk_hdl_adjust_cur1, dlg_regs->vready_after_vcount0, dlg_regs->dst_y_delta_drq_limit,
 209                                 dlg_regs->xfc_reg_transfer_delay, dlg_regs->xfc_reg_precharge_delay,
 210                                 dlg_regs->xfc_reg_remote_surface_flip_latency);
 211         }
 212
 213         DTN_INFO("========TTU========\n");
 214         DTN_INFO("HUBP:  qos_ll_wm  qos_lh_wm  mn_ttu_vb  qos_l_flp  rc_rd_p_l  rc_rd_l    rc_rd_p_c"
 215                         "  rc_rd_c    rc_rd_c0   rc_rd_pc0  rc_rd_c1   rc_rd_pc1  qos_lf_l   qos_rds_l"
 216                         "  qos_lf_c   qos_rds_c  qos_lf_c0  qos_rds_c0 qos_lf_c1  qos_rds_c1\n");
 217         for (i = 0; i < pool->pipe_count; i++) {
 218                 struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);
 219                 struct _vcs_dpi_display_ttu_regs_st *ttu_regs = &s->ttu_attr;
 220
 221                 if (!s->blank_en)
 222                         DTN_INFO("[%2d]:  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh\n",
 223                                 pool->hubps[i]->inst, ttu_regs->qos_level_low_wm, ttu_regs->qos_level_high_wm, ttu_regs->min_ttu_vblank,
 224                                 ttu_regs->qos_level_flip, ttu_regs->refcyc_per_req_delivery_pre_l, ttu_regs->refcyc_per_req_delivery_l,
 225                                 ttu_regs->refcyc_per_req_delivery_pre_c, ttu_regs->refcyc_per_req_delivery_c, ttu_regs->refcyc_per_req_delivery_cur0,
 226                                 ttu_regs->refcyc_per_req_delivery_pre_cur0, ttu_regs->refcyc_per_req_delivery_cur1,
 227                                 ttu_regs->refcyc_per_req_delivery_pre_cur1, ttu_regs->qos_level_fixed_l, ttu_regs->qos_ramp_disable_l,
 228                                 ttu_regs->qos_level_fixed_c, ttu_regs->qos_ramp_disable_c, ttu_regs->qos_level_fixed_cur0,
 229                                 ttu_regs->qos_ramp_disable_cur0, ttu_regs->qos_level_fixed_cur1, ttu_regs->qos_ramp_disable_cur1);
 230         }
 231         DTN_INFO("\n");
 232 }
 233
 234 void dcn10_log_hw_state(struct dc *dc,
 235         struct dc_log_buffer_ctx *log_ctx)
 236 {
 237         struct dc_context *dc_ctx = dc->ctx;
 238         struct resource_pool *pool = dc->res_pool;
 239         int i;
 240
 241         DTN_INFO_BEGIN();
 242
 243         dcn10_log_hubbub_state(dc, log_ctx);
 244
 245         dcn10_log_hubp_states(dc, log_ctx);
 246
 247         DTN_INFO("DPP:    IGAM format  IGAM mode    DGAM mode    RGAM mode"
 248                         "  GAMUT mode  C11 C12   C13 C14   C21 C22   C23 C24   "
 249                         "C31 C32   C33 C34\n");
 250         for (i = 0; i < pool->pipe_count; i++) {
 251                 struct dpp *dpp = pool->dpps[i];
 252                 struct dcn_dpp_state s = {0};
 253
 254                 dpp->funcs->dpp_read_state(dpp, &s);
 255
 256                 if (!s.is_enabled)
 257                         continue;
 258
 259                 DTN_INFO("[%2d]:  %11xh  %-11s  %-11s  %-11s"
 260                                 "%8x    %08xh %08xh %08xh %08xh %08xh %08xh",
 261                                 dpp->inst,
 262                                 s.igam_input_format,
 263                                 (s.igam_lut_mode == 0) ? "BypassFixed" :
 264                                         ((s.igam_lut_mode == 1) ? "BypassFloat" :
 265                                         ((s.igam_lut_mode == 2) ? "RAM" :
 266                                         ((s.igam_lut_mode == 3) ? "RAM" :
 267                                                                  "Unknown"))),
 268                                 (s.dgam_lut_mode == 0) ? "Bypass" :
 269                                         ((s.dgam_lut_mode == 1) ? "sRGB" :
 270                                         ((s.dgam_lut_mode == 2) ? "Ycc" :
 271                                         ((s.dgam_lut_mode == 3) ? "RAM" :
 272                                         ((s.dgam_lut_mode == 4) ? "RAM" :
 273                                                                  "Unknown")))),
 274                                 (s.rgam_lut_mode == 0) ? "Bypass" :
 275                                         ((s.rgam_lut_mode == 1) ? "sRGB" :
 276                                         ((s.rgam_lut_mode == 2) ? "Ycc" :
 277                                         ((s.rgam_lut_mode == 3) ? "RAM" :
 278                                         ((s.rgam_lut_mode == 4) ? "RAM" :
 279                                                                  "Unknown")))),
 280                                 s.gamut_remap_mode,
 281                                 s.gamut_remap_c11_c12,
 282                                 s.gamut_remap_c13_c14,
 283                                 s.gamut_remap_c21_c22,
 284                                 s.gamut_remap_c23_c24,
 285                                 s.gamut_remap_c31_c32,
 286                                 s.gamut_remap_c33_c34);
 287                 DTN_INFO("\n");
 288         }
 289         DTN_INFO("\n");
 290
 291         DTN_INFO("MPCC:  OPP  DPP  MPCCBOT  MODE  ALPHA_MODE  PREMULT  OVERLAP_ONLY  IDLE\n");
 292         for (i = 0; i < pool->pipe_count; i++) {
 293                 struct mpcc_state s = {0};
 294
 295                 pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s);
 296                 if (s.opp_id != 0xf)
 297                         DTN_INFO("[%2d]:  %2xh  %2xh  %6xh  %4d  %10d  %7d  %12d  %4d\n",
 298                                 i, s.opp_id, s.dpp_id, s.bot_mpcc_id,
 299                                 s.mode, s.alpha_mode, s.pre_multiplied_alpha, s.overlap_only,
 300                                 s.idle);
 301         }
 302         DTN_INFO("\n");
 303
 304         DTN_INFO("OTG:  v_bs  v_be  v_ss  v_se  vpol  vmax  vmin  vmax_sel  vmin_sel"
 305                         "  h_bs  h_be  h_ss  h_se  hpol  htot  vtot  underflow\n");
 306
 307         for (i = 0; i < pool->timing_generator_count; i++) {
 308                 struct timing_generator *tg = pool->timing_generators[i];
 309                 struct dcn_otg_state s = {0};
 310
 311                 optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s);
 312
 313                 //only print if OTG master is enabled
 314                 if ((s.otg_enabled & 1) == 0)
 315                         continue;
 316
 317                 DTN_INFO("[%d]: %5d %5d %5d %5d %5d %5d %5d %9d %9d %5d %5d %5d"
 318                                 " %5d %5d %5d %5d  %9d\n",
 319                                 tg->inst,
 320                                 s.v_blank_start,
 321                                 s.v_blank_end,
 322                                 s.v_sync_a_start,
 323                                 s.v_sync_a_end,
 324                                 s.v_sync_a_pol,
 325                                 s.v_total_max,
 326                                 s.v_total_min,
 327                                 s.v_total_max_sel,
 328                                 s.v_total_min_sel,
 329                                 s.h_blank_start,
 330                                 s.h_blank_end,
 331                                 s.h_sync_a_start,
 332                                 s.h_sync_a_end,
 333                                 s.h_sync_a_pol,
 334                                 s.h_total,
 335                                 s.v_total,
 336                                 s.underflow_occurred_status);
 337
 338                 // Clear underflow for debug purposes
 339                 // We want to keep underflow sticky bit on for the longevity tests outside of test environment.
 340                 // This function is called only from Windows or Diags test environment, hence it's safe to clear
 341                 // it from here without affecting the original intent.
 342                 tg->funcs->clear_optc_underflow(tg);
 343         }
 344         DTN_INFO("\n");
 345
 346         DTN_INFO("\nCALCULATED Clocks: dcfclk_khz:%d  dcfclk_deep_sleep_khz:%d  dispclk_khz:%d\n"
 347                 "dppclk_khz:%d  max_supported_dppclk_khz:%d  fclk_khz:%d  socclk_khz:%d\n\n",
 348                         dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_khz,
 349                         dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz,
 350                         dc->current_state->bw_ctx.bw.dcn.clk.dispclk_khz,
 351                         dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz,
 352                         dc->current_state->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz,
 353                         dc->current_state->bw_ctx.bw.dcn.clk.fclk_khz,
 354                         dc->current_state->bw_ctx.bw.dcn.clk.socclk_khz);
 355
 356         log_mpc_crc(dc, log_ctx);
 357
 358         DTN_INFO_END();
 359 }
 360
 361 static void enable_power_gating_plane(
 362         struct dce_hwseq *hws,
 363         bool enable)
 364 {
 365         bool force_on = 1; /* disable power gating */
 366
 367         if (enable)
 368                 force_on = 0;
 369
 370         /* DCHUBP0/1/2/3 */
 371         REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on);
 372         REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on);
 373         REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on);
 374         REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on);
 375
 376         /* DPP0/1/2/3 */
 377         REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on);
 378         REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on);
 379         REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on);
 380         REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);
 381 }
 382
 383 static void disable_vga(
 384         struct dce_hwseq *hws)
 385 {
 386         unsigned int in_vga1_mode = 0;
 387         unsigned int in_vga2_mode = 0;
 388         unsigned int in_vga3_mode = 0;
 389         unsigned int in_vga4_mode = 0;
 390
 391         REG_GET(D1VGA_CONTROL, D1VGA_MODE_ENABLE, &in_vga1_mode);
 392         REG_GET(D2VGA_CONTROL, D2VGA_MODE_ENABLE, &in_vga2_mode);
 393         REG_GET(D3VGA_CONTROL, D3VGA_MODE_ENABLE, &in_vga3_mode);
 394         REG_GET(D4VGA_CONTROL, D4VGA_MODE_ENABLE, &in_vga4_mode);
 395
 396         if (in_vga1_mode == 0 && in_vga2_mode == 0 &&
 397                         in_vga3_mode == 0 && in_vga4_mode == 0)
 398                 return;
 399
 400         REG_WRITE(D1VGA_CONTROL, 0);
 401         REG_WRITE(D2VGA_CONTROL, 0);
 402         REG_WRITE(D3VGA_CONTROL, 0);
 403         REG_WRITE(D4VGA_CONTROL, 0);
 404
 405         /* HW Engineer's Notes:
 406          *  During switch from vga->extended, if we set the VGA_TEST_ENABLE and
 407          *  then hit the VGA_TEST_RENDER_START, then the DCHUBP timing gets updated correctly.
 408          *
 409          *  Then vBIOS will have it poll for the VGA_TEST_RENDER_DONE and unset
 410          *  VGA_TEST_ENABLE, to leave it in the same state as before.
 411          */
 412         REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_ENABLE, 1);
 413         REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_RENDER_START, 1);
 414 }
 415
 416 static void dpp_pg_control(
 417                 struct dce_hwseq *hws,
 418                 unsigned int dpp_inst,
 419                 bool power_on)
 420 {
 421         uint32_t power_gate = power_on ? 0 : 1;
 422         uint32_t pwr_status = power_on ? 0 : 2;
 423
 424         if (hws->ctx->dc->debug.disable_dpp_power_gate)
 425                 return;
 426         if (REG(DOMAIN1_PG_CONFIG) == 0)
 427                 return;
 428
 429         switch (dpp_inst) {
 430         case 0: /* DPP0 */
 431                 REG_UPDATE(DOMAIN1_PG_CONFIG,
 432                                 DOMAIN1_POWER_GATE, power_gate);
 433
 434                 REG_WAIT(DOMAIN1_PG_STATUS,
 435                                 DOMAIN1_PGFSM_PWR_STATUS, pwr_status,
 436                                 1, 1000);
 437                 break;
 438         case 1: /* DPP1 */
 439                 REG_UPDATE(DOMAIN3_PG_CONFIG,
 440                                 DOMAIN3_POWER_GATE, power_gate);
 441
 442                 REG_WAIT(DOMAIN3_PG_STATUS,
 443                                 DOMAIN3_PGFSM_PWR_STATUS, pwr_status,
 444                                 1, 1000);
 445                 break;
 446         case 2: /* DPP2 */
 447                 REG_UPDATE(DOMAIN5_PG_CONFIG,
 448                                 DOMAIN5_POWER_GATE, power_gate);
 449
 450                 REG_WAIT(DOMAIN5_PG_STATUS,
 451                                 DOMAIN5_PGFSM_PWR_STATUS, pwr_status,
 452                                 1, 1000);
 453                 break;
 454         case 3: /* DPP3 */
 455                 REG_UPDATE(DOMAIN7_PG_CONFIG,
 456                                 DOMAIN7_POWER_GATE, power_gate);
 457
 458                 REG_WAIT(DOMAIN7_PG_STATUS,
 459                                 DOMAIN7_PGFSM_PWR_STATUS, pwr_status,
 460                                 1, 1000);
 461                 break;
 462         default:
 463                 BREAK_TO_DEBUGGER();
 464                 break;
 465         }
 466 }
 467
 468 static void hubp_pg_control(
 469                 struct dce_hwseq *hws,
 470                 unsigned int hubp_inst,
 471                 bool power_on)
 472 {
 473         uint32_t power_gate = power_on ? 0 : 1;
 474         uint32_t pwr_status = power_on ? 0 : 2;
 475
 476         if (hws->ctx->dc->debug.disable_hubp_power_gate)
 477                 return;
 478         if (REG(DOMAIN0_PG_CONFIG) == 0)
 479                 return;
 480
 481         switch (hubp_inst) {
 482         case 0: /* DCHUBP0 */
 483                 REG_UPDATE(DOMAIN0_PG_CONFIG,
 484                                 DOMAIN0_POWER_GATE, power_gate);
 485
 486                 REG_WAIT(DOMAIN0_PG_STATUS,
 487                                 DOMAIN0_PGFSM_PWR_STATUS, pwr_status,
 488                                 1, 1000);
 489                 break;
 490         case 1: /* DCHUBP1 */
 491                 REG_UPDATE(DOMAIN2_PG_CONFIG,
 492                                 DOMAIN2_POWER_GATE, power_gate);
 493
 494                 REG_WAIT(DOMAIN2_PG_STATUS,
 495                                 DOMAIN2_PGFSM_PWR_STATUS, pwr_status,
 496                                 1, 1000);
 497                 break;
 498         case 2: /* DCHUBP2 */
 499                 REG_UPDATE(DOMAIN4_PG_CONFIG,
 500                                 DOMAIN4_POWER_GATE, power_gate);
 501
 502                 REG_WAIT(DOMAIN4_PG_STATUS,
 503                                 DOMAIN4_PGFSM_PWR_STATUS, pwr_status,
 504                                 1, 1000);
 505                 break;
 506         case 3: /* DCHUBP3 */
 507                 REG_UPDATE(DOMAIN6_PG_CONFIG,
 508                                 DOMAIN6_POWER_GATE, power_gate);
 509
 510                 REG_WAIT(DOMAIN6_PG_STATUS,
 511                                 DOMAIN6_PGFSM_PWR_STATUS, pwr_status,
 512                                 1, 1000);
 513                 break;
 514         default:
 515                 BREAK_TO_DEBUGGER();
 516                 break;
 517         }
 518 }
 519
 520 static void power_on_plane(
 521         struct dce_hwseq *hws,
 522         int plane_id)
 523 {
 524         DC_LOGGER_INIT(hws->ctx->logger);
 525         if (REG(DC_IP_REQUEST_CNTL)) {
 526                 REG_SET(DC_IP_REQUEST_CNTL, 0,
 527                                 IP_REQUEST_EN, 1);
 528                 dpp_pg_control(hws, plane_id, true);
 529                 hubp_pg_control(hws, plane_id, true);
 530                 REG_SET(DC_IP_REQUEST_CNTL, 0,
 531                                 IP_REQUEST_EN, 0);
 532                 DC_LOG_DEBUG(
 533                                 "Un-gated front end for pipe %d\n", plane_id);
 534         }
 535 }
 536
 537 static void undo_DEGVIDCN10_253_wa(struct dc *dc)
 538 {
 539         struct dce_hwseq *hws = dc->hwseq;
 540         struct hubp *hubp = dc->res_pool->hubps[0];
 541
 542         if (!hws->wa_state.DEGVIDCN10_253_applied)
 543                 return;
 544
 545         hubp->funcs->set_blank(hubp, true);
 546
 547         REG_SET(DC_IP_REQUEST_CNTL, 0,
 548                         IP_REQUEST_EN, 1);
 549
 550         hubp_pg_control(hws, 0, false);
 551         REG_SET(DC_IP_REQUEST_CNTL, 0,
 552                         IP_REQUEST_EN, 0);
 553
 554         hws->wa_state.DEGVIDCN10_253_applied = false;
 555 }
 556
 557 static void apply_DEGVIDCN10_253_wa(struct dc *dc)
 558 {
 559         struct dce_hwseq *hws = dc->hwseq;
 560         struct hubp *hubp = dc->res_pool->hubps[0];
 561         int i;
 562
 563         if (dc->debug.disable_stutter)
 564                 return;
 565
 566         if (!hws->wa.DEGVIDCN10_253)
 567                 return;
 568
 569         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 570                 if (!dc->res_pool->hubps[i]->power_gated)
 571                         return;
 572         }
 573
 574         /* all pipe power gated, apply work around to enable stutter. */
 575
 576         REG_SET(DC_IP_REQUEST_CNTL, 0,
 577                         IP_REQUEST_EN, 1);
 578
 579         hubp_pg_control(hws, 0, true);
 580         REG_SET(DC_IP_REQUEST_CNTL, 0,
 581                         IP_REQUEST_EN, 0);
 582
 583         hubp->funcs->set_hubp_blank_en(hubp, false);
 584         hws->wa_state.DEGVIDCN10_253_applied = true;
 585 }
 586
 587 static void bios_golden_init(struct dc *dc)
 588 {
 589         struct dc_bios *bp = dc->ctx->dc_bios;
 590         int i;
 591
 592         /* initialize dcn global */
 593         bp->funcs->enable_disp_power_gating(bp,
 594                         CONTROLLER_ID_D0, ASIC_PIPE_INIT);
 595
 596         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 597                 /* initialize dcn per pipe */
 598                 bp->funcs->enable_disp_power_gating(bp,
 599                                 CONTROLLER_ID_D0 + i, ASIC_PIPE_DISABLE);
 600         }
 601 }
 602
 603 static void false_optc_underflow_wa(
 604                 struct dc *dc,
 605                 const struct dc_stream_state *stream,
 606                 struct timing_generator *tg)
 607 {
 608         int i;
 609         bool underflow;
 610
 611         if (!dc->hwseq->wa.false_optc_underflow)
 612                 return;
 613
 614         underflow = tg->funcs->is_optc_underflow_occurred(tg);
 615
 616         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 617                 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
 618
 619                 if (old_pipe_ctx->stream != stream)
 620                         continue;
 621
 622                 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, old_pipe_ctx);
 623         }
 624
 625         tg->funcs->set_blank_data_double_buffer(tg, true);
 626
 627         if (tg->funcs->is_optc_underflow_occurred(tg) && !underflow)
 628                 tg->funcs->clear_optc_underflow(tg);
 629 }
 630
 631 static enum dc_status dcn10_enable_stream_timing(
 632                 struct pipe_ctx *pipe_ctx,
 633                 struct dc_state *context,
 634                 struct dc *dc)
 635 {
 636         struct dc_stream_state *stream = pipe_ctx->stream;
 637         enum dc_color_space color_space;
 638         struct tg_color black_color = {0};
 639
 640         /* by upper caller loop, pipe0 is parent pipe and be called first.
 641          * back end is set up by for pipe0. Other children pipe share back end
 642          * with pipe 0. No program is needed.
 643          */
 644         if (pipe_ctx->top_pipe != NULL)
 645                 return DC_OK;
 646
 647         /* TODO check if timing_changed, disable stream if timing changed */
 648
 649         /* HW program guide assume display already disable
 650          * by unplug sequence. OTG assume stop.
 651          */
 652         pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true);
 653
 654         if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
 655                         pipe_ctx->clock_source,
 656                         &pipe_ctx->stream_res.pix_clk_params,
 657                         &pipe_ctx->pll_settings)) {
 658                 BREAK_TO_DEBUGGER();
 659                 return DC_ERROR_UNEXPECTED;
 660         }
 661         pipe_ctx->stream_res.tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset;
 662         pipe_ctx->stream_res.tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start;
 663         pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset;
 664         pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_width = pipe_ctx->pipe_dlg_param.vupdate_width;
 665
 666         pipe_ctx->stream_res.tg->dlg_otg_param.signal =  pipe_ctx->stream->signal;
 667
 668         pipe_ctx->stream_res.tg->funcs->program_timing(
 669                         pipe_ctx->stream_res.tg,
 670                         &stream->timing,
 671                         true);
 672
 673 #if 0 /* move to after enable_crtc */
 674         /* TODO: OPP FMT, ABM. etc. should be done here. */
 675         /* or FPGA now. instance 0 only. TODO: move to opp.c */
 676
 677         inst_offset = reg_offsets[pipe_ctx->stream_res.tg->inst].fmt;
 678
 679         pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
 680                                 pipe_ctx->stream_res.opp,
 681                                 &stream->bit_depth_params,
 682                                 &stream->clamping);
 683 #endif
 684         /* program otg blank color */
 685         color_space = stream->output_color_space;
 686         color_space_to_black_color(dc, color_space, &black_color);
 687
 688         if (pipe_ctx->stream_res.tg->funcs->set_blank_color)
 689                 pipe_ctx->stream_res.tg->funcs->set_blank_color(
 690                                 pipe_ctx->stream_res.tg,
 691                                 &black_color);
 692
 693         if (pipe_ctx->stream_res.tg->funcs->is_blanked &&
 694                         !pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg)) {
 695                 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);
 696                 hwss_wait_for_blank_complete(pipe_ctx->stream_res.tg);
 697                 false_optc_underflow_wa(dc, pipe_ctx->stream, pipe_ctx->stream_res.tg);
 698         }
 699
 700         /* VTG is  within DCHUB command block. DCFCLK is always on */
 701         if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {
 702                 BREAK_TO_DEBUGGER();
 703                 return DC_ERROR_UNEXPECTED;
 704         }
 705
 706         /* TODO program crtc source select for non-virtual signal*/
 707         /* TODO program FMT */
 708         /* TODO setup link_enc */
 709         /* TODO set stream attributes */
 710         /* TODO program audio */
 711         /* TODO enable stream if timing changed */
 712         /* TODO unblank stream if DP */
 713
 714         return DC_OK;
 715 }
 716
 717 static void dcn10_reset_back_end_for_pipe(
 718                 struct dc *dc,
 719                 struct pipe_ctx *pipe_ctx,
 720                 struct dc_state *context)
 721 {
 722         int i;
 723         DC_LOGGER_INIT(dc->ctx->logger);
 724         if (pipe_ctx->stream_res.stream_enc == NULL) {
 725                 pipe_ctx->stream = NULL;
 726                 return;
 727         }
 728
 729         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
 730                 /* DPMS may already disable */
 731                 if (!pipe_ctx->stream->dpms_off)
 732                         core_link_disable_stream(pipe_ctx, FREE_ACQUIRED_RESOURCE);
 733                 else if (pipe_ctx->stream_res.audio) {
 734                         dc->hwss.disable_audio_stream(pipe_ctx, FREE_ACQUIRED_RESOURCE);
 735                 }
 736
 737         }
 738
 739         /* by upper caller loop, parent pipe: pipe0, will be reset last.
 740          * back end share by all pipes and will be disable only when disable
 741          * parent pipe.
 742          */
 743         if (pipe_ctx->top_pipe == NULL) {
 744                 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
 745
 746                 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
 747         }
 748
 749         for (i = 0; i < dc->res_pool->pipe_count; i++)
 750                 if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx)
 751                         break;
 752
 753         if (i == dc->res_pool->pipe_count)
 754                 return;
 755
 756         pipe_ctx->stream = NULL;
 757         DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n",
 758                                         pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
 759 }
 760
 761 static bool dcn10_hw_wa_force_recovery(struct dc *dc)
 762 {
 763         struct hubp *hubp ;
 764         unsigned int i;
 765         bool need_recover = true;
 766
 767         if (!dc->debug.recovery_enabled)
 768                 return false;
 769
 770         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 771                 struct pipe_ctx *pipe_ctx =
 772                         &dc->current_state->res_ctx.pipe_ctx[i];
 773                 if (pipe_ctx != NULL) {
 774                         hubp = pipe_ctx->plane_res.hubp;
 775                         if (hubp != NULL && hubp->funcs->hubp_get_underflow_status) {
 776                                 if (hubp->funcs->hubp_get_underflow_status(hubp) != 0) {
 777                                         /* one pipe underflow, we will reset all the pipes*/
 778                                         need_recover = true;
 779                                 }
 780                         }
 781                 }
 782         }
 783         if (!need_recover)
 784                 return false;
 785         /*
 786         DCHUBP_CNTL:HUBP_BLANK_EN=1
 787         DCHUBBUB_SOFT_RESET:DCHUBBUB_GLOBAL_SOFT_RESET=1
 788         DCHUBP_CNTL:HUBP_DISABLE=1
 789         DCHUBP_CNTL:HUBP_DISABLE=0
 790         DCHUBBUB_SOFT_RESET:DCHUBBUB_GLOBAL_SOFT_RESET=0
 791         DCSURF_PRIMARY_SURFACE_ADDRESS
 792         DCHUBP_CNTL:HUBP_BLANK_EN=0
 793         */
 794
 795         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 796                 struct pipe_ctx *pipe_ctx =
 797                         &dc->current_state->res_ctx.pipe_ctx[i];
 798                 if (pipe_ctx != NULL) {
 799                         hubp = pipe_ctx->plane_res.hubp;
 800                         /*DCHUBP_CNTL:HUBP_BLANK_EN=1*/
 801                         if (hubp != NULL && hubp->funcs->set_hubp_blank_en)
 802                                 hubp->funcs->set_hubp_blank_en(hubp, true);
 803                 }
 804         }
 805         /*DCHUBBUB_SOFT_RESET:DCHUBBUB_GLOBAL_SOFT_RESET=1*/
 806         hubbub1_soft_reset(dc->res_pool->hubbub, true);
 807
 808         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 809                 struct pipe_ctx *pipe_ctx =
 810                         &dc->current_state->res_ctx.pipe_ctx[i];
 811                 if (pipe_ctx != NULL) {
 812                         hubp = pipe_ctx->plane_res.hubp;
 813                         /*DCHUBP_CNTL:HUBP_DISABLE=1*/
 814                         if (hubp != NULL && hubp->funcs->hubp_disable_control)
 815                                 hubp->funcs->hubp_disable_control(hubp, true);
 816                 }
 817         }
 818         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 819                 struct pipe_ctx *pipe_ctx =
 820                         &dc->current_state->res_ctx.pipe_ctx[i];
 821                 if (pipe_ctx != NULL) {
 822                         hubp = pipe_ctx->plane_res.hubp;
 823                         /*DCHUBP_CNTL:HUBP_DISABLE=0*/
 824                         if (hubp != NULL && hubp->funcs->hubp_disable_control)
 825                                 hubp->funcs->hubp_disable_control(hubp, true);
 826                 }
 827         }
 828         /*DCHUBBUB_SOFT_RESET:DCHUBBUB_GLOBAL_SOFT_RESET=0*/
 829         hubbub1_soft_reset(dc->res_pool->hubbub, false);
 830         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 831                 struct pipe_ctx *pipe_ctx =
 832                         &dc->current_state->res_ctx.pipe_ctx[i];
 833                 if (pipe_ctx != NULL) {
 834                         hubp = pipe_ctx->plane_res.hubp;
 835                         /*DCHUBP_CNTL:HUBP_BLANK_EN=0*/
 836                         if (hubp != NULL && hubp->funcs->set_hubp_blank_en)
 837                                 hubp->funcs->set_hubp_blank_en(hubp, true);
 838                 }
 839         }
 840         return true;
 841
 842 }
 843
 844
 845 void dcn10_verify_allow_pstate_change_high(struct dc *dc)
 846 {
 847         static bool should_log_hw_state; /* prevent hw state log by default */
 848
 849         if (!hubbub1_verify_allow_pstate_change_high(dc->res_pool->hubbub)) {
 850                 if (should_log_hw_state) {
 851                         dcn10_log_hw_state(dc, NULL);
 852                 }
 853                 BREAK_TO_DEBUGGER();
 854                 if (dcn10_hw_wa_force_recovery(dc)) {
 855                 /*check again*/
 856                         if (!hubbub1_verify_allow_pstate_change_high(dc->res_pool->hubbub))
 857                                 BREAK_TO_DEBUGGER();
 858                 }
 859         }
 860 }
 861
 862 /* trigger HW to start disconnect plane from stream on the next vsync */
 863 void hwss1_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx)
 864 {
 865         struct hubp *hubp = pipe_ctx->plane_res.hubp;
 866         int dpp_id = pipe_ctx->plane_res.dpp->inst;
 867         struct mpc *mpc = dc->res_pool->mpc;
 868         struct mpc_tree *mpc_tree_params;
 869         struct mpcc *mpcc_to_remove = NULL;
 870         struct output_pixel_processor *opp = pipe_ctx->stream_res.opp;
 871
 872         mpc_tree_params = &(opp->mpc_tree_params);
 873         mpcc_to_remove = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, dpp_id);
 874
 875         /*Already reset*/
 876         if (mpcc_to_remove == NULL)
 877                 return;
 878
 879         mpc->funcs->remove_mpcc(mpc, mpc_tree_params, mpcc_to_remove);
 880         if (opp != NULL)
 881                 opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
 882
 883         dc->optimized_required = true;
 884
 885         if (hubp->funcs->hubp_disconnect)
 886                 hubp->funcs->hubp_disconnect(hubp);
 887
 888         if (dc->debug.sanity_checks)
 889                 dcn10_verify_allow_pstate_change_high(dc);
 890 }
 891
 892 static void plane_atomic_power_down(struct dc *dc,
 893                 struct dpp *dpp,
 894                 struct hubp *hubp)
 895 {
 896         struct dce_hwseq *hws = dc->hwseq;
 897         DC_LOGGER_INIT(dc->ctx->logger);
 898
 899         if (REG(DC_IP_REQUEST_CNTL)) {
 900                 REG_SET(DC_IP_REQUEST_CNTL, 0,
 901                                 IP_REQUEST_EN, 1);
 902                 dpp_pg_control(hws, dpp->inst, false);
 903                 hubp_pg_control(hws, hubp->inst, false);
 904                 dpp->funcs->dpp_reset(dpp);
 905                 REG_SET(DC_IP_REQUEST_CNTL, 0,
 906                                 IP_REQUEST_EN, 0);
 907                 DC_LOG_DEBUG(
 908                                 "Power gated front end %d\n", hubp->inst);
 909         }
 910 }
 911
 912 /* disable HW used by plane.
 913  * note:  cannot disable until disconnect is complete
 914  */
 915 static void plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
 916 {
 917         struct hubp *hubp = pipe_ctx->plane_res.hubp;
 918         struct dpp *dpp = pipe_ctx->plane_res.dpp;
 919         int opp_id = hubp->opp_id;
 920
 921         dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);
 922
 923         hubp->funcs->hubp_clk_cntl(hubp, false);
 924
 925         dpp->funcs->dpp_dppclk_control(dpp, false, false);
 926
 927         if (opp_id != 0xf && pipe_ctx->stream_res.opp->mpc_tree_params.opp_list == NULL)
 928                 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
 929                                 pipe_ctx->stream_res.opp,
 930                                 false);
 931
 932         hubp->power_gated = true;
 933         dc->optimized_required = false; /* We're powering off, no need to optimize */
 934
 935         plane_atomic_power_down(dc,
 936                         pipe_ctx->plane_res.dpp,
 937                         pipe_ctx->plane_res.hubp);
 938
 939         pipe_ctx->stream = NULL;
 940         memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res));
 941         memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res));
 942         pipe_ctx->top_pipe = NULL;
 943         pipe_ctx->bottom_pipe = NULL;
 944         pipe_ctx->plane_state = NULL;
 945 }
 946
 947 static void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
 948 {
 949         DC_LOGGER_INIT(dc->ctx->logger);
 950
 951         if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)
 952                 return;
 953
 954         plane_atomic_disable(dc, pipe_ctx);
 955
 956         apply_DEGVIDCN10_253_wa(dc);
 957
 958         DC_LOG_DC("Power down front end %d\n",
 959                                         pipe_ctx->pipe_idx);
 960 }
 961
 962 static void dcn10_init_pipes(struct dc *dc, struct dc_state *context)
 963 {
 964         int i;
 965         bool can_apply_seamless_boot = false;
 966
 967         for (i = 0; i < context->stream_count; i++) {
 968                 if (context->streams[i]->apply_seamless_boot_optimization) {
 969                         can_apply_seamless_boot = true;
 970                         break;
 971                 }
 972         }
 973
 974         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 975                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
 976                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
 977
 978                 /* There is assumption that pipe_ctx is not mapping irregularly
 979                  * to non-preferred front end. If pipe_ctx->stream is not NULL,
 980                  * we will use the pipe, so don't disable
 981                  */
 982                 if (pipe_ctx->stream != NULL && can_apply_seamless_boot)
 983                         continue;
 984
 985                 /* Blank controller using driver code instead of
 986                  * command table.
 987                  */
 988                 if (tg->funcs->is_tg_enabled(tg)) {
 989                         tg->funcs->lock(tg);
 990                         tg->funcs->set_blank(tg, true);
 991                         hwss_wait_for_blank_complete(tg);
 992                 }
 993         }
 994
 995         /* Cannot reset the MPC mux if seamless boot */
 996         if (!can_apply_seamless_boot)
 997                 dc->res_pool->mpc->funcs->mpc_init(dc->res_pool->mpc);
 998
 999         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1000                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
1001                 struct hubp *hubp = dc->res_pool->hubps[i];
1002                 struct dpp *dpp = dc->res_pool->dpps[i];
1003                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1004
1005                 /* There is assumption that pipe_ctx is not mapping irregularly
1006                  * to non-preferred front end. If pipe_ctx->stream is not NULL,
1007                  * we will use the pipe, so don't disable
1008                  */
1009                 if (can_apply_seamless_boot &&
1010                         pipe_ctx->stream != NULL &&
1011                         pipe_ctx->stream_res.tg->funcs->is_tg_enabled(
1012                                 pipe_ctx->stream_res.tg))
1013                         continue;
1014
1015                 /* Disable on the current state so the new one isn't cleared. */
1016                 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
1017
1018                 dpp->funcs->dpp_reset(dpp);
1019
1020                 pipe_ctx->stream_res.tg = tg;
1021                 pipe_ctx->pipe_idx = i;
1022
1023                 pipe_ctx->plane_res.hubp = hubp;
1024                 pipe_ctx->plane_res.dpp = dpp;
1025                 pipe_ctx->plane_res.mpcc_inst = dpp->inst;
1026                 hubp->mpcc_id = dpp->inst;
1027                 hubp->opp_id = 0xf;
1028                 hubp->power_gated = false;
1029
1030                 dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
1031                 dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
1032                 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
1033                 pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
1034
1035                 hwss1_plane_atomic_disconnect(dc, pipe_ctx);
1036
1037                 if (tg->funcs->is_tg_enabled(tg))
1038                         tg->funcs->unlock(tg);
1039
1040                 dcn10_disable_plane(dc, pipe_ctx);
1041
1042                 pipe_ctx->stream_res.tg = NULL;
1043                 pipe_ctx->plane_res.hubp = NULL;
1044
1045                 tg->funcs->tg_init(tg);
1046         }
1047 }
1048
1049 static void dcn10_init_hw(struct dc *dc)
1050 {
1051         int i;
1052         struct abm *abm = dc->res_pool->abm;
1053         struct dmcu *dmcu = dc->res_pool->dmcu;
1054         struct dce_hwseq *hws = dc->hwseq;
1055         struct dc_bios *dcb = dc->ctx->dc_bios;
1056
1057         if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
1058                 REG_WRITE(REFCLK_CNTL, 0);
1059                 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
1060                 REG_WRITE(DIO_MEM_PWR_CTRL, 0);
1061
1062                 if (!dc->debug.disable_clock_gate) {
1063                         /* enable all DCN clock gating */
1064                         REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
1065
1066                         REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
1067
1068                         REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
1069                 }
1070
1071                 enable_power_gating_plane(dc->hwseq, true);
1072
1073                 /* end of FPGA. Below if real ASIC */
1074                 return;
1075         }
1076
1077         if (!dcb->funcs->is_accelerated_mode(dcb)) {
1078                 bool allow_self_fresh_force_enable =
1079                         hububu1_is_allow_self_refresh_enabled(
1080                                                 dc->res_pool->hubbub);
1081
1082                 bios_golden_init(dc);
1083
1084                 /* WA for making DF sleep when idle after resume from S0i3.
1085                  * DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE is set to 1 by
1086                  * command table, if DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE = 0
1087                  * before calling command table and it changed to 1 after,
1088                  * it should be set back to 0.
1089                  */
1090                 if (allow_self_fresh_force_enable == false &&
1091                                 hububu1_is_allow_self_refresh_enabled(dc->res_pool->hubbub))
1092                         hubbub1_allow_self_refresh_control(dc->res_pool->hubbub, true);
1093
1094                 disable_vga(dc->hwseq);
1095         }
1096
1097         for (i = 0; i < dc->link_count; i++) {
1098                 /* Power up AND update implementation according to the
1099                  * required signal (which may be different from the
1100                  * default signal on connector).
1101                  */
1102                 struct dc_link *link = dc->links[i];
1103
1104                 if (link->link_enc->connector.id == CONNECTOR_ID_EDP)
1105                         dc->hwss.edp_power_control(link, true);
1106
1107                 link->link_enc->funcs->hw_init(link->link_enc);
1108
1109                 /* Check for enabled DIG to identify enabled display */
1110                 if (link->link_enc->funcs->is_dig_enabled &&
1111                         link->link_enc->funcs->is_dig_enabled(link->link_enc))
1112                         link->link_status.link_active = true;
1113         }
1114
1115         /* If taking control over from VBIOS, we may want to optimize our first
1116          * mode set, so we need to skip powering down pipes until we know which
1117          * pipes we want to use.
1118          * Otherwise, if taking control is not possible, we need to power
1119          * everything down.
1120          */
1121         if (dcb->funcs->is_accelerated_mode(dcb) || dc->config.power_down_display_on_boot) {
1122                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1123                         struct hubp *hubp = dc->res_pool->hubps[i];
1124                         struct dpp *dpp = dc->res_pool->dpps[i];
1125
1126                         hubp->funcs->hubp_init(hubp);
1127                         dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
1128                         plane_atomic_power_down(dc, dpp, hubp);
1129                 }
1130
1131                 apply_DEGVIDCN10_253_wa(dc);
1132         }
1133
1134         for (i = 0; i < dc->res_pool->audio_count; i++) {
1135                 struct audio *audio = dc->res_pool->audios[i];
1136
1137                 audio->funcs->hw_init(audio);
1138         }
1139
1140         if (abm != NULL) {
1141                 abm->funcs->init_backlight(abm);
1142                 abm->funcs->abm_init(abm);
1143         }
1144
1145         if (dmcu != NULL)
1146                 dmcu->funcs->dmcu_init(dmcu);
1147
1148         /* power AFMT HDMI memory TODO: may move to dis/en output save power*/
1149         REG_WRITE(DIO_MEM_PWR_CTRL, 0);
1150
1151         if (!dc->debug.disable_clock_gate) {
1152                 /* enable all DCN clock gating */
1153                 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
1154
1155                 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
1156
1157                 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
1158         }
1159
1160         enable_power_gating_plane(dc->hwseq, true);
1161
1162         memset(&dc->res_pool->clk_mgr->clks, 0, sizeof(dc->res_pool->clk_mgr->clks));
1163 }
1164
1165 static void dcn10_reset_hw_ctx_wrap(
1166                 struct dc *dc,
1167                 struct dc_state *context)
1168 {
1169         int i;
1170
1171         /* Reset Back End*/
1172         for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
1173                 struct pipe_ctx *pipe_ctx_old =
1174                         &dc->current_state->res_ctx.pipe_ctx[i];
1175                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1176
1177                 if (!pipe_ctx_old->stream)
1178                         continue;
1179
1180                 if (pipe_ctx_old->top_pipe)
1181                         continue;
1182
1183                 if (!pipe_ctx->stream ||
1184                                 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
1185                         struct clock_source *old_clk = pipe_ctx_old->clock_source;
1186
1187                         dcn10_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
1188                         if (dc->hwss.enable_stream_gating)
1189                                 dc->hwss.enable_stream_gating(dc, pipe_ctx);
1190                         if (old_clk)
1191                                 old_clk->funcs->cs_power_down(old_clk);
1192                 }
1193         }
1194 }
1195
1196 static bool patch_address_for_sbs_tb_stereo(
1197                 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr)
1198 {
1199         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1200         bool sec_split = pipe_ctx->top_pipe &&
1201                         pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
1202         if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
1203                 (pipe_ctx->stream->timing.timing_3d_format ==
1204                  TIMING_3D_FORMAT_SIDE_BY_SIDE ||
1205                  pipe_ctx->stream->timing.timing_3d_format ==
1206                  TIMING_3D_FORMAT_TOP_AND_BOTTOM)) {
1207                 *addr = plane_state->address.grph_stereo.left_addr;
1208                 plane_state->address.grph_stereo.left_addr =
1209                 plane_state->address.grph_stereo.right_addr;
1210                 return true;
1211         } else {
1212                 if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE &&
1213                         plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) {
1214                         plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO;
1215                         plane_state->address.grph_stereo.right_addr =
1216                         plane_state->address.grph_stereo.left_addr;
1217                 }
1218         }
1219         return false;
1220 }
1221
1222
1223
1224 static void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)
1225 {
1226         bool addr_patched = false;
1227         PHYSICAL_ADDRESS_LOC addr;
1228         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1229
1230         if (plane_state == NULL)
1231                 return;
1232
1233         addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);
1234
1235         pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(
1236                         pipe_ctx->plane_res.hubp,
1237                         &plane_state->address,
1238                         plane_state->flip_immediate,
1239                         0);
1240
1241         plane_state->status.requested_address = plane_state->address;
1242
1243         if (plane_state->flip_immediate)
1244                 plane_state->status.current_address = plane_state->address;
1245
1246         if (addr_patched)
1247                 pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;
1248 }
1249
1250 static bool dcn10_set_input_transfer_func(struct pipe_ctx *pipe_ctx,
1251                                           const struct dc_plane_state *plane_state)
1252 {
1253         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
1254         const struct dc_transfer_func *tf = NULL;
1255         bool result = true;
1256
1257         if (dpp_base == NULL)
1258                 return false;
1259
1260         if (plane_state->in_transfer_func)
1261                 tf = plane_state->in_transfer_func;
1262
1263         if (plane_state->gamma_correction &&
1264                 !dpp_base->ctx->dc->debug.always_use_regamma
1265                 && !plane_state->gamma_correction->is_identity
1266                         && dce_use_lut(plane_state->format))
1267                 dpp_base->funcs->dpp_program_input_lut(dpp_base, plane_state->gamma_correction);
1268
1269         if (tf == NULL)
1270                 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
1271         else if (tf->type == TF_TYPE_PREDEFINED) {
1272                 switch (tf->tf) {
1273                 case TRANSFER_FUNCTION_SRGB:
1274                         dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_sRGB);
1275                         break;
1276                 case TRANSFER_FUNCTION_BT709:
1277                         dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_xvYCC);
1278                         break;
1279                 case TRANSFER_FUNCTION_LINEAR:
1280                         dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
1281                         break;
1282                 case TRANSFER_FUNCTION_PQ:
1283                 default:
1284                         result = false;
1285                         break;
1286                 }
1287         } else if (tf->type == TF_TYPE_BYPASS) {
1288                 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
1289         } else {
1290                 cm_helper_translate_curve_to_degamma_hw_format(tf,
1291                                         &dpp_base->degamma_params);
1292                 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base,
1293                                 &dpp_base->degamma_params);
1294                 result = true;
1295         }
1296
1297         return result;
1298 }
1299
1300
1301
1302
1303
1304 static bool
1305 dcn10_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
1306                                const struct dc_stream_state *stream)
1307 {
1308         struct dpp *dpp = pipe_ctx->plane_res.dpp;
1309
1310         if (dpp == NULL)
1311                 return false;
1312
1313         dpp->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
1314
1315         if (stream->out_transfer_func &&
1316             stream->out_transfer_func->type == TF_TYPE_PREDEFINED &&
1317             stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB)
1318                 dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_SRGB);
1319
1320         /* dcn10_translate_regamma_to_hw_format takes 750us, only do it when full
1321          * update.
1322          */
1323         else if (cm_helper_translate_curve_to_hw_format(
1324                         stream->out_transfer_func,
1325                         &dpp->regamma_params, false)) {
1326                 dpp->funcs->dpp_program_regamma_pwl(
1327                                 dpp,
1328                                 &dpp->regamma_params, OPP_REGAMMA_USER);
1329         } else
1330                 dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_BYPASS);
1331
1332         return true;
1333 }
1334
1335 static void dcn10_pipe_control_lock(
1336         struct dc *dc,
1337         struct pipe_ctx *pipe,
1338         bool lock)
1339 {
1340         /* use TG master update lock to lock everything on the TG
1341          * therefore only top pipe need to lock
1342          */
1343         if (pipe->top_pipe)
1344                 return;
1345
1346         if (dc->debug.sanity_checks)
1347                 dcn10_verify_allow_pstate_change_high(dc);
1348
1349         if (lock)
1350                 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);
1351         else
1352                 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);
1353
1354         if (dc->debug.sanity_checks)
1355                 dcn10_verify_allow_pstate_change_high(dc);
1356 }
1357
1358 static bool wait_for_reset_trigger_to_occur(
1359         struct dc_context *dc_ctx,
1360         struct timing_generator *tg)
1361 {
1362         bool rc = false;
1363
1364         /* To avoid endless loop we wait at most
1365          * frames_to_wait_on_triggered_reset frames for the reset to occur. */
1366         const uint32_t frames_to_wait_on_triggered_reset = 10;
1367         int i;
1368
1369         for (i = 0; i < frames_to_wait_on_triggered_reset; i++) {
1370
1371                 if (!tg->funcs->is_counter_moving(tg)) {
1372                         DC_ERROR("TG counter is not moving!\n");
1373                         break;
1374                 }
1375
1376                 if (tg->funcs->did_triggered_reset_occur(tg)) {
1377                         rc = true;
1378                         /* usually occurs at i=1 */
1379                         DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",
1380                                         i);
1381                         break;
1382                 }
1383
1384                 /* Wait for one frame. */
1385                 tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);
1386                 tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
1387         }
1388
1389         if (false == rc)
1390                 DC_ERROR("GSL: Timeout on reset trigger!\n");
1391
1392         return rc;
1393 }
1394
1395 static void dcn10_enable_timing_synchronization(
1396         struct dc *dc,
1397         int group_index,
1398         int group_size,
1399         struct pipe_ctx *grouped_pipes[])
1400 {
1401         struct dc_context *dc_ctx = dc->ctx;
1402         int i;
1403
1404         DC_SYNC_INFO("Setting up OTG reset trigger\n");
1405
1406         for (i = 1; i < group_size; i++)
1407                 grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger(
1408                                 grouped_pipes[i]->stream_res.tg,
1409                                 grouped_pipes[0]->stream_res.tg->inst);
1410
1411         DC_SYNC_INFO("Waiting for trigger\n");
1412
1413         /* Need to get only check 1 pipe for having reset as all the others are
1414          * synchronized. Look at last pipe programmed to reset.
1415          */
1416
1417         wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[1]->stream_res.tg);
1418         for (i = 1; i < group_size; i++)
1419                 grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(
1420                                 grouped_pipes[i]->stream_res.tg);
1421
1422         DC_SYNC_INFO("Sync complete\n");
1423 }
1424
1425 static void dcn10_enable_per_frame_crtc_position_reset(
1426         struct dc *dc,
1427         int group_size,
1428         struct pipe_ctx *grouped_pipes[])
1429 {
1430         struct dc_context *dc_ctx = dc->ctx;
1431         int i;
1432
1433         DC_SYNC_INFO("Setting up\n");
1434         for (i = 0; i < group_size; i++)
1435                 if (grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset)
1436                         grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset(
1437                                         grouped_pipes[i]->stream_res.tg,
1438                                         0,
1439                                         &grouped_pipes[i]->stream->triggered_crtc_reset);
1440
1441         DC_SYNC_INFO("Waiting for trigger\n");
1442
1443         for (i = 0; i < group_size; i++)
1444                 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
1445
1446         DC_SYNC_INFO("Multi-display sync is complete\n");
1447 }
1448
1449 /*static void print_rq_dlg_ttu(
1450                 struct dc *core_dc,
1451                 struct pipe_ctx *pipe_ctx)
1452 {
1453         DC_LOG_BANDWIDTH_CALCS(core_dc->ctx->logger,
1454                         "\n============== DML TTU Output parameters [%d] ==============\n"
1455                         "qos_level_low_wm: %d, \n"
1456                         "qos_level_high_wm: %d, \n"
1457                         "min_ttu_vblank: %d, \n"
1458                         "qos_level_flip: %d, \n"
1459                         "refcyc_per_req_delivery_l: %d, \n"
1460                         "qos_level_fixed_l: %d, \n"
1461                         "qos_ramp_disable_l: %d, \n"
1462                         "refcyc_per_req_delivery_pre_l: %d, \n"
1463                         "refcyc_per_req_delivery_c: %d, \n"
1464                         "qos_level_fixed_c: %d, \n"
1465                         "qos_ramp_disable_c: %d, \n"
1466                         "refcyc_per_req_delivery_pre_c: %d\n"
1467                         "=============================================================\n",
1468                         pipe_ctx->pipe_idx,
1469                         pipe_ctx->ttu_regs.qos_level_low_wm,
1470                         pipe_ctx->ttu_regs.qos_level_high_wm,
1471                         pipe_ctx->ttu_regs.min_ttu_vblank,
1472                         pipe_ctx->ttu_regs.qos_level_flip,
1473                         pipe_ctx->ttu_regs.refcyc_per_req_delivery_l,
1474                         pipe_ctx->ttu_regs.qos_level_fixed_l,
1475                         pipe_ctx->ttu_regs.qos_ramp_disable_l,
1476                         pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_l,
1477                         pipe_ctx->ttu_regs.refcyc_per_req_delivery_c,
1478                         pipe_ctx->ttu_regs.qos_level_fixed_c,
1479                         pipe_ctx->ttu_regs.qos_ramp_disable_c,
1480                         pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_c
1481                         );
1482
1483         DC_LOG_BANDWIDTH_CALCS(core_dc->ctx->logger,
1484                         "\n============== DML DLG Output parameters [%d] ==============\n"
1485                         "refcyc_h_blank_end: %d, \n"
1486                         "dlg_vblank_end: %d, \n"
1487                         "min_dst_y_next_start: %d, \n"
1488                         "refcyc_per_htotal: %d, \n"
1489                         "refcyc_x_after_scaler: %d, \n"
1490                         "dst_y_after_scaler: %d, \n"
1491                         "dst_y_prefetch: %d, \n"
1492                         "dst_y_per_vm_vblank: %d, \n"
1493                         "dst_y_per_row_vblank: %d, \n"
1494                         "ref_freq_to_pix_freq: %d, \n"
1495                         "vratio_prefetch: %d, \n"
1496                         "refcyc_per_pte_group_vblank_l: %d, \n"
1497                         "refcyc_per_meta_chunk_vblank_l: %d, \n"
1498                         "dst_y_per_pte_row_nom_l: %d, \n"
1499                         "refcyc_per_pte_group_nom_l: %d, \n",
1500                         pipe_ctx->pipe_idx,
1501                         pipe_ctx->dlg_regs.refcyc_h_blank_end,
1502                         pipe_ctx->dlg_regs.dlg_vblank_end,
1503                         pipe_ctx->dlg_regs.min_dst_y_next_start,
1504                         pipe_ctx->dlg_regs.refcyc_per_htotal,
1505                         pipe_ctx->dlg_regs.refcyc_x_after_scaler,
1506                         pipe_ctx->dlg_regs.dst_y_after_scaler,
1507                         pipe_ctx->dlg_regs.dst_y_prefetch,
1508                         pipe_ctx->dlg_regs.dst_y_per_vm_vblank,
1509                         pipe_ctx->dlg_regs.dst_y_per_row_vblank,
1510                         pipe_ctx->dlg_regs.ref_freq_to_pix_freq,
1511                         pipe_ctx->dlg_regs.vratio_prefetch,
1512                         pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_l,
1513                         pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_l,
1514                         pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_l,
1515                         pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_l
1516                         );
1517
1518         DC_LOG_BANDWIDTH_CALCS(core_dc->ctx->logger,
1519                         "\ndst_y_per_meta_row_nom_l: %d, \n"
1520                         "refcyc_per_meta_chunk_nom_l: %d, \n"
1521                         "refcyc_per_line_delivery_pre_l: %d, \n"
1522                         "refcyc_per_line_delivery_l: %d, \n"
1523                         "vratio_prefetch_c: %d, \n"
1524                         "refcyc_per_pte_group_vblank_c: %d, \n"
1525                         "refcyc_per_meta_chunk_vblank_c: %d, \n"
1526                         "dst_y_per_pte_row_nom_c: %d, \n"
1527                         "refcyc_per_pte_group_nom_c: %d, \n"
1528                         "dst_y_per_meta_row_nom_c: %d, \n"
1529                         "refcyc_per_meta_chunk_nom_c: %d, \n"
1530                         "refcyc_per_line_delivery_pre_c: %d, \n"
1531                         "refcyc_per_line_delivery_c: %d \n"
1532                         "========================================================\n",
1533                         pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_l,
1534                         pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_l,
1535                         pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_l,
1536                         pipe_ctx->dlg_regs.refcyc_per_line_delivery_l,
1537                         pipe_ctx->dlg_regs.vratio_prefetch_c,
1538                         pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_c,
1539                         pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_c,
1540                         pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_c,
1541                         pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_c,
1542                         pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_c,
1543                         pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_c,
1544                         pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_c,
1545                         pipe_ctx->dlg_regs.refcyc_per_line_delivery_c
1546                         );
1547
1548         DC_LOG_BANDWIDTH_CALCS(core_dc->ctx->logger,
1549                         "\n============== DML RQ Output parameters [%d] ==============\n"
1550                         "chunk_size: %d \n"
1551                         "min_chunk_size: %d \n"
1552                         "meta_chunk_size: %d \n"
1553                         "min_meta_chunk_size: %d \n"
1554                         "dpte_group_size: %d \n"
1555                         "mpte_group_size: %d \n"
1556                         "swath_height: %d \n"
1557                         "pte_row_height_linear: %d \n"
1558                         "========================================================\n",
1559                         pipe_ctx->pipe_idx,
1560                         pipe_ctx->rq_regs.rq_regs_l.chunk_size,
1561                         pipe_ctx->rq_regs.rq_regs_l.min_chunk_size,
1562                         pipe_ctx->rq_regs.rq_regs_l.meta_chunk_size,
1563                         pipe_ctx->rq_regs.rq_regs_l.min_meta_chunk_size,
1564                         pipe_ctx->rq_regs.rq_regs_l.dpte_group_size,
1565                         pipe_ctx->rq_regs.rq_regs_l.mpte_group_size,
1566                         pipe_ctx->rq_regs.rq_regs_l.swath_height,
1567                         pipe_ctx->rq_regs.rq_regs_l.pte_row_height_linear
1568                         );
1569 }
1570 */
1571
1572 static void mmhub_read_vm_system_aperture_settings(struct dcn10_hubp *hubp1,
1573                 struct vm_system_aperture_param *apt,
1574                 struct dce_hwseq *hws)
1575 {
1576         PHYSICAL_ADDRESS_LOC physical_page_number;
1577         uint32_t logical_addr_low;
1578         uint32_t logical_addr_high;
1579
1580         REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
1581                         PHYSICAL_PAGE_NUMBER_MSB, &physical_page_number.high_part);
1582         REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
1583                         PHYSICAL_PAGE_NUMBER_LSB, &physical_page_number.low_part);
1584
1585         REG_GET(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1586                         LOGICAL_ADDR, &logical_addr_low);
1587
1588         REG_GET(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1589                         LOGICAL_ADDR, &logical_addr_high);
1590
1591         apt->sys_default.quad_part =  physical_page_number.quad_part << 12;
1592         apt->sys_low.quad_part =  (int64_t)logical_addr_low << 18;
1593         apt->sys_high.quad_part =  (int64_t)logical_addr_high << 18;
1594 }
1595
1596 /* Temporary read settings, future will get values from kmd directly */
1597 static void mmhub_read_vm_context0_settings(struct dcn10_hubp *hubp1,
1598                 struct vm_context0_param *vm0,
1599                 struct dce_hwseq *hws)
1600 {
1601         PHYSICAL_ADDRESS_LOC fb_base;
1602         PHYSICAL_ADDRESS_LOC fb_offset;
1603         uint32_t fb_base_value;
1604         uint32_t fb_offset_value;
1605
1606         REG_GET(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, &fb_base_value);
1607         REG_GET(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, &fb_offset_value);
1608
1609         REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
1610                         PAGE_DIRECTORY_ENTRY_HI32, &vm0->pte_base.high_part);
1611         REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
1612                         PAGE_DIRECTORY_ENTRY_LO32, &vm0->pte_base.low_part);
1613
1614         REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
1615                         LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_start.high_part);
1616         REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
1617                         LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_start.low_part);
1618
1619         REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
1620                         LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_end.high_part);
1621         REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
1622                         LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_end.low_part);
1623
1624         REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
1625                         PHYSICAL_PAGE_ADDR_HI4, &vm0->fault_default.high_part);
1626         REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
1627                         PHYSICAL_PAGE_ADDR_LO32, &vm0->fault_default.low_part);
1628
1629         /*
1630          * The values in VM_CONTEXT0_PAGE_TABLE_BASE_ADDR is in UMA space.
1631          * Therefore we need to do
1632          * DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
1633          * - DCHUBBUB_SDPIF_FB_OFFSET + DCHUBBUB_SDPIF_FB_BASE
1634          */
1635         fb_base.quad_part = (uint64_t)fb_base_value << 24;
1636         fb_offset.quad_part = (uint64_t)fb_offset_value << 24;
1637         vm0->pte_base.quad_part += fb_base.quad_part;
1638         vm0->pte_base.quad_part -= fb_offset.quad_part;
1639 }
1640
1641
1642 void dcn10_program_pte_vm(struct dce_hwseq *hws, struct hubp *hubp)
1643 {
1644         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
1645         struct vm_system_aperture_param apt = { {{ 0 } } };
1646         struct vm_context0_param vm0 = { { { 0 } } };
1647
1648         mmhub_read_vm_system_aperture_settings(hubp1, &apt, hws);
1649         mmhub_read_vm_context0_settings(hubp1, &vm0, hws);
1650
1651         hubp->funcs->hubp_set_vm_system_aperture_settings(hubp, &apt);
1652         hubp->funcs->hubp_set_vm_context0_settings(hubp, &vm0);
1653 }
1654
1655 static void dcn10_enable_plane(
1656         struct dc *dc,
1657         struct pipe_ctx *pipe_ctx,
1658         struct dc_state *context)
1659 {
1660         struct dce_hwseq *hws = dc->hwseq;
1661
1662         if (dc->debug.sanity_checks) {
1663                 dcn10_verify_allow_pstate_change_high(dc);
1664         }
1665
1666         undo_DEGVIDCN10_253_wa(dc);
1667
1668         power_on_plane(dc->hwseq,
1669                 pipe_ctx->plane_res.hubp->inst);
1670
1671         /* enable DCFCLK current DCHUB */
1672         pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);
1673
1674         /* make sure OPP_PIPE_CLOCK_EN = 1 */
1675         pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
1676                         pipe_ctx->stream_res.opp,
1677                         true);
1678
1679 /* TODO: enable/disable in dm as per update type.
1680         if (plane_state) {
1681                 DC_LOG_DC(dc->ctx->logger,
1682                                 "Pipe:%d 0x%x: addr hi:0x%x, "
1683                                 "addr low:0x%x, "
1684                                 "src: %d, %d, %d,"
1685                                 " %d; dst: %d, %d, %d, %d;\n",
1686                                 pipe_ctx->pipe_idx,
1687                                 plane_state,
1688                                 plane_state->address.grph.addr.high_part,
1689                                 plane_state->address.grph.addr.low_part,
1690                                 plane_state->src_rect.x,
1691                                 plane_state->src_rect.y,
1692                                 plane_state->src_rect.width,
1693                                 plane_state->src_rect.height,
1694                                 plane_state->dst_rect.x,
1695                                 plane_state->dst_rect.y,
1696                                 plane_state->dst_rect.width,
1697                                 plane_state->dst_rect.height);
1698
1699                 DC_LOG_DC(dc->ctx->logger,
1700                                 "Pipe %d: width, height, x, y         format:%d\n"
1701                                 "viewport:%d, %d, %d, %d\n"
1702                                 "recout:  %d, %d, %d, %d\n",
1703                                 pipe_ctx->pipe_idx,
1704                                 plane_state->format,
1705                                 pipe_ctx->plane_res.scl_data.viewport.width,
1706                                 pipe_ctx->plane_res.scl_data.viewport.height,
1707                                 pipe_ctx->plane_res.scl_data.viewport.x,
1708                                 pipe_ctx->plane_res.scl_data.viewport.y,
1709                                 pipe_ctx->plane_res.scl_data.recout.width,
1710                                 pipe_ctx->plane_res.scl_data.recout.height,
1711                                 pipe_ctx->plane_res.scl_data.recout.x,
1712                                 pipe_ctx->plane_res.scl_data.recout.y);
1713                 print_rq_dlg_ttu(dc, pipe_ctx);
1714         }
1715 */
1716         if (dc->config.gpu_vm_support)
1717                 dcn10_program_pte_vm(hws, pipe_ctx->plane_res.hubp);
1718
1719         if (dc->debug.sanity_checks) {
1720                 dcn10_verify_allow_pstate_change_high(dc);
1721         }
1722 }
1723
1724 static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
1725 {
1726         int i = 0;
1727         struct dpp_grph_csc_adjustment adjust;
1728         memset(&adjust, 0, sizeof(adjust));
1729         adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
1730
1731
1732         if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
1733                 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
1734                 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
1735                         adjust.temperature_matrix[i] =
1736                                 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
1737         }
1738
1739         pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp, &adjust);
1740 }
1741
1742 static void dcn10_program_output_csc(struct dc *dc,
1743                 struct pipe_ctx *pipe_ctx,
1744                 enum dc_color_space colorspace,
1745                 uint16_t *matrix,
1746                 int opp_id)
1747 {
1748         if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
1749                 if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment != NULL)
1750                         pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, matrix);
1751         } else {
1752                 if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default != NULL)
1753                         pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default(pipe_ctx->plane_res.dpp, colorspace);
1754         }
1755 }
1756
1757 bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
1758 {
1759         if (pipe_ctx->plane_state->visible)
1760                 return true;
1761         if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
1762                 return true;
1763         return false;
1764 }
1765
1766 bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
1767 {
1768         if (pipe_ctx->plane_state->visible)
1769                 return true;
1770         if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
1771                 return true;
1772         return false;
1773 }
1774
1775 bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
1776 {
1777         if (pipe_ctx->plane_state->visible)
1778                 return true;
1779         if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
1780                 return true;
1781         if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
1782                 return true;
1783         return false;
1784 }
1785
1786 bool is_rgb_cspace(enum dc_color_space output_color_space)
1787 {
1788         switch (output_color_space) {
1789         case COLOR_SPACE_SRGB:
1790         case COLOR_SPACE_SRGB_LIMITED:
1791         case COLOR_SPACE_2020_RGB_FULLRANGE:
1792         case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
1793         case COLOR_SPACE_ADOBERGB:
1794                 return true;
1795         case COLOR_SPACE_YCBCR601:
1796         case COLOR_SPACE_YCBCR709:
1797         case COLOR_SPACE_YCBCR601_LIMITED:
1798         case COLOR_SPACE_YCBCR709_LIMITED:
1799         case COLOR_SPACE_2020_YCBCR:
1800                 return false;
1801         default:
1802                 /* Add a case to switch */
1803                 BREAK_TO_DEBUGGER();
1804                 return false;
1805         }
1806 }
1807
1808 void dcn10_get_surface_visual_confirm_color(
1809                 const struct pipe_ctx *pipe_ctx,
1810                 struct tg_color *color)
1811 {
1812         uint32_t color_value = MAX_TG_COLOR_VALUE;
1813
1814         switch (pipe_ctx->plane_res.scl_data.format) {
1815         case PIXEL_FORMAT_ARGB8888:
1816                 /* set boarder color to red */
1817                 color->color_r_cr = color_value;
1818                 break;
1819
1820         case PIXEL_FORMAT_ARGB2101010:
1821                 /* set boarder color to blue */
1822                 color->color_b_cb = color_value;
1823                 break;
1824         case PIXEL_FORMAT_420BPP8:
1825                 /* set boarder color to green */
1826                 color->color_g_y = color_value;
1827                 break;
1828         case PIXEL_FORMAT_420BPP10:
1829                 /* set boarder color to yellow */
1830                 color->color_g_y = color_value;
1831                 color->color_r_cr = color_value;
1832                 break;
1833         case PIXEL_FORMAT_FP16:
1834                 /* set boarder color to white */
1835                 color->color_r_cr = color_value;
1836                 color->color_b_cb = color_value;
1837                 color->color_g_y = color_value;
1838                 break;
1839         default:
1840                 break;
1841         }
1842 }
1843
1844 void dcn10_get_hdr_visual_confirm_color(
1845                 struct pipe_ctx *pipe_ctx,
1846                 struct tg_color *color)
1847 {
1848         uint32_t color_value = MAX_TG_COLOR_VALUE;
1849
1850         // Determine the overscan color based on the top-most (desktop) plane's context
1851         struct pipe_ctx *top_pipe_ctx  = pipe_ctx;
1852
1853         while (top_pipe_ctx->top_pipe != NULL)
1854                 top_pipe_ctx = top_pipe_ctx->top_pipe;
1855
1856         switch (top_pipe_ctx->plane_res.scl_data.format) {
1857         case PIXEL_FORMAT_ARGB2101010:
1858                 if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_PQ) {
1859                         /* HDR10, ARGB2101010 - set boarder color to red */
1860                         color->color_r_cr = color_value;
1861                 }
1862                 break;
1863         case PIXEL_FORMAT_FP16:
1864                 if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_PQ) {
1865                         /* HDR10, FP16 - set boarder color to blue */
1866                         color->color_b_cb = color_value;
1867                 } else if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22) {
1868                         /* FreeSync 2 HDR - set boarder color to green */
1869                         color->color_g_y = color_value;
1870                 }
1871                 break;
1872         default:
1873                 /* SDR - set boarder color to Gray */
1874                 color->color_r_cr = color_value/2;
1875                 color->color_b_cb = color_value/2;
1876                 color->color_g_y = color_value/2;
1877                 break;
1878         }
1879 }
1880
1881 static uint16_t fixed_point_to_int_frac(
1882         struct fixed31_32 arg,
1883         uint8_t integer_bits,
1884         uint8_t fractional_bits)
1885 {
1886         int32_t numerator;
1887         int32_t divisor = 1 << fractional_bits;
1888
1889         uint16_t result;
1890
1891         uint16_t d = (uint16_t)dc_fixpt_floor(
1892                 dc_fixpt_abs(
1893                         arg));
1894
1895         if (d <= (uint16_t)(1 << integer_bits) - (1 / (uint16_t)divisor))
1896                 numerator = (uint16_t)dc_fixpt_floor(
1897                         dc_fixpt_mul_int(
1898                                 arg,
1899                                 divisor));
1900         else {
1901                 numerator = dc_fixpt_floor(
1902                         dc_fixpt_sub(
1903                                 dc_fixpt_from_int(
1904                                         1LL << integer_bits),
1905                                 dc_fixpt_recip(
1906                                         dc_fixpt_from_int(
1907                                                 divisor))));
1908         }
1909
1910         if (numerator >= 0)
1911                 result = (uint16_t)numerator;
1912         else
1913                 result = (uint16_t)(
1914                 (1 << (integer_bits + fractional_bits + 1)) + numerator);
1915
1916         if ((result != 0) && dc_fixpt_lt(
1917                 arg, dc_fixpt_zero))
1918                 result |= 1 << (integer_bits + fractional_bits);
1919
1920         return result;
1921 }
1922
1923 void build_prescale_params(struct  dc_bias_and_scale *bias_and_scale,
1924                 const struct dc_plane_state *plane_state)
1925 {
1926         if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
1927                         && plane_state->format != SURFACE_PIXEL_FORMAT_INVALID
1928                         && plane_state->input_csc_color_matrix.enable_adjustment
1929                         && plane_state->coeff_reduction_factor.value != 0) {
1930                 bias_and_scale->scale_blue = fixed_point_to_int_frac(
1931                         dc_fixpt_mul(plane_state->coeff_reduction_factor,
1932                                         dc_fixpt_from_fraction(256, 255)),
1933                                 2,
1934                                 13);
1935                 bias_and_scale->scale_red = bias_and_scale->scale_blue;
1936                 bias_and_scale->scale_green = bias_and_scale->scale_blue;
1937         } else {
1938                 bias_and_scale->scale_blue = 0x2000;
1939                 bias_and_scale->scale_red = 0x2000;
1940                 bias_and_scale->scale_green = 0x2000;
1941         }
1942 }
1943
1944 static void update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state)
1945 {
1946         struct dc_bias_and_scale bns_params = {0};
1947
1948         // program the input csc
1949         dpp->funcs->dpp_setup(dpp,
1950                         plane_state->format,
1951                         EXPANSION_MODE_ZERO,
1952                         plane_state->input_csc_color_matrix,
1953                         plane_state->color_space);
1954
1955         //set scale and bias registers
1956         build_prescale_params(&bns_params, plane_state);
1957         if (dpp->funcs->dpp_program_bias_and_scale)
1958                 dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
1959 }
1960
1961 static void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
1962 {
1963         struct hubp *hubp = pipe_ctx->plane_res.hubp;
1964         struct mpcc_blnd_cfg blnd_cfg = {{0}};
1965         bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
1966         int mpcc_id;
1967         struct mpcc *new_mpcc;
1968         struct mpc *mpc = dc->res_pool->mpc;
1969         struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);
1970
1971         if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) {
1972                 dcn10_get_hdr_visual_confirm_color(
1973                                 pipe_ctx, &blnd_cfg.black_color);
1974         } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) {
1975                 dcn10_get_surface_visual_confirm_color(
1976                                 pipe_ctx, &blnd_cfg.black_color);
1977         } else {
1978                 color_space_to_black_color(
1979                                 dc, pipe_ctx->stream->output_color_space,
1980                                 &blnd_cfg.black_color);
1981         }
1982
1983         if (per_pixel_alpha)
1984                 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;
1985         else
1986                 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA;
1987
1988         blnd_cfg.overlap_only = false;
1989         blnd_cfg.global_gain = 0xff;
1990
1991         if (pipe_ctx->plane_state->global_alpha)
1992                 blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value;
1993         else
1994                 blnd_cfg.global_alpha = 0xff;
1995
1996         /* DCN1.0 has output CM before MPC which seems to screw with
1997          * pre-multiplied alpha.
1998          */
1999         blnd_cfg.pre_multiplied_alpha = is_rgb_cspace(
2000                         pipe_ctx->stream->output_color_space)
2001                                         && per_pixel_alpha;
2002
2003
2004         /*
2005          * TODO: remove hack
2006          * Note: currently there is a bug in init_hw such that
2007          * on resume from hibernate, BIOS sets up MPCC0, and
2008          * we do mpcc_remove but the mpcc cannot go to idle
2009          * after remove. This cause us to pick mpcc1 here,
2010          * which causes a pstate hang for yet unknown reason.
2011          */
2012         mpcc_id = hubp->inst;
2013
2014         /* If there is no full update, don't need to touch MPC tree*/
2015         if (!pipe_ctx->plane_state->update_flags.bits.full_update) {
2016                 mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id);
2017                 return;
2018         }
2019
2020         /* check if this MPCC is already being used */
2021         new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id);
2022         /* remove MPCC if being used */
2023         if (new_mpcc != NULL)
2024                 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc);
2025         else
2026                 if (dc->debug.sanity_checks)
2027                         mpc->funcs->assert_mpcc_idle_before_connect(
2028                                         dc->res_pool->mpc, mpcc_id);
2029
2030         /* Call MPC to insert new plane */
2031         new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,
2032                         mpc_tree_params,
2033                         &blnd_cfg,
2034                         NULL,
2035                         NULL,
2036                         hubp->inst,
2037                         mpcc_id);
2038
2039         ASSERT(new_mpcc != NULL);
2040
2041         hubp->opp_id = pipe_ctx->stream_res.opp->inst;
2042         hubp->mpcc_id = mpcc_id;
2043 }
2044
2045 static void update_scaler(struct pipe_ctx *pipe_ctx)
2046 {
2047         bool per_pixel_alpha =
2048                         pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
2049
2050         pipe_ctx->plane_res.scl_data.lb_params.alpha_en = per_pixel_alpha;
2051         pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
2052         /* scaler configuration */
2053         pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(
2054                         pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);
2055 }
2056
2057 void update_dchubp_dpp(
2058         struct dc *dc,
2059         struct pipe_ctx *pipe_ctx,
2060         struct dc_state *context)
2061 {
2062         struct hubp *hubp = pipe_ctx->plane_res.hubp;
2063         struct dpp *dpp = pipe_ctx->plane_res.dpp;
2064         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2065         union plane_size size = plane_state->plane_size;
2066         unsigned int compat_level = 0;
2067
2068         /* depends on DML calculation, DPP clock value may change dynamically */
2069         /* If request max dpp clk is lower than current dispclk, no need to
2070          * divided by 2
2071          */
2072         if (plane_state->update_flags.bits.full_update) {
2073                 bool should_divided_by_2 = context->bw_ctx.bw.dcn.clk.dppclk_khz <=
2074                                 dc->res_pool->clk_mgr->clks.dispclk_khz / 2;
2075
2076                 dpp->funcs->dpp_dppclk_control(
2077                                 dpp,
2078                                 should_divided_by_2,
2079                                 true);
2080
2081                 if (dc->res_pool->dccg)
2082                         dc->res_pool->dccg->funcs->update_dpp_dto(
2083                                         dc->res_pool->dccg,
2084                                         dpp->inst,
2085                                         pipe_ctx->plane_res.bw.dppclk_khz);
2086                 else
2087                         dc->res_pool->clk_mgr->clks.dppclk_khz = should_divided_by_2 ?
2088                                                 dc->res_pool->clk_mgr->clks.dispclk_khz / 2 :
2089                                                         dc->res_pool->clk_mgr->clks.dispclk_khz;
2090         }
2091
2092         /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG
2093          * VTG is within DCHUBBUB which is commond block share by each pipe HUBP.
2094          * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG
2095          */
2096         if (plane_state->update_flags.bits.full_update) {
2097                 hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst);
2098
2099                 hubp->funcs->hubp_setup(
2100                         hubp,
2101                         &pipe_ctx->dlg_regs,
2102                         &pipe_ctx->ttu_regs,
2103                         &pipe_ctx->rq_regs,
2104                         &pipe_ctx->pipe_dlg_param);
2105                 hubp->funcs->hubp_setup_interdependent(
2106                         hubp,
2107                         &pipe_ctx->dlg_regs,
2108                         &pipe_ctx->ttu_regs);
2109         }
2110
2111         size.grph.surface_size = pipe_ctx->plane_res.scl_data.viewport;
2112
2113         if (plane_state->update_flags.bits.full_update ||
2114                 plane_state->update_flags.bits.bpp_change)
2115                 update_dpp(dpp, plane_state);
2116
2117         if (plane_state->update_flags.bits.full_update ||
2118                 plane_state->update_flags.bits.per_pixel_alpha_change ||
2119                 plane_state->update_flags.bits.global_alpha_change)
2120                 dc->hwss.update_mpcc(dc, pipe_ctx);
2121
2122         if (plane_state->update_flags.bits.full_update ||
2123                 plane_state->update_flags.bits.per_pixel_alpha_change ||
2124                 plane_state->update_flags.bits.global_alpha_change ||
2125                 plane_state->update_flags.bits.scaling_change ||
2126                 plane_state->update_flags.bits.position_change) {
2127                 update_scaler(pipe_ctx);
2128         }
2129
2130         if (plane_state->update_flags.bits.full_update ||
2131                 plane_state->update_flags.bits.scaling_change ||
2132                 plane_state->update_flags.bits.position_change) {
2133                 hubp->funcs->mem_program_viewport(
2134                         hubp,
2135                         &pipe_ctx->plane_res.scl_data.viewport,
2136                         &pipe_ctx->plane_res.scl_data.viewport_c);
2137         }
2138
2139         if (pipe_ctx->stream->cursor_attributes.address.quad_part != 0) {
2140                 dc->hwss.set_cursor_position(pipe_ctx);
2141                 dc->hwss.set_cursor_attribute(pipe_ctx);
2142
2143                 if (dc->hwss.set_cursor_sdr_white_level)
2144                         dc->hwss.set_cursor_sdr_white_level(pipe_ctx);
2145         }
2146
2147         if (plane_state->update_flags.bits.full_update) {
2148                 /*gamut remap*/
2149                 program_gamut_remap(pipe_ctx);
2150
2151                 dc->hwss.program_output_csc(dc,
2152                                 pipe_ctx,
2153                                 pipe_ctx->stream->output_color_space,
2154                                 pipe_ctx->stream->csc_color_matrix.matrix,
2155                                 hubp->opp_id);
2156         }
2157
2158         if (plane_state->update_flags.bits.full_update ||
2159                 plane_state->update_flags.bits.pixel_format_change ||
2160                 plane_state->update_flags.bits.horizontal_mirror_change ||
2161                 plane_state->update_flags.bits.rotation_change ||
2162                 plane_state->update_flags.bits.swizzle_change ||
2163                 plane_state->update_flags.bits.dcc_change ||
2164                 plane_state->update_flags.bits.bpp_change ||
2165                 plane_state->update_flags.bits.scaling_change ||
2166                 plane_state->update_flags.bits.plane_size_change) {
2167                 hubp->funcs->hubp_program_surface_config(
2168                         hubp,
2169                         plane_state->format,
2170                         &plane_state->tiling_info,
2171                         &size,
2172                         plane_state->rotation,
2173                         &plane_state->dcc,
2174                         plane_state->horizontal_mirror,
2175                         compat_level);
2176         }
2177
2178         hubp->power_gated = false;
2179
2180         dc->hwss.update_plane_addr(dc, pipe_ctx);
2181
2182         if (is_pipe_tree_visible(pipe_ctx))
2183                 hubp->funcs->set_blank(hubp, false);
2184 }
2185
2186 static void dcn10_blank_pixel_data(
2187                 struct dc *dc,
2188                 struct pipe_ctx *pipe_ctx,
2189                 bool blank)
2190 {
2191         enum dc_color_space color_space;
2192         struct tg_color black_color = {0};
2193         struct stream_resource *stream_res = &pipe_ctx->stream_res;
2194         struct dc_stream_state *stream = pipe_ctx->stream;
2195
2196         /* program otg blank color */
2197         color_space = stream->output_color_space;
2198         color_space_to_black_color(dc, color_space, &black_color);
2199
2200         /*
2201          * The way 420 is packed, 2 channels carry Y component, 1 channel
2202          * alternate between Cb and Cr, so both channels need the pixel
2203          * value for Y
2204          */
2205         if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
2206                 black_color.color_r_cr = black_color.color_g_y;
2207
2208
2209         if (stream_res->tg->funcs->set_blank_color)
2210                 stream_res->tg->funcs->set_blank_color(
2211                                 stream_res->tg,
2212                                 &black_color);
2213
2214         if (!blank) {
2215                 if (stream_res->tg->funcs->set_blank)
2216                         stream_res->tg->funcs->set_blank(stream_res->tg, blank);
2217                 if (stream_res->abm) {
2218                         stream_res->abm->funcs->set_pipe(stream_res->abm, stream_res->tg->inst + 1);
2219                         stream_res->abm->funcs->set_abm_level(stream_res->abm, stream->abm_level);
2220                 }
2221         } else if (blank) {
2222                 if (stream_res->abm)
2223                         stream_res->abm->funcs->set_abm_immediate_disable(stream_res->abm);
2224                 if (stream_res->tg->funcs->set_blank)
2225                         stream_res->tg->funcs->set_blank(stream_res->tg, blank);
2226         }
2227 }
2228
2229 void set_hdr_multiplier(struct pipe_ctx *pipe_ctx)
2230 {
2231         struct fixed31_32 multiplier = dc_fixpt_from_fraction(
2232                         pipe_ctx->plane_state->sdr_white_level, 80);
2233         uint32_t hw_mult = 0x1f000; // 1.0 default multiplier
2234         struct custom_float_format fmt;
2235
2236         fmt.exponenta_bits = 6;
2237         fmt.mantissa_bits = 12;
2238         fmt.sign = true;
2239
2240         if (pipe_ctx->plane_state->sdr_white_level > 80)
2241                 convert_to_custom_float_format(multiplier, &fmt, &hw_mult);
2242
2243         pipe_ctx->plane_res.dpp->funcs->dpp_set_hdr_multiplier(
2244                         pipe_ctx->plane_res.dpp, hw_mult);
2245 }
2246
2247 void dcn10_program_pipe(
2248                 struct dc *dc,
2249                 struct pipe_ctx *pipe_ctx,
2250                 struct dc_state *context)
2251 {
2252         if (pipe_ctx->plane_state->update_flags.bits.full_update)
2253                 dcn10_enable_plane(dc, pipe_ctx, context);
2254
2255         update_dchubp_dpp(dc, pipe_ctx, context);
2256
2257         set_hdr_multiplier(pipe_ctx);
2258
2259         if (pipe_ctx->plane_state->update_flags.bits.full_update ||
2260                         pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
2261                         pipe_ctx->plane_state->update_flags.bits.gamma_change)
2262                 dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state);
2263
2264         /* dcn10_translate_regamma_to_hw_format takes 750us to finish
2265          * only do gamma programming for full update.
2266          * TODO: This can be further optimized/cleaned up
2267          * Always call this for now since it does memcmp inside before
2268          * doing heavy calculation and programming
2269          */
2270         if (pipe_ctx->plane_state->update_flags.bits.full_update)
2271                 dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);
2272 }
2273
2274 static void program_all_pipe_in_tree(
2275                 struct dc *dc,
2276                 struct pipe_ctx *pipe_ctx,
2277                 struct dc_state *context)
2278 {
2279         if (pipe_ctx->top_pipe == NULL) {
2280                 bool blank = !is_pipe_tree_visible(pipe_ctx);
2281
2282                 pipe_ctx->stream_res.tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset;
2283                 pipe_ctx->stream_res.tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start;
2284                 pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset;
2285                 pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_width = pipe_ctx->pipe_dlg_param.vupdate_width;
2286                 pipe_ctx->stream_res.tg->dlg_otg_param.signal =  pipe_ctx->stream->signal;
2287
2288                 pipe_ctx->stream_res.tg->funcs->program_global_sync(
2289                                 pipe_ctx->stream_res.tg);
2290
2291                 dc->hwss.blank_pixel_data(dc, pipe_ctx, blank);
2292
2293         }
2294
2295         if (pipe_ctx->plane_state != NULL)
2296                 dcn10_program_pipe(dc, pipe_ctx, context);
2297
2298         if (pipe_ctx->bottom_pipe != NULL && pipe_ctx->bottom_pipe != pipe_ctx)
2299                 program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context);
2300 }
2301
2302 struct pipe_ctx *find_top_pipe_for_stream(
2303                 struct dc *dc,
2304                 struct dc_state *context,
2305                 const struct dc_stream_state *stream)
2306 {
2307         int i;
2308
2309         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2310                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2311                 struct pipe_ctx *old_pipe_ctx =
2312                                 &dc->current_state->res_ctx.pipe_ctx[i];
2313
2314                 if (!pipe_ctx->plane_state && !old_pipe_ctx->plane_state)
2315                         continue;
2316
2317                 if (pipe_ctx->stream != stream)
2318                         continue;
2319
2320                 if (!pipe_ctx->top_pipe)
2321                         return pipe_ctx;
2322         }
2323         return NULL;
2324 }
2325
2326 static void dcn10_apply_ctx_for_surface(
2327                 struct dc *dc,
2328                 const struct dc_stream_state *stream,
2329                 int num_planes,
2330                 struct dc_state *context)
2331 {
2332         int i;
2333         struct timing_generator *tg;
2334         bool removed_pipe[4] = { false };
2335         bool interdependent_update = false;
2336         struct pipe_ctx *top_pipe_to_program =
2337                         find_top_pipe_for_stream(dc, context, stream);
2338         DC_LOGGER_INIT(dc->ctx->logger);
2339
2340         if (!top_pipe_to_program)
2341                 return;
2342
2343         tg = top_pipe_to_program->stream_res.tg;
2344
2345         interdependent_update = top_pipe_to_program->plane_state &&
2346                 top_pipe_to_program->plane_state->update_flags.bits.full_update;
2347
2348         if (interdependent_update)
2349                 lock_all_pipes(dc, context, true);
2350         else
2351                 dcn10_pipe_control_lock(dc, top_pipe_to_program, true);
2352
2353         if (num_planes == 0) {
2354                 /* OTG blank before remove all front end */
2355                 dc->hwss.blank_pixel_data(dc, top_pipe_to_program, true);
2356         }
2357
2358         /* Disconnect unused mpcc */
2359         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2360                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2361                 struct pipe_ctx *old_pipe_ctx =
2362                                 &dc->current_state->res_ctx.pipe_ctx[i];
2363                 /*
2364                  * Powergate reused pipes that are not powergated
2365                  * fairly hacky right now, using opp_id as indicator
2366                  * TODO: After move dc_post to dc_update, this will
2367                  * be removed.
2368                  */
2369                 if (pipe_ctx->plane_state && !old_pipe_ctx->plane_state) {
2370                         if (old_pipe_ctx->stream_res.tg == tg &&
2371                             old_pipe_ctx->plane_res.hubp &&
2372                             old_pipe_ctx->plane_res.hubp->opp_id != 0xf)
2373                                 dcn10_disable_plane(dc, old_pipe_ctx);
2374                 }
2375
2376                 if ((!pipe_ctx->plane_state ||
2377                      pipe_ctx->stream_res.tg != old_pipe_ctx->stream_res.tg) &&
2378                     old_pipe_ctx->plane_state &&
2379                     old_pipe_ctx->stream_res.tg == tg) {
2380
2381                         dc->hwss.plane_atomic_disconnect(dc, old_pipe_ctx);
2382                         removed_pipe[i] = true;
2383
2384                         DC_LOG_DC("Reset mpcc for pipe %d\n",
2385                                         old_pipe_ctx->pipe_idx);
2386                 }
2387         }
2388
2389         if (num_planes > 0)
2390                 program_all_pipe_in_tree(dc, top_pipe_to_program, context);
2391
2392         if (interdependent_update)
2393                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2394                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2395                         /* Skip inactive pipes and ones already updated */
2396                         if (!pipe_ctx->stream || pipe_ctx->stream == stream ||
2397                             !pipe_ctx->plane_state || !tg->funcs->is_tg_enabled(tg))
2398                                 continue;
2399
2400                         pipe_ctx->plane_res.hubp->funcs->hubp_setup_interdependent(
2401                                 pipe_ctx->plane_res.hubp,
2402                                 &pipe_ctx->dlg_regs,
2403                                 &pipe_ctx->ttu_regs);
2404                 }
2405
2406         if (interdependent_update)
2407                 lock_all_pipes(dc, context, false);
2408         else
2409                 dcn10_pipe_control_lock(dc, top_pipe_to_program, false);
2410
2411         if (num_planes == 0)
2412                 false_optc_underflow_wa(dc, stream, tg);
2413
2414         for (i = 0; i < dc->res_pool->pipe_count; i++)
2415                 if (removed_pipe[i])
2416                         dcn10_disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
2417
2418         if (dc->hwseq->wa.DEGVIDCN10_254)
2419                 hubbub1_wm_change_req_wa(dc->res_pool->hubbub);
2420 }
2421
2422 static void dcn10_stereo_hw_frame_pack_wa(struct dc *dc, struct dc_state *context)
2423 {
2424         uint8_t i;
2425
2426         for (i = 0; i < context->stream_count; i++) {
2427                 if (context->streams[i]->timing.timing_3d_format
2428                                 == TIMING_3D_FORMAT_HW_FRAME_PACKING) {
2429                         /*
2430                          * Disable stutter
2431                          */
2432                         hubbub1_allow_self_refresh_control(dc->res_pool->hubbub, false);
2433                         break;
2434                 }
2435         }
2436 }
2437
2438 static void dcn10_prepare_bandwidth(
2439                 struct dc *dc,
2440                 struct dc_state *context)
2441 {
2442         struct hubbub *hubbub = dc->res_pool->hubbub;
2443
2444         if (dc->debug.sanity_checks)
2445                 dcn10_verify_allow_pstate_change_high(dc);
2446
2447         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
2448                 if (context->stream_count == 0)
2449                         context->bw_ctx.bw.dcn.clk.phyclk_khz = 0;
2450
2451                 dc->res_pool->clk_mgr->funcs->update_clocks(
2452                                 dc->res_pool->clk_mgr,
2453                                 context,
2454                                 false);
2455         }
2456
2457         hubbub->funcs->program_watermarks(hubbub,
2458                         &context->bw_ctx.bw.dcn.watermarks,
2459                         dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
2460                         true);
2461         dcn10_stereo_hw_frame_pack_wa(dc, context);
2462
2463         if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE)
2464                 dcn_bw_notify_pplib_of_wm_ranges(dc);
2465
2466         if (dc->debug.sanity_checks)
2467                 dcn10_verify_allow_pstate_change_high(dc);
2468 }
2469
2470 static void dcn10_optimize_bandwidth(
2471                 struct dc *dc,
2472                 struct dc_state *context)
2473 {
2474         struct hubbub *hubbub = dc->res_pool->hubbub;
2475
2476         if (dc->debug.sanity_checks)
2477                 dcn10_verify_allow_pstate_change_high(dc);
2478
2479         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
2480                 if (context->stream_count == 0)
2481                         context->bw_ctx.bw.dcn.clk.phyclk_khz = 0;
2482
2483                 dc->res_pool->clk_mgr->funcs->update_clocks(
2484                                 dc->res_pool->clk_mgr,
2485                                 context,
2486                                 true);
2487         }
2488
2489         hubbub->funcs->program_watermarks(hubbub,
2490                         &context->bw_ctx.bw.dcn.watermarks,
2491                         dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
2492                         true);
2493         dcn10_stereo_hw_frame_pack_wa(dc, context);
2494
2495         if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE)
2496                 dcn_bw_notify_pplib_of_wm_ranges(dc);
2497
2498         if (dc->debug.sanity_checks)
2499                 dcn10_verify_allow_pstate_change_high(dc);
2500 }
2501
2502 static void set_drr(struct pipe_ctx **pipe_ctx,
2503                 int num_pipes, int vmin, int vmax)
2504 {
2505         int i = 0;
2506         struct drr_params params = {0};
2507         // DRR should set trigger event to monitor surface update event
2508         unsigned int event_triggers = 0x80;
2509
2510         params.vertical_total_max = vmax;
2511         params.vertical_total_min = vmin;
2512
2513         /* TODO: If multiple pipes are to be supported, you need
2514          * some GSL stuff. Static screen triggers may be programmed differently
2515          * as well.
2516          */
2517         for (i = 0; i < num_pipes; i++) {
2518                 pipe_ctx[i]->stream_res.tg->funcs->set_drr(
2519                         pipe_ctx[i]->stream_res.tg, &params);
2520                 if (vmax != 0 && vmin != 0)
2521                         pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control(
2522                                         pipe_ctx[i]->stream_res.tg,
2523                                         event_triggers);
2524         }
2525 }
2526
2527 static void get_position(struct pipe_ctx **pipe_ctx,
2528                 int num_pipes,
2529                 struct crtc_position *position)
2530 {
2531         int i = 0;
2532
2533         /* TODO: handle pipes > 1
2534          */
2535         for (i = 0; i < num_pipes; i++)
2536                 pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);
2537 }
2538
2539 static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
2540                 int num_pipes, const struct dc_static_screen_events *events)
2541 {
2542         unsigned int i;
2543         unsigned int value = 0;
2544
2545         if (events->surface_update)
2546                 value |= 0x80;
2547         if (events->cursor_update)
2548                 value |= 0x2;
2549         if (events->force_trigger)
2550                 value |= 0x1;
2551
2552         for (i = 0; i < num_pipes; i++)
2553                 pipe_ctx[i]->stream_res.tg->funcs->
2554                         set_static_screen_control(pipe_ctx[i]->stream_res.tg, value);
2555 }
2556
2557 static void dcn10_config_stereo_parameters(
2558                 struct dc_stream_state *stream, struct crtc_stereo_flags *flags)
2559 {
2560         enum view_3d_format view_format = stream->view_format;
2561         enum dc_timing_3d_format timing_3d_format =\
2562                         stream->timing.timing_3d_format;
2563         bool non_stereo_timing = false;
2564
2565         if (timing_3d_format == TIMING_3D_FORMAT_NONE ||
2566                 timing_3d_format == TIMING_3D_FORMAT_SIDE_BY_SIDE ||
2567                 timing_3d_format == TIMING_3D_FORMAT_TOP_AND_BOTTOM)
2568                 non_stereo_timing = true;
2569
2570         if (non_stereo_timing == false &&
2571                 view_format == VIEW_3D_FORMAT_FRAME_SEQUENTIAL) {
2572
2573                 flags->PROGRAM_STEREO         = 1;
2574                 flags->PROGRAM_POLARITY       = 1;
2575                 if (timing_3d_format == TIMING_3D_FORMAT_INBAND_FA ||
2576                         timing_3d_format == TIMING_3D_FORMAT_DP_HDMI_INBAND_FA ||
2577                         timing_3d_format == TIMING_3D_FORMAT_SIDEBAND_FA) {
2578                         enum display_dongle_type dongle = \
2579                                         stream->link->ddc->dongle_type;
2580                         if (dongle == DISPLAY_DONGLE_DP_VGA_CONVERTER ||
2581                                 dongle == DISPLAY_DONGLE_DP_DVI_CONVERTER ||
2582                                 dongle == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
2583                                 flags->DISABLE_STEREO_DP_SYNC = 1;
2584                 }
2585                 flags->RIGHT_EYE_POLARITY =\
2586                                 stream->timing.flags.RIGHT_EYE_3D_POLARITY;
2587                 if (timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
2588                         flags->FRAME_PACKED = 1;
2589         }
2590
2591         return;
2592 }
2593
2594 static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc)
2595 {
2596         struct crtc_stereo_flags flags = { 0 };
2597         struct dc_stream_state *stream = pipe_ctx->stream;
2598
2599         dcn10_config_stereo_parameters(stream, &flags);
2600
2601         pipe_ctx->stream_res.opp->funcs->opp_program_stereo(
2602                 pipe_ctx->stream_res.opp,
2603                 flags.PROGRAM_STEREO == 1 ? true:false,
2604                 &stream->timing);
2605
2606         pipe_ctx->stream_res.tg->funcs->program_stereo(
2607                 pipe_ctx->stream_res.tg,
2608                 &stream->timing,
2609                 &flags);
2610
2611         return;
2612 }
2613
2614 static struct hubp *get_hubp_by_inst(struct resource_pool *res_pool, int mpcc_inst)
2615 {
2616         int i;
2617
2618         for (i = 0; i < res_pool->pipe_count; i++) {
2619                 if (res_pool->hubps[i]->inst == mpcc_inst)
2620                         return res_pool->hubps[i];
2621         }
2622         ASSERT(false);
2623         return NULL;
2624 }
2625
2626 static void dcn10_wait_for_mpcc_disconnect(
2627                 struct dc *dc,
2628                 struct resource_pool *res_pool,
2629                 struct pipe_ctx *pipe_ctx)
2630 {
2631         int mpcc_inst;
2632
2633         if (dc->debug.sanity_checks) {
2634                 dcn10_verify_allow_pstate_change_high(dc);
2635         }
2636
2637         if (!pipe_ctx->stream_res.opp)
2638                 return;
2639
2640         for (mpcc_inst = 0; mpcc_inst < MAX_PIPES; mpcc_inst++) {
2641                 if (pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst]) {
2642                         struct hubp *hubp = get_hubp_by_inst(res_pool, mpcc_inst);
2643
2644                         res_pool->mpc->funcs->wait_for_idle(res_pool->mpc, mpcc_inst);
2645                         pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst] = false;
2646                         hubp->funcs->set_blank(hubp, true);
2647                         /*DC_LOG_ERROR(dc->ctx->logger,
2648                                         "[debug_mpo: wait_for_mpcc finished waiting on mpcc %d]\n",
2649                                         i);*/
2650                 }
2651         }
2652
2653         if (dc->debug.sanity_checks) {
2654                 dcn10_verify_allow_pstate_change_high(dc);
2655         }
2656
2657 }
2658
2659 static bool dcn10_dummy_display_power_gating(
2660         struct dc *dc,
2661         uint8_t controller_id,
2662         struct dc_bios *dcb,
2663         enum pipe_gating_control power_gating)
2664 {
2665         return true;
2666 }
2667
2668 static void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx)
2669 {
2670         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2671         struct timing_generator *tg = pipe_ctx->stream_res.tg;
2672         bool flip_pending;
2673
2674         if (plane_state == NULL)
2675                 return;
2676
2677         flip_pending = pipe_ctx->plane_res.hubp->funcs->hubp_is_flip_pending(
2678                                         pipe_ctx->plane_res.hubp);
2679
2680         plane_state->status.is_flip_pending = plane_state->status.is_flip_pending || flip_pending;
2681
2682         if (!flip_pending)
2683                 plane_state->status.current_address = plane_state->status.requested_address;
2684
2685         if (plane_state->status.current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2686                         tg->funcs->is_stereo_left_eye) {
2687                 plane_state->status.is_right_eye =
2688                                 !tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);
2689         }
2690 }
2691
2692 static void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data)
2693 {
2694         if (hws->ctx->dc->res_pool->hubbub != NULL) {
2695                 struct hubp *hubp = hws->ctx->dc->res_pool->hubps[0];
2696
2697                 if (hubp->funcs->hubp_update_dchub)
2698                         hubp->funcs->hubp_update_dchub(hubp, dh_data);
2699                 else
2700                         hubbub1_update_dchub(hws->ctx->dc->res_pool->hubbub, dh_data);
2701         }
2702 }
2703
2704 static void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)
2705 {
2706         struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;
2707         struct hubp *hubp = pipe_ctx->plane_res.hubp;
2708         struct dpp *dpp = pipe_ctx->plane_res.dpp;
2709         struct dc_cursor_mi_param param = {
2710                 .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10,
2711                 .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz,
2712                 .viewport = pipe_ctx->plane_res.scl_data.viewport,
2713                 .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz,
2714                 .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert,
2715                 .rotation = pipe_ctx->plane_state->rotation,
2716                 .mirror = pipe_ctx->plane_state->horizontal_mirror
2717         };
2718         uint32_t x_plane = pipe_ctx->plane_state->dst_rect.x;
2719         uint32_t y_plane = pipe_ctx->plane_state->dst_rect.y;
2720         uint32_t x_offset = min(x_plane, pos_cpy.x);
2721         uint32_t y_offset = min(y_plane, pos_cpy.y);
2722
2723         pos_cpy.x -= x_offset;
2724         pos_cpy.y -= y_offset;
2725         pos_cpy.x_hotspot += (x_plane - x_offset);
2726         pos_cpy.y_hotspot += (y_plane - y_offset);
2727
2728         if (pipe_ctx->plane_state->address.type
2729                         == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
2730                 pos_cpy.enable = false;
2731
2732         hubp->funcs->set_cursor_position(hubp, &pos_cpy, &param);
2733         dpp->funcs->set_cursor_position(dpp, &pos_cpy, &param, hubp->curs_attr.width, hubp->curs_attr.height);
2734 }
2735
2736 static void dcn10_set_cursor_attribute(struct pipe_ctx *pipe_ctx)
2737 {
2738         struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;
2739
2740         pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes(
2741                         pipe_ctx->plane_res.hubp, attributes);
2742         pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes(
2743                 pipe_ctx->plane_res.dpp, attributes->color_format);
2744 }
2745
2746 static void dcn10_set_cursor_sdr_white_level(struct pipe_ctx *pipe_ctx)
2747 {
2748         uint32_t sdr_white_level = pipe_ctx->stream->cursor_attributes.sdr_white_level;
2749         struct fixed31_32 multiplier;
2750         struct dpp_cursor_attributes opt_attr = { 0 };
2751         uint32_t hw_scale = 0x3c00; // 1.0 default multiplier
2752         struct custom_float_format fmt;
2753
2754         if (!pipe_ctx->plane_res.dpp->funcs->set_optional_cursor_attributes)
2755                 return;
2756
2757         fmt.exponenta_bits = 5;
2758         fmt.mantissa_bits = 10;
2759         fmt.sign = true;
2760
2761         if (sdr_white_level > 80) {
2762                 multiplier = dc_fixpt_from_fraction(sdr_white_level, 80);
2763                 convert_to_custom_float_format(multiplier, &fmt, &hw_scale);
2764         }
2765
2766         opt_attr.scale = hw_scale;
2767         opt_attr.bias = 0;
2768
2769         pipe_ctx->plane_res.dpp->funcs->set_optional_cursor_attributes(
2770                         pipe_ctx->plane_res.dpp, &opt_attr);
2771 }
2772
2773 /**
2774 * apply_front_porch_workaround  TODO FPGA still need?
2775 *
2776 * This is a workaround for a bug that has existed since R5xx and has not been
2777 * fixed keep Front porch at minimum 2 for Interlaced mode or 1 for progressive.
2778 */
2779 static void apply_front_porch_workaround(
2780         struct dc_crtc_timing *timing)
2781 {
2782         if (timing->flags.INTERLACE == 1) {
2783                 if (timing->v_front_porch < 2)
2784                         timing->v_front_porch = 2;
2785         } else {
2786                 if (timing->v_front_porch < 1)
2787                         timing->v_front_porch = 1;
2788         }
2789 }
2790
2791 int get_vupdate_offset_from_vsync(struct pipe_ctx *pipe_ctx)
2792 {
2793         struct timing_generator *optc = pipe_ctx->stream_res.tg;
2794         const struct dc_crtc_timing *dc_crtc_timing = &pipe_ctx->stream->timing;
2795         struct dc_crtc_timing patched_crtc_timing;
2796         int vesa_sync_start;
2797         int asic_blank_end;
2798         int interlace_factor;
2799         int vertical_line_start;
2800
2801         patched_crtc_timing = *dc_crtc_timing;
2802         apply_front_porch_workaround(&patched_crtc_timing);
2803
2804         interlace_factor = patched_crtc_timing.flags.INTERLACE ? 2 : 1;
2805
2806         vesa_sync_start = patched_crtc_timing.v_addressable +
2807                         patched_crtc_timing.v_border_bottom +
2808                         patched_crtc_timing.v_front_porch;
2809
2810         asic_blank_end = (patched_crtc_timing.v_total -
2811                         vesa_sync_start -
2812                         patched_crtc_timing.v_border_top)
2813                         * interlace_factor;
2814
2815         vertical_line_start = asic_blank_end -
2816                         optc->dlg_otg_param.vstartup_start + 1;
2817
2818         return vertical_line_start;
2819 }
2820
2821 void lock_all_pipes(struct dc *dc,
2822         struct dc_state *context,
2823         bool lock)
2824 {
2825         struct pipe_ctx *pipe_ctx;
2826         struct timing_generator *tg;
2827         int i;
2828
2829         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2830                 pipe_ctx = &context->res_ctx.pipe_ctx[i];
2831                 tg = pipe_ctx->stream_res.tg;
2832                 /*
2833                  * Only lock the top pipe's tg to prevent redundant
2834                  * (un)locking. Also skip if pipe is disabled.
2835                  */
2836                 if (pipe_ctx->top_pipe ||
2837                     !pipe_ctx->stream || !pipe_ctx->plane_state ||
2838                     !tg->funcs->is_tg_enabled(tg))
2839                         continue;
2840
2841                 if (lock)
2842                         tg->funcs->lock(tg);
2843                 else
2844                         tg->funcs->unlock(tg);
2845         }
2846 }
2847
2848 static void calc_vupdate_position(
2849                 struct pipe_ctx *pipe_ctx,
2850                 uint32_t *start_line,
2851                 uint32_t *end_line)
2852 {
2853         const struct dc_crtc_timing *dc_crtc_timing = &pipe_ctx->stream->timing;
2854         int vline_int_offset_from_vupdate =
2855                         pipe_ctx->stream->periodic_interrupt0.lines_offset;
2856         int vupdate_offset_from_vsync = get_vupdate_offset_from_vsync(pipe_ctx);
2857         int start_position;
2858
2859         if (vline_int_offset_from_vupdate > 0)
2860                 vline_int_offset_from_vupdate--;
2861         else if (vline_int_offset_from_vupdate < 0)
2862                 vline_int_offset_from_vupdate++;
2863
2864         start_position = vline_int_offset_from_vupdate + vupdate_offset_from_vsync;
2865
2866         if (start_position >= 0)
2867                 *start_line = start_position;
2868         else
2869                 *start_line = dc_crtc_timing->v_total + start_position - 1;
2870
2871         *end_line = *start_line + 2;
2872
2873         if (*end_line >= dc_crtc_timing->v_total)
2874                 *end_line = 2;
2875 }
2876
2877 static void cal_vline_position(
2878                 struct pipe_ctx *pipe_ctx,
2879                 enum vline_select vline,
2880                 uint32_t *start_line,
2881                 uint32_t *end_line)
2882 {
2883         enum vertical_interrupt_ref_point ref_point = INVALID_POINT;
2884
2885         if (vline == VLINE0)
2886                 ref_point = pipe_ctx->stream->periodic_interrupt0.ref_point;
2887         else if (vline == VLINE1)
2888                 ref_point = pipe_ctx->stream->periodic_interrupt1.ref_point;
2889
2890         switch (ref_point) {
2891         case START_V_UPDATE:
2892                 calc_vupdate_position(
2893                                 pipe_ctx,
2894                                 start_line,
2895                                 end_line);
2896                 break;
2897         case START_V_SYNC:
2898                 // Suppose to do nothing because vsync is 0;
2899                 break;
2900         default:
2901                 ASSERT(0);
2902                 break;
2903         }
2904 }
2905
2906 static void dcn10_setup_periodic_interrupt(
2907                 struct pipe_ctx *pipe_ctx,
2908                 enum vline_select vline)
2909 {
2910         struct timing_generator *tg = pipe_ctx->stream_res.tg;
2911
2912         if (vline == VLINE0) {
2913                 uint32_t start_line = 0;
2914                 uint32_t end_line = 0;
2915
2916                 cal_vline_position(pipe_ctx, vline, &start_line, &end_line);
2917
2918                 tg->funcs->setup_vertical_interrupt0(tg, start_line, end_line);
2919
2920         } else if (vline == VLINE1) {
2921                 pipe_ctx->stream_res.tg->funcs->setup_vertical_interrupt1(
2922                                 tg,
2923                                 pipe_ctx->stream->periodic_interrupt1.lines_offset);
2924         }
2925 }
2926
2927 static void dcn10_setup_vupdate_interrupt(struct pipe_ctx *pipe_ctx)
2928 {
2929         struct timing_generator *tg = pipe_ctx->stream_res.tg;
2930         int start_line = get_vupdate_offset_from_vsync(pipe_ctx);
2931
2932         if (start_line < 0) {
2933                 ASSERT(0);
2934                 start_line = 0;
2935         }
2936
2937         if (tg->funcs->setup_vertical_interrupt2)
2938                 tg->funcs->setup_vertical_interrupt2(tg, start_line);
2939 }
2940
2941 static void dcn10_unblank_stream(struct pipe_ctx *pipe_ctx,
2942                 struct dc_link_settings *link_settings)
2943 {
2944         struct encoder_unblank_param params = { { 0 } };
2945         struct dc_stream_state *stream = pipe_ctx->stream;
2946         struct dc_link *link = stream->link;
2947
2948         /* only 3 items below are used by unblank */
2949         params.timing = pipe_ctx->stream->timing;
2950
2951         params.link_settings.link_rate = link_settings->link_rate;
2952
2953         if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
2954                 if (params.timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
2955                         params.timing.pix_clk_100hz /= 2;
2956                 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, &params);
2957         }
2958
2959         if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
2960                 link->dc->hwss.edp_backlight_control(link, true);
2961         }
2962 }
2963
2964 static const struct hw_sequencer_funcs dcn10_funcs = {
2965         .program_gamut_remap = program_gamut_remap,
2966         .init_hw = dcn10_init_hw,
2967         .init_pipes = dcn10_init_pipes,
2968         .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
2969         .apply_ctx_for_surface = dcn10_apply_ctx_for_surface,
2970         .update_plane_addr = dcn10_update_plane_addr,
2971         .plane_atomic_disconnect = hwss1_plane_atomic_disconnect,
2972         .update_dchub = dcn10_update_dchub,
2973         .update_mpcc = dcn10_update_mpcc,
2974         .update_pending_status = dcn10_update_pending_status,
2975         .set_input_transfer_func = dcn10_set_input_transfer_func,
2976         .set_output_transfer_func = dcn10_set_output_transfer_func,
2977         .program_output_csc = dcn10_program_output_csc,
2978         .power_down = dce110_power_down,
2979         .enable_accelerated_mode = dce110_enable_accelerated_mode,
2980         .enable_timing_synchronization = dcn10_enable_timing_synchronization,
2981         .enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,
2982         .update_info_frame = dce110_update_info_frame,
2983         .enable_stream = dce110_enable_stream,
2984         .disable_stream = dce110_disable_stream,
2985         .unblank_stream = dcn10_unblank_stream,
2986         .blank_stream = dce110_blank_stream,
2987         .enable_audio_stream = dce110_enable_audio_stream,
2988         .disable_audio_stream = dce110_disable_audio_stream,
2989         .enable_display_power_gating = dcn10_dummy_display_power_gating,
2990         .disable_plane = dcn10_disable_plane,
2991         .blank_pixel_data = dcn10_blank_pixel_data,
2992         .pipe_control_lock = dcn10_pipe_control_lock,
2993         .prepare_bandwidth = dcn10_prepare_bandwidth,
2994         .optimize_bandwidth = dcn10_optimize_bandwidth,
2995         .reset_hw_ctx_wrap = dcn10_reset_hw_ctx_wrap,
2996         .enable_stream_timing = dcn10_enable_stream_timing,
2997         .set_drr = set_drr,
2998         .get_position = get_position,
2999         .set_static_screen_control = set_static_screen_control,
3000         .setup_stereo = dcn10_setup_stereo,
3001         .set_avmute = dce110_set_avmute,
3002         .log_hw_state = dcn10_log_hw_state,
3003         .get_hw_state = dcn10_get_hw_state,
3004         .clear_status_bits = dcn10_clear_status_bits,
3005         .wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
3006         .edp_backlight_control = hwss_edp_backlight_control,
3007         .edp_power_control = hwss_edp_power_control,
3008         .edp_wait_for_hpd_ready = hwss_edp_wait_for_hpd_ready,
3009         .set_cursor_position = dcn10_set_cursor_position,
3010         .set_cursor_attribute = dcn10_set_cursor_attribute,
3011         .set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,
3012         .disable_stream_gating = NULL,
3013         .enable_stream_gating = NULL,
3014         .setup_periodic_interrupt = dcn10_setup_periodic_interrupt,
3015         .setup_vupdate_interrupt = dcn10_setup_vupdate_interrupt
3016 };
3017
3018
3019 void dcn10_hw_sequencer_construct(struct dc *dc)
3020 {
3021         dc->hwss = dcn10_funcs;
3022 }
3023