drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/delay.h>
  27 #include "dm_services.h"
  28 #include "basics/dc_common.h"
  29 #include "core_types.h"
  30 #include "resource.h"
  31 #include "custom_float.h"
  32 #include "dcn10_hw_sequencer.h"
  33 #include "dcn10_hw_sequencer_debug.h"
  34 #include "dce/dce_hwseq.h"
  35 #include "abm.h"
  36 #include "dmcu.h"
  37 #include "dcn10_optc.h"
  38 #include "dcn10_dpp.h"
  39 #include "dcn10_mpc.h"
  40 #include "timing_generator.h"
  41 #include "opp.h"
  42 #include "ipp.h"
  43 #include "mpc.h"
  44 #include "reg_helper.h"
  45 #include "dcn10_hubp.h"
  46 #include "dcn10_hubbub.h"
  47 #include "dcn10_cm_common.h"
  48 #include "dc_link_dp.h"
  49 #include "dccg.h"
  50 #include "clk_mgr.h"
  51
  52
  53 #include "dsc.h"
  54
  55 #define DC_LOGGER_INIT(logger)
  56
  57 #define CTX \
  58         hws->ctx
  59 #define REG(reg)\
  60         hws->regs->reg
  61
  62 #undef FN
  63 #define FN(reg_name, field_name) \
  64         hws->shifts->field_name, hws->masks->field_name
  65
  66 /*print is 17 wide, first two characters are spaces*/
  67 #define DTN_INFO_MICRO_SEC(ref_cycle) \
  68         print_microsec(dc_ctx, log_ctx, ref_cycle)
  69
  70 #define GAMMA_HW_POINTS_NUM 256
  71
  72 void print_microsec(struct dc_context *dc_ctx,
  73         struct dc_log_buffer_ctx *log_ctx,
  74         uint32_t ref_cycle)
  75 {
  76         const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000;
  77         static const unsigned int frac = 1000;
  78         uint32_t us_x10 = (ref_cycle * frac) / ref_clk_mhz;
  79
  80         DTN_INFO("  %11d.%03d",
  81                         us_x10 / frac,
  82                         us_x10 % frac);
  83 }
  84
  85 static void dcn10_lock_all_pipes(struct dc *dc,
  86         struct dc_state *context,
  87         bool lock)
  88 {
  89         struct pipe_ctx *pipe_ctx;
  90         struct timing_generator *tg;
  91         int i;
  92
  93         for (i = 0; i < dc->res_pool->pipe_count; i++) {
  94                 pipe_ctx = &context->res_ctx.pipe_ctx[i];
  95                 tg = pipe_ctx->stream_res.tg;
  96                 /*
  97                  * Only lock the top pipe's tg to prevent redundant
  98                  * (un)locking. Also skip if pipe is disabled.
  99                  */
 100                 if (pipe_ctx->top_pipe ||
 101                     !pipe_ctx->stream || !pipe_ctx->plane_state ||
 102                     !tg->funcs->is_tg_enabled(tg))
 103                         continue;
 104
 105                 if (lock)
 106                         tg->funcs->lock(tg);
 107                 else
 108                         tg->funcs->unlock(tg);
 109         }
 110 }
 111
 112 static void log_mpc_crc(struct dc *dc,
 113         struct dc_log_buffer_ctx *log_ctx)
 114 {
 115         struct dc_context *dc_ctx = dc->ctx;
 116         struct dce_hwseq *hws = dc->hwseq;
 117
 118         if (REG(MPC_CRC_RESULT_GB))
 119                 DTN_INFO("MPC_CRC_RESULT_GB:%d MPC_CRC_RESULT_C:%d MPC_CRC_RESULT_AR:%d\n",
 120                 REG_READ(MPC_CRC_RESULT_GB), REG_READ(MPC_CRC_RESULT_C), REG_READ(MPC_CRC_RESULT_AR));
 121         if (REG(DPP_TOP0_DPP_CRC_VAL_B_A))
 122                 DTN_INFO("DPP_TOP0_DPP_CRC_VAL_B_A:%d DPP_TOP0_DPP_CRC_VAL_R_G:%d\n",
 123                 REG_READ(DPP_TOP0_DPP_CRC_VAL_B_A), REG_READ(DPP_TOP0_DPP_CRC_VAL_R_G));
 124 }
 125
 126 void dcn10_log_hubbub_state(struct dc *dc, struct dc_log_buffer_ctx *log_ctx)
 127 {
 128         struct dc_context *dc_ctx = dc->ctx;
 129         struct dcn_hubbub_wm wm;
 130         int i;
 131
 132         memset(&wm, 0, sizeof(struct dcn_hubbub_wm));
 133         dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm);
 134
 135         DTN_INFO("HUBBUB WM:      data_urgent  pte_meta_urgent"
 136                         "         sr_enter          sr_exit  dram_clk_change\n");
 137
 138         for (i = 0; i < 4; i++) {
 139                 struct dcn_hubbub_wm_set *s;
 140
 141                 s = &wm.sets[i];
 142                 DTN_INFO("WM_Set[%d]:", s->wm_set);
 143                 DTN_INFO_MICRO_SEC(s->data_urgent);
 144                 DTN_INFO_MICRO_SEC(s->pte_meta_urgent);
 145                 DTN_INFO_MICRO_SEC(s->sr_enter);
 146                 DTN_INFO_MICRO_SEC(s->sr_exit);
 147                 DTN_INFO_MICRO_SEC(s->dram_clk_chanage);
 148                 DTN_INFO("\n");
 149         }
 150
 151         DTN_INFO("\n");
 152 }
 153
 154 static void dcn10_log_hubp_states(struct dc *dc, void *log_ctx)
 155 {
 156         struct dc_context *dc_ctx = dc->ctx;
 157         struct resource_pool *pool = dc->res_pool;
 158         int i;
 159
 160         DTN_INFO(
 161                 "HUBP:  format  addr_hi  width  height  rot  mir  sw_mode  dcc_en  blank_en  clock_en  ttu_dis  underflow   min_ttu_vblank       qos_low_wm      qos_high_wm\n");
 162         for (i = 0; i < pool->pipe_count; i++) {
 163                 struct hubp *hubp = pool->hubps[i];
 164                 struct dcn_hubp_state *s = &(TO_DCN10_HUBP(hubp)->state);
 165
 166                 hubp->funcs->hubp_read_state(hubp);
 167
 168                 if (!s->blank_en) {
 169                         DTN_INFO("[%2d]:  %5xh  %6xh  %5d  %6d  %2xh  %2xh  %6xh  %6d  %8d  %8d  %7d  %8xh",
 170                                         hubp->inst,
 171                                         s->pixel_format,
 172                                         s->inuse_addr_hi,
 173                                         s->viewport_width,
 174                                         s->viewport_height,
 175                                         s->rotation_angle,
 176                                         s->h_mirror_en,
 177                                         s->sw_mode,
 178                                         s->dcc_en,
 179                                         s->blank_en,
 180                                         s->clock_en,
 181                                         s->ttu_disable,
 182                                         s->underflow_status);
 183                         DTN_INFO_MICRO_SEC(s->min_ttu_vblank);
 184                         DTN_INFO_MICRO_SEC(s->qos_level_low_wm);
 185                         DTN_INFO_MICRO_SEC(s->qos_level_high_wm);
 186                         DTN_INFO("\n");
 187                 }
 188         }
 189
 190         DTN_INFO("\n=========RQ========\n");
 191         DTN_INFO("HUBP:  drq_exp_m  prq_exp_m  mrq_exp_m  crq_exp_m  plane1_ba  L:chunk_s  min_chu_s  meta_ch_s"
 192                 "  min_m_c_s  dpte_gr_s  mpte_gr_s  swath_hei  pte_row_h  C:chunk_s  min_chu_s  meta_ch_s"
 193                 "  min_m_c_s  dpte_gr_s  mpte_gr_s  swath_hei  pte_row_h\n");
 194         for (i = 0; i < pool->pipe_count; i++) {
 195                 struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);
 196                 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;
 197
 198                 if (!s->blank_en)
 199                         DTN_INFO("[%2d]:  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh\n",
 200                                 pool->hubps[i]->inst, rq_regs->drq_expansion_mode, rq_regs->prq_expansion_mode, rq_regs->mrq_expansion_mode,
 201                                 rq_regs->crq_expansion_mode, rq_regs->plane1_base_address, rq_regs->rq_regs_l.chunk_size,
 202                                 rq_regs->rq_regs_l.min_chunk_size, rq_regs->rq_regs_l.meta_chunk_size,
 203                                 rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs->rq_regs_l.dpte_group_size,
 204                                 rq_regs->rq_regs_l.mpte_group_size, rq_regs->rq_regs_l.swath_height,
 205                                 rq_regs->rq_regs_l.pte_row_height_linear, rq_regs->rq_regs_c.chunk_size, rq_regs->rq_regs_c.min_chunk_size,
 206                                 rq_regs->rq_regs_c.meta_chunk_size, rq_regs->rq_regs_c.min_meta_chunk_size,
 207                                 rq_regs->rq_regs_c.dpte_group_size, rq_regs->rq_regs_c.mpte_group_size,
 208                                 rq_regs->rq_regs_c.swath_height, rq_regs->rq_regs_c.pte_row_height_linear);
 209         }
 210
 211         DTN_INFO("========DLG========\n");
 212         DTN_INFO("HUBP:  rc_hbe     dlg_vbe    min_d_y_n  rc_per_ht  rc_x_a_s "
 213                         "  dst_y_a_s  dst_y_pf   dst_y_vvb  dst_y_rvb  dst_y_vfl  dst_y_rfl  rf_pix_fq"
 214                         "  vratio_pf  vrat_pf_c  rc_pg_vbl  rc_pg_vbc  rc_mc_vbl  rc_mc_vbc  rc_pg_fll"
 215                         "  rc_pg_flc  rc_mc_fll  rc_mc_flc  pr_nom_l   pr_nom_c   rc_pg_nl   rc_pg_nc "
 216                         "  mr_nom_l   mr_nom_c   rc_mc_nl   rc_mc_nc   rc_ld_pl   rc_ld_pc   rc_ld_l  "
 217                         "  rc_ld_c    cha_cur0   ofst_cur1  cha_cur1   vr_af_vc0  ddrq_limt  x_rt_dlay"
 218                         "  x_rp_dlay  x_rr_sfl\n");
 219         for (i = 0; i < pool->pipe_count; i++) {
 220                 struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);
 221                 struct _vcs_dpi_display_dlg_regs_st *dlg_regs = &s->dlg_attr;
 222
 223                 if (!s->blank_en)
 224                         DTN_INFO("[%2d]:  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh"
 225                                 "%  8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh"
 226                                 "  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh\n",
 227                                 pool->hubps[i]->inst, dlg_regs->refcyc_h_blank_end, dlg_regs->dlg_vblank_end, dlg_regs->min_dst_y_next_start,
 228                                 dlg_regs->refcyc_per_htotal, dlg_regs->refcyc_x_after_scaler, dlg_regs->dst_y_after_scaler,
 229                                 dlg_regs->dst_y_prefetch, dlg_regs->dst_y_per_vm_vblank, dlg_regs->dst_y_per_row_vblank,
 230                                 dlg_regs->dst_y_per_vm_flip, dlg_regs->dst_y_per_row_flip, dlg_regs->ref_freq_to_pix_freq,
 231                                 dlg_regs->vratio_prefetch, dlg_regs->vratio_prefetch_c, dlg_regs->refcyc_per_pte_group_vblank_l,
 232                                 dlg_regs->refcyc_per_pte_group_vblank_c, dlg_regs->refcyc_per_meta_chunk_vblank_l,
 233                                 dlg_regs->refcyc_per_meta_chunk_vblank_c, dlg_regs->refcyc_per_pte_group_flip_l,
 234                                 dlg_regs->refcyc_per_pte_group_flip_c, dlg_regs->refcyc_per_meta_chunk_flip_l,
 235                                 dlg_regs->refcyc_per_meta_chunk_flip_c, dlg_regs->dst_y_per_pte_row_nom_l,
 236                                 dlg_regs->dst_y_per_pte_row_nom_c, dlg_regs->refcyc_per_pte_group_nom_l,
 237                                 dlg_regs->refcyc_per_pte_group_nom_c, dlg_regs->dst_y_per_meta_row_nom_l,
 238                                 dlg_regs->dst_y_per_meta_row_nom_c, dlg_regs->refcyc_per_meta_chunk_nom_l,
 239                                 dlg_regs->refcyc_per_meta_chunk_nom_c, dlg_regs->refcyc_per_line_delivery_pre_l,
 240                                 dlg_regs->refcyc_per_line_delivery_pre_c, dlg_regs->refcyc_per_line_delivery_l,
 241                                 dlg_regs->refcyc_per_line_delivery_c, dlg_regs->chunk_hdl_adjust_cur0, dlg_regs->dst_y_offset_cur1,
 242                                 dlg_regs->chunk_hdl_adjust_cur1, dlg_regs->vready_after_vcount0, dlg_regs->dst_y_delta_drq_limit,
 243                                 dlg_regs->xfc_reg_transfer_delay, dlg_regs->xfc_reg_precharge_delay,
 244                                 dlg_regs->xfc_reg_remote_surface_flip_latency);
 245         }
 246
 247         DTN_INFO("========TTU========\n");
 248         DTN_INFO("HUBP:  qos_ll_wm  qos_lh_wm  mn_ttu_vb  qos_l_flp  rc_rd_p_l  rc_rd_l    rc_rd_p_c"
 249                         "  rc_rd_c    rc_rd_c0   rc_rd_pc0  rc_rd_c1   rc_rd_pc1  qos_lf_l   qos_rds_l"
 250                         "  qos_lf_c   qos_rds_c  qos_lf_c0  qos_rds_c0 qos_lf_c1  qos_rds_c1\n");
 251         for (i = 0; i < pool->pipe_count; i++) {
 252                 struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);
 253                 struct _vcs_dpi_display_ttu_regs_st *ttu_regs = &s->ttu_attr;
 254
 255                 if (!s->blank_en)
 256                         DTN_INFO("[%2d]:  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh\n",
 257                                 pool->hubps[i]->inst, ttu_regs->qos_level_low_wm, ttu_regs->qos_level_high_wm, ttu_regs->min_ttu_vblank,
 258                                 ttu_regs->qos_level_flip, ttu_regs->refcyc_per_req_delivery_pre_l, ttu_regs->refcyc_per_req_delivery_l,
 259                                 ttu_regs->refcyc_per_req_delivery_pre_c, ttu_regs->refcyc_per_req_delivery_c, ttu_regs->refcyc_per_req_delivery_cur0,
 260                                 ttu_regs->refcyc_per_req_delivery_pre_cur0, ttu_regs->refcyc_per_req_delivery_cur1,
 261                                 ttu_regs->refcyc_per_req_delivery_pre_cur1, ttu_regs->qos_level_fixed_l, ttu_regs->qos_ramp_disable_l,
 262                                 ttu_regs->qos_level_fixed_c, ttu_regs->qos_ramp_disable_c, ttu_regs->qos_level_fixed_cur0,
 263                                 ttu_regs->qos_ramp_disable_cur0, ttu_regs->qos_level_fixed_cur1, ttu_regs->qos_ramp_disable_cur1);
 264         }
 265         DTN_INFO("\n");
 266 }
 267
 268 void dcn10_log_hw_state(struct dc *dc,
 269         struct dc_log_buffer_ctx *log_ctx)
 270 {
 271         struct dc_context *dc_ctx = dc->ctx;
 272         struct resource_pool *pool = dc->res_pool;
 273         int i;
 274
 275         DTN_INFO_BEGIN();
 276
 277         dcn10_log_hubbub_state(dc, log_ctx);
 278
 279         dcn10_log_hubp_states(dc, log_ctx);
 280
 281         DTN_INFO("DPP:    IGAM format  IGAM mode    DGAM mode    RGAM mode"
 282                         "  GAMUT mode  C11 C12   C13 C14   C21 C22   C23 C24   "
 283                         "C31 C32   C33 C34\n");
 284         for (i = 0; i < pool->pipe_count; i++) {
 285                 struct dpp *dpp = pool->dpps[i];
 286                 struct dcn_dpp_state s = {0};
 287
 288                 dpp->funcs->dpp_read_state(dpp, &s);
 289
 290                 if (!s.is_enabled)
 291                         continue;
 292
 293                 DTN_INFO("[%2d]:  %11xh  %-11s  %-11s  %-11s"
 294                                 "%8x    %08xh %08xh %08xh %08xh %08xh %08xh",
 295                                 dpp->inst,
 296                                 s.igam_input_format,
 297                                 (s.igam_lut_mode == 0) ? "BypassFixed" :
 298                                         ((s.igam_lut_mode == 1) ? "BypassFloat" :
 299                                         ((s.igam_lut_mode == 2) ? "RAM" :
 300                                         ((s.igam_lut_mode == 3) ? "RAM" :
 301                                                                  "Unknown"))),
 302                                 (s.dgam_lut_mode == 0) ? "Bypass" :
 303                                         ((s.dgam_lut_mode == 1) ? "sRGB" :
 304                                         ((s.dgam_lut_mode == 2) ? "Ycc" :
 305                                         ((s.dgam_lut_mode == 3) ? "RAM" :
 306                                         ((s.dgam_lut_mode == 4) ? "RAM" :
 307                                                                  "Unknown")))),
 308                                 (s.rgam_lut_mode == 0) ? "Bypass" :
 309                                         ((s.rgam_lut_mode == 1) ? "sRGB" :
 310                                         ((s.rgam_lut_mode == 2) ? "Ycc" :
 311                                         ((s.rgam_lut_mode == 3) ? "RAM" :
 312                                         ((s.rgam_lut_mode == 4) ? "RAM" :
 313                                                                  "Unknown")))),
 314                                 s.gamut_remap_mode,
 315                                 s.gamut_remap_c11_c12,
 316                                 s.gamut_remap_c13_c14,
 317                                 s.gamut_remap_c21_c22,
 318                                 s.gamut_remap_c23_c24,
 319                                 s.gamut_remap_c31_c32,
 320                                 s.gamut_remap_c33_c34);
 321                 DTN_INFO("\n");
 322         }
 323         DTN_INFO("\n");
 324
 325         DTN_INFO("MPCC:  OPP  DPP  MPCCBOT  MODE  ALPHA_MODE  PREMULT  OVERLAP_ONLY  IDLE\n");
 326         for (i = 0; i < pool->pipe_count; i++) {
 327                 struct mpcc_state s = {0};
 328
 329                 pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s);
 330                 if (s.opp_id != 0xf)
 331                         DTN_INFO("[%2d]:  %2xh  %2xh  %6xh  %4d  %10d  %7d  %12d  %4d\n",
 332                                 i, s.opp_id, s.dpp_id, s.bot_mpcc_id,
 333                                 s.mode, s.alpha_mode, s.pre_multiplied_alpha, s.overlap_only,
 334                                 s.idle);
 335         }
 336         DTN_INFO("\n");
 337
 338         DTN_INFO("OTG:  v_bs  v_be  v_ss  v_se  vpol  vmax  vmin  vmax_sel  vmin_sel  h_bs  h_be  h_ss  h_se  hpol  htot  vtot  underflow blank_en\n");
 339
 340         for (i = 0; i < pool->timing_generator_count; i++) {
 341                 struct timing_generator *tg = pool->timing_generators[i];
 342                 struct dcn_otg_state s = {0};
 343                 /* Read shared OTG state registers for all DCNx */
 344                 optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s);
 345
 346                 /*
 347                  * For DCN2 and greater, a register on the OPP is used to
 348                  * determine if the CRTC is blanked instead of the OTG. So use
 349                  * dpg_is_blanked() if exists, otherwise fallback on otg.
 350                  *
 351                  * TODO: Implement DCN-specific read_otg_state hooks.
 352                  */
 353                 if (pool->opps[i]->funcs->dpg_is_blanked)
 354                         s.blank_enabled = pool->opps[i]->funcs->dpg_is_blanked(pool->opps[i]);
 355                 else
 356                         s.blank_enabled = tg->funcs->is_blanked(tg);
 357
 358                 //only print if OTG master is enabled
 359                 if ((s.otg_enabled & 1) == 0)
 360                         continue;
 361
 362                 DTN_INFO("[%d]: %5d %5d %5d %5d %5d %5d %5d %9d %9d %5d %5d %5d %5d %5d %5d %5d  %9d %8d\n",
 363                                 tg->inst,
 364                                 s.v_blank_start,
 365                                 s.v_blank_end,
 366                                 s.v_sync_a_start,
 367                                 s.v_sync_a_end,
 368                                 s.v_sync_a_pol,
 369                                 s.v_total_max,
 370                                 s.v_total_min,
 371                                 s.v_total_max_sel,
 372                                 s.v_total_min_sel,
 373                                 s.h_blank_start,
 374                                 s.h_blank_end,
 375                                 s.h_sync_a_start,
 376                                 s.h_sync_a_end,
 377                                 s.h_sync_a_pol,
 378                                 s.h_total,
 379                                 s.v_total,
 380                                 s.underflow_occurred_status,
 381                                 s.blank_enabled);
 382
 383                 // Clear underflow for debug purposes
 384                 // We want to keep underflow sticky bit on for the longevity tests outside of test environment.
 385                 // This function is called only from Windows or Diags test environment, hence it's safe to clear
 386                 // it from here without affecting the original intent.
 387                 tg->funcs->clear_optc_underflow(tg);
 388         }
 389         DTN_INFO("\n");
 390
 391         DTN_INFO("DSC: CLOCK_EN  SLICE_WIDTH  Bytes_pp\n");
 392         for (i = 0; i < pool->res_cap->num_dsc; i++) {
 393                 struct display_stream_compressor *dsc = pool->dscs[i];
 394                 struct dcn_dsc_state s = {0};
 395
 396                 dsc->funcs->dsc_read_state(dsc, &s);
 397                 DTN_INFO("[%d]: %-9d %-12d %-10d\n",
 398                 dsc->inst,
 399                         s.dsc_clock_en,
 400                         s.dsc_slice_width,
 401                         s.dsc_bytes_per_pixel);
 402                 DTN_INFO("\n");
 403         }
 404         DTN_INFO("\n");
 405
 406         DTN_INFO("S_ENC: DSC_MODE  SEC_GSP7_LINE_NUM"
 407                         "  VBID6_LINE_REFERENCE  VBID6_LINE_NUM  SEC_GSP7_ENABLE  SEC_STREAM_ENABLE\n");
 408         for (i = 0; i < pool->stream_enc_count; i++) {
 409                 struct stream_encoder *enc = pool->stream_enc[i];
 410                 struct enc_state s = {0};
 411
 412                 if (enc->funcs->enc_read_state) {
 413                         enc->funcs->enc_read_state(enc, &s);
 414                         DTN_INFO("[%-3d]: %-9d %-18d %-21d %-15d %-16d %-17d\n",
 415                                 enc->id,
 416                                 s.dsc_mode,
 417                                 s.sec_gsp_pps_line_num,
 418                                 s.vbid6_line_reference,
 419                                 s.vbid6_line_num,
 420                                 s.sec_gsp_pps_enable,
 421                                 s.sec_stream_enable);
 422                         DTN_INFO("\n");
 423                 }
 424         }
 425         DTN_INFO("\n");
 426
 427         DTN_INFO("L_ENC: DPHY_FEC_EN  DPHY_FEC_READY_SHADOW  DPHY_FEC_ACTIVE_STATUS  DP_LINK_TRAINING_COMPLETE\n");
 428         for (i = 0; i < dc->link_count; i++) {
 429                 struct link_encoder *lenc = dc->links[i]->link_enc;
 430
 431                 struct link_enc_state s = {0};
 432
 433                 if (lenc->funcs->read_state) {
 434                         lenc->funcs->read_state(lenc, &s);
 435                         DTN_INFO("[%-3d]: %-12d %-22d %-22d %-25d\n",
 436                                 i,
 437                                 s.dphy_fec_en,
 438                                 s.dphy_fec_ready_shadow,
 439                                 s.dphy_fec_active_status,
 440                                 s.dp_link_training_complete);
 441                         DTN_INFO("\n");
 442                 }
 443         }
 444         DTN_INFO("\n");
 445
 446         DTN_INFO("\nCALCULATED Clocks: dcfclk_khz:%d  dcfclk_deep_sleep_khz:%d  dispclk_khz:%d\n"
 447                 "dppclk_khz:%d  max_supported_dppclk_khz:%d  fclk_khz:%d  socclk_khz:%d\n\n",
 448                         dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_khz,
 449                         dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz,
 450                         dc->current_state->bw_ctx.bw.dcn.clk.dispclk_khz,
 451                         dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz,
 452                         dc->current_state->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz,
 453                         dc->current_state->bw_ctx.bw.dcn.clk.fclk_khz,
 454                         dc->current_state->bw_ctx.bw.dcn.clk.socclk_khz);
 455
 456         log_mpc_crc(dc, log_ctx);
 457
 458         DTN_INFO_END();
 459 }
 460
 461 bool dcn10_did_underflow_occur(struct dc *dc, struct pipe_ctx *pipe_ctx)
 462 {
 463         struct hubp *hubp = pipe_ctx->plane_res.hubp;
 464         struct timing_generator *tg = pipe_ctx->stream_res.tg;
 465
 466         if (tg->funcs->is_optc_underflow_occurred(tg)) {
 467                 tg->funcs->clear_optc_underflow(tg);
 468                 return true;
 469         }
 470
 471         if (hubp->funcs->hubp_get_underflow_status(hubp)) {
 472                 hubp->funcs->hubp_clear_underflow(hubp);
 473                 return true;
 474         }
 475         return false;
 476 }
 477
 478 void dcn10_enable_power_gating_plane(
 479         struct dce_hwseq *hws,
 480         bool enable)
 481 {
 482         bool force_on = 1; /* disable power gating */
 483
 484         if (enable)
 485                 force_on = 0;
 486
 487         /* DCHUBP0/1/2/3 */
 488         REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on);
 489         REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on);
 490         REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on);
 491         REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on);
 492
 493         /* DPP0/1/2/3 */
 494         REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on);
 495         REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on);
 496         REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on);
 497         REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);
 498 }
 499
 500 void dcn10_disable_vga(
 501         struct dce_hwseq *hws)
 502 {
 503         unsigned int in_vga1_mode = 0;
 504         unsigned int in_vga2_mode = 0;
 505         unsigned int in_vga3_mode = 0;
 506         unsigned int in_vga4_mode = 0;
 507
 508         REG_GET(D1VGA_CONTROL, D1VGA_MODE_ENABLE, &in_vga1_mode);
 509         REG_GET(D2VGA_CONTROL, D2VGA_MODE_ENABLE, &in_vga2_mode);
 510         REG_GET(D3VGA_CONTROL, D3VGA_MODE_ENABLE, &in_vga3_mode);
 511         REG_GET(D4VGA_CONTROL, D4VGA_MODE_ENABLE, &in_vga4_mode);
 512
 513         if (in_vga1_mode == 0 && in_vga2_mode == 0 &&
 514                         in_vga3_mode == 0 && in_vga4_mode == 0)
 515                 return;
 516
 517         REG_WRITE(D1VGA_CONTROL, 0);
 518         REG_WRITE(D2VGA_CONTROL, 0);
 519         REG_WRITE(D3VGA_CONTROL, 0);
 520         REG_WRITE(D4VGA_CONTROL, 0);
 521
 522         /* HW Engineer's Notes:
 523          *  During switch from vga->extended, if we set the VGA_TEST_ENABLE and
 524          *  then hit the VGA_TEST_RENDER_START, then the DCHUBP timing gets updated correctly.
 525          *
 526          *  Then vBIOS will have it poll for the VGA_TEST_RENDER_DONE and unset
 527          *  VGA_TEST_ENABLE, to leave it in the same state as before.
 528          */
 529         REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_ENABLE, 1);
 530         REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_RENDER_START, 1);
 531 }
 532
 533 void dcn10_dpp_pg_control(
 534                 struct dce_hwseq *hws,
 535                 unsigned int dpp_inst,
 536                 bool power_on)
 537 {
 538         uint32_t power_gate = power_on ? 0 : 1;
 539         uint32_t pwr_status = power_on ? 0 : 2;
 540
 541         if (hws->ctx->dc->debug.disable_dpp_power_gate)
 542                 return;
 543         if (REG(DOMAIN1_PG_CONFIG) == 0)
 544                 return;
 545
 546         switch (dpp_inst) {
 547         case 0: /* DPP0 */
 548                 REG_UPDATE(DOMAIN1_PG_CONFIG,
 549                                 DOMAIN1_POWER_GATE, power_gate);
 550
 551                 REG_WAIT(DOMAIN1_PG_STATUS,
 552                                 DOMAIN1_PGFSM_PWR_STATUS, pwr_status,
 553                                 1, 1000);
 554                 break;
 555         case 1: /* DPP1 */
 556                 REG_UPDATE(DOMAIN3_PG_CONFIG,
 557                                 DOMAIN3_POWER_GATE, power_gate);
 558
 559                 REG_WAIT(DOMAIN3_PG_STATUS,
 560                                 DOMAIN3_PGFSM_PWR_STATUS, pwr_status,
 561                                 1, 1000);
 562                 break;
 563         case 2: /* DPP2 */
 564                 REG_UPDATE(DOMAIN5_PG_CONFIG,
 565                                 DOMAIN5_POWER_GATE, power_gate);
 566
 567                 REG_WAIT(DOMAIN5_PG_STATUS,
 568                                 DOMAIN5_PGFSM_PWR_STATUS, pwr_status,
 569                                 1, 1000);
 570                 break;
 571         case 3: /* DPP3 */
 572                 REG_UPDATE(DOMAIN7_PG_CONFIG,
 573                                 DOMAIN7_POWER_GATE, power_gate);
 574
 575                 REG_WAIT(DOMAIN7_PG_STATUS,
 576                                 DOMAIN7_PGFSM_PWR_STATUS, pwr_status,
 577                                 1, 1000);
 578                 break;
 579         default:
 580                 BREAK_TO_DEBUGGER();
 581                 break;
 582         }
 583 }
 584
 585 void dcn10_hubp_pg_control(
 586                 struct dce_hwseq *hws,
 587                 unsigned int hubp_inst,
 588                 bool power_on)
 589 {
 590         uint32_t power_gate = power_on ? 0 : 1;
 591         uint32_t pwr_status = power_on ? 0 : 2;
 592
 593         if (hws->ctx->dc->debug.disable_hubp_power_gate)
 594                 return;
 595         if (REG(DOMAIN0_PG_CONFIG) == 0)
 596                 return;
 597
 598         switch (hubp_inst) {
 599         case 0: /* DCHUBP0 */
 600                 REG_UPDATE(DOMAIN0_PG_CONFIG,
 601                                 DOMAIN0_POWER_GATE, power_gate);
 602
 603                 REG_WAIT(DOMAIN0_PG_STATUS,
 604                                 DOMAIN0_PGFSM_PWR_STATUS, pwr_status,
 605                                 1, 1000);
 606                 break;
 607         case 1: /* DCHUBP1 */
 608                 REG_UPDATE(DOMAIN2_PG_CONFIG,
 609                                 DOMAIN2_POWER_GATE, power_gate);
 610
 611                 REG_WAIT(DOMAIN2_PG_STATUS,
 612                                 DOMAIN2_PGFSM_PWR_STATUS, pwr_status,
 613                                 1, 1000);
 614                 break;
 615         case 2: /* DCHUBP2 */
 616                 REG_UPDATE(DOMAIN4_PG_CONFIG,
 617                                 DOMAIN4_POWER_GATE, power_gate);
 618
 619                 REG_WAIT(DOMAIN4_PG_STATUS,
 620                                 DOMAIN4_PGFSM_PWR_STATUS, pwr_status,
 621                                 1, 1000);
 622                 break;
 623         case 3: /* DCHUBP3 */
 624                 REG_UPDATE(DOMAIN6_PG_CONFIG,
 625                                 DOMAIN6_POWER_GATE, power_gate);
 626
 627                 REG_WAIT(DOMAIN6_PG_STATUS,
 628                                 DOMAIN6_PGFSM_PWR_STATUS, pwr_status,
 629                                 1, 1000);
 630                 break;
 631         default:
 632                 BREAK_TO_DEBUGGER();
 633                 break;
 634         }
 635 }
 636
 637 static void power_on_plane(
 638         struct dce_hwseq *hws,
 639         int plane_id)
 640 {
 641         DC_LOGGER_INIT(hws->ctx->logger);
 642         if (REG(DC_IP_REQUEST_CNTL)) {
 643                 REG_SET(DC_IP_REQUEST_CNTL, 0,
 644                                 IP_REQUEST_EN, 1);
 645                 hws->ctx->dc->hwss.dpp_pg_control(hws, plane_id, true);
 646                 hws->ctx->dc->hwss.hubp_pg_control(hws, plane_id, true);
 647                 REG_SET(DC_IP_REQUEST_CNTL, 0,
 648                                 IP_REQUEST_EN, 0);
 649                 DC_LOG_DEBUG(
 650                                 "Un-gated front end for pipe %d\n", plane_id);
 651         }
 652 }
 653
 654 static void undo_DEGVIDCN10_253_wa(struct dc *dc)
 655 {
 656         struct dce_hwseq *hws = dc->hwseq;
 657         struct hubp *hubp = dc->res_pool->hubps[0];
 658
 659         if (!hws->wa_state.DEGVIDCN10_253_applied)
 660                 return;
 661
 662         hubp->funcs->set_blank(hubp, true);
 663
 664         REG_SET(DC_IP_REQUEST_CNTL, 0,
 665                         IP_REQUEST_EN, 1);
 666
 667         dc->hwss.hubp_pg_control(hws, 0, false);
 668         REG_SET(DC_IP_REQUEST_CNTL, 0,
 669                         IP_REQUEST_EN, 0);
 670
 671         hws->wa_state.DEGVIDCN10_253_applied = false;
 672 }
 673
 674 static void apply_DEGVIDCN10_253_wa(struct dc *dc)
 675 {
 676         struct dce_hwseq *hws = dc->hwseq;
 677         struct hubp *hubp = dc->res_pool->hubps[0];
 678         int i;
 679
 680         if (dc->debug.disable_stutter)
 681                 return;
 682
 683         if (!hws->wa.DEGVIDCN10_253)
 684                 return;
 685
 686         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 687                 if (!dc->res_pool->hubps[i]->power_gated)
 688                         return;
 689         }
 690
 691         /* all pipe power gated, apply work around to enable stutter. */
 692
 693         REG_SET(DC_IP_REQUEST_CNTL, 0,
 694                         IP_REQUEST_EN, 1);
 695
 696         dc->hwss.hubp_pg_control(hws, 0, true);
 697         REG_SET(DC_IP_REQUEST_CNTL, 0,
 698                         IP_REQUEST_EN, 0);
 699
 700         hubp->funcs->set_hubp_blank_en(hubp, false);
 701         hws->wa_state.DEGVIDCN10_253_applied = true;
 702 }
 703
 704 void dcn10_bios_golden_init(struct dc *dc)
 705 {
 706         struct dc_bios *bp = dc->ctx->dc_bios;
 707         int i;
 708         bool allow_self_fresh_force_enable = true;
 709
 710         if (dc->hwss.s0i3_golden_init_wa && dc->hwss.s0i3_golden_init_wa(dc))
 711                 return;
 712         if (dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled)
 713                 allow_self_fresh_force_enable =
 714                                 dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled(dc->res_pool->hubbub);
 715
 716
 717         /* WA for making DF sleep when idle after resume from S0i3.
 718          * DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE is set to 1 by
 719          * command table, if DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE = 0
 720          * before calling command table and it changed to 1 after,
 721          * it should be set back to 0.
 722          */
 723
 724         /* initialize dcn global */
 725         bp->funcs->enable_disp_power_gating(bp,
 726                         CONTROLLER_ID_D0, ASIC_PIPE_INIT);
 727
 728         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 729                 /* initialize dcn per pipe */
 730                 bp->funcs->enable_disp_power_gating(bp,
 731                                 CONTROLLER_ID_D0 + i, ASIC_PIPE_DISABLE);
 732         }
 733
 734         if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)
 735                 if (allow_self_fresh_force_enable == false &&
 736                                 dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled(dc->res_pool->hubbub))
 737                         dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, true);
 738
 739 }
 740
 741 static void false_optc_underflow_wa(
 742                 struct dc *dc,
 743                 const struct dc_stream_state *stream,
 744                 struct timing_generator *tg)
 745 {
 746         int i;
 747         bool underflow;
 748
 749         if (!dc->hwseq->wa.false_optc_underflow)
 750                 return;
 751
 752         underflow = tg->funcs->is_optc_underflow_occurred(tg);
 753
 754         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 755                 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
 756
 757                 if (old_pipe_ctx->stream != stream)
 758                         continue;
 759
 760                 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, old_pipe_ctx);
 761         }
 762
 763         if (tg->funcs->set_blank_data_double_buffer)
 764                 tg->funcs->set_blank_data_double_buffer(tg, true);
 765
 766         if (tg->funcs->is_optc_underflow_occurred(tg) && !underflow)
 767                 tg->funcs->clear_optc_underflow(tg);
 768 }
 769
 770 enum dc_status dcn10_enable_stream_timing(
 771                 struct pipe_ctx *pipe_ctx,
 772                 struct dc_state *context,
 773                 struct dc *dc)
 774 {
 775         struct dc_stream_state *stream = pipe_ctx->stream;
 776         enum dc_color_space color_space;
 777         struct tg_color black_color = {0};
 778
 779         /* by upper caller loop, pipe0 is parent pipe and be called first.
 780          * back end is set up by for pipe0. Other children pipe share back end
 781          * with pipe 0. No program is needed.
 782          */
 783         if (pipe_ctx->top_pipe != NULL)
 784                 return DC_OK;
 785
 786         /* TODO check if timing_changed, disable stream if timing changed */
 787
 788         /* HW program guide assume display already disable
 789          * by unplug sequence. OTG assume stop.
 790          */
 791         pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true);
 792
 793         if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
 794                         pipe_ctx->clock_source,
 795                         &pipe_ctx->stream_res.pix_clk_params,
 796                         &pipe_ctx->pll_settings)) {
 797                 BREAK_TO_DEBUGGER();
 798                 return DC_ERROR_UNEXPECTED;
 799         }
 800
 801         pipe_ctx->stream_res.tg->funcs->program_timing(
 802                         pipe_ctx->stream_res.tg,
 803                         &stream->timing,
 804                         pipe_ctx->pipe_dlg_param.vready_offset,
 805                         pipe_ctx->pipe_dlg_param.vstartup_start,
 806                         pipe_ctx->pipe_dlg_param.vupdate_offset,
 807                         pipe_ctx->pipe_dlg_param.vupdate_width,
 808                         pipe_ctx->stream->signal,
 809                         true);
 810
 811 #if 0 /* move to after enable_crtc */
 812         /* TODO: OPP FMT, ABM. etc. should be done here. */
 813         /* or FPGA now. instance 0 only. TODO: move to opp.c */
 814
 815         inst_offset = reg_offsets[pipe_ctx->stream_res.tg->inst].fmt;
 816
 817         pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
 818                                 pipe_ctx->stream_res.opp,
 819                                 &stream->bit_depth_params,
 820                                 &stream->clamping);
 821 #endif
 822         /* program otg blank color */
 823         color_space = stream->output_color_space;
 824         color_space_to_black_color(dc, color_space, &black_color);
 825
 826         if (pipe_ctx->stream_res.tg->funcs->set_blank_color)
 827                 pipe_ctx->stream_res.tg->funcs->set_blank_color(
 828                                 pipe_ctx->stream_res.tg,
 829                                 &black_color);
 830
 831         if (pipe_ctx->stream_res.tg->funcs->is_blanked &&
 832                         !pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg)) {
 833                 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);
 834                 hwss_wait_for_blank_complete(pipe_ctx->stream_res.tg);
 835                 false_optc_underflow_wa(dc, pipe_ctx->stream, pipe_ctx->stream_res.tg);
 836         }
 837
 838         /* VTG is  within DCHUB command block. DCFCLK is always on */
 839         if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {
 840                 BREAK_TO_DEBUGGER();
 841                 return DC_ERROR_UNEXPECTED;
 842         }
 843
 844         /* TODO program crtc source select for non-virtual signal*/
 845         /* TODO program FMT */
 846         /* TODO setup link_enc */
 847         /* TODO set stream attributes */
 848         /* TODO program audio */
 849         /* TODO enable stream if timing changed */
 850         /* TODO unblank stream if DP */
 851
 852         return DC_OK;
 853 }
 854
 855 static void dcn10_reset_back_end_for_pipe(
 856                 struct dc *dc,
 857                 struct pipe_ctx *pipe_ctx,
 858                 struct dc_state *context)
 859 {
 860         int i;
 861         DC_LOGGER_INIT(dc->ctx->logger);
 862         if (pipe_ctx->stream_res.stream_enc == NULL) {
 863                 pipe_ctx->stream = NULL;
 864                 return;
 865         }
 866
 867         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
 868                 /* DPMS may already disable */
 869                 if (!pipe_ctx->stream->dpms_off)
 870                         core_link_disable_stream(pipe_ctx);
 871                 else if (pipe_ctx->stream_res.audio)
 872                         dc->hwss.disable_audio_stream(pipe_ctx);
 873
 874                 if (pipe_ctx->stream_res.audio) {
 875                         /*disable az_endpoint*/
 876                         pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
 877
 878                         /*free audio*/
 879                         if (dc->caps.dynamic_audio == true) {
 880                                 /*we have to dynamic arbitrate the audio endpoints*/
 881                                 /*we free the resource, need reset is_audio_acquired*/
 882                                 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
 883                                                 pipe_ctx->stream_res.audio, false);
 884                                 pipe_ctx->stream_res.audio = NULL;
 885                         }
 886                 }
 887         }
 888
 889         /* by upper caller loop, parent pipe: pipe0, will be reset last.
 890          * back end share by all pipes and will be disable only when disable
 891          * parent pipe.
 892          */
 893         if (pipe_ctx->top_pipe == NULL) {
 894                 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
 895
 896                 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
 897                 if (pipe_ctx->stream_res.tg->funcs->set_drr)
 898                         pipe_ctx->stream_res.tg->funcs->set_drr(
 899                                         pipe_ctx->stream_res.tg, NULL);
 900         }
 901
 902         for (i = 0; i < dc->res_pool->pipe_count; i++)
 903                 if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx)
 904                         break;
 905
 906         if (i == dc->res_pool->pipe_count)
 907                 return;
 908
 909         pipe_ctx->stream = NULL;
 910         DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n",
 911                                         pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
 912 }
 913
 914 static bool dcn10_hw_wa_force_recovery(struct dc *dc)
 915 {
 916         struct hubp *hubp ;
 917         unsigned int i;
 918         bool need_recover = true;
 919
 920         if (!dc->debug.recovery_enabled)
 921                 return false;
 922
 923         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 924                 struct pipe_ctx *pipe_ctx =
 925                         &dc->current_state->res_ctx.pipe_ctx[i];
 926                 if (pipe_ctx != NULL) {
 927                         hubp = pipe_ctx->plane_res.hubp;
 928                         if (hubp != NULL && hubp->funcs->hubp_get_underflow_status) {
 929                                 if (hubp->funcs->hubp_get_underflow_status(hubp) != 0) {
 930                                         /* one pipe underflow, we will reset all the pipes*/
 931                                         need_recover = true;
 932                                 }
 933                         }
 934                 }
 935         }
 936         if (!need_recover)
 937                 return false;
 938         /*
 939         DCHUBP_CNTL:HUBP_BLANK_EN=1
 940         DCHUBBUB_SOFT_RESET:DCHUBBUB_GLOBAL_SOFT_RESET=1
 941         DCHUBP_CNTL:HUBP_DISABLE=1
 942         DCHUBP_CNTL:HUBP_DISABLE=0
 943         DCHUBBUB_SOFT_RESET:DCHUBBUB_GLOBAL_SOFT_RESET=0
 944         DCSURF_PRIMARY_SURFACE_ADDRESS
 945         DCHUBP_CNTL:HUBP_BLANK_EN=0
 946         */
 947
 948         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 949                 struct pipe_ctx *pipe_ctx =
 950                         &dc->current_state->res_ctx.pipe_ctx[i];
 951                 if (pipe_ctx != NULL) {
 952                         hubp = pipe_ctx->plane_res.hubp;
 953                         /*DCHUBP_CNTL:HUBP_BLANK_EN=1*/
 954                         if (hubp != NULL && hubp->funcs->set_hubp_blank_en)
 955                                 hubp->funcs->set_hubp_blank_en(hubp, true);
 956                 }
 957         }
 958         /*DCHUBBUB_SOFT_RESET:DCHUBBUB_GLOBAL_SOFT_RESET=1*/
 959         hubbub1_soft_reset(dc->res_pool->hubbub, true);
 960
 961         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 962                 struct pipe_ctx *pipe_ctx =
 963                         &dc->current_state->res_ctx.pipe_ctx[i];
 964                 if (pipe_ctx != NULL) {
 965                         hubp = pipe_ctx->plane_res.hubp;
 966                         /*DCHUBP_CNTL:HUBP_DISABLE=1*/
 967                         if (hubp != NULL && hubp->funcs->hubp_disable_control)
 968                                 hubp->funcs->hubp_disable_control(hubp, true);
 969                 }
 970         }
 971         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 972                 struct pipe_ctx *pipe_ctx =
 973                         &dc->current_state->res_ctx.pipe_ctx[i];
 974                 if (pipe_ctx != NULL) {
 975                         hubp = pipe_ctx->plane_res.hubp;
 976                         /*DCHUBP_CNTL:HUBP_DISABLE=0*/
 977                         if (hubp != NULL && hubp->funcs->hubp_disable_control)
 978                                 hubp->funcs->hubp_disable_control(hubp, true);
 979                 }
 980         }
 981         /*DCHUBBUB_SOFT_RESET:DCHUBBUB_GLOBAL_SOFT_RESET=0*/
 982         hubbub1_soft_reset(dc->res_pool->hubbub, false);
 983         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 984                 struct pipe_ctx *pipe_ctx =
 985                         &dc->current_state->res_ctx.pipe_ctx[i];
 986                 if (pipe_ctx != NULL) {
 987                         hubp = pipe_ctx->plane_res.hubp;
 988                         /*DCHUBP_CNTL:HUBP_BLANK_EN=0*/
 989                         if (hubp != NULL && hubp->funcs->set_hubp_blank_en)
 990                                 hubp->funcs->set_hubp_blank_en(hubp, true);
 991                 }
 992         }
 993         return true;
 994
 995 }
 996
 997
 998 void dcn10_verify_allow_pstate_change_high(struct dc *dc)
 999 {
1000         static bool should_log_hw_state; /* prevent hw state log by default */
1001
1002         if (!hubbub1_verify_allow_pstate_change_high(dc->res_pool->hubbub)) {
1003                 if (should_log_hw_state) {
1004                         dcn10_log_hw_state(dc, NULL);
1005                 }
1006                 BREAK_TO_DEBUGGER();
1007                 if (dcn10_hw_wa_force_recovery(dc)) {
1008                 /*check again*/
1009                         if (!hubbub1_verify_allow_pstate_change_high(dc->res_pool->hubbub))
1010                                 BREAK_TO_DEBUGGER();
1011                 }
1012         }
1013 }
1014
1015 /* trigger HW to start disconnect plane from stream on the next vsync */
1016 void dcn10_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx)
1017 {
1018         struct hubp *hubp = pipe_ctx->plane_res.hubp;
1019         int dpp_id = pipe_ctx->plane_res.dpp->inst;
1020         struct mpc *mpc = dc->res_pool->mpc;
1021         struct mpc_tree *mpc_tree_params;
1022         struct mpcc *mpcc_to_remove = NULL;
1023         struct output_pixel_processor *opp = pipe_ctx->stream_res.opp;
1024
1025         mpc_tree_params = &(opp->mpc_tree_params);
1026         mpcc_to_remove = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, dpp_id);
1027
1028         /*Already reset*/
1029         if (mpcc_to_remove == NULL)
1030                 return;
1031
1032         mpc->funcs->remove_mpcc(mpc, mpc_tree_params, mpcc_to_remove);
1033         if (opp != NULL)
1034                 opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
1035
1036         dc->optimized_required = true;
1037
1038         if (hubp->funcs->hubp_disconnect)
1039                 hubp->funcs->hubp_disconnect(hubp);
1040
1041         if (dc->debug.sanity_checks)
1042                 dc->hwss.verify_allow_pstate_change_high(dc);
1043 }
1044
1045 void dcn10_plane_atomic_power_down(struct dc *dc,
1046                 struct dpp *dpp,
1047                 struct hubp *hubp)
1048 {
1049         struct dce_hwseq *hws = dc->hwseq;
1050         DC_LOGGER_INIT(dc->ctx->logger);
1051
1052         if (REG(DC_IP_REQUEST_CNTL)) {
1053                 REG_SET(DC_IP_REQUEST_CNTL, 0,
1054                                 IP_REQUEST_EN, 1);
1055                 dc->hwss.dpp_pg_control(hws, dpp->inst, false);
1056                 dc->hwss.hubp_pg_control(hws, hubp->inst, false);
1057                 dpp->funcs->dpp_reset(dpp);
1058                 REG_SET(DC_IP_REQUEST_CNTL, 0,
1059                                 IP_REQUEST_EN, 0);
1060                 DC_LOG_DEBUG(
1061                                 "Power gated front end %d\n", hubp->inst);
1062         }
1063 }
1064
1065 /* disable HW used by plane.
1066  * note:  cannot disable until disconnect is complete
1067  */
1068 void dcn10_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
1069 {
1070         struct hubp *hubp = pipe_ctx->plane_res.hubp;
1071         struct dpp *dpp = pipe_ctx->plane_res.dpp;
1072         int opp_id = hubp->opp_id;
1073
1074         dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);
1075
1076         hubp->funcs->hubp_clk_cntl(hubp, false);
1077
1078         dpp->funcs->dpp_dppclk_control(dpp, false, false);
1079
1080         if (opp_id != 0xf && pipe_ctx->stream_res.opp->mpc_tree_params.opp_list == NULL)
1081                 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
1082                                 pipe_ctx->stream_res.opp,
1083                                 false);
1084
1085         hubp->power_gated = true;
1086         dc->optimized_required = false; /* We're powering off, no need to optimize */
1087
1088         dc->hwss.plane_atomic_power_down(dc,
1089                         pipe_ctx->plane_res.dpp,
1090                         pipe_ctx->plane_res.hubp);
1091
1092         pipe_ctx->stream = NULL;
1093         memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res));
1094         memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res));
1095         pipe_ctx->top_pipe = NULL;
1096         pipe_ctx->bottom_pipe = NULL;
1097         pipe_ctx->plane_state = NULL;
1098 }
1099
1100 void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
1101 {
1102         DC_LOGGER_INIT(dc->ctx->logger);
1103
1104         if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)
1105                 return;
1106
1107         dc->hwss.plane_atomic_disable(dc, pipe_ctx);
1108
1109         apply_DEGVIDCN10_253_wa(dc);
1110
1111         DC_LOG_DC("Power down front end %d\n",
1112                                         pipe_ctx->pipe_idx);
1113 }
1114
1115 void dcn10_init_pipes(struct dc *dc, struct dc_state *context)
1116 {
1117         int i;
1118         bool can_apply_seamless_boot = false;
1119
1120         for (i = 0; i < context->stream_count; i++) {
1121                 if (context->streams[i]->apply_seamless_boot_optimization) {
1122                         can_apply_seamless_boot = true;
1123                         break;
1124                 }
1125         }
1126
1127         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1128                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
1129                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1130
1131                 /* There is assumption that pipe_ctx is not mapping irregularly
1132                  * to non-preferred front end. If pipe_ctx->stream is not NULL,
1133                  * we will use the pipe, so don't disable
1134                  */
1135                 if (pipe_ctx->stream != NULL && can_apply_seamless_boot)
1136                         continue;
1137
1138                 /* Blank controller using driver code instead of
1139                  * command table.
1140                  */
1141                 if (tg->funcs->is_tg_enabled(tg)) {
1142                         if (dc->hwss.init_blank != NULL) {
1143                                 dc->hwss.init_blank(dc, tg);
1144                                 tg->funcs->lock(tg);
1145                         } else {
1146                                 tg->funcs->lock(tg);
1147                                 tg->funcs->set_blank(tg, true);
1148                                 hwss_wait_for_blank_complete(tg);
1149                         }
1150                 }
1151         }
1152
1153         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1154                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1155
1156                 /* Cannot reset the MPC mux if seamless boot */
1157                 if (pipe_ctx->stream != NULL && can_apply_seamless_boot)
1158                         continue;
1159
1160                 dc->res_pool->mpc->funcs->mpc_init_single_inst(
1161                                 dc->res_pool->mpc, i);
1162         }
1163
1164         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1165                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
1166                 struct hubp *hubp = dc->res_pool->hubps[i];
1167                 struct dpp *dpp = dc->res_pool->dpps[i];
1168                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1169
1170                 /* There is assumption that pipe_ctx is not mapping irregularly
1171                  * to non-preferred front end. If pipe_ctx->stream is not NULL,
1172                  * we will use the pipe, so don't disable
1173                  */
1174                 if (can_apply_seamless_boot &&
1175                         pipe_ctx->stream != NULL &&
1176                         pipe_ctx->stream_res.tg->funcs->is_tg_enabled(
1177                                 pipe_ctx->stream_res.tg))
1178                         continue;
1179
1180                 /* Disable on the current state so the new one isn't cleared. */
1181                 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
1182
1183                 dpp->funcs->dpp_reset(dpp);
1184
1185                 pipe_ctx->stream_res.tg = tg;
1186                 pipe_ctx->pipe_idx = i;
1187
1188                 pipe_ctx->plane_res.hubp = hubp;
1189                 pipe_ctx->plane_res.dpp = dpp;
1190                 pipe_ctx->plane_res.mpcc_inst = dpp->inst;
1191                 hubp->mpcc_id = dpp->inst;
1192                 hubp->opp_id = OPP_ID_INVALID;
1193                 hubp->power_gated = false;
1194
1195                 dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
1196                 dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
1197                 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
1198                 pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
1199
1200                 dc->hwss.plane_atomic_disconnect(dc, pipe_ctx);
1201
1202                 if (tg->funcs->is_tg_enabled(tg))
1203                         tg->funcs->unlock(tg);
1204
1205                 dc->hwss.disable_plane(dc, pipe_ctx);
1206
1207                 pipe_ctx->stream_res.tg = NULL;
1208                 pipe_ctx->plane_res.hubp = NULL;
1209
1210                 tg->funcs->tg_init(tg);
1211         }
1212 }
1213
1214 void dcn10_init_hw(struct dc *dc)
1215 {
1216         int i;
1217         struct abm *abm = dc->res_pool->abm;
1218         struct dmcu *dmcu = dc->res_pool->dmcu;
1219         struct dce_hwseq *hws = dc->hwseq;
1220         struct dc_bios *dcb = dc->ctx->dc_bios;
1221         struct resource_pool *res_pool = dc->res_pool;
1222
1223         if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
1224                 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
1225
1226         // Initialize the dccg
1227         if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->dccg_init)
1228                 dc->res_pool->dccg->funcs->dccg_init(res_pool->dccg);
1229
1230         if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
1231
1232                 REG_WRITE(REFCLK_CNTL, 0);
1233                 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
1234                 REG_WRITE(DIO_MEM_PWR_CTRL, 0);
1235
1236                 if (!dc->debug.disable_clock_gate) {
1237                         /* enable all DCN clock gating */
1238                         REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
1239
1240                         REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
1241
1242                         REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
1243                 }
1244
1245                 //Enable ability to power gate / don't force power on permanently
1246                 dc->hwss.enable_power_gating_plane(hws, true);
1247
1248                 return;
1249         }
1250
1251         if (!dcb->funcs->is_accelerated_mode(dcb))
1252                 dc->hwss.disable_vga(dc->hwseq);
1253
1254         dc->hwss.bios_golden_init(dc);
1255         if (dc->ctx->dc_bios->fw_info_valid) {
1256                 res_pool->ref_clocks.xtalin_clock_inKhz =
1257                                 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
1258
1259                 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
1260                         if (res_pool->dccg && res_pool->hubbub) {
1261
1262                                 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
1263                                                 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
1264                                                 &res_pool->ref_clocks.dccg_ref_clock_inKhz);
1265
1266                                 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
1267                                                 res_pool->ref_clocks.dccg_ref_clock_inKhz,
1268                                                 &res_pool->ref_clocks.dchub_ref_clock_inKhz);
1269                         } else {
1270                                 // Not all ASICs have DCCG sw component
1271                                 res_pool->ref_clocks.dccg_ref_clock_inKhz =
1272                                                 res_pool->ref_clocks.xtalin_clock_inKhz;
1273                                 res_pool->ref_clocks.dchub_ref_clock_inKhz =
1274                                                 res_pool->ref_clocks.xtalin_clock_inKhz;
1275                         }
1276                 }
1277         } else
1278                 ASSERT_CRITICAL(false);
1279
1280         for (i = 0; i < dc->link_count; i++) {
1281                 /* Power up AND update implementation according to the
1282                  * required signal (which may be different from the
1283                  * default signal on connector).
1284                  */
1285                 struct dc_link *link = dc->links[i];
1286
1287                 link->link_enc->funcs->hw_init(link->link_enc);
1288
1289                 /* Check for enabled DIG to identify enabled display */
1290                 if (link->link_enc->funcs->is_dig_enabled &&
1291                         link->link_enc->funcs->is_dig_enabled(link->link_enc))
1292                         link->link_status.link_active = true;
1293         }
1294
1295         /* Power gate DSCs */
1296         for (i = 0; i < res_pool->res_cap->num_dsc; i++)
1297                 if (dc->hwss.dsc_pg_control != NULL)
1298                         dc->hwss.dsc_pg_control(hws, res_pool->dscs[i]->inst, false);
1299
1300         /* If taking control over from VBIOS, we may want to optimize our first
1301          * mode set, so we need to skip powering down pipes until we know which
1302          * pipes we want to use.
1303          * Otherwise, if taking control is not possible, we need to power
1304          * everything down.
1305          */
1306         if (dcb->funcs->is_accelerated_mode(dcb) || dc->config.power_down_display_on_boot) {
1307                 dc->hwss.init_pipes(dc, dc->current_state);
1308         }
1309
1310         for (i = 0; i < res_pool->audio_count; i++) {
1311                 struct audio *audio = res_pool->audios[i];
1312
1313                 audio->funcs->hw_init(audio);
1314         }
1315
1316         if (abm != NULL) {
1317                 abm->funcs->init_backlight(abm);
1318                 abm->funcs->abm_init(abm);
1319         }
1320
1321         if (dmcu != NULL && !dmcu->auto_load_dmcu)
1322                 dmcu->funcs->dmcu_init(dmcu);
1323
1324         if (abm != NULL && dmcu != NULL)
1325                 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
1326
1327         /* power AFMT HDMI memory TODO: may move to dis/en output save power*/
1328         REG_WRITE(DIO_MEM_PWR_CTRL, 0);
1329
1330         if (!dc->debug.disable_clock_gate) {
1331                 /* enable all DCN clock gating */
1332                 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
1333
1334                 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
1335
1336                 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
1337         }
1338
1339         dc->hwss.enable_power_gating_plane(dc->hwseq, true);
1340
1341         if (dc->clk_mgr->funcs->notify_wm_ranges)
1342                 dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);
1343
1344 }
1345
1346 void dcn10_reset_hw_ctx_wrap(
1347                 struct dc *dc,
1348                 struct dc_state *context)
1349 {
1350         int i;
1351
1352         /* Reset Back End*/
1353         for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
1354                 struct pipe_ctx *pipe_ctx_old =
1355                         &dc->current_state->res_ctx.pipe_ctx[i];
1356                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1357
1358                 if (!pipe_ctx_old->stream)
1359                         continue;
1360
1361                 if (pipe_ctx_old->top_pipe)
1362                         continue;
1363
1364                 if (!pipe_ctx->stream ||
1365                                 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
1366                         struct clock_source *old_clk = pipe_ctx_old->clock_source;
1367
1368                         dcn10_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
1369                         if (dc->hwss.enable_stream_gating)
1370                                 dc->hwss.enable_stream_gating(dc, pipe_ctx);
1371                         if (old_clk)
1372                                 old_clk->funcs->cs_power_down(old_clk);
1373                 }
1374         }
1375 }
1376
1377 static bool patch_address_for_sbs_tb_stereo(
1378                 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr)
1379 {
1380         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1381         bool sec_split = pipe_ctx->top_pipe &&
1382                         pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
1383         if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
1384                 (pipe_ctx->stream->timing.timing_3d_format ==
1385                  TIMING_3D_FORMAT_SIDE_BY_SIDE ||
1386                  pipe_ctx->stream->timing.timing_3d_format ==
1387                  TIMING_3D_FORMAT_TOP_AND_BOTTOM)) {
1388                 *addr = plane_state->address.grph_stereo.left_addr;
1389                 plane_state->address.grph_stereo.left_addr =
1390                 plane_state->address.grph_stereo.right_addr;
1391                 return true;
1392         } else {
1393                 if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE &&
1394                         plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) {
1395                         plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO;
1396                         plane_state->address.grph_stereo.right_addr =
1397                         plane_state->address.grph_stereo.left_addr;
1398                 }
1399         }
1400         return false;
1401 }
1402
1403 void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)
1404 {
1405         bool addr_patched = false;
1406         PHYSICAL_ADDRESS_LOC addr;
1407         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1408
1409         if (plane_state == NULL)
1410                 return;
1411
1412         addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);
1413
1414         pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(
1415                         pipe_ctx->plane_res.hubp,
1416                         &plane_state->address,
1417                         plane_state->flip_immediate);
1418
1419         plane_state->status.requested_address = plane_state->address;
1420
1421         if (plane_state->flip_immediate)
1422                 plane_state->status.current_address = plane_state->address;
1423
1424         if (addr_patched)
1425                 pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;
1426 }
1427
1428 bool dcn10_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
1429                         const struct dc_plane_state *plane_state)
1430 {
1431         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
1432         const struct dc_transfer_func *tf = NULL;
1433         bool result = true;
1434
1435         if (dpp_base == NULL)
1436                 return false;
1437
1438         if (plane_state->in_transfer_func)
1439                 tf = plane_state->in_transfer_func;
1440
1441         if (plane_state->gamma_correction &&
1442                 !dpp_base->ctx->dc->debug.always_use_regamma
1443                 && !plane_state->gamma_correction->is_identity
1444                         && dce_use_lut(plane_state->format))
1445                 dpp_base->funcs->dpp_program_input_lut(dpp_base, plane_state->gamma_correction);
1446
1447         if (tf == NULL)
1448                 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
1449         else if (tf->type == TF_TYPE_PREDEFINED) {
1450                 switch (tf->tf) {
1451                 case TRANSFER_FUNCTION_SRGB:
1452                         dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_sRGB);
1453                         break;
1454                 case TRANSFER_FUNCTION_BT709:
1455                         dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_xvYCC);
1456                         break;
1457                 case TRANSFER_FUNCTION_LINEAR:
1458                         dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
1459                         break;
1460                 case TRANSFER_FUNCTION_PQ:
1461                 default:
1462                         result = false;
1463                         break;
1464                 }
1465         } else if (tf->type == TF_TYPE_BYPASS) {
1466                 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
1467         } else {
1468                 cm_helper_translate_curve_to_degamma_hw_format(tf,
1469                                         &dpp_base->degamma_params);
1470                 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base,
1471                                 &dpp_base->degamma_params);
1472                 result = true;
1473         }
1474
1475         return result;
1476 }
1477
1478 #define MAX_NUM_HW_POINTS 0x200
1479
1480 static void log_tf(struct dc_context *ctx,
1481                                 struct dc_transfer_func *tf, uint32_t hw_points_num)
1482 {
1483         // DC_LOG_GAMMA is default logging of all hw points
1484         // DC_LOG_ALL_GAMMA logs all points, not only hw points
1485         // DC_LOG_ALL_TF_POINTS logs all channels of the tf
1486         int i = 0;
1487
1488         DC_LOGGER_INIT(ctx->logger);
1489         DC_LOG_GAMMA("Gamma Correction TF");
1490         DC_LOG_ALL_GAMMA("Logging all tf points...");
1491         DC_LOG_ALL_TF_CHANNELS("Logging all channels...");
1492
1493         for (i = 0; i < hw_points_num; i++) {
1494                 DC_LOG_GAMMA("R\t%d\t%llu", i, tf->tf_pts.red[i].value);
1495                 DC_LOG_ALL_TF_CHANNELS("G\t%d\t%llu", i, tf->tf_pts.green[i].value);
1496                 DC_LOG_ALL_TF_CHANNELS("B\t%d\t%llu", i, tf->tf_pts.blue[i].value);
1497         }
1498
1499         for (i = hw_points_num; i < MAX_NUM_HW_POINTS; i++) {
1500                 DC_LOG_ALL_GAMMA("R\t%d\t%llu", i, tf->tf_pts.red[i].value);
1501                 DC_LOG_ALL_TF_CHANNELS("G\t%d\t%llu", i, tf->tf_pts.green[i].value);
1502                 DC_LOG_ALL_TF_CHANNELS("B\t%d\t%llu", i, tf->tf_pts.blue[i].value);
1503         }
1504 }
1505
1506 bool dcn10_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
1507                                 const struct dc_stream_state *stream)
1508 {
1509         struct dpp *dpp = pipe_ctx->plane_res.dpp;
1510
1511         if (dpp == NULL)
1512                 return false;
1513
1514         dpp->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
1515
1516         if (stream->out_transfer_func &&
1517             stream->out_transfer_func->type == TF_TYPE_PREDEFINED &&
1518             stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB)
1519                 dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_SRGB);
1520
1521         /* dcn10_translate_regamma_to_hw_format takes 750us, only do it when full
1522          * update.
1523          */
1524         else if (cm_helper_translate_curve_to_hw_format(
1525                         stream->out_transfer_func,
1526                         &dpp->regamma_params, false)) {
1527                 dpp->funcs->dpp_program_regamma_pwl(
1528                                 dpp,
1529                                 &dpp->regamma_params, OPP_REGAMMA_USER);
1530         } else
1531                 dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_BYPASS);
1532
1533         if (stream != NULL && stream->ctx != NULL &&
1534                         stream->out_transfer_func != NULL) {
1535                 log_tf(stream->ctx,
1536                                 stream->out_transfer_func,
1537                                 dpp->regamma_params.hw_points_num);
1538         }
1539
1540         return true;
1541 }
1542
1543 void dcn10_pipe_control_lock(
1544         struct dc *dc,
1545         struct pipe_ctx *pipe,
1546         bool lock)
1547 {
1548         /* use TG master update lock to lock everything on the TG
1549          * therefore only top pipe need to lock
1550          */
1551         if (pipe->top_pipe)
1552                 return;
1553
1554         if (dc->debug.sanity_checks)
1555                 dc->hwss.verify_allow_pstate_change_high(dc);
1556
1557         if (lock)
1558                 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);
1559         else
1560                 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);
1561
1562         if (dc->debug.sanity_checks)
1563                 dc->hwss.verify_allow_pstate_change_high(dc);
1564 }
1565
1566 static bool wait_for_reset_trigger_to_occur(
1567         struct dc_context *dc_ctx,
1568         struct timing_generator *tg)
1569 {
1570         bool rc = false;
1571
1572         /* To avoid endless loop we wait at most
1573          * frames_to_wait_on_triggered_reset frames for the reset to occur. */
1574         const uint32_t frames_to_wait_on_triggered_reset = 10;
1575         int i;
1576
1577         for (i = 0; i < frames_to_wait_on_triggered_reset; i++) {
1578
1579                 if (!tg->funcs->is_counter_moving(tg)) {
1580                         DC_ERROR("TG counter is not moving!\n");
1581                         break;
1582                 }
1583
1584                 if (tg->funcs->did_triggered_reset_occur(tg)) {
1585                         rc = true;
1586                         /* usually occurs at i=1 */
1587                         DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",
1588                                         i);
1589                         break;
1590                 }
1591
1592                 /* Wait for one frame. */
1593                 tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);
1594                 tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
1595         }
1596
1597         if (false == rc)
1598                 DC_ERROR("GSL: Timeout on reset trigger!\n");
1599
1600         return rc;
1601 }
1602
1603 void dcn10_enable_timing_synchronization(
1604         struct dc *dc,
1605         int group_index,
1606         int group_size,
1607         struct pipe_ctx *grouped_pipes[])
1608 {
1609         struct dc_context *dc_ctx = dc->ctx;
1610         int i;
1611
1612         DC_SYNC_INFO("Setting up OTG reset trigger\n");
1613
1614         for (i = 1; i < group_size; i++)
1615                 grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger(
1616                                 grouped_pipes[i]->stream_res.tg,
1617                                 grouped_pipes[0]->stream_res.tg->inst);
1618
1619         DC_SYNC_INFO("Waiting for trigger\n");
1620
1621         /* Need to get only check 1 pipe for having reset as all the others are
1622          * synchronized. Look at last pipe programmed to reset.
1623          */
1624
1625         wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[1]->stream_res.tg);
1626         for (i = 1; i < group_size; i++)
1627                 grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(
1628                                 grouped_pipes[i]->stream_res.tg);
1629
1630         DC_SYNC_INFO("Sync complete\n");
1631 }
1632
1633 void dcn10_enable_per_frame_crtc_position_reset(
1634         struct dc *dc,
1635         int group_size,
1636         struct pipe_ctx *grouped_pipes[])
1637 {
1638         struct dc_context *dc_ctx = dc->ctx;
1639         int i;
1640
1641         DC_SYNC_INFO("Setting up\n");
1642         for (i = 0; i < group_size; i++)
1643                 if (grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset)
1644                         grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset(
1645                                         grouped_pipes[i]->stream_res.tg,
1646                                         0,
1647                                         &grouped_pipes[i]->stream->triggered_crtc_reset);
1648
1649         DC_SYNC_INFO("Waiting for trigger\n");
1650
1651         for (i = 0; i < group_size; i++)
1652                 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
1653
1654         DC_SYNC_INFO("Multi-display sync is complete\n");
1655 }
1656
1657 /*static void print_rq_dlg_ttu(
1658                 struct dc *dc,
1659                 struct pipe_ctx *pipe_ctx)
1660 {
1661         DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger,
1662                         "\n============== DML TTU Output parameters [%d] ==============\n"
1663                         "qos_level_low_wm: %d, \n"
1664                         "qos_level_high_wm: %d, \n"
1665                         "min_ttu_vblank: %d, \n"
1666                         "qos_level_flip: %d, \n"
1667                         "refcyc_per_req_delivery_l: %d, \n"
1668                         "qos_level_fixed_l: %d, \n"
1669                         "qos_ramp_disable_l: %d, \n"
1670                         "refcyc_per_req_delivery_pre_l: %d, \n"
1671                         "refcyc_per_req_delivery_c: %d, \n"
1672                         "qos_level_fixed_c: %d, \n"
1673                         "qos_ramp_disable_c: %d, \n"
1674                         "refcyc_per_req_delivery_pre_c: %d\n"
1675                         "=============================================================\n",
1676                         pipe_ctx->pipe_idx,
1677                         pipe_ctx->ttu_regs.qos_level_low_wm,
1678                         pipe_ctx->ttu_regs.qos_level_high_wm,
1679                         pipe_ctx->ttu_regs.min_ttu_vblank,
1680                         pipe_ctx->ttu_regs.qos_level_flip,
1681                         pipe_ctx->ttu_regs.refcyc_per_req_delivery_l,
1682                         pipe_ctx->ttu_regs.qos_level_fixed_l,
1683                         pipe_ctx->ttu_regs.qos_ramp_disable_l,
1684                         pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_l,
1685                         pipe_ctx->ttu_regs.refcyc_per_req_delivery_c,
1686                         pipe_ctx->ttu_regs.qos_level_fixed_c,
1687                         pipe_ctx->ttu_regs.qos_ramp_disable_c,
1688                         pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_c
1689                         );
1690
1691         DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger,
1692                         "\n============== DML DLG Output parameters [%d] ==============\n"
1693                         "refcyc_h_blank_end: %d, \n"
1694                         "dlg_vblank_end: %d, \n"
1695                         "min_dst_y_next_start: %d, \n"
1696                         "refcyc_per_htotal: %d, \n"
1697                         "refcyc_x_after_scaler: %d, \n"
1698                         "dst_y_after_scaler: %d, \n"
1699                         "dst_y_prefetch: %d, \n"
1700                         "dst_y_per_vm_vblank: %d, \n"
1701                         "dst_y_per_row_vblank: %d, \n"
1702                         "ref_freq_to_pix_freq: %d, \n"
1703                         "vratio_prefetch: %d, \n"
1704                         "refcyc_per_pte_group_vblank_l: %d, \n"
1705                         "refcyc_per_meta_chunk_vblank_l: %d, \n"
1706                         "dst_y_per_pte_row_nom_l: %d, \n"
1707                         "refcyc_per_pte_group_nom_l: %d, \n",
1708                         pipe_ctx->pipe_idx,
1709                         pipe_ctx->dlg_regs.refcyc_h_blank_end,
1710                         pipe_ctx->dlg_regs.dlg_vblank_end,
1711                         pipe_ctx->dlg_regs.min_dst_y_next_start,
1712                         pipe_ctx->dlg_regs.refcyc_per_htotal,
1713                         pipe_ctx->dlg_regs.refcyc_x_after_scaler,
1714                         pipe_ctx->dlg_regs.dst_y_after_scaler,
1715                         pipe_ctx->dlg_regs.dst_y_prefetch,
1716                         pipe_ctx->dlg_regs.dst_y_per_vm_vblank,
1717                         pipe_ctx->dlg_regs.dst_y_per_row_vblank,
1718                         pipe_ctx->dlg_regs.ref_freq_to_pix_freq,
1719                         pipe_ctx->dlg_regs.vratio_prefetch,
1720                         pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_l,
1721                         pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_l,
1722                         pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_l,
1723                         pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_l
1724                         );
1725
1726         DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger,
1727                         "\ndst_y_per_meta_row_nom_l: %d, \n"
1728                         "refcyc_per_meta_chunk_nom_l: %d, \n"
1729                         "refcyc_per_line_delivery_pre_l: %d, \n"
1730                         "refcyc_per_line_delivery_l: %d, \n"
1731                         "vratio_prefetch_c: %d, \n"
1732                         "refcyc_per_pte_group_vblank_c: %d, \n"
1733                         "refcyc_per_meta_chunk_vblank_c: %d, \n"
1734                         "dst_y_per_pte_row_nom_c: %d, \n"
1735                         "refcyc_per_pte_group_nom_c: %d, \n"
1736                         "dst_y_per_meta_row_nom_c: %d, \n"
1737                         "refcyc_per_meta_chunk_nom_c: %d, \n"
1738                         "refcyc_per_line_delivery_pre_c: %d, \n"
1739                         "refcyc_per_line_delivery_c: %d \n"
1740                         "========================================================\n",
1741                         pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_l,
1742                         pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_l,
1743                         pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_l,
1744                         pipe_ctx->dlg_regs.refcyc_per_line_delivery_l,
1745                         pipe_ctx->dlg_regs.vratio_prefetch_c,
1746                         pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_c,
1747                         pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_c,
1748                         pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_c,
1749                         pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_c,
1750                         pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_c,
1751                         pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_c,
1752                         pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_c,
1753                         pipe_ctx->dlg_regs.refcyc_per_line_delivery_c
1754                         );
1755
1756         DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger,
1757                         "\n============== DML RQ Output parameters [%d] ==============\n"
1758                         "chunk_size: %d \n"
1759                         "min_chunk_size: %d \n"
1760                         "meta_chunk_size: %d \n"
1761                         "min_meta_chunk_size: %d \n"
1762                         "dpte_group_size: %d \n"
1763                         "mpte_group_size: %d \n"
1764                         "swath_height: %d \n"
1765                         "pte_row_height_linear: %d \n"
1766                         "========================================================\n",
1767                         pipe_ctx->pipe_idx,
1768                         pipe_ctx->rq_regs.rq_regs_l.chunk_size,
1769                         pipe_ctx->rq_regs.rq_regs_l.min_chunk_size,
1770                         pipe_ctx->rq_regs.rq_regs_l.meta_chunk_size,
1771                         pipe_ctx->rq_regs.rq_regs_l.min_meta_chunk_size,
1772                         pipe_ctx->rq_regs.rq_regs_l.dpte_group_size,
1773                         pipe_ctx->rq_regs.rq_regs_l.mpte_group_size,
1774                         pipe_ctx->rq_regs.rq_regs_l.swath_height,
1775                         pipe_ctx->rq_regs.rq_regs_l.pte_row_height_linear
1776                         );
1777 }
1778 */
1779
1780 static void mmhub_read_vm_system_aperture_settings(struct dcn10_hubp *hubp1,
1781                 struct vm_system_aperture_param *apt,
1782                 struct dce_hwseq *hws)
1783 {
1784         PHYSICAL_ADDRESS_LOC physical_page_number;
1785         uint32_t logical_addr_low;
1786         uint32_t logical_addr_high;
1787
1788         REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
1789                         PHYSICAL_PAGE_NUMBER_MSB, &physical_page_number.high_part);
1790         REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
1791                         PHYSICAL_PAGE_NUMBER_LSB, &physical_page_number.low_part);
1792
1793         REG_GET(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1794                         LOGICAL_ADDR, &logical_addr_low);
1795
1796         REG_GET(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1797                         LOGICAL_ADDR, &logical_addr_high);
1798
1799         apt->sys_default.quad_part =  physical_page_number.quad_part << 12;
1800         apt->sys_low.quad_part =  (int64_t)logical_addr_low << 18;
1801         apt->sys_high.quad_part =  (int64_t)logical_addr_high << 18;
1802 }
1803
1804 /* Temporary read settings, future will get values from kmd directly */
1805 static void mmhub_read_vm_context0_settings(struct dcn10_hubp *hubp1,
1806                 struct vm_context0_param *vm0,
1807                 struct dce_hwseq *hws)
1808 {
1809         PHYSICAL_ADDRESS_LOC fb_base;
1810         PHYSICAL_ADDRESS_LOC fb_offset;
1811         uint32_t fb_base_value;
1812         uint32_t fb_offset_value;
1813
1814         REG_GET(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, &fb_base_value);
1815         REG_GET(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, &fb_offset_value);
1816
1817         REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
1818                         PAGE_DIRECTORY_ENTRY_HI32, &vm0->pte_base.high_part);
1819         REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
1820                         PAGE_DIRECTORY_ENTRY_LO32, &vm0->pte_base.low_part);
1821
1822         REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
1823                         LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_start.high_part);
1824         REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
1825                         LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_start.low_part);
1826
1827         REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
1828                         LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_end.high_part);
1829         REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
1830                         LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_end.low_part);
1831
1832         REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
1833                         PHYSICAL_PAGE_ADDR_HI4, &vm0->fault_default.high_part);
1834         REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
1835                         PHYSICAL_PAGE_ADDR_LO32, &vm0->fault_default.low_part);
1836
1837         /*
1838          * The values in VM_CONTEXT0_PAGE_TABLE_BASE_ADDR is in UMA space.
1839          * Therefore we need to do
1840          * DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
1841          * - DCHUBBUB_SDPIF_FB_OFFSET + DCHUBBUB_SDPIF_FB_BASE
1842          */
1843         fb_base.quad_part = (uint64_t)fb_base_value << 24;
1844         fb_offset.quad_part = (uint64_t)fb_offset_value << 24;
1845         vm0->pte_base.quad_part += fb_base.quad_part;
1846         vm0->pte_base.quad_part -= fb_offset.quad_part;
1847 }
1848
1849
1850 void dcn10_program_pte_vm(struct dce_hwseq *hws, struct hubp *hubp)
1851 {
1852         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
1853         struct vm_system_aperture_param apt = { {{ 0 } } };
1854         struct vm_context0_param vm0 = { { { 0 } } };
1855
1856         mmhub_read_vm_system_aperture_settings(hubp1, &apt, hws);
1857         mmhub_read_vm_context0_settings(hubp1, &vm0, hws);
1858
1859         hubp->funcs->hubp_set_vm_system_aperture_settings(hubp, &apt);
1860         hubp->funcs->hubp_set_vm_context0_settings(hubp, &vm0);
1861 }
1862
1863 static void dcn10_enable_plane(
1864         struct dc *dc,
1865         struct pipe_ctx *pipe_ctx,
1866         struct dc_state *context)
1867 {
1868         struct dce_hwseq *hws = dc->hwseq;
1869
1870         if (dc->debug.sanity_checks) {
1871                 dc->hwss.verify_allow_pstate_change_high(dc);
1872         }
1873
1874         undo_DEGVIDCN10_253_wa(dc);
1875
1876         power_on_plane(dc->hwseq,
1877                 pipe_ctx->plane_res.hubp->inst);
1878
1879         /* enable DCFCLK current DCHUB */
1880         pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);
1881
1882         /* make sure OPP_PIPE_CLOCK_EN = 1 */
1883         pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
1884                         pipe_ctx->stream_res.opp,
1885                         true);
1886
1887 /* TODO: enable/disable in dm as per update type.
1888         if (plane_state) {
1889                 DC_LOG_DC(dc->ctx->logger,
1890                                 "Pipe:%d 0x%x: addr hi:0x%x, "
1891                                 "addr low:0x%x, "
1892                                 "src: %d, %d, %d,"
1893                                 " %d; dst: %d, %d, %d, %d;\n",
1894                                 pipe_ctx->pipe_idx,
1895                                 plane_state,
1896                                 plane_state->address.grph.addr.high_part,
1897                                 plane_state->address.grph.addr.low_part,
1898                                 plane_state->src_rect.x,
1899                                 plane_state->src_rect.y,
1900                                 plane_state->src_rect.width,
1901                                 plane_state->src_rect.height,
1902                                 plane_state->dst_rect.x,
1903                                 plane_state->dst_rect.y,
1904                                 plane_state->dst_rect.width,
1905                                 plane_state->dst_rect.height);
1906
1907                 DC_LOG_DC(dc->ctx->logger,
1908                                 "Pipe %d: width, height, x, y         format:%d\n"
1909                                 "viewport:%d, %d, %d, %d\n"
1910                                 "recout:  %d, %d, %d, %d\n",
1911                                 pipe_ctx->pipe_idx,
1912                                 plane_state->format,
1913                                 pipe_ctx->plane_res.scl_data.viewport.width,
1914                                 pipe_ctx->plane_res.scl_data.viewport.height,
1915                                 pipe_ctx->plane_res.scl_data.viewport.x,
1916                                 pipe_ctx->plane_res.scl_data.viewport.y,
1917                                 pipe_ctx->plane_res.scl_data.recout.width,
1918                                 pipe_ctx->plane_res.scl_data.recout.height,
1919                                 pipe_ctx->plane_res.scl_data.recout.x,
1920                                 pipe_ctx->plane_res.scl_data.recout.y);
1921                 print_rq_dlg_ttu(dc, pipe_ctx);
1922         }
1923 */
1924         if (dc->config.gpu_vm_support)
1925                 dcn10_program_pte_vm(hws, pipe_ctx->plane_res.hubp);
1926
1927         if (dc->debug.sanity_checks) {
1928                 dc->hwss.verify_allow_pstate_change_high(dc);
1929         }
1930 }
1931
1932 void dcn10_program_gamut_remap(struct pipe_ctx *pipe_ctx)
1933 {
1934         int i = 0;
1935         struct dpp_grph_csc_adjustment adjust;
1936         memset(&adjust, 0, sizeof(adjust));
1937         adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
1938
1939
1940         if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
1941                 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
1942                 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
1943                         adjust.temperature_matrix[i] =
1944                                 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
1945         }
1946
1947         pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp, &adjust);
1948 }
1949
1950
1951 static bool dcn10_is_rear_mpo_fix_required(struct pipe_ctx *pipe_ctx, enum dc_color_space colorspace)
1952 {
1953         if (pipe_ctx->plane_state && pipe_ctx->plane_state->layer_index > 0 && is_rgb_cspace(colorspace)) {
1954                 if (pipe_ctx->top_pipe) {
1955                         struct pipe_ctx *top = pipe_ctx->top_pipe;
1956
1957                         while (top->top_pipe)
1958                                 top = top->top_pipe; // Traverse to top pipe_ctx
1959                         if (top->plane_state && top->plane_state->layer_index == 0)
1960                                 return true; // Front MPO plane not hidden
1961                 }
1962         }
1963         return false;
1964 }
1965
1966 static void dcn10_set_csc_adjustment_rgb_mpo_fix(struct pipe_ctx *pipe_ctx, uint16_t *matrix)
1967 {
1968         // Override rear plane RGB bias to fix MPO brightness
1969         uint16_t rgb_bias = matrix[3];
1970
1971         matrix[3] = 0;
1972         matrix[7] = 0;
1973         matrix[11] = 0;
1974         pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, matrix);
1975         matrix[3] = rgb_bias;
1976         matrix[7] = rgb_bias;
1977         matrix[11] = rgb_bias;
1978 }
1979
1980 void dcn10_program_output_csc(struct dc *dc,
1981                 struct pipe_ctx *pipe_ctx,
1982                 enum dc_color_space colorspace,
1983                 uint16_t *matrix,
1984                 int opp_id)
1985 {
1986         if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
1987                 if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment != NULL) {
1988
1989                         /* MPO is broken with RGB colorspaces when OCSC matrix
1990                          * brightness offset >= 0 on DCN1 due to OCSC before MPC
1991                          * Blending adds offsets from front + rear to rear plane
1992                          *
1993                          * Fix is to set RGB bias to 0 on rear plane, top plane
1994                          * black value pixels add offset instead of rear + front
1995                          */
1996
1997                         int16_t rgb_bias = matrix[3];
1998                         // matrix[3/7/11] are all the same offset value
1999
2000                         if (rgb_bias > 0 && dcn10_is_rear_mpo_fix_required(pipe_ctx, colorspace)) {
2001                                 dcn10_set_csc_adjustment_rgb_mpo_fix(pipe_ctx, matrix);
2002                         } else {
2003                                 pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, matrix);
2004                         }
2005                 }
2006         } else {
2007                 if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default != NULL)
2008                         pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default(pipe_ctx->plane_res.dpp, colorspace);
2009         }
2010 }
2011
2012 void dcn10_get_surface_visual_confirm_color(
2013                 const struct pipe_ctx *pipe_ctx,
2014                 struct tg_color *color)
2015 {
2016         uint32_t color_value = MAX_TG_COLOR_VALUE;
2017
2018         switch (pipe_ctx->plane_res.scl_data.format) {
2019         case PIXEL_FORMAT_ARGB8888:
2020                 /* set boarder color to red */
2021                 color->color_r_cr = color_value;
2022                 break;
2023
2024         case PIXEL_FORMAT_ARGB2101010:
2025                 /* set boarder color to blue */
2026                 color->color_b_cb = color_value;
2027                 break;
2028         case PIXEL_FORMAT_420BPP8:
2029                 /* set boarder color to green */
2030                 color->color_g_y = color_value;
2031                 break;
2032         case PIXEL_FORMAT_420BPP10:
2033                 /* set boarder color to yellow */
2034                 color->color_g_y = color_value;
2035                 color->color_r_cr = color_value;
2036                 break;
2037         case PIXEL_FORMAT_FP16:
2038                 /* set boarder color to white */
2039                 color->color_r_cr = color_value;
2040                 color->color_b_cb = color_value;
2041                 color->color_g_y = color_value;
2042                 break;
2043         default:
2044                 break;
2045         }
2046 }
2047
2048 void dcn10_get_hdr_visual_confirm_color(
2049                 struct pipe_ctx *pipe_ctx,
2050                 struct tg_color *color)
2051 {
2052         uint32_t color_value = MAX_TG_COLOR_VALUE;
2053
2054         // Determine the overscan color based on the top-most (desktop) plane's context
2055         struct pipe_ctx *top_pipe_ctx  = pipe_ctx;
2056
2057         while (top_pipe_ctx->top_pipe != NULL)
2058                 top_pipe_ctx = top_pipe_ctx->top_pipe;
2059
2060         switch (top_pipe_ctx->plane_res.scl_data.format) {
2061         case PIXEL_FORMAT_ARGB2101010:
2062                 if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_PQ) {
2063                         /* HDR10, ARGB2101010 - set boarder color to red */
2064                         color->color_r_cr = color_value;
2065                 }
2066                 break;
2067         case PIXEL_FORMAT_FP16:
2068                 if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_PQ) {
2069                         /* HDR10, FP16 - set boarder color to blue */
2070                         color->color_b_cb = color_value;
2071                 } else if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22) {
2072                         /* FreeSync 2 HDR - set boarder color to green */
2073                         color->color_g_y = color_value;
2074                 }
2075                 break;
2076         default:
2077                 /* SDR - set boarder color to Gray */
2078                 color->color_r_cr = color_value/2;
2079                 color->color_b_cb = color_value/2;
2080                 color->color_g_y = color_value/2;
2081                 break;
2082         }
2083 }
2084
2085 static void dcn10_update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state)
2086 {
2087         struct dc_bias_and_scale bns_params = {0};
2088
2089         // program the input csc
2090         dpp->funcs->dpp_setup(dpp,
2091                         plane_state->format,
2092                         EXPANSION_MODE_ZERO,
2093                         plane_state->input_csc_color_matrix,
2094                         plane_state->color_space,
2095                         NULL);
2096
2097         //set scale and bias registers
2098         build_prescale_params(&bns_params, plane_state);
2099         if (dpp->funcs->dpp_program_bias_and_scale)
2100                 dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
2101 }
2102
2103 void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
2104 {
2105         struct hubp *hubp = pipe_ctx->plane_res.hubp;
2106         struct mpcc_blnd_cfg blnd_cfg = {{0}};
2107         bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
2108         int mpcc_id;
2109         struct mpcc *new_mpcc;
2110         struct mpc *mpc = dc->res_pool->mpc;
2111         struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);
2112
2113         if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) {
2114                 dc->hwss.get_hdr_visual_confirm_color(
2115                                 pipe_ctx, &blnd_cfg.black_color);
2116         } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) {
2117                 dc->hwss.get_surface_visual_confirm_color(
2118                                 pipe_ctx, &blnd_cfg.black_color);
2119         } else {
2120                 color_space_to_black_color(
2121                                 dc, pipe_ctx->stream->output_color_space,
2122                                 &blnd_cfg.black_color);
2123         }
2124
2125         if (per_pixel_alpha)
2126                 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;
2127         else
2128                 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA;
2129
2130         blnd_cfg.overlap_only = false;
2131         blnd_cfg.global_gain = 0xff;
2132
2133         if (pipe_ctx->plane_state->global_alpha)
2134                 blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value;
2135         else
2136                 blnd_cfg.global_alpha = 0xff;
2137
2138         /* DCN1.0 has output CM before MPC which seems to screw with
2139          * pre-multiplied alpha.
2140          */
2141         blnd_cfg.pre_multiplied_alpha = is_rgb_cspace(
2142                         pipe_ctx->stream->output_color_space)
2143                                         && per_pixel_alpha;
2144
2145
2146         /*
2147          * TODO: remove hack
2148          * Note: currently there is a bug in init_hw such that
2149          * on resume from hibernate, BIOS sets up MPCC0, and
2150          * we do mpcc_remove but the mpcc cannot go to idle
2151          * after remove. This cause us to pick mpcc1 here,
2152          * which causes a pstate hang for yet unknown reason.
2153          */
2154         mpcc_id = hubp->inst;
2155
2156         /* If there is no full update, don't need to touch MPC tree*/
2157         if (!pipe_ctx->plane_state->update_flags.bits.full_update) {
2158                 mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id);
2159                 return;
2160         }
2161
2162         /* check if this MPCC is already being used */
2163         new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id);
2164         /* remove MPCC if being used */
2165         if (new_mpcc != NULL)
2166                 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc);
2167         else
2168                 if (dc->debug.sanity_checks)
2169                         mpc->funcs->assert_mpcc_idle_before_connect(
2170                                         dc->res_pool->mpc, mpcc_id);
2171
2172         /* Call MPC to insert new plane */
2173         new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,
2174                         mpc_tree_params,
2175                         &blnd_cfg,
2176                         NULL,
2177                         NULL,
2178                         hubp->inst,
2179                         mpcc_id);
2180
2181         ASSERT(new_mpcc != NULL);
2182
2183         hubp->opp_id = pipe_ctx->stream_res.opp->inst;
2184         hubp->mpcc_id = mpcc_id;
2185 }
2186
2187 static void update_scaler(struct pipe_ctx *pipe_ctx)
2188 {
2189         bool per_pixel_alpha =
2190                         pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
2191
2192         pipe_ctx->plane_res.scl_data.lb_params.alpha_en = per_pixel_alpha;
2193         pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
2194         /* scaler configuration */
2195         pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(
2196                         pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);
2197 }
2198
2199 static void dcn10_update_dchubp_dpp(
2200         struct dc *dc,
2201         struct pipe_ctx *pipe_ctx,
2202         struct dc_state *context)
2203 {
2204         struct hubp *hubp = pipe_ctx->plane_res.hubp;
2205         struct dpp *dpp = pipe_ctx->plane_res.dpp;
2206         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2207         struct plane_size size = plane_state->plane_size;
2208         unsigned int compat_level = 0;
2209
2210         /* depends on DML calculation, DPP clock value may change dynamically */
2211         /* If request max dpp clk is lower than current dispclk, no need to
2212          * divided by 2
2213          */
2214         if (plane_state->update_flags.bits.full_update) {
2215                 bool should_divided_by_2 = context->bw_ctx.bw.dcn.clk.dppclk_khz <=
2216                                 dc->clk_mgr->clks.dispclk_khz / 2;
2217
2218                 dpp->funcs->dpp_dppclk_control(
2219                                 dpp,
2220                                 should_divided_by_2,
2221                                 true);
2222
2223                 if (dc->res_pool->dccg)
2224                         dc->res_pool->dccg->funcs->update_dpp_dto(
2225                                         dc->res_pool->dccg,
2226                                         dpp->inst,
2227                                         pipe_ctx->plane_res.bw.dppclk_khz);
2228                 else
2229                         dc->clk_mgr->clks.dppclk_khz = should_divided_by_2 ?
2230                                                 dc->clk_mgr->clks.dispclk_khz / 2 :
2231                                                         dc->clk_mgr->clks.dispclk_khz;
2232         }
2233
2234         /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG
2235          * VTG is within DCHUBBUB which is commond block share by each pipe HUBP.
2236          * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG
2237          */
2238         if (plane_state->update_flags.bits.full_update) {
2239                 hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst);
2240
2241                 hubp->funcs->hubp_setup(
2242                         hubp,
2243                         &pipe_ctx->dlg_regs,
2244                         &pipe_ctx->ttu_regs,
2245                         &pipe_ctx->rq_regs,
2246                         &pipe_ctx->pipe_dlg_param);
2247                 hubp->funcs->hubp_setup_interdependent(
2248                         hubp,
2249                         &pipe_ctx->dlg_regs,
2250                         &pipe_ctx->ttu_regs);
2251         }
2252
2253         size.surface_size = pipe_ctx->plane_res.scl_data.viewport;
2254
2255         if (plane_state->update_flags.bits.full_update ||
2256                 plane_state->update_flags.bits.bpp_change)
2257                 dcn10_update_dpp(dpp, plane_state);
2258
2259         if (plane_state->update_flags.bits.full_update ||
2260                 plane_state->update_flags.bits.per_pixel_alpha_change ||
2261                 plane_state->update_flags.bits.global_alpha_change)
2262                 dc->hwss.update_mpcc(dc, pipe_ctx);
2263
2264         if (plane_state->update_flags.bits.full_update ||
2265                 plane_state->update_flags.bits.per_pixel_alpha_change ||
2266                 plane_state->update_flags.bits.global_alpha_change ||
2267                 plane_state->update_flags.bits.scaling_change ||
2268                 plane_state->update_flags.bits.position_change) {
2269                 update_scaler(pipe_ctx);
2270         }
2271
2272         if (plane_state->update_flags.bits.full_update ||
2273                 plane_state->update_flags.bits.scaling_change ||
2274                 plane_state->update_flags.bits.position_change) {
2275                 hubp->funcs->mem_program_viewport(
2276                         hubp,
2277                         &pipe_ctx->plane_res.scl_data.viewport,
2278                         &pipe_ctx->plane_res.scl_data.viewport_c);
2279         }
2280
2281         if (pipe_ctx->stream->cursor_attributes.address.quad_part != 0) {
2282                 dc->hwss.set_cursor_position(pipe_ctx);
2283                 dc->hwss.set_cursor_attribute(pipe_ctx);
2284
2285                 if (dc->hwss.set_cursor_sdr_white_level)
2286                         dc->hwss.set_cursor_sdr_white_level(pipe_ctx);
2287         }
2288
2289         if (plane_state->update_flags.bits.full_update) {
2290                 /*gamut remap*/
2291                 dc->hwss.program_gamut_remap(pipe_ctx);
2292
2293                 dc->hwss.program_output_csc(dc,
2294                                 pipe_ctx,
2295                                 pipe_ctx->stream->output_color_space,
2296                                 pipe_ctx->stream->csc_color_matrix.matrix,
2297                                 pipe_ctx->stream_res.opp->inst);
2298         }
2299
2300         if (plane_state->update_flags.bits.full_update ||
2301                 plane_state->update_flags.bits.pixel_format_change ||
2302                 plane_state->update_flags.bits.horizontal_mirror_change ||
2303                 plane_state->update_flags.bits.rotation_change ||
2304                 plane_state->update_flags.bits.swizzle_change ||
2305                 plane_state->update_flags.bits.dcc_change ||
2306                 plane_state->update_flags.bits.bpp_change ||
2307                 plane_state->update_flags.bits.scaling_change ||
2308                 plane_state->update_flags.bits.plane_size_change) {
2309                 hubp->funcs->hubp_program_surface_config(
2310                         hubp,
2311                         plane_state->format,
2312                         &plane_state->tiling_info,
2313                         &size,
2314                         plane_state->rotation,
2315                         &plane_state->dcc,
2316                         plane_state->horizontal_mirror,
2317                         compat_level);
2318         }
2319
2320         hubp->power_gated = false;
2321
2322         dc->hwss.update_plane_addr(dc, pipe_ctx);
2323
2324         if (is_pipe_tree_visible(pipe_ctx))
2325                 hubp->funcs->set_blank(hubp, false);
2326 }
2327
2328 void dcn10_blank_pixel_data(
2329                 struct dc *dc,
2330                 struct pipe_ctx *pipe_ctx,
2331                 bool blank)
2332 {
2333         enum dc_color_space color_space;
2334         struct tg_color black_color = {0};
2335         struct stream_resource *stream_res = &pipe_ctx->stream_res;
2336         struct dc_stream_state *stream = pipe_ctx->stream;
2337
2338         /* program otg blank color */
2339         color_space = stream->output_color_space;
2340         color_space_to_black_color(dc, color_space, &black_color);
2341
2342         /*
2343          * The way 420 is packed, 2 channels carry Y component, 1 channel
2344          * alternate between Cb and Cr, so both channels need the pixel
2345          * value for Y
2346          */
2347         if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
2348                 black_color.color_r_cr = black_color.color_g_y;
2349
2350
2351         if (stream_res->tg->funcs->set_blank_color)
2352                 stream_res->tg->funcs->set_blank_color(
2353                                 stream_res->tg,
2354                                 &black_color);
2355
2356         if (!blank) {
2357                 if (stream_res->tg->funcs->set_blank)
2358                         stream_res->tg->funcs->set_blank(stream_res->tg, blank);
2359                 if (stream_res->abm) {
2360                         stream_res->abm->funcs->set_pipe(stream_res->abm, stream_res->tg->inst + 1);
2361                         stream_res->abm->funcs->set_abm_level(stream_res->abm, stream->abm_level);
2362                 }
2363         } else if (blank) {
2364                 if (stream_res->abm)
2365                         stream_res->abm->funcs->set_abm_immediate_disable(stream_res->abm);
2366                 if (stream_res->tg->funcs->set_blank)
2367                         stream_res->tg->funcs->set_blank(stream_res->tg, blank);
2368         }
2369 }
2370
2371 void dcn10_set_hdr_multiplier(struct pipe_ctx *pipe_ctx)
2372 {
2373         struct fixed31_32 multiplier = pipe_ctx->plane_state->hdr_mult;
2374         uint32_t hw_mult = 0x1f000; // 1.0 default multiplier
2375         struct custom_float_format fmt;
2376         bool mult_negative; // True if fixed31_32 sign bit indicates negative value
2377         uint32_t mult_int; // int component of fixed31_32
2378
2379         fmt.exponenta_bits = 6;
2380         fmt.mantissa_bits = 12;
2381         fmt.sign = true;
2382
2383         mult_negative = multiplier.value >> 63 != 0;
2384         mult_int = multiplier.value >> 32;
2385
2386         if (mult_int && !mult_negative) // Check if greater than 1
2387                 convert_to_custom_float_format(multiplier, &fmt, &hw_mult);
2388
2389         pipe_ctx->plane_res.dpp->funcs->dpp_set_hdr_multiplier(
2390                         pipe_ctx->plane_res.dpp, hw_mult);
2391 }
2392
2393 void dcn10_program_pipe(
2394                 struct dc *dc,
2395                 struct pipe_ctx *pipe_ctx,
2396                 struct dc_state *context)
2397 {
2398         if (pipe_ctx->plane_state->update_flags.bits.full_update)
2399                 dcn10_enable_plane(dc, pipe_ctx, context);
2400
2401         dcn10_update_dchubp_dpp(dc, pipe_ctx, context);
2402
2403         dc->hwss.set_hdr_multiplier(pipe_ctx);
2404
2405         if (pipe_ctx->plane_state->update_flags.bits.full_update ||
2406                         pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
2407                         pipe_ctx->plane_state->update_flags.bits.gamma_change)
2408                 dc->hwss.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);
2409
2410         /* dcn10_translate_regamma_to_hw_format takes 750us to finish
2411          * only do gamma programming for full update.
2412          * TODO: This can be further optimized/cleaned up
2413          * Always call this for now since it does memcmp inside before
2414          * doing heavy calculation and programming
2415          */
2416         if (pipe_ctx->plane_state->update_flags.bits.full_update)
2417                 dc->hwss.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
2418 }
2419
2420 static void dcn10_program_all_pipe_in_tree(
2421                 struct dc *dc,
2422                 struct pipe_ctx *pipe_ctx,
2423                 struct dc_state *context)
2424 {
2425         if (pipe_ctx->top_pipe == NULL) {
2426                 bool blank = !is_pipe_tree_visible(pipe_ctx);
2427
2428                 pipe_ctx->stream_res.tg->funcs->program_global_sync(
2429                                 pipe_ctx->stream_res.tg,
2430                                 pipe_ctx->pipe_dlg_param.vready_offset,
2431                                 pipe_ctx->pipe_dlg_param.vstartup_start,
2432                                 pipe_ctx->pipe_dlg_param.vupdate_offset,
2433                                 pipe_ctx->pipe_dlg_param.vupdate_width);
2434
2435                 pipe_ctx->stream_res.tg->funcs->set_vtg_params(
2436                                 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
2437
2438                 if (dc->hwss.setup_vupdate_interrupt)
2439                         dc->hwss.setup_vupdate_interrupt(dc, pipe_ctx);
2440
2441                 dc->hwss.blank_pixel_data(dc, pipe_ctx, blank);
2442         }
2443
2444         if (pipe_ctx->plane_state != NULL)
2445                 dc->hwss.program_pipe(dc, pipe_ctx, context);
2446
2447         if (pipe_ctx->bottom_pipe != NULL && pipe_ctx->bottom_pipe != pipe_ctx)
2448                 dcn10_program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context);
2449 }
2450
2451 static struct pipe_ctx *dcn10_find_top_pipe_for_stream(
2452                 struct dc *dc,
2453                 struct dc_state *context,
2454                 const struct dc_stream_state *stream)
2455 {
2456         int i;
2457
2458         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2459                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2460                 struct pipe_ctx *old_pipe_ctx =
2461                                 &dc->current_state->res_ctx.pipe_ctx[i];
2462
2463                 if (!pipe_ctx->plane_state && !old_pipe_ctx->plane_state)
2464                         continue;
2465
2466                 if (pipe_ctx->stream != stream)
2467                         continue;
2468
2469                 if (!pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe)
2470                         return pipe_ctx;
2471         }
2472         return NULL;
2473 }
2474
2475 void dcn10_apply_ctx_for_surface(
2476                 struct dc *dc,
2477                 const struct dc_stream_state *stream,
2478                 int num_planes,
2479                 struct dc_state *context)
2480 {
2481         int i;
2482         struct timing_generator *tg;
2483         uint32_t underflow_check_delay_us;
2484         bool removed_pipe[4] = { false };
2485         bool interdependent_update = false;
2486         struct pipe_ctx *top_pipe_to_program =
2487                         dcn10_find_top_pipe_for_stream(dc, context, stream);
2488         DC_LOGGER_INIT(dc->ctx->logger);
2489
2490         if (!top_pipe_to_program)
2491                 return;
2492
2493         tg = top_pipe_to_program->stream_res.tg;
2494
2495         interdependent_update = top_pipe_to_program->plane_state &&
2496                 top_pipe_to_program->plane_state->update_flags.bits.full_update;
2497
2498         underflow_check_delay_us = dc->debug.underflow_assert_delay_us;
2499
2500         if (underflow_check_delay_us != 0xFFFFFFFF && dc->hwss.did_underflow_occur)
2501                 ASSERT(dc->hwss.did_underflow_occur(dc, top_pipe_to_program));
2502
2503         if (interdependent_update)
2504                 dcn10_lock_all_pipes(dc, context, true);
2505         else
2506                 dcn10_pipe_control_lock(dc, top_pipe_to_program, true);
2507
2508         if (underflow_check_delay_us != 0xFFFFFFFF)
2509                 udelay(underflow_check_delay_us);
2510
2511         if (underflow_check_delay_us != 0xFFFFFFFF && dc->hwss.did_underflow_occur)
2512                 ASSERT(dc->hwss.did_underflow_occur(dc, top_pipe_to_program));
2513
2514         if (num_planes == 0) {
2515                 /* OTG blank before remove all front end */
2516                 dc->hwss.blank_pixel_data(dc, top_pipe_to_program, true);
2517         }
2518
2519         /* Disconnect unused mpcc */
2520         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2521                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2522                 struct pipe_ctx *old_pipe_ctx =
2523                                 &dc->current_state->res_ctx.pipe_ctx[i];
2524                 /*
2525                  * Powergate reused pipes that are not powergated
2526                  * fairly hacky right now, using opp_id as indicator
2527                  * TODO: After move dc_post to dc_update, this will
2528                  * be removed.
2529                  */
2530                 if (pipe_ctx->plane_state && !old_pipe_ctx->plane_state) {
2531                         if (old_pipe_ctx->stream_res.tg == tg &&
2532                             old_pipe_ctx->plane_res.hubp &&
2533                             old_pipe_ctx->plane_res.hubp->opp_id != OPP_ID_INVALID)
2534                                 dc->hwss.disable_plane(dc, old_pipe_ctx);
2535                 }
2536
2537                 if ((!pipe_ctx->plane_state ||
2538                      pipe_ctx->stream_res.tg != old_pipe_ctx->stream_res.tg) &&
2539                     old_pipe_ctx->plane_state &&
2540                     old_pipe_ctx->stream_res.tg == tg) {
2541
2542                         dc->hwss.plane_atomic_disconnect(dc, old_pipe_ctx);
2543                         removed_pipe[i] = true;
2544
2545                         DC_LOG_DC("Reset mpcc for pipe %d\n",
2546                                         old_pipe_ctx->pipe_idx);
2547                 }
2548         }
2549
2550         if (num_planes > 0)
2551                 dcn10_program_all_pipe_in_tree(dc, top_pipe_to_program, context);
2552
2553         /* Program secondary blending tree and writeback pipes */
2554         if ((stream->num_wb_info > 0) && (dc->hwss.program_all_writeback_pipes_in_tree))
2555                 dc->hwss.program_all_writeback_pipes_in_tree(dc, stream, context);
2556         if (interdependent_update)
2557                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2558                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2559                         /* Skip inactive pipes and ones already updated */
2560                         if (!pipe_ctx->stream || pipe_ctx->stream == stream ||
2561                             !pipe_ctx->plane_state || !tg->funcs->is_tg_enabled(tg))
2562                                 continue;
2563
2564                         pipe_ctx->plane_res.hubp->funcs->hubp_setup_interdependent(
2565                                 pipe_ctx->plane_res.hubp,
2566                                 &pipe_ctx->dlg_regs,
2567                                 &pipe_ctx->ttu_regs);
2568                 }
2569
2570         if (interdependent_update)
2571                 dcn10_lock_all_pipes(dc, context, false);
2572         else
2573                 dcn10_pipe_control_lock(dc, top_pipe_to_program, false);
2574
2575         if (num_planes == 0)
2576                 false_optc_underflow_wa(dc, stream, tg);
2577
2578         for (i = 0; i < dc->res_pool->pipe_count; i++)
2579                 if (removed_pipe[i])
2580                         dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
2581
2582         for (i = 0; i < dc->res_pool->pipe_count; i++)
2583                 if (removed_pipe[i]) {
2584                         dc->hwss.optimize_bandwidth(dc, context);
2585                         break;
2586                 }
2587
2588         if (dc->hwseq->wa.DEGVIDCN10_254)
2589                 hubbub1_wm_change_req_wa(dc->res_pool->hubbub);
2590 }
2591
2592 static void dcn10_stereo_hw_frame_pack_wa(struct dc *dc, struct dc_state *context)
2593 {
2594         uint8_t i;
2595
2596         for (i = 0; i < context->stream_count; i++) {
2597                 if (context->streams[i]->timing.timing_3d_format
2598                                 == TIMING_3D_FORMAT_HW_FRAME_PACKING) {
2599                         /*
2600                          * Disable stutter
2601                          */
2602                         hubbub1_allow_self_refresh_control(dc->res_pool->hubbub, false);
2603                         break;
2604                 }
2605         }
2606 }
2607
2608 void dcn10_prepare_bandwidth(
2609                 struct dc *dc,
2610                 struct dc_state *context)
2611 {
2612         struct hubbub *hubbub = dc->res_pool->hubbub;
2613
2614         if (dc->debug.sanity_checks)
2615                 dc->hwss.verify_allow_pstate_change_high(dc);
2616
2617         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
2618                 if (context->stream_count == 0)
2619                         context->bw_ctx.bw.dcn.clk.phyclk_khz = 0;
2620
2621                 dc->clk_mgr->funcs->update_clocks(
2622                                 dc->clk_mgr,
2623                                 context,
2624                                 false);
2625         }
2626
2627         hubbub->funcs->program_watermarks(hubbub,
2628                         &context->bw_ctx.bw.dcn.watermarks,
2629                         dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
2630                         true);
2631         dcn10_stereo_hw_frame_pack_wa(dc, context);
2632
2633         if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE)
2634                 dcn_bw_notify_pplib_of_wm_ranges(dc);
2635
2636         if (dc->debug.sanity_checks)
2637                 dc->hwss.verify_allow_pstate_change_high(dc);
2638 }
2639
2640 void dcn10_optimize_bandwidth(
2641                 struct dc *dc,
2642                 struct dc_state *context)
2643 {
2644         struct hubbub *hubbub = dc->res_pool->hubbub;
2645
2646         if (dc->debug.sanity_checks)
2647                 dc->hwss.verify_allow_pstate_change_high(dc);
2648
2649         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
2650                 if (context->stream_count == 0)
2651                         context->bw_ctx.bw.dcn.clk.phyclk_khz = 0;
2652
2653                 dc->clk_mgr->funcs->update_clocks(
2654                                 dc->clk_mgr,
2655                                 context,
2656                                 true);
2657         }
2658
2659         hubbub->funcs->program_watermarks(hubbub,
2660                         &context->bw_ctx.bw.dcn.watermarks,
2661                         dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
2662                         true);
2663         dcn10_stereo_hw_frame_pack_wa(dc, context);
2664
2665         if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE)
2666                 dcn_bw_notify_pplib_of_wm_ranges(dc);
2667
2668         if (dc->debug.sanity_checks)
2669                 dc->hwss.verify_allow_pstate_change_high(dc);
2670 }
2671
2672 void dcn10_set_drr(struct pipe_ctx **pipe_ctx,
2673                 int num_pipes, unsigned int vmin, unsigned int vmax,
2674                 unsigned int vmid, unsigned int vmid_frame_number)
2675 {
2676         int i = 0;
2677         struct drr_params params = {0};
2678         // DRR set trigger event mapped to OTG_TRIG_A (bit 11) for manual control flow
2679         unsigned int event_triggers = 0x800;
2680
2681         params.vertical_total_max = vmax;
2682         params.vertical_total_min = vmin;
2683         params.vertical_total_mid = vmid;
2684         params.vertical_total_mid_frame_num = vmid_frame_number;
2685
2686         /* TODO: If multiple pipes are to be supported, you need
2687          * some GSL stuff. Static screen triggers may be programmed differently
2688          * as well.
2689          */
2690         for (i = 0; i < num_pipes; i++) {
2691                 pipe_ctx[i]->stream_res.tg->funcs->set_drr(
2692                         pipe_ctx[i]->stream_res.tg, &params);
2693                 if (vmax != 0 && vmin != 0)
2694                         pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control(
2695                                         pipe_ctx[i]->stream_res.tg,
2696                                         event_triggers);
2697         }
2698 }
2699
2700 void dcn10_get_position(struct pipe_ctx **pipe_ctx,
2701                 int num_pipes,
2702                 struct crtc_position *position)
2703 {
2704         int i = 0;
2705
2706         /* TODO: handle pipes > 1
2707          */
2708         for (i = 0; i < num_pipes; i++)
2709                 pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);
2710 }
2711
2712 void dcn10_set_static_screen_control(struct pipe_ctx **pipe_ctx,
2713                 int num_pipes, const struct dc_static_screen_events *events)
2714 {
2715         unsigned int i;
2716         unsigned int value = 0;
2717
2718         if (events->surface_update)
2719                 value |= 0x80;
2720         if (events->cursor_update)
2721                 value |= 0x2;
2722         if (events->force_trigger)
2723                 value |= 0x1;
2724
2725         for (i = 0; i < num_pipes; i++)
2726                 pipe_ctx[i]->stream_res.tg->funcs->
2727                         set_static_screen_control(pipe_ctx[i]->stream_res.tg, value);
2728 }
2729
2730 static void dcn10_config_stereo_parameters(
2731                 struct dc_stream_state *stream, struct crtc_stereo_flags *flags)
2732 {
2733         enum view_3d_format view_format = stream->view_format;
2734         enum dc_timing_3d_format timing_3d_format =\
2735                         stream->timing.timing_3d_format;
2736         bool non_stereo_timing = false;
2737
2738         if (timing_3d_format == TIMING_3D_FORMAT_NONE ||
2739                 timing_3d_format == TIMING_3D_FORMAT_SIDE_BY_SIDE ||
2740                 timing_3d_format == TIMING_3D_FORMAT_TOP_AND_BOTTOM)
2741                 non_stereo_timing = true;
2742
2743         if (non_stereo_timing == false &&
2744                 view_format == VIEW_3D_FORMAT_FRAME_SEQUENTIAL) {
2745
2746                 flags->PROGRAM_STEREO         = 1;
2747                 flags->PROGRAM_POLARITY       = 1;
2748                 if (timing_3d_format == TIMING_3D_FORMAT_INBAND_FA ||
2749                         timing_3d_format == TIMING_3D_FORMAT_DP_HDMI_INBAND_FA ||
2750                         timing_3d_format == TIMING_3D_FORMAT_SIDEBAND_FA) {
2751                         enum display_dongle_type dongle = \
2752                                         stream->link->ddc->dongle_type;
2753                         if (dongle == DISPLAY_DONGLE_DP_VGA_CONVERTER ||
2754                                 dongle == DISPLAY_DONGLE_DP_DVI_CONVERTER ||
2755                                 dongle == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
2756                                 flags->DISABLE_STEREO_DP_SYNC = 1;
2757                 }
2758                 flags->RIGHT_EYE_POLARITY =\
2759                                 stream->timing.flags.RIGHT_EYE_3D_POLARITY;
2760                 if (timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
2761                         flags->FRAME_PACKED = 1;
2762         }
2763
2764         return;
2765 }
2766
2767 void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc)
2768 {
2769         struct crtc_stereo_flags flags = { 0 };
2770         struct dc_stream_state *stream = pipe_ctx->stream;
2771
2772         dcn10_config_stereo_parameters(stream, &flags);
2773
2774         if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_SIDEBAND_FA) {
2775                 if (!dc_set_generic_gpio_for_stereo(true, dc->ctx->gpio_service))
2776                         dc_set_generic_gpio_for_stereo(false, dc->ctx->gpio_service);
2777         } else {
2778                 dc_set_generic_gpio_for_stereo(false, dc->ctx->gpio_service);
2779         }
2780
2781         pipe_ctx->stream_res.opp->funcs->opp_program_stereo(
2782                 pipe_ctx->stream_res.opp,
2783                 flags.PROGRAM_STEREO == 1 ? true:false,
2784                 &stream->timing);
2785
2786         pipe_ctx->stream_res.tg->funcs->program_stereo(
2787                 pipe_ctx->stream_res.tg,
2788                 &stream->timing,
2789                 &flags);
2790
2791         return;
2792 }
2793
2794 static struct hubp *get_hubp_by_inst(struct resource_pool *res_pool, int mpcc_inst)
2795 {
2796         int i;
2797
2798         for (i = 0; i < res_pool->pipe_count; i++) {
2799                 if (res_pool->hubps[i]->inst == mpcc_inst)
2800                         return res_pool->hubps[i];
2801         }
2802         ASSERT(false);
2803         return NULL;
2804 }
2805
2806 void dcn10_wait_for_mpcc_disconnect(
2807                 struct dc *dc,
2808                 struct resource_pool *res_pool,
2809                 struct pipe_ctx *pipe_ctx)
2810 {
2811         int mpcc_inst;
2812
2813         if (dc->debug.sanity_checks) {
2814                 dc->hwss.verify_allow_pstate_change_high(dc);
2815         }
2816
2817         if (!pipe_ctx->stream_res.opp)
2818                 return;
2819
2820         for (mpcc_inst = 0; mpcc_inst < MAX_PIPES; mpcc_inst++) {
2821                 if (pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst]) {
2822                         struct hubp *hubp = get_hubp_by_inst(res_pool, mpcc_inst);
2823
2824                         res_pool->mpc->funcs->wait_for_idle(res_pool->mpc, mpcc_inst);
2825                         pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst] = false;
2826                         hubp->funcs->set_blank(hubp, true);
2827                 }
2828         }
2829
2830         if (dc->debug.sanity_checks) {
2831                 dc->hwss.verify_allow_pstate_change_high(dc);
2832         }
2833
2834 }
2835
2836 bool dcn10_dummy_display_power_gating(
2837         struct dc *dc,
2838         uint8_t controller_id,
2839         struct dc_bios *dcb,
2840         enum pipe_gating_control power_gating)
2841 {
2842         return true;
2843 }
2844
2845 void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx)
2846 {
2847         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2848         struct timing_generator *tg = pipe_ctx->stream_res.tg;
2849         bool flip_pending;
2850
2851         if (plane_state == NULL)
2852                 return;
2853
2854         flip_pending = pipe_ctx->plane_res.hubp->funcs->hubp_is_flip_pending(
2855                                         pipe_ctx->plane_res.hubp);
2856
2857         plane_state->status.is_flip_pending = plane_state->status.is_flip_pending || flip_pending;
2858
2859         if (!flip_pending)
2860                 plane_state->status.current_address = plane_state->status.requested_address;
2861
2862         if (plane_state->status.current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2863                         tg->funcs->is_stereo_left_eye) {
2864                 plane_state->status.is_right_eye =
2865                                 !tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);
2866         }
2867 }
2868
2869 void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data)
2870 {
2871         struct hubbub *hubbub = hws->ctx->dc->res_pool->hubbub;
2872
2873         /* In DCN, this programming sequence is owned by the hubbub */
2874         hubbub->funcs->update_dchub(hubbub, dh_data);
2875 }
2876
2877 void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)
2878 {
2879         struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;
2880         struct hubp *hubp = pipe_ctx->plane_res.hubp;
2881         struct dpp *dpp = pipe_ctx->plane_res.dpp;
2882         struct dc_cursor_mi_param param = {
2883                 .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10,
2884                 .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz,
2885                 .viewport = pipe_ctx->plane_res.scl_data.viewport,
2886                 .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz,
2887                 .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert,
2888                 .rotation = pipe_ctx->plane_state->rotation,
2889                 .mirror = pipe_ctx->plane_state->horizontal_mirror
2890         };
2891         uint32_t x_plane = pipe_ctx->plane_state->dst_rect.x;
2892         uint32_t y_plane = pipe_ctx->plane_state->dst_rect.y;
2893         uint32_t x_offset = min(x_plane, pos_cpy.x);
2894         uint32_t y_offset = min(y_plane, pos_cpy.y);
2895
2896         pos_cpy.x -= x_offset;
2897         pos_cpy.y -= y_offset;
2898         pos_cpy.x_hotspot += (x_plane - x_offset);
2899         pos_cpy.y_hotspot += (y_plane - y_offset);
2900
2901         if (pipe_ctx->plane_state->address.type
2902                         == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
2903                 pos_cpy.enable = false;
2904
2905         // Swap axis and mirror horizontally
2906         if (param.rotation == ROTATION_ANGLE_90) {
2907                 uint32_t temp_x = pos_cpy.x;
2908                 pos_cpy.x = pipe_ctx->plane_res.scl_data.viewport.width -
2909                                 (pos_cpy.y - pipe_ctx->plane_res.scl_data.viewport.x) + pipe_ctx->plane_res.scl_data.viewport.x;
2910                 pos_cpy.y = temp_x;
2911         }
2912         // Swap axis and mirror vertically
2913         else if (param.rotation == ROTATION_ANGLE_270) {
2914                 uint32_t temp_y = pos_cpy.y;
2915                 if (pos_cpy.x >  pipe_ctx->plane_res.scl_data.viewport.height) {
2916                         pos_cpy.x = pos_cpy.x - pipe_ctx->plane_res.scl_data.viewport.height;
2917                         pos_cpy.y = pipe_ctx->plane_res.scl_data.viewport.height - pos_cpy.x;
2918                 } else {
2919                         pos_cpy.y = 2 * pipe_ctx->plane_res.scl_data.viewport.height - pos_cpy.x;
2920                 }
2921                 pos_cpy.x = temp_y;
2922         }
2923         // Mirror horizontally and vertically
2924         else if (param.rotation == ROTATION_ANGLE_180) {
2925                 if (pos_cpy.x >= pipe_ctx->plane_res.scl_data.viewport.width + pipe_ctx->plane_res.scl_data.viewport.x) {
2926                         pos_cpy.x = 2 * pipe_ctx->plane_res.scl_data.viewport.width
2927                                         - pos_cpy.x + 2 * pipe_ctx->plane_res.scl_data.viewport.x;
2928                 } else {
2929                         uint32_t temp_x = pos_cpy.x;
2930                         pos_cpy.x = 2 * pipe_ctx->plane_res.scl_data.viewport.x - pos_cpy.x;
2931                         if (temp_x >= pipe_ctx->plane_res.scl_data.viewport.x + (int)hubp->curs_attr.width
2932                                         || pos_cpy.x <= (int)hubp->curs_attr.width + pipe_ctx->plane_state->src_rect.x) {
2933                                 pos_cpy.x = temp_x + pipe_ctx->plane_res.scl_data.viewport.width;
2934                         }
2935                 }
2936                 pos_cpy.y = pipe_ctx->plane_res.scl_data.viewport.height - pos_cpy.y;
2937         }
2938
2939         hubp->funcs->set_cursor_position(hubp, &pos_cpy, &param);
2940         dpp->funcs->set_cursor_position(dpp, &pos_cpy, &param, hubp->curs_attr.width, hubp->curs_attr.height);
2941 }
2942
2943 void dcn10_set_cursor_attribute(struct pipe_ctx *pipe_ctx)
2944 {
2945         struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;
2946
2947         pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes(
2948                         pipe_ctx->plane_res.hubp, attributes);
2949         pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes(
2950                 pipe_ctx->plane_res.dpp, attributes);
2951 }
2952
2953 void dcn10_set_cursor_sdr_white_level(struct pipe_ctx *pipe_ctx)
2954 {
2955         uint32_t sdr_white_level = pipe_ctx->stream->cursor_attributes.sdr_white_level;
2956         struct fixed31_32 multiplier;
2957         struct dpp_cursor_attributes opt_attr = { 0 };
2958         uint32_t hw_scale = 0x3c00; // 1.0 default multiplier
2959         struct custom_float_format fmt;
2960
2961         if (!pipe_ctx->plane_res.dpp->funcs->set_optional_cursor_attributes)
2962                 return;
2963
2964         fmt.exponenta_bits = 5;
2965         fmt.mantissa_bits = 10;
2966         fmt.sign = true;
2967
2968         if (sdr_white_level > 80) {
2969                 multiplier = dc_fixpt_from_fraction(sdr_white_level, 80);
2970                 convert_to_custom_float_format(multiplier, &fmt, &hw_scale);
2971         }
2972
2973         opt_attr.scale = hw_scale;
2974         opt_attr.bias = 0;
2975
2976         pipe_ctx->plane_res.dpp->funcs->set_optional_cursor_attributes(
2977                         pipe_ctx->plane_res.dpp, &opt_attr);
2978 }
2979
2980 /*
2981  * apply_front_porch_workaround  TODO FPGA still need?
2982  *
2983  * This is a workaround for a bug that has existed since R5xx and has not been
2984  * fixed keep Front porch at minimum 2 for Interlaced mode or 1 for progressive.
2985  */
2986 static void apply_front_porch_workaround(
2987         struct dc_crtc_timing *timing)
2988 {
2989         if (timing->flags.INTERLACE == 1) {
2990                 if (timing->v_front_porch < 2)
2991                         timing->v_front_porch = 2;
2992         } else {
2993                 if (timing->v_front_porch < 1)
2994                         timing->v_front_porch = 1;
2995         }
2996 }
2997
2998 int dcn10_get_vupdate_offset_from_vsync(struct pipe_ctx *pipe_ctx)
2999 {
3000         const struct dc_crtc_timing *dc_crtc_timing = &pipe_ctx->stream->timing;
3001         struct dc_crtc_timing patched_crtc_timing;
3002         int vesa_sync_start;
3003         int asic_blank_end;
3004         int interlace_factor;
3005         int vertical_line_start;
3006
3007         patched_crtc_timing = *dc_crtc_timing;
3008         apply_front_porch_workaround(&patched_crtc_timing);
3009
3010         interlace_factor = patched_crtc_timing.flags.INTERLACE ? 2 : 1;
3011
3012         vesa_sync_start = patched_crtc_timing.v_addressable +
3013                         patched_crtc_timing.v_border_bottom +
3014                         patched_crtc_timing.v_front_porch;
3015
3016         asic_blank_end = (patched_crtc_timing.v_total -
3017                         vesa_sync_start -
3018                         patched_crtc_timing.v_border_top)
3019                         * interlace_factor;
3020
3021         vertical_line_start = asic_blank_end -
3022                         pipe_ctx->pipe_dlg_param.vstartup_start + 1;
3023
3024         return vertical_line_start;
3025 }
3026
3027 static void dcn10_calc_vupdate_position(
3028                 struct dc *dc,
3029                 struct pipe_ctx *pipe_ctx,
3030                 uint32_t *start_line,
3031                 uint32_t *end_line)
3032 {
3033         const struct dc_crtc_timing *dc_crtc_timing = &pipe_ctx->stream->timing;
3034         int vline_int_offset_from_vupdate =
3035                         pipe_ctx->stream->periodic_interrupt0.lines_offset;
3036         int vupdate_offset_from_vsync = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);
3037         int start_position;
3038
3039         if (vline_int_offset_from_vupdate > 0)
3040                 vline_int_offset_from_vupdate--;
3041         else if (vline_int_offset_from_vupdate < 0)
3042                 vline_int_offset_from_vupdate++;
3043
3044         start_position = vline_int_offset_from_vupdate + vupdate_offset_from_vsync;
3045
3046         if (start_position >= 0)
3047                 *start_line = start_position;
3048         else
3049                 *start_line = dc_crtc_timing->v_total + start_position - 1;
3050
3051         *end_line = *start_line + 2;
3052
3053         if (*end_line >= dc_crtc_timing->v_total)
3054                 *end_line = 2;
3055 }
3056
3057 static void dcn10_cal_vline_position(
3058                 struct dc *dc,
3059                 struct pipe_ctx *pipe_ctx,
3060                 enum vline_select vline,
3061                 uint32_t *start_line,
3062                 uint32_t *end_line)
3063 {
3064         enum vertical_interrupt_ref_point ref_point = INVALID_POINT;
3065
3066         if (vline == VLINE0)
3067                 ref_point = pipe_ctx->stream->periodic_interrupt0.ref_point;
3068         else if (vline == VLINE1)
3069                 ref_point = pipe_ctx->stream->periodic_interrupt1.ref_point;
3070
3071         switch (ref_point) {
3072         case START_V_UPDATE:
3073                 dcn10_calc_vupdate_position(
3074                                 dc,
3075                                 pipe_ctx,
3076                                 start_line,
3077                                 end_line);
3078                 break;
3079         case START_V_SYNC:
3080                 // Suppose to do nothing because vsync is 0;
3081                 break;
3082         default:
3083                 ASSERT(0);
3084                 break;
3085         }
3086 }
3087
3088 void dcn10_setup_periodic_interrupt(
3089                 struct dc *dc,
3090                 struct pipe_ctx *pipe_ctx,
3091                 enum vline_select vline)
3092 {
3093         struct timing_generator *tg = pipe_ctx->stream_res.tg;
3094
3095         if (vline == VLINE0) {
3096                 uint32_t start_line = 0;
3097                 uint32_t end_line = 0;
3098
3099                 dcn10_cal_vline_position(dc, pipe_ctx, vline, &start_line, &end_line);
3100
3101                 tg->funcs->setup_vertical_interrupt0(tg, start_line, end_line);
3102
3103         } else if (vline == VLINE1) {
3104                 pipe_ctx->stream_res.tg->funcs->setup_vertical_interrupt1(
3105                                 tg,
3106                                 pipe_ctx->stream->periodic_interrupt1.lines_offset);
3107         }
3108 }
3109
3110 void dcn10_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx)
3111 {
3112         struct timing_generator *tg = pipe_ctx->stream_res.tg;
3113         int start_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);
3114
3115         if (start_line < 0) {
3116                 ASSERT(0);
3117                 start_line = 0;
3118         }
3119
3120         if (tg->funcs->setup_vertical_interrupt2)
3121                 tg->funcs->setup_vertical_interrupt2(tg, start_line);
3122 }
3123
3124 void dcn10_unblank_stream(struct pipe_ctx *pipe_ctx,
3125                 struct dc_link_settings *link_settings)
3126 {
3127         struct encoder_unblank_param params = { { 0 } };
3128         struct dc_stream_state *stream = pipe_ctx->stream;
3129         struct dc_link *link = stream->link;
3130
3131         /* only 3 items below are used by unblank */
3132         params.timing = pipe_ctx->stream->timing;
3133
3134         params.link_settings.link_rate = link_settings->link_rate;
3135
3136         if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
3137                 if (params.timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
3138                         params.timing.pix_clk_100hz /= 2;
3139                 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, &params);
3140         }
3141
3142         if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
3143                 link->dc->hwss.edp_backlight_control(link, true);
3144         }
3145 }
3146
3147 void dcn10_send_immediate_sdp_message(struct pipe_ctx *pipe_ctx,
3148                                 const uint8_t *custom_sdp_message,
3149                                 unsigned int sdp_message_size)
3150 {
3151         if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
3152                 pipe_ctx->stream_res.stream_enc->funcs->send_immediate_sdp_message(
3153                                 pipe_ctx->stream_res.stream_enc,
3154                                 custom_sdp_message,
3155                                 sdp_message_size);
3156         }
3157 }
3158 enum dc_status dcn10_set_clock(struct dc *dc,
3159                         enum dc_clock_type clock_type,
3160                         uint32_t clk_khz,
3161                         uint32_t stepping)
3162 {
3163         struct dc_state *context = dc->current_state;
3164         struct dc_clock_config clock_cfg = {0};
3165         struct dc_clocks *current_clocks = &context->bw_ctx.bw.dcn.clk;
3166
3167         if (dc->clk_mgr && dc->clk_mgr->funcs->get_clock)
3168                                 dc->clk_mgr->funcs->get_clock(dc->clk_mgr,
3169                                                 context, clock_type, &clock_cfg);
3170
3171         if (!dc->clk_mgr->funcs->get_clock)
3172                 return DC_FAIL_UNSUPPORTED_1;
3173
3174         if (clk_khz > clock_cfg.max_clock_khz)
3175                 return DC_FAIL_CLK_EXCEED_MAX;
3176
3177         if (clk_khz < clock_cfg.min_clock_khz)
3178                 return DC_FAIL_CLK_BELOW_MIN;
3179
3180         if (clk_khz < clock_cfg.bw_requirequired_clock_khz)
3181                 return DC_FAIL_CLK_BELOW_CFG_REQUIRED;
3182
3183         /*update internal request clock for update clock use*/
3184         if (clock_type == DC_CLOCK_TYPE_DISPCLK)
3185                 current_clocks->dispclk_khz = clk_khz;
3186         else if (clock_type == DC_CLOCK_TYPE_DPPCLK)
3187                 current_clocks->dppclk_khz = clk_khz;
3188         else
3189                 return DC_ERROR_UNEXPECTED;
3190
3191         if (dc->clk_mgr && dc->clk_mgr->funcs->update_clocks)
3192                                 dc->clk_mgr->funcs->update_clocks(dc->clk_mgr,
3193                                 context, true);
3194         return DC_OK;
3195
3196 }
3197
3198 void dcn10_get_clock(struct dc *dc,
3199                         enum dc_clock_type clock_type,
3200                         struct dc_clock_config *clock_cfg)
3201 {
3202         struct dc_state *context = dc->current_state;
3203
3204         if (dc->clk_mgr && dc->clk_mgr->funcs->get_clock)
3205                                 dc->clk_mgr->funcs->get_clock(dc->clk_mgr, context, clock_type, clock_cfg);
3206
3207 }