drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/delay.h>
  27 #include "dm_services.h"
  28 #include "core_types.h"
  29 #include "resource.h"
  30 #include "custom_float.h"
  31 #include "dcn10_hw_sequencer.h"
  32 #include "dce110/dce110_hw_sequencer.h"
  33 #include "dce/dce_hwseq.h"
  34 #include "abm.h"
  35 #include "dmcu.h"
  36 #include "dcn10_optc.h"
  37 #include "dcn10/dcn10_dpp.h"
  38 #include "dcn10/dcn10_mpc.h"
  39 #include "timing_generator.h"
  40 #include "opp.h"
  41 #include "ipp.h"
  42 #include "mpc.h"
  43 #include "reg_helper.h"
  44 #include "dcn10_hubp.h"
  45 #include "dcn10_hubbub.h"
  46 #include "dcn10_cm_common.h"
  47 #include "dc_link_dp.h"
  48 #include "dccg.h"
  49 #include "clk_mgr.h"
  50
  51
  52 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
  53 #include "dsc.h"
  54 #endif
  55
  56 #define DC_LOGGER_INIT(logger)
  57
  58 #define CTX \
  59         hws->ctx
  60 #define REG(reg)\
  61         hws->regs->reg
  62
  63 #undef FN
  64 #define FN(reg_name, field_name) \
  65         hws->shifts->field_name, hws->masks->field_name
  66
  67 /*print is 17 wide, first two characters are spaces*/
  68 #define DTN_INFO_MICRO_SEC(ref_cycle) \
  69         print_microsec(dc_ctx, log_ctx, ref_cycle)
  70
  71 void print_microsec(struct dc_context *dc_ctx,
  72         struct dc_log_buffer_ctx *log_ctx,
  73         uint32_t ref_cycle)
  74 {
  75         const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000;
  76         static const unsigned int frac = 1000;
  77         uint32_t us_x10 = (ref_cycle * frac) / ref_clk_mhz;
  78
  79         DTN_INFO("  %11d.%03d",
  80                         us_x10 / frac,
  81                         us_x10 % frac);
  82 }
  83
  84 static void log_mpc_crc(struct dc *dc,
  85         struct dc_log_buffer_ctx *log_ctx)
  86 {
  87         struct dc_context *dc_ctx = dc->ctx;
  88         struct dce_hwseq *hws = dc->hwseq;
  89
  90         if (REG(MPC_CRC_RESULT_GB))
  91                 DTN_INFO("MPC_CRC_RESULT_GB:%d MPC_CRC_RESULT_C:%d MPC_CRC_RESULT_AR:%d\n",
  92                 REG_READ(MPC_CRC_RESULT_GB), REG_READ(MPC_CRC_RESULT_C), REG_READ(MPC_CRC_RESULT_AR));
  93         if (REG(DPP_TOP0_DPP_CRC_VAL_B_A))
  94                 DTN_INFO("DPP_TOP0_DPP_CRC_VAL_B_A:%d DPP_TOP0_DPP_CRC_VAL_R_G:%d\n",
  95                 REG_READ(DPP_TOP0_DPP_CRC_VAL_B_A), REG_READ(DPP_TOP0_DPP_CRC_VAL_R_G));
  96 }
  97
  98 void dcn10_log_hubbub_state(struct dc *dc, struct dc_log_buffer_ctx *log_ctx)
  99 {
 100         struct dc_context *dc_ctx = dc->ctx;
 101         struct dcn_hubbub_wm wm;
 102         int i;
 103
 104         memset(&wm, 0, sizeof(struct dcn_hubbub_wm));
 105         dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm);
 106
 107         DTN_INFO("HUBBUB WM:      data_urgent  pte_meta_urgent"
 108                         "         sr_enter          sr_exit  dram_clk_change\n");
 109
 110         for (i = 0; i < 4; i++) {
 111                 struct dcn_hubbub_wm_set *s;
 112
 113                 s = &wm.sets[i];
 114                 DTN_INFO("WM_Set[%d]:", s->wm_set);
 115                 DTN_INFO_MICRO_SEC(s->data_urgent);
 116                 DTN_INFO_MICRO_SEC(s->pte_meta_urgent);
 117                 DTN_INFO_MICRO_SEC(s->sr_enter);
 118                 DTN_INFO_MICRO_SEC(s->sr_exit);
 119                 DTN_INFO_MICRO_SEC(s->dram_clk_chanage);
 120                 DTN_INFO("\n");
 121         }
 122
 123         DTN_INFO("\n");
 124 }
 125
 126 static void dcn10_log_hubp_states(struct dc *dc, void *log_ctx)
 127 {
 128         struct dc_context *dc_ctx = dc->ctx;
 129         struct resource_pool *pool = dc->res_pool;
 130         int i;
 131
 132         DTN_INFO("HUBP:  format  addr_hi  width  height"
 133                         "  rot  mir  sw_mode  dcc_en  blank_en  ttu_dis  underflow"
 134                         "   min_ttu_vblank       qos_low_wm      qos_high_wm\n");
 135         for (i = 0; i < pool->pipe_count; i++) {
 136                 struct hubp *hubp = pool->hubps[i];
 137                 struct dcn_hubp_state *s = &(TO_DCN10_HUBP(hubp)->state);
 138
 139                 hubp->funcs->hubp_read_state(hubp);
 140
 141                 if (!s->blank_en) {
 142                         DTN_INFO("[%2d]:  %5xh  %6xh  %5d  %6d  %2xh  %2xh  %6xh"
 143                                         "  %6d  %8d  %7d  %8xh",
 144                                         hubp->inst,
 145                                         s->pixel_format,
 146                                         s->inuse_addr_hi,
 147                                         s->viewport_width,
 148                                         s->viewport_height,
 149                                         s->rotation_angle,
 150                                         s->h_mirror_en,
 151                                         s->sw_mode,
 152                                         s->dcc_en,
 153                                         s->blank_en,
 154                                         s->ttu_disable,
 155                                         s->underflow_status);
 156                         DTN_INFO_MICRO_SEC(s->min_ttu_vblank);
 157                         DTN_INFO_MICRO_SEC(s->qos_level_low_wm);
 158                         DTN_INFO_MICRO_SEC(s->qos_level_high_wm);
 159                         DTN_INFO("\n");
 160                 }
 161         }
 162
 163         DTN_INFO("\n=========RQ========\n");
 164         DTN_INFO("HUBP:  drq_exp_m  prq_exp_m  mrq_exp_m  crq_exp_m  plane1_ba  L:chunk_s  min_chu_s  meta_ch_s"
 165                 "  min_m_c_s  dpte_gr_s  mpte_gr_s  swath_hei  pte_row_h  C:chunk_s  min_chu_s  meta_ch_s"
 166                 "  min_m_c_s  dpte_gr_s  mpte_gr_s  swath_hei  pte_row_h\n");
 167         for (i = 0; i < pool->pipe_count; i++) {
 168                 struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);
 169                 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;
 170
 171                 if (!s->blank_en)
 172                         DTN_INFO("[%2d]:  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh\n",
 173                                 pool->hubps[i]->inst, rq_regs->drq_expansion_mode, rq_regs->prq_expansion_mode, rq_regs->mrq_expansion_mode,
 174                                 rq_regs->crq_expansion_mode, rq_regs->plane1_base_address, rq_regs->rq_regs_l.chunk_size,
 175                                 rq_regs->rq_regs_l.min_chunk_size, rq_regs->rq_regs_l.meta_chunk_size,
 176                                 rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs->rq_regs_l.dpte_group_size,
 177                                 rq_regs->rq_regs_l.mpte_group_size, rq_regs->rq_regs_l.swath_height,
 178                                 rq_regs->rq_regs_l.pte_row_height_linear, rq_regs->rq_regs_c.chunk_size, rq_regs->rq_regs_c.min_chunk_size,
 179                                 rq_regs->rq_regs_c.meta_chunk_size, rq_regs->rq_regs_c.min_meta_chunk_size,
 180                                 rq_regs->rq_regs_c.dpte_group_size, rq_regs->rq_regs_c.mpte_group_size,
 181                                 rq_regs->rq_regs_c.swath_height, rq_regs->rq_regs_c.pte_row_height_linear);
 182         }
 183
 184         DTN_INFO("========DLG========\n");
 185         DTN_INFO("HUBP:  rc_hbe     dlg_vbe    min_d_y_n  rc_per_ht  rc_x_a_s "
 186                         "  dst_y_a_s  dst_y_pf   dst_y_vvb  dst_y_rvb  dst_y_vfl  dst_y_rfl  rf_pix_fq"
 187                         "  vratio_pf  vrat_pf_c  rc_pg_vbl  rc_pg_vbc  rc_mc_vbl  rc_mc_vbc  rc_pg_fll"
 188                         "  rc_pg_flc  rc_mc_fll  rc_mc_flc  pr_nom_l   pr_nom_c   rc_pg_nl   rc_pg_nc "
 189                         "  mr_nom_l   mr_nom_c   rc_mc_nl   rc_mc_nc   rc_ld_pl   rc_ld_pc   rc_ld_l  "
 190                         "  rc_ld_c    cha_cur0   ofst_cur1  cha_cur1   vr_af_vc0  ddrq_limt  x_rt_dlay"
 191                         "  x_rp_dlay  x_rr_sfl\n");
 192         for (i = 0; i < pool->pipe_count; i++) {
 193                 struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);
 194                 struct _vcs_dpi_display_dlg_regs_st *dlg_regs = &s->dlg_attr;
 195
 196                 if (!s->blank_en)
 197                         DTN_INFO("[%2d]:  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh"
 198                                 "%  8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh"
 199                                 "  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh\n",
 200                                 pool->hubps[i]->inst, dlg_regs->refcyc_h_blank_end, dlg_regs->dlg_vblank_end, dlg_regs->min_dst_y_next_start,
 201                                 dlg_regs->refcyc_per_htotal, dlg_regs->refcyc_x_after_scaler, dlg_regs->dst_y_after_scaler,
 202                                 dlg_regs->dst_y_prefetch, dlg_regs->dst_y_per_vm_vblank, dlg_regs->dst_y_per_row_vblank,
 203                                 dlg_regs->dst_y_per_vm_flip, dlg_regs->dst_y_per_row_flip, dlg_regs->ref_freq_to_pix_freq,
 204                                 dlg_regs->vratio_prefetch, dlg_regs->vratio_prefetch_c, dlg_regs->refcyc_per_pte_group_vblank_l,
 205                                 dlg_regs->refcyc_per_pte_group_vblank_c, dlg_regs->refcyc_per_meta_chunk_vblank_l,
 206                                 dlg_regs->refcyc_per_meta_chunk_vblank_c, dlg_regs->refcyc_per_pte_group_flip_l,
 207                                 dlg_regs->refcyc_per_pte_group_flip_c, dlg_regs->refcyc_per_meta_chunk_flip_l,
 208                                 dlg_regs->refcyc_per_meta_chunk_flip_c, dlg_regs->dst_y_per_pte_row_nom_l,
 209                                 dlg_regs->dst_y_per_pte_row_nom_c, dlg_regs->refcyc_per_pte_group_nom_l,
 210                                 dlg_regs->refcyc_per_pte_group_nom_c, dlg_regs->dst_y_per_meta_row_nom_l,
 211                                 dlg_regs->dst_y_per_meta_row_nom_c, dlg_regs->refcyc_per_meta_chunk_nom_l,
 212                                 dlg_regs->refcyc_per_meta_chunk_nom_c, dlg_regs->refcyc_per_line_delivery_pre_l,
 213                                 dlg_regs->refcyc_per_line_delivery_pre_c, dlg_regs->refcyc_per_line_delivery_l,
 214                                 dlg_regs->refcyc_per_line_delivery_c, dlg_regs->chunk_hdl_adjust_cur0, dlg_regs->dst_y_offset_cur1,
 215                                 dlg_regs->chunk_hdl_adjust_cur1, dlg_regs->vready_after_vcount0, dlg_regs->dst_y_delta_drq_limit,
 216                                 dlg_regs->xfc_reg_transfer_delay, dlg_regs->xfc_reg_precharge_delay,
 217                                 dlg_regs->xfc_reg_remote_surface_flip_latency);
 218         }
 219
 220         DTN_INFO("========TTU========\n");
 221         DTN_INFO("HUBP:  qos_ll_wm  qos_lh_wm  mn_ttu_vb  qos_l_flp  rc_rd_p_l  rc_rd_l    rc_rd_p_c"
 222                         "  rc_rd_c    rc_rd_c0   rc_rd_pc0  rc_rd_c1   rc_rd_pc1  qos_lf_l   qos_rds_l"
 223                         "  qos_lf_c   qos_rds_c  qos_lf_c0  qos_rds_c0 qos_lf_c1  qos_rds_c1\n");
 224         for (i = 0; i < pool->pipe_count; i++) {
 225                 struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);
 226                 struct _vcs_dpi_display_ttu_regs_st *ttu_regs = &s->ttu_attr;
 227
 228                 if (!s->blank_en)
 229                         DTN_INFO("[%2d]:  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh\n",
 230                                 pool->hubps[i]->inst, ttu_regs->qos_level_low_wm, ttu_regs->qos_level_high_wm, ttu_regs->min_ttu_vblank,
 231                                 ttu_regs->qos_level_flip, ttu_regs->refcyc_per_req_delivery_pre_l, ttu_regs->refcyc_per_req_delivery_l,
 232                                 ttu_regs->refcyc_per_req_delivery_pre_c, ttu_regs->refcyc_per_req_delivery_c, ttu_regs->refcyc_per_req_delivery_cur0,
 233                                 ttu_regs->refcyc_per_req_delivery_pre_cur0, ttu_regs->refcyc_per_req_delivery_cur1,
 234                                 ttu_regs->refcyc_per_req_delivery_pre_cur1, ttu_regs->qos_level_fixed_l, ttu_regs->qos_ramp_disable_l,
 235                                 ttu_regs->qos_level_fixed_c, ttu_regs->qos_ramp_disable_c, ttu_regs->qos_level_fixed_cur0,
 236                                 ttu_regs->qos_ramp_disable_cur0, ttu_regs->qos_level_fixed_cur1, ttu_regs->qos_ramp_disable_cur1);
 237         }
 238         DTN_INFO("\n");
 239 }
 240
 241 void dcn10_log_hw_state(struct dc *dc,
 242         struct dc_log_buffer_ctx *log_ctx)
 243 {
 244         struct dc_context *dc_ctx = dc->ctx;
 245         struct resource_pool *pool = dc->res_pool;
 246         int i;
 247
 248         DTN_INFO_BEGIN();
 249
 250         dcn10_log_hubbub_state(dc, log_ctx);
 251
 252         dcn10_log_hubp_states(dc, log_ctx);
 253
 254         DTN_INFO("DPP:    IGAM format  IGAM mode    DGAM mode    RGAM mode"
 255                         "  GAMUT mode  C11 C12   C13 C14   C21 C22   C23 C24   "
 256                         "C31 C32   C33 C34\n");
 257         for (i = 0; i < pool->pipe_count; i++) {
 258                 struct dpp *dpp = pool->dpps[i];
 259                 struct dcn_dpp_state s = {0};
 260
 261                 dpp->funcs->dpp_read_state(dpp, &s);
 262
 263                 if (!s.is_enabled)
 264                         continue;
 265
 266                 DTN_INFO("[%2d]:  %11xh  %-11s  %-11s  %-11s"
 267                                 "%8x    %08xh %08xh %08xh %08xh %08xh %08xh",
 268                                 dpp->inst,
 269                                 s.igam_input_format,
 270                                 (s.igam_lut_mode == 0) ? "BypassFixed" :
 271                                         ((s.igam_lut_mode == 1) ? "BypassFloat" :
 272                                         ((s.igam_lut_mode == 2) ? "RAM" :
 273                                         ((s.igam_lut_mode == 3) ? "RAM" :
 274                                                                  "Unknown"))),
 275                                 (s.dgam_lut_mode == 0) ? "Bypass" :
 276                                         ((s.dgam_lut_mode == 1) ? "sRGB" :
 277                                         ((s.dgam_lut_mode == 2) ? "Ycc" :
 278                                         ((s.dgam_lut_mode == 3) ? "RAM" :
 279                                         ((s.dgam_lut_mode == 4) ? "RAM" :
 280                                                                  "Unknown")))),
 281                                 (s.rgam_lut_mode == 0) ? "Bypass" :
 282                                         ((s.rgam_lut_mode == 1) ? "sRGB" :
 283                                         ((s.rgam_lut_mode == 2) ? "Ycc" :
 284                                         ((s.rgam_lut_mode == 3) ? "RAM" :
 285                                         ((s.rgam_lut_mode == 4) ? "RAM" :
 286                                                                  "Unknown")))),
 287                                 s.gamut_remap_mode,
 288                                 s.gamut_remap_c11_c12,
 289                                 s.gamut_remap_c13_c14,
 290                                 s.gamut_remap_c21_c22,
 291                                 s.gamut_remap_c23_c24,
 292                                 s.gamut_remap_c31_c32,
 293                                 s.gamut_remap_c33_c34);
 294                 DTN_INFO("\n");
 295         }
 296         DTN_INFO("\n");
 297
 298         DTN_INFO("MPCC:  OPP  DPP  MPCCBOT  MODE  ALPHA_MODE  PREMULT  OVERLAP_ONLY  IDLE\n");
 299         for (i = 0; i < pool->pipe_count; i++) {
 300                 struct mpcc_state s = {0};
 301
 302                 pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s);
 303                 if (s.opp_id != 0xf)
 304                         DTN_INFO("[%2d]:  %2xh  %2xh  %6xh  %4d  %10d  %7d  %12d  %4d\n",
 305                                 i, s.opp_id, s.dpp_id, s.bot_mpcc_id,
 306                                 s.mode, s.alpha_mode, s.pre_multiplied_alpha, s.overlap_only,
 307                                 s.idle);
 308         }
 309         DTN_INFO("\n");
 310
 311         DTN_INFO("OTG:  v_bs  v_be  v_ss  v_se  vpol  vmax  vmin  vmax_sel  vmin_sel"
 312                         "  h_bs  h_be  h_ss  h_se  hpol  htot  vtot  underflow\n");
 313
 314         for (i = 0; i < pool->timing_generator_count; i++) {
 315                 struct timing_generator *tg = pool->timing_generators[i];
 316                 struct dcn_otg_state s = {0};
 317
 318                 optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s);
 319
 320                 //only print if OTG master is enabled
 321                 if ((s.otg_enabled & 1) == 0)
 322                         continue;
 323
 324                 DTN_INFO("[%d]: %5d %5d %5d %5d %5d %5d %5d %9d %9d %5d %5d %5d"
 325                                 " %5d %5d %5d %5d  %9d\n",
 326                                 tg->inst,
 327                                 s.v_blank_start,
 328                                 s.v_blank_end,
 329                                 s.v_sync_a_start,
 330                                 s.v_sync_a_end,
 331                                 s.v_sync_a_pol,
 332                                 s.v_total_max,
 333                                 s.v_total_min,
 334                                 s.v_total_max_sel,
 335                                 s.v_total_min_sel,
 336                                 s.h_blank_start,
 337                                 s.h_blank_end,
 338                                 s.h_sync_a_start,
 339                                 s.h_sync_a_end,
 340                                 s.h_sync_a_pol,
 341                                 s.h_total,
 342                                 s.v_total,
 343                                 s.underflow_occurred_status);
 344
 345                 // Clear underflow for debug purposes
 346                 // We want to keep underflow sticky bit on for the longevity tests outside of test environment.
 347                 // This function is called only from Windows or Diags test environment, hence it's safe to clear
 348                 // it from here without affecting the original intent.
 349                 tg->funcs->clear_optc_underflow(tg);
 350         }
 351         DTN_INFO("\n");
 352
 353 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
 354         DTN_INFO("DSC: CLOCK_EN  SLICE_WIDTH  Bytes_pp\n");
 355         for (i = 0; i < pool->res_cap->num_dsc; i++) {
 356                 struct display_stream_compressor *dsc = pool->dscs[i];
 357                 struct dcn_dsc_state s = {0};
 358
 359                 dsc->funcs->dsc_read_state(dsc, &s);
 360                 DTN_INFO("[%d]: %-9d %-12d %-10d\n",
 361                 dsc->inst,
 362                         s.dsc_clock_en,
 363                         s.dsc_slice_width,
 364                         s.dsc_bytes_per_pixel);
 365                 DTN_INFO("\n");
 366         }
 367         DTN_INFO("\n");
 368
 369         DTN_INFO("S_ENC: DSC_MODE  SEC_GSP7_LINE_NUM"
 370                         "  VBID6_LINE_REFERENCE  VBID6_LINE_NUM  SEC_GSP7_ENABLE  SEC_STREAM_ENABLE\n");
 371         for (i = 0; i < pool->stream_enc_count; i++) {
 372                 struct stream_encoder *enc = pool->stream_enc[i];
 373                 struct enc_state s = {0};
 374
 375                 if (enc->funcs->enc_read_state) {
 376                         enc->funcs->enc_read_state(enc, &s);
 377                         DTN_INFO("[%-3d]: %-9d %-18d %-21d %-15d %-16d %-17d\n",
 378                                 enc->id,
 379                                 s.dsc_mode,
 380                                 s.sec_gsp_pps_line_num,
 381                                 s.vbid6_line_reference,
 382                                 s.vbid6_line_num,
 383                                 s.sec_gsp_pps_enable,
 384                                 s.sec_stream_enable);
 385                         DTN_INFO("\n");
 386                 }
 387         }
 388         DTN_INFO("\n");
 389
 390         DTN_INFO("L_ENC: DPHY_FEC_EN  DPHY_FEC_READY_SHADOW  DPHY_FEC_ACTIVE_STATUS\n");
 391         for (i = 0; i < dc->link_count; i++) {
 392                 struct link_encoder *lenc = dc->links[i]->link_enc;
 393
 394                 struct link_enc_state s = {0};
 395
 396                 if (lenc->funcs->read_state) {
 397                         lenc->funcs->read_state(lenc, &s);
 398                         DTN_INFO("[%-3d]: %-12d %-22d %-22d\n",
 399                                 i,
 400                                 s.dphy_fec_en,
 401                                 s.dphy_fec_ready_shadow,
 402                                 s.dphy_fec_active_status);
 403                         DTN_INFO("\n");
 404                 }
 405         }
 406         DTN_INFO("\n");
 407 #endif
 408
 409         DTN_INFO("\nCALCULATED Clocks: dcfclk_khz:%d  dcfclk_deep_sleep_khz:%d  dispclk_khz:%d\n"
 410                 "dppclk_khz:%d  max_supported_dppclk_khz:%d  fclk_khz:%d  socclk_khz:%d\n\n",
 411                         dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_khz,
 412                         dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz,
 413                         dc->current_state->bw_ctx.bw.dcn.clk.dispclk_khz,
 414                         dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz,
 415                         dc->current_state->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz,
 416                         dc->current_state->bw_ctx.bw.dcn.clk.fclk_khz,
 417                         dc->current_state->bw_ctx.bw.dcn.clk.socclk_khz);
 418
 419         log_mpc_crc(dc, log_ctx);
 420
 421         DTN_INFO_END();
 422 }
 423
 424 bool dcn10_did_underflow_occur(struct dc *dc, struct pipe_ctx *pipe_ctx)
 425 {
 426         struct hubp *hubp = pipe_ctx->plane_res.hubp;
 427         struct timing_generator *tg = pipe_ctx->stream_res.tg;
 428
 429         if (tg->funcs->is_optc_underflow_occurred(tg)) {
 430                 tg->funcs->clear_optc_underflow(tg);
 431                 return true;
 432         }
 433
 434         if (hubp->funcs->hubp_get_underflow_status(hubp)) {
 435                 hubp->funcs->hubp_clear_underflow(hubp);
 436                 return true;
 437         }
 438         return false;
 439 }
 440
 441 static void dcn10_enable_power_gating_plane(
 442         struct dce_hwseq *hws,
 443         bool enable)
 444 {
 445         bool force_on = 1; /* disable power gating */
 446
 447         if (enable)
 448                 force_on = 0;
 449
 450         /* DCHUBP0/1/2/3 */
 451         REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on);
 452         REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on);
 453         REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on);
 454         REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on);
 455
 456         /* DPP0/1/2/3 */
 457         REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on);
 458         REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on);
 459         REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on);
 460         REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);
 461 }
 462
 463 static void dcn10_disable_vga(
 464         struct dce_hwseq *hws)
 465 {
 466         unsigned int in_vga1_mode = 0;
 467         unsigned int in_vga2_mode = 0;
 468         unsigned int in_vga3_mode = 0;
 469         unsigned int in_vga4_mode = 0;
 470
 471         REG_GET(D1VGA_CONTROL, D1VGA_MODE_ENABLE, &in_vga1_mode);
 472         REG_GET(D2VGA_CONTROL, D2VGA_MODE_ENABLE, &in_vga2_mode);
 473         REG_GET(D3VGA_CONTROL, D3VGA_MODE_ENABLE, &in_vga3_mode);
 474         REG_GET(D4VGA_CONTROL, D4VGA_MODE_ENABLE, &in_vga4_mode);
 475
 476         if (in_vga1_mode == 0 && in_vga2_mode == 0 &&
 477                         in_vga3_mode == 0 && in_vga4_mode == 0)
 478                 return;
 479
 480         REG_WRITE(D1VGA_CONTROL, 0);
 481         REG_WRITE(D2VGA_CONTROL, 0);
 482         REG_WRITE(D3VGA_CONTROL, 0);
 483         REG_WRITE(D4VGA_CONTROL, 0);
 484
 485         /* HW Engineer's Notes:
 486          *  During switch from vga->extended, if we set the VGA_TEST_ENABLE and
 487          *  then hit the VGA_TEST_RENDER_START, then the DCHUBP timing gets updated correctly.
 488          *
 489          *  Then vBIOS will have it poll for the VGA_TEST_RENDER_DONE and unset
 490          *  VGA_TEST_ENABLE, to leave it in the same state as before.
 491          */
 492         REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_ENABLE, 1);
 493         REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_RENDER_START, 1);
 494 }
 495
 496 static void dcn10_dpp_pg_control(
 497                 struct dce_hwseq *hws,
 498                 unsigned int dpp_inst,
 499                 bool power_on)
 500 {
 501         uint32_t power_gate = power_on ? 0 : 1;
 502         uint32_t pwr_status = power_on ? 0 : 2;
 503
 504         if (hws->ctx->dc->debug.disable_dpp_power_gate)
 505                 return;
 506         if (REG(DOMAIN1_PG_CONFIG) == 0)
 507                 return;
 508
 509         switch (dpp_inst) {
 510         case 0: /* DPP0 */
 511                 REG_UPDATE(DOMAIN1_PG_CONFIG,
 512                                 DOMAIN1_POWER_GATE, power_gate);
 513
 514                 REG_WAIT(DOMAIN1_PG_STATUS,
 515                                 DOMAIN1_PGFSM_PWR_STATUS, pwr_status,
 516                                 1, 1000);
 517                 break;
 518         case 1: /* DPP1 */
 519                 REG_UPDATE(DOMAIN3_PG_CONFIG,
 520                                 DOMAIN3_POWER_GATE, power_gate);
 521
 522                 REG_WAIT(DOMAIN3_PG_STATUS,
 523                                 DOMAIN3_PGFSM_PWR_STATUS, pwr_status,
 524                                 1, 1000);
 525                 break;
 526         case 2: /* DPP2 */
 527                 REG_UPDATE(DOMAIN5_PG_CONFIG,
 528                                 DOMAIN5_POWER_GATE, power_gate);
 529
 530                 REG_WAIT(DOMAIN5_PG_STATUS,
 531                                 DOMAIN5_PGFSM_PWR_STATUS, pwr_status,
 532                                 1, 1000);
 533                 break;
 534         case 3: /* DPP3 */
 535                 REG_UPDATE(DOMAIN7_PG_CONFIG,
 536                                 DOMAIN7_POWER_GATE, power_gate);
 537
 538                 REG_WAIT(DOMAIN7_PG_STATUS,
 539                                 DOMAIN7_PGFSM_PWR_STATUS, pwr_status,
 540                                 1, 1000);
 541                 break;
 542         default:
 543                 BREAK_TO_DEBUGGER();
 544                 break;
 545         }
 546 }
 547
 548 static void dcn10_hubp_pg_control(
 549                 struct dce_hwseq *hws,
 550                 unsigned int hubp_inst,
 551                 bool power_on)
 552 {
 553         uint32_t power_gate = power_on ? 0 : 1;
 554         uint32_t pwr_status = power_on ? 0 : 2;
 555
 556         if (hws->ctx->dc->debug.disable_hubp_power_gate)
 557                 return;
 558         if (REG(DOMAIN0_PG_CONFIG) == 0)
 559                 return;
 560
 561         switch (hubp_inst) {
 562         case 0: /* DCHUBP0 */
 563                 REG_UPDATE(DOMAIN0_PG_CONFIG,
 564                                 DOMAIN0_POWER_GATE, power_gate);
 565
 566                 REG_WAIT(DOMAIN0_PG_STATUS,
 567                                 DOMAIN0_PGFSM_PWR_STATUS, pwr_status,
 568                                 1, 1000);
 569                 break;
 570         case 1: /* DCHUBP1 */
 571                 REG_UPDATE(DOMAIN2_PG_CONFIG,
 572                                 DOMAIN2_POWER_GATE, power_gate);
 573
 574                 REG_WAIT(DOMAIN2_PG_STATUS,
 575                                 DOMAIN2_PGFSM_PWR_STATUS, pwr_status,
 576                                 1, 1000);
 577                 break;
 578         case 2: /* DCHUBP2 */
 579                 REG_UPDATE(DOMAIN4_PG_CONFIG,
 580                                 DOMAIN4_POWER_GATE, power_gate);
 581
 582                 REG_WAIT(DOMAIN4_PG_STATUS,
 583                                 DOMAIN4_PGFSM_PWR_STATUS, pwr_status,
 584                                 1, 1000);
 585                 break;
 586         case 3: /* DCHUBP3 */
 587                 REG_UPDATE(DOMAIN6_PG_CONFIG,
 588                                 DOMAIN6_POWER_GATE, power_gate);
 589
 590                 REG_WAIT(DOMAIN6_PG_STATUS,
 591                                 DOMAIN6_PGFSM_PWR_STATUS, pwr_status,
 592                                 1, 1000);
 593                 break;
 594         default:
 595                 BREAK_TO_DEBUGGER();
 596                 break;
 597         }
 598 }
 599
 600 static void power_on_plane(
 601         struct dce_hwseq *hws,
 602         int plane_id)
 603 {
 604         DC_LOGGER_INIT(hws->ctx->logger);
 605         if (REG(DC_IP_REQUEST_CNTL)) {
 606                 REG_SET(DC_IP_REQUEST_CNTL, 0,
 607                                 IP_REQUEST_EN, 1);
 608                 hws->ctx->dc->hwss.dpp_pg_control(hws, plane_id, true);
 609                 hws->ctx->dc->hwss.hubp_pg_control(hws, plane_id, true);
 610                 REG_SET(DC_IP_REQUEST_CNTL, 0,
 611                                 IP_REQUEST_EN, 0);
 612                 DC_LOG_DEBUG(
 613                                 "Un-gated front end for pipe %d\n", plane_id);
 614         }
 615 }
 616
 617 static void undo_DEGVIDCN10_253_wa(struct dc *dc)
 618 {
 619         struct dce_hwseq *hws = dc->hwseq;
 620         struct hubp *hubp = dc->res_pool->hubps[0];
 621
 622         if (!hws->wa_state.DEGVIDCN10_253_applied)
 623                 return;
 624
 625         hubp->funcs->set_blank(hubp, true);
 626
 627         REG_SET(DC_IP_REQUEST_CNTL, 0,
 628                         IP_REQUEST_EN, 1);
 629
 630         dc->hwss.hubp_pg_control(hws, 0, false);
 631         REG_SET(DC_IP_REQUEST_CNTL, 0,
 632                         IP_REQUEST_EN, 0);
 633
 634         hws->wa_state.DEGVIDCN10_253_applied = false;
 635 }
 636
 637 static void apply_DEGVIDCN10_253_wa(struct dc *dc)
 638 {
 639         struct dce_hwseq *hws = dc->hwseq;
 640         struct hubp *hubp = dc->res_pool->hubps[0];
 641         int i;
 642
 643         if (dc->debug.disable_stutter)
 644                 return;
 645
 646         if (!hws->wa.DEGVIDCN10_253)
 647                 return;
 648
 649         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 650                 if (!dc->res_pool->hubps[i]->power_gated)
 651                         return;
 652         }
 653
 654         /* all pipe power gated, apply work around to enable stutter. */
 655
 656         REG_SET(DC_IP_REQUEST_CNTL, 0,
 657                         IP_REQUEST_EN, 1);
 658
 659         dc->hwss.hubp_pg_control(hws, 0, true);
 660         REG_SET(DC_IP_REQUEST_CNTL, 0,
 661                         IP_REQUEST_EN, 0);
 662
 663         hubp->funcs->set_hubp_blank_en(hubp, false);
 664         hws->wa_state.DEGVIDCN10_253_applied = true;
 665 }
 666
 667 static void dcn10_bios_golden_init(struct dc *dc)
 668 {
 669         struct dc_bios *bp = dc->ctx->dc_bios;
 670         int i;
 671         bool allow_self_fresh_force_enable = true;
 672
 673 #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
 674         if (dc->hwss.s0i3_golden_init_wa && dc->hwss.s0i3_golden_init_wa(dc))
 675                 return;
 676 #endif
 677         if (dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled)
 678                 allow_self_fresh_force_enable =
 679                                 dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled(dc->res_pool->hubbub);
 680
 681
 682         /* WA for making DF sleep when idle after resume from S0i3.
 683          * DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE is set to 1 by
 684          * command table, if DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE = 0
 685          * before calling command table and it changed to 1 after,
 686          * it should be set back to 0.
 687          */
 688
 689         /* initialize dcn global */
 690         bp->funcs->enable_disp_power_gating(bp,
 691                         CONTROLLER_ID_D0, ASIC_PIPE_INIT);
 692
 693         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 694                 /* initialize dcn per pipe */
 695                 bp->funcs->enable_disp_power_gating(bp,
 696                                 CONTROLLER_ID_D0 + i, ASIC_PIPE_DISABLE);
 697         }
 698
 699         if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)
 700                 if (allow_self_fresh_force_enable == false &&
 701                                 dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled(dc->res_pool->hubbub))
 702                         dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, true);
 703
 704 }
 705
 706 static void false_optc_underflow_wa(
 707                 struct dc *dc,
 708                 const struct dc_stream_state *stream,
 709                 struct timing_generator *tg)
 710 {
 711         int i;
 712         bool underflow;
 713
 714         if (!dc->hwseq->wa.false_optc_underflow)
 715                 return;
 716
 717         underflow = tg->funcs->is_optc_underflow_occurred(tg);
 718
 719         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 720                 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
 721
 722                 if (old_pipe_ctx->stream != stream)
 723                         continue;
 724
 725                 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, old_pipe_ctx);
 726         }
 727
 728         if (tg->funcs->set_blank_data_double_buffer)
 729                 tg->funcs->set_blank_data_double_buffer(tg, true);
 730
 731         if (tg->funcs->is_optc_underflow_occurred(tg) && !underflow)
 732                 tg->funcs->clear_optc_underflow(tg);
 733 }
 734
 735 static enum dc_status dcn10_enable_stream_timing(
 736                 struct pipe_ctx *pipe_ctx,
 737                 struct dc_state *context,
 738                 struct dc *dc)
 739 {
 740         struct dc_stream_state *stream = pipe_ctx->stream;
 741         enum dc_color_space color_space;
 742         struct tg_color black_color = {0};
 743
 744         /* by upper caller loop, pipe0 is parent pipe and be called first.
 745          * back end is set up by for pipe0. Other children pipe share back end
 746          * with pipe 0. No program is needed.
 747          */
 748         if (pipe_ctx->top_pipe != NULL)
 749                 return DC_OK;
 750
 751         /* TODO check if timing_changed, disable stream if timing changed */
 752
 753         /* HW program guide assume display already disable
 754          * by unplug sequence. OTG assume stop.
 755          */
 756         pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true);
 757
 758         if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
 759                         pipe_ctx->clock_source,
 760                         &pipe_ctx->stream_res.pix_clk_params,
 761                         &pipe_ctx->pll_settings)) {
 762                 BREAK_TO_DEBUGGER();
 763                 return DC_ERROR_UNEXPECTED;
 764         }
 765
 766         pipe_ctx->stream_res.tg->funcs->program_timing(
 767                         pipe_ctx->stream_res.tg,
 768                         &stream->timing,
 769                         pipe_ctx->pipe_dlg_param.vready_offset,
 770                         pipe_ctx->pipe_dlg_param.vstartup_start,
 771                         pipe_ctx->pipe_dlg_param.vupdate_offset,
 772                         pipe_ctx->pipe_dlg_param.vupdate_width,
 773                         pipe_ctx->stream->signal,
 774                         true);
 775
 776 #if 0 /* move to after enable_crtc */
 777         /* TODO: OPP FMT, ABM. etc. should be done here. */
 778         /* or FPGA now. instance 0 only. TODO: move to opp.c */
 779
 780         inst_offset = reg_offsets[pipe_ctx->stream_res.tg->inst].fmt;
 781
 782         pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
 783                                 pipe_ctx->stream_res.opp,
 784                                 &stream->bit_depth_params,
 785                                 &stream->clamping);
 786 #endif
 787         /* program otg blank color */
 788         color_space = stream->output_color_space;
 789         color_space_to_black_color(dc, color_space, &black_color);
 790
 791         if (pipe_ctx->stream_res.tg->funcs->set_blank_color)
 792                 pipe_ctx->stream_res.tg->funcs->set_blank_color(
 793                                 pipe_ctx->stream_res.tg,
 794                                 &black_color);
 795
 796         if (pipe_ctx->stream_res.tg->funcs->is_blanked &&
 797                         !pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg)) {
 798                 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);
 799                 hwss_wait_for_blank_complete(pipe_ctx->stream_res.tg);
 800                 false_optc_underflow_wa(dc, pipe_ctx->stream, pipe_ctx->stream_res.tg);
 801         }
 802
 803         /* VTG is  within DCHUB command block. DCFCLK is always on */
 804         if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {
 805                 BREAK_TO_DEBUGGER();
 806                 return DC_ERROR_UNEXPECTED;
 807         }
 808
 809         /* TODO program crtc source select for non-virtual signal*/
 810         /* TODO program FMT */
 811         /* TODO setup link_enc */
 812         /* TODO set stream attributes */
 813         /* TODO program audio */
 814         /* TODO enable stream if timing changed */
 815         /* TODO unblank stream if DP */
 816
 817         return DC_OK;
 818 }
 819
 820 static void dcn10_reset_back_end_for_pipe(
 821                 struct dc *dc,
 822                 struct pipe_ctx *pipe_ctx,
 823                 struct dc_state *context)
 824 {
 825         int i;
 826         DC_LOGGER_INIT(dc->ctx->logger);
 827         if (pipe_ctx->stream_res.stream_enc == NULL) {
 828                 pipe_ctx->stream = NULL;
 829                 return;
 830         }
 831
 832         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
 833                 /* DPMS may already disable */
 834                 if (!pipe_ctx->stream->dpms_off)
 835                         core_link_disable_stream(pipe_ctx);
 836                 else if (pipe_ctx->stream_res.audio)
 837                         dc->hwss.disable_audio_stream(pipe_ctx);
 838
 839                 if (pipe_ctx->stream_res.audio) {
 840                         /*disable az_endpoint*/
 841                         pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
 842
 843                         /*free audio*/
 844                         if (dc->caps.dynamic_audio == true) {
 845                                 /*we have to dynamic arbitrate the audio endpoints*/
 846                                 /*we free the resource, need reset is_audio_acquired*/
 847                                 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
 848                                                 pipe_ctx->stream_res.audio, false);
 849                                 pipe_ctx->stream_res.audio = NULL;
 850                         }
 851                 }
 852         }
 853
 854         /* by upper caller loop, parent pipe: pipe0, will be reset last.
 855          * back end share by all pipes and will be disable only when disable
 856          * parent pipe.
 857          */
 858         if (pipe_ctx->top_pipe == NULL) {
 859                 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
 860
 861                 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
 862                 if (pipe_ctx->stream_res.tg->funcs->set_drr)
 863                         pipe_ctx->stream_res.tg->funcs->set_drr(
 864                                         pipe_ctx->stream_res.tg, NULL);
 865         }
 866
 867         for (i = 0; i < dc->res_pool->pipe_count; i++)
 868                 if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx)
 869                         break;
 870
 871         if (i == dc->res_pool->pipe_count)
 872                 return;
 873
 874         pipe_ctx->stream = NULL;
 875         DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n",
 876                                         pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
 877 }
 878
 879 static bool dcn10_hw_wa_force_recovery(struct dc *dc)
 880 {
 881         struct hubp *hubp ;
 882         unsigned int i;
 883         bool need_recover = true;
 884
 885         if (!dc->debug.recovery_enabled)
 886                 return false;
 887
 888         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 889                 struct pipe_ctx *pipe_ctx =
 890                         &dc->current_state->res_ctx.pipe_ctx[i];
 891                 if (pipe_ctx != NULL) {
 892                         hubp = pipe_ctx->plane_res.hubp;
 893                         if (hubp != NULL && hubp->funcs->hubp_get_underflow_status) {
 894                                 if (hubp->funcs->hubp_get_underflow_status(hubp) != 0) {
 895                                         /* one pipe underflow, we will reset all the pipes*/
 896                                         need_recover = true;
 897                                 }
 898                         }
 899                 }
 900         }
 901         if (!need_recover)
 902                 return false;
 903         /*
 904         DCHUBP_CNTL:HUBP_BLANK_EN=1
 905         DCHUBBUB_SOFT_RESET:DCHUBBUB_GLOBAL_SOFT_RESET=1
 906         DCHUBP_CNTL:HUBP_DISABLE=1
 907         DCHUBP_CNTL:HUBP_DISABLE=0
 908         DCHUBBUB_SOFT_RESET:DCHUBBUB_GLOBAL_SOFT_RESET=0
 909         DCSURF_PRIMARY_SURFACE_ADDRESS
 910         DCHUBP_CNTL:HUBP_BLANK_EN=0
 911         */
 912
 913         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 914                 struct pipe_ctx *pipe_ctx =
 915                         &dc->current_state->res_ctx.pipe_ctx[i];
 916                 if (pipe_ctx != NULL) {
 917                         hubp = pipe_ctx->plane_res.hubp;
 918                         /*DCHUBP_CNTL:HUBP_BLANK_EN=1*/
 919                         if (hubp != NULL && hubp->funcs->set_hubp_blank_en)
 920                                 hubp->funcs->set_hubp_blank_en(hubp, true);
 921                 }
 922         }
 923         /*DCHUBBUB_SOFT_RESET:DCHUBBUB_GLOBAL_SOFT_RESET=1*/
 924         hubbub1_soft_reset(dc->res_pool->hubbub, true);
 925
 926         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 927                 struct pipe_ctx *pipe_ctx =
 928                         &dc->current_state->res_ctx.pipe_ctx[i];
 929                 if (pipe_ctx != NULL) {
 930                         hubp = pipe_ctx->plane_res.hubp;
 931                         /*DCHUBP_CNTL:HUBP_DISABLE=1*/
 932                         if (hubp != NULL && hubp->funcs->hubp_disable_control)
 933                                 hubp->funcs->hubp_disable_control(hubp, true);
 934                 }
 935         }
 936         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 937                 struct pipe_ctx *pipe_ctx =
 938                         &dc->current_state->res_ctx.pipe_ctx[i];
 939                 if (pipe_ctx != NULL) {
 940                         hubp = pipe_ctx->plane_res.hubp;
 941                         /*DCHUBP_CNTL:HUBP_DISABLE=0*/
 942                         if (hubp != NULL && hubp->funcs->hubp_disable_control)
 943                                 hubp->funcs->hubp_disable_control(hubp, true);
 944                 }
 945         }
 946         /*DCHUBBUB_SOFT_RESET:DCHUBBUB_GLOBAL_SOFT_RESET=0*/
 947         hubbub1_soft_reset(dc->res_pool->hubbub, false);
 948         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 949                 struct pipe_ctx *pipe_ctx =
 950                         &dc->current_state->res_ctx.pipe_ctx[i];
 951                 if (pipe_ctx != NULL) {
 952                         hubp = pipe_ctx->plane_res.hubp;
 953                         /*DCHUBP_CNTL:HUBP_BLANK_EN=0*/
 954                         if (hubp != NULL && hubp->funcs->set_hubp_blank_en)
 955                                 hubp->funcs->set_hubp_blank_en(hubp, true);
 956                 }
 957         }
 958         return true;
 959
 960 }
 961
 962
 963 void dcn10_verify_allow_pstate_change_high(struct dc *dc)
 964 {
 965         static bool should_log_hw_state; /* prevent hw state log by default */
 966
 967         if (!hubbub1_verify_allow_pstate_change_high(dc->res_pool->hubbub)) {
 968                 if (should_log_hw_state) {
 969                         dcn10_log_hw_state(dc, NULL);
 970                 }
 971                 BREAK_TO_DEBUGGER();
 972                 if (dcn10_hw_wa_force_recovery(dc)) {
 973                 /*check again*/
 974                         if (!hubbub1_verify_allow_pstate_change_high(dc->res_pool->hubbub))
 975                                 BREAK_TO_DEBUGGER();
 976                 }
 977         }
 978 }
 979
 980 /* trigger HW to start disconnect plane from stream on the next vsync */
 981 void hwss1_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx)
 982 {
 983         struct hubp *hubp = pipe_ctx->plane_res.hubp;
 984         int dpp_id = pipe_ctx->plane_res.dpp->inst;
 985         struct mpc *mpc = dc->res_pool->mpc;
 986         struct mpc_tree *mpc_tree_params;
 987         struct mpcc *mpcc_to_remove = NULL;
 988         struct output_pixel_processor *opp = pipe_ctx->stream_res.opp;
 989
 990         mpc_tree_params = &(opp->mpc_tree_params);
 991         mpcc_to_remove = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, dpp_id);
 992
 993         /*Already reset*/
 994         if (mpcc_to_remove == NULL)
 995                 return;
 996
 997         mpc->funcs->remove_mpcc(mpc, mpc_tree_params, mpcc_to_remove);
 998         if (opp != NULL)
 999                 opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
1000
1001         dc->optimized_required = true;
1002
1003         if (hubp->funcs->hubp_disconnect)
1004                 hubp->funcs->hubp_disconnect(hubp);
1005
1006         if (dc->debug.sanity_checks)
1007                 dcn10_verify_allow_pstate_change_high(dc);
1008 }
1009
1010 static void dcn10_plane_atomic_power_down(struct dc *dc,
1011                 struct dpp *dpp,
1012                 struct hubp *hubp)
1013 {
1014         struct dce_hwseq *hws = dc->hwseq;
1015         DC_LOGGER_INIT(dc->ctx->logger);
1016
1017         if (REG(DC_IP_REQUEST_CNTL)) {
1018                 REG_SET(DC_IP_REQUEST_CNTL, 0,
1019                                 IP_REQUEST_EN, 1);
1020                 dc->hwss.dpp_pg_control(hws, dpp->inst, false);
1021                 dc->hwss.hubp_pg_control(hws, hubp->inst, false);
1022                 dpp->funcs->dpp_reset(dpp);
1023                 REG_SET(DC_IP_REQUEST_CNTL, 0,
1024                                 IP_REQUEST_EN, 0);
1025                 DC_LOG_DEBUG(
1026                                 "Power gated front end %d\n", hubp->inst);
1027         }
1028 }
1029
1030 /* disable HW used by plane.
1031  * note:  cannot disable until disconnect is complete
1032  */
1033 static void dcn10_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
1034 {
1035         struct hubp *hubp = pipe_ctx->plane_res.hubp;
1036         struct dpp *dpp = pipe_ctx->plane_res.dpp;
1037         int opp_id = hubp->opp_id;
1038
1039         dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);
1040
1041         hubp->funcs->hubp_clk_cntl(hubp, false);
1042
1043         dpp->funcs->dpp_dppclk_control(dpp, false, false);
1044
1045         if (opp_id != 0xf && pipe_ctx->stream_res.opp->mpc_tree_params.opp_list == NULL)
1046                 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
1047                                 pipe_ctx->stream_res.opp,
1048                                 false);
1049
1050         hubp->power_gated = true;
1051         dc->optimized_required = false; /* We're powering off, no need to optimize */
1052
1053         dc->hwss.plane_atomic_power_down(dc,
1054                         pipe_ctx->plane_res.dpp,
1055                         pipe_ctx->plane_res.hubp);
1056
1057         pipe_ctx->stream = NULL;
1058         memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res));
1059         memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res));
1060         pipe_ctx->top_pipe = NULL;
1061         pipe_ctx->bottom_pipe = NULL;
1062         pipe_ctx->plane_state = NULL;
1063 }
1064
1065 static void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
1066 {
1067         DC_LOGGER_INIT(dc->ctx->logger);
1068
1069         if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)
1070                 return;
1071
1072         dc->hwss.plane_atomic_disable(dc, pipe_ctx);
1073
1074         apply_DEGVIDCN10_253_wa(dc);
1075
1076         DC_LOG_DC("Power down front end %d\n",
1077                                         pipe_ctx->pipe_idx);
1078 }
1079
1080 static void dcn10_init_pipes(struct dc *dc, struct dc_state *context)
1081 {
1082         int i;
1083         bool can_apply_seamless_boot = false;
1084
1085         for (i = 0; i < context->stream_count; i++) {
1086                 if (context->streams[i]->apply_seamless_boot_optimization) {
1087                         can_apply_seamless_boot = true;
1088                         break;
1089                 }
1090         }
1091
1092         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1093                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
1094                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1095
1096                 /* There is assumption that pipe_ctx is not mapping irregularly
1097                  * to non-preferred front end. If pipe_ctx->stream is not NULL,
1098                  * we will use the pipe, so don't disable
1099                  */
1100                 if (pipe_ctx->stream != NULL && can_apply_seamless_boot)
1101                         continue;
1102
1103                 /* Blank controller using driver code instead of
1104                  * command table.
1105                  */
1106                 if (tg->funcs->is_tg_enabled(tg)) {
1107                         if (dc->hwss.init_blank != NULL) {
1108                                 dc->hwss.init_blank(dc, tg);
1109                                 tg->funcs->lock(tg);
1110                         } else {
1111                                 tg->funcs->lock(tg);
1112                                 tg->funcs->set_blank(tg, true);
1113                                 hwss_wait_for_blank_complete(tg);
1114                         }
1115                 }
1116         }
1117
1118         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1119                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1120
1121                 /* Cannot reset the MPC mux if seamless boot */
1122                 if (pipe_ctx->stream != NULL && can_apply_seamless_boot)
1123                         continue;
1124
1125                 dc->res_pool->mpc->funcs->mpc_init_single_inst(
1126                                 dc->res_pool->mpc, i);
1127         }
1128
1129         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1130                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
1131                 struct hubp *hubp = dc->res_pool->hubps[i];
1132                 struct dpp *dpp = dc->res_pool->dpps[i];
1133                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1134
1135                 /* There is assumption that pipe_ctx is not mapping irregularly
1136                  * to non-preferred front end. If pipe_ctx->stream is not NULL,
1137                  * we will use the pipe, so don't disable
1138                  */
1139                 if (can_apply_seamless_boot &&
1140                         pipe_ctx->stream != NULL &&
1141                         pipe_ctx->stream_res.tg->funcs->is_tg_enabled(
1142                                 pipe_ctx->stream_res.tg))
1143                         continue;
1144
1145                 /* Disable on the current state so the new one isn't cleared. */
1146                 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
1147
1148                 dpp->funcs->dpp_reset(dpp);
1149
1150                 pipe_ctx->stream_res.tg = tg;
1151                 pipe_ctx->pipe_idx = i;
1152
1153                 pipe_ctx->plane_res.hubp = hubp;
1154                 pipe_ctx->plane_res.dpp = dpp;
1155                 pipe_ctx->plane_res.mpcc_inst = dpp->inst;
1156                 hubp->mpcc_id = dpp->inst;
1157                 hubp->opp_id = OPP_ID_INVALID;
1158                 hubp->power_gated = false;
1159
1160                 dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
1161                 dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
1162                 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
1163                 pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
1164
1165                 dc->hwss.plane_atomic_disconnect(dc, pipe_ctx);
1166
1167                 if (tg->funcs->is_tg_enabled(tg))
1168                         tg->funcs->unlock(tg);
1169
1170                 dc->hwss.disable_plane(dc, pipe_ctx);
1171
1172                 pipe_ctx->stream_res.tg = NULL;
1173                 pipe_ctx->plane_res.hubp = NULL;
1174
1175                 tg->funcs->tg_init(tg);
1176         }
1177 }
1178
1179 static void dcn10_init_hw(struct dc *dc)
1180 {
1181         int i;
1182         struct abm *abm = dc->res_pool->abm;
1183         struct dmcu *dmcu = dc->res_pool->dmcu;
1184         struct dce_hwseq *hws = dc->hwseq;
1185         struct dc_bios *dcb = dc->ctx->dc_bios;
1186         struct resource_pool *res_pool = dc->res_pool;
1187
1188         if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
1189                 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
1190
1191         // Initialize the dccg
1192         if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->dccg_init)
1193                 dc->res_pool->dccg->funcs->dccg_init(res_pool->dccg);
1194
1195         if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
1196
1197                 REG_WRITE(REFCLK_CNTL, 0);
1198                 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
1199                 REG_WRITE(DIO_MEM_PWR_CTRL, 0);
1200
1201                 if (!dc->debug.disable_clock_gate) {
1202                         /* enable all DCN clock gating */
1203                         REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
1204
1205                         REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
1206
1207                         REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
1208                 }
1209
1210                 //Enable ability to power gate / don't force power on permanently
1211                 dc->hwss.enable_power_gating_plane(hws, true);
1212
1213                 return;
1214         }
1215
1216         if (!dcb->funcs->is_accelerated_mode(dcb))
1217                 dc->hwss.disable_vga(dc->hwseq);
1218
1219         dc->hwss.bios_golden_init(dc);
1220         if (dc->ctx->dc_bios->fw_info_valid) {
1221                 res_pool->ref_clocks.xtalin_clock_inKhz =
1222                                 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
1223
1224                 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
1225                         if (res_pool->dccg && res_pool->hubbub) {
1226
1227                                 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
1228                                                 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
1229                                                 &res_pool->ref_clocks.dccg_ref_clock_inKhz);
1230
1231                                 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
1232                                                 res_pool->ref_clocks.dccg_ref_clock_inKhz,
1233                                                 &res_pool->ref_clocks.dchub_ref_clock_inKhz);
1234                         } else {
1235                                 // Not all ASICs have DCCG sw component
1236                                 res_pool->ref_clocks.dccg_ref_clock_inKhz =
1237                                                 res_pool->ref_clocks.xtalin_clock_inKhz;
1238                                 res_pool->ref_clocks.dchub_ref_clock_inKhz =
1239                                                 res_pool->ref_clocks.xtalin_clock_inKhz;
1240                         }
1241                 }
1242         } else
1243                 ASSERT_CRITICAL(false);
1244
1245         for (i = 0; i < dc->link_count; i++) {
1246                 /* Power up AND update implementation according to the
1247                  * required signal (which may be different from the
1248                  * default signal on connector).
1249                  */
1250                 struct dc_link *link = dc->links[i];
1251
1252                 link->link_enc->funcs->hw_init(link->link_enc);
1253
1254                 /* Check for enabled DIG to identify enabled display */
1255                 if (link->link_enc->funcs->is_dig_enabled &&
1256                         link->link_enc->funcs->is_dig_enabled(link->link_enc))
1257                         link->link_status.link_active = true;
1258         }
1259
1260         /* Power gate DSCs */
1261 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1262         for (i = 0; i < res_pool->res_cap->num_dsc; i++)
1263                 if (dc->hwss.dsc_pg_control != NULL)
1264                         dc->hwss.dsc_pg_control(hws, res_pool->dscs[i]->inst, false);
1265 #endif
1266
1267         /* If taking control over from VBIOS, we may want to optimize our first
1268          * mode set, so we need to skip powering down pipes until we know which
1269          * pipes we want to use.
1270          * Otherwise, if taking control is not possible, we need to power
1271          * everything down.
1272          */
1273         if (dcb->funcs->is_accelerated_mode(dcb) || dc->config.power_down_display_on_boot) {
1274                 dc->hwss.init_pipes(dc, dc->current_state);
1275         }
1276
1277         for (i = 0; i < res_pool->audio_count; i++) {
1278                 struct audio *audio = res_pool->audios[i];
1279
1280                 audio->funcs->hw_init(audio);
1281         }
1282
1283         if (abm != NULL) {
1284                 abm->funcs->init_backlight(abm);
1285                 abm->funcs->abm_init(abm);
1286         }
1287
1288         if (dmcu != NULL)
1289                 dmcu->funcs->dmcu_init(dmcu);
1290
1291         if (abm != NULL && dmcu != NULL)
1292                 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
1293
1294         /* power AFMT HDMI memory TODO: may move to dis/en output save power*/
1295         REG_WRITE(DIO_MEM_PWR_CTRL, 0);
1296
1297         if (!dc->debug.disable_clock_gate) {
1298                 /* enable all DCN clock gating */
1299                 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
1300
1301                 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
1302
1303                 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
1304         }
1305
1306         dc->hwss.enable_power_gating_plane(dc->hwseq, true);
1307
1308         if (dc->clk_mgr->funcs->notify_wm_ranges)
1309                 dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);
1310
1311 }
1312
1313 static void dcn10_reset_hw_ctx_wrap(
1314                 struct dc *dc,
1315                 struct dc_state *context)
1316 {
1317         int i;
1318
1319         /* Reset Back End*/
1320         for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
1321                 struct pipe_ctx *pipe_ctx_old =
1322                         &dc->current_state->res_ctx.pipe_ctx[i];
1323                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1324
1325                 if (!pipe_ctx_old->stream)
1326                         continue;
1327
1328                 if (pipe_ctx_old->top_pipe)
1329                         continue;
1330
1331                 if (!pipe_ctx->stream ||
1332                                 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
1333                         struct clock_source *old_clk = pipe_ctx_old->clock_source;
1334
1335                         dcn10_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
1336                         if (dc->hwss.enable_stream_gating)
1337                                 dc->hwss.enable_stream_gating(dc, pipe_ctx);
1338                         if (old_clk)
1339                                 old_clk->funcs->cs_power_down(old_clk);
1340                 }
1341         }
1342 }
1343
1344 static bool patch_address_for_sbs_tb_stereo(
1345                 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr)
1346 {
1347         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1348         bool sec_split = pipe_ctx->top_pipe &&
1349                         pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
1350         if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
1351                 (pipe_ctx->stream->timing.timing_3d_format ==
1352                  TIMING_3D_FORMAT_SIDE_BY_SIDE ||
1353                  pipe_ctx->stream->timing.timing_3d_format ==
1354                  TIMING_3D_FORMAT_TOP_AND_BOTTOM)) {
1355                 *addr = plane_state->address.grph_stereo.left_addr;
1356                 plane_state->address.grph_stereo.left_addr =
1357                 plane_state->address.grph_stereo.right_addr;
1358                 return true;
1359         } else {
1360                 if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE &&
1361                         plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) {
1362                         plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO;
1363                         plane_state->address.grph_stereo.right_addr =
1364                         plane_state->address.grph_stereo.left_addr;
1365                 }
1366         }
1367         return false;
1368 }
1369
1370
1371
1372 static void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)
1373 {
1374         bool addr_patched = false;
1375         PHYSICAL_ADDRESS_LOC addr;
1376         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1377
1378         if (plane_state == NULL)
1379                 return;
1380
1381         addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);
1382
1383         pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(
1384                         pipe_ctx->plane_res.hubp,
1385                         &plane_state->address,
1386                         plane_state->flip_immediate);
1387
1388         plane_state->status.requested_address = plane_state->address;
1389
1390         if (plane_state->flip_immediate)
1391                 plane_state->status.current_address = plane_state->address;
1392
1393         if (addr_patched)
1394                 pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;
1395 }
1396
1397 static bool dcn10_set_input_transfer_func(struct pipe_ctx *pipe_ctx,
1398                                           const struct dc_plane_state *plane_state)
1399 {
1400         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
1401         const struct dc_transfer_func *tf = NULL;
1402         bool result = true;
1403
1404         if (dpp_base == NULL)
1405                 return false;
1406
1407         if (plane_state->in_transfer_func)
1408                 tf = plane_state->in_transfer_func;
1409
1410         if (plane_state->gamma_correction &&
1411                 !dpp_base->ctx->dc->debug.always_use_regamma
1412                 && !plane_state->gamma_correction->is_identity
1413                         && dce_use_lut(plane_state->format))
1414                 dpp_base->funcs->dpp_program_input_lut(dpp_base, plane_state->gamma_correction);
1415
1416         if (tf == NULL)
1417                 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
1418         else if (tf->type == TF_TYPE_PREDEFINED) {
1419                 switch (tf->tf) {
1420                 case TRANSFER_FUNCTION_SRGB:
1421                         dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_sRGB);
1422                         break;
1423                 case TRANSFER_FUNCTION_BT709:
1424                         dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_xvYCC);
1425                         break;
1426                 case TRANSFER_FUNCTION_LINEAR:
1427                         dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
1428                         break;
1429                 case TRANSFER_FUNCTION_PQ:
1430                 default:
1431                         result = false;
1432                         break;
1433                 }
1434         } else if (tf->type == TF_TYPE_BYPASS) {
1435                 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
1436         } else {
1437                 cm_helper_translate_curve_to_degamma_hw_format(tf,
1438                                         &dpp_base->degamma_params);
1439                 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base,
1440                                 &dpp_base->degamma_params);
1441                 result = true;
1442         }
1443
1444         return result;
1445 }
1446
1447 #define MAX_NUM_HW_POINTS 0x200
1448
1449 static void log_tf(struct dc_context *ctx,
1450                                 struct dc_transfer_func *tf, uint32_t hw_points_num)
1451 {
1452         // DC_LOG_GAMMA is default logging of all hw points
1453         // DC_LOG_ALL_GAMMA logs all points, not only hw points
1454         // DC_LOG_ALL_TF_POINTS logs all channels of the tf
1455         int i = 0;
1456
1457         DC_LOGGER_INIT(ctx->logger);
1458         DC_LOG_GAMMA("Gamma Correction TF");
1459         DC_LOG_ALL_GAMMA("Logging all tf points...");
1460         DC_LOG_ALL_TF_CHANNELS("Logging all channels...");
1461
1462         for (i = 0; i < hw_points_num; i++) {
1463                 DC_LOG_GAMMA("R\t%d\t%llu", i, tf->tf_pts.red[i].value);
1464                 DC_LOG_ALL_TF_CHANNELS("G\t%d\t%llu", i, tf->tf_pts.green[i].value);
1465                 DC_LOG_ALL_TF_CHANNELS("B\t%d\t%llu", i, tf->tf_pts.blue[i].value);
1466         }
1467
1468         for (i = hw_points_num; i < MAX_NUM_HW_POINTS; i++) {
1469                 DC_LOG_ALL_GAMMA("R\t%d\t%llu", i, tf->tf_pts.red[i].value);
1470                 DC_LOG_ALL_TF_CHANNELS("G\t%d\t%llu", i, tf->tf_pts.green[i].value);
1471                 DC_LOG_ALL_TF_CHANNELS("B\t%d\t%llu", i, tf->tf_pts.blue[i].value);
1472         }
1473 }
1474
1475 static bool
1476 dcn10_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
1477                                const struct dc_stream_state *stream)
1478 {
1479         struct dpp *dpp = pipe_ctx->plane_res.dpp;
1480
1481         if (dpp == NULL)
1482                 return false;
1483
1484         dpp->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
1485
1486         if (stream->out_transfer_func &&
1487             stream->out_transfer_func->type == TF_TYPE_PREDEFINED &&
1488             stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB)
1489                 dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_SRGB);
1490
1491         /* dcn10_translate_regamma_to_hw_format takes 750us, only do it when full
1492          * update.
1493          */
1494         else if (cm_helper_translate_curve_to_hw_format(
1495                         stream->out_transfer_func,
1496                         &dpp->regamma_params, false)) {
1497                 dpp->funcs->dpp_program_regamma_pwl(
1498                                 dpp,
1499                                 &dpp->regamma_params, OPP_REGAMMA_USER);
1500         } else
1501                 dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_BYPASS);
1502
1503         if (stream != NULL && stream->ctx != NULL &&
1504                         stream->out_transfer_func != NULL) {
1505                 log_tf(stream->ctx,
1506                                 stream->out_transfer_func,
1507                                 dpp->regamma_params.hw_points_num);
1508         }
1509
1510         return true;
1511 }
1512
1513 static void dcn10_pipe_control_lock(
1514         struct dc *dc,
1515         struct pipe_ctx *pipe,
1516         bool lock)
1517 {
1518         /* use TG master update lock to lock everything on the TG
1519          * therefore only top pipe need to lock
1520          */
1521         if (pipe->top_pipe)
1522                 return;
1523
1524         if (dc->debug.sanity_checks)
1525                 dcn10_verify_allow_pstate_change_high(dc);
1526
1527         if (lock)
1528                 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);
1529         else
1530                 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);
1531
1532         if (dc->debug.sanity_checks)
1533                 dcn10_verify_allow_pstate_change_high(dc);
1534 }
1535
1536 static bool wait_for_reset_trigger_to_occur(
1537         struct dc_context *dc_ctx,
1538         struct timing_generator *tg)
1539 {
1540         bool rc = false;
1541
1542         /* To avoid endless loop we wait at most
1543          * frames_to_wait_on_triggered_reset frames for the reset to occur. */
1544         const uint32_t frames_to_wait_on_triggered_reset = 10;
1545         int i;
1546
1547         for (i = 0; i < frames_to_wait_on_triggered_reset; i++) {
1548
1549                 if (!tg->funcs->is_counter_moving(tg)) {
1550                         DC_ERROR("TG counter is not moving!\n");
1551                         break;
1552                 }
1553
1554                 if (tg->funcs->did_triggered_reset_occur(tg)) {
1555                         rc = true;
1556                         /* usually occurs at i=1 */
1557                         DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",
1558                                         i);
1559                         break;
1560                 }
1561
1562                 /* Wait for one frame. */
1563                 tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);
1564                 tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
1565         }
1566
1567         if (false == rc)
1568                 DC_ERROR("GSL: Timeout on reset trigger!\n");
1569
1570         return rc;
1571 }
1572
1573 static void dcn10_enable_timing_synchronization(
1574         struct dc *dc,
1575         int group_index,
1576         int group_size,
1577         struct pipe_ctx *grouped_pipes[])
1578 {
1579         struct dc_context *dc_ctx = dc->ctx;
1580         int i;
1581
1582         DC_SYNC_INFO("Setting up OTG reset trigger\n");
1583
1584         for (i = 1; i < group_size; i++)
1585                 grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger(
1586                                 grouped_pipes[i]->stream_res.tg,
1587                                 grouped_pipes[0]->stream_res.tg->inst);
1588
1589         DC_SYNC_INFO("Waiting for trigger\n");
1590
1591         /* Need to get only check 1 pipe for having reset as all the others are
1592          * synchronized. Look at last pipe programmed to reset.
1593          */
1594
1595         wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[1]->stream_res.tg);
1596         for (i = 1; i < group_size; i++)
1597                 grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(
1598                                 grouped_pipes[i]->stream_res.tg);
1599
1600         DC_SYNC_INFO("Sync complete\n");
1601 }
1602
1603 static void dcn10_enable_per_frame_crtc_position_reset(
1604         struct dc *dc,
1605         int group_size,
1606         struct pipe_ctx *grouped_pipes[])
1607 {
1608         struct dc_context *dc_ctx = dc->ctx;
1609         int i;
1610
1611         DC_SYNC_INFO("Setting up\n");
1612         for (i = 0; i < group_size; i++)
1613                 if (grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset)
1614                         grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset(
1615                                         grouped_pipes[i]->stream_res.tg,
1616                                         0,
1617                                         &grouped_pipes[i]->stream->triggered_crtc_reset);
1618
1619         DC_SYNC_INFO("Waiting for trigger\n");
1620
1621         for (i = 0; i < group_size; i++)
1622                 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
1623
1624         DC_SYNC_INFO("Multi-display sync is complete\n");
1625 }
1626
1627 /*static void print_rq_dlg_ttu(
1628                 struct dc *core_dc,
1629                 struct pipe_ctx *pipe_ctx)
1630 {
1631         DC_LOG_BANDWIDTH_CALCS(core_dc->ctx->logger,
1632                         "\n============== DML TTU Output parameters [%d] ==============\n"
1633                         "qos_level_low_wm: %d, \n"
1634                         "qos_level_high_wm: %d, \n"
1635                         "min_ttu_vblank: %d, \n"
1636                         "qos_level_flip: %d, \n"
1637                         "refcyc_per_req_delivery_l: %d, \n"
1638                         "qos_level_fixed_l: %d, \n"
1639                         "qos_ramp_disable_l: %d, \n"
1640                         "refcyc_per_req_delivery_pre_l: %d, \n"
1641                         "refcyc_per_req_delivery_c: %d, \n"
1642                         "qos_level_fixed_c: %d, \n"
1643                         "qos_ramp_disable_c: %d, \n"
1644                         "refcyc_per_req_delivery_pre_c: %d\n"
1645                         "=============================================================\n",
1646                         pipe_ctx->pipe_idx,
1647                         pipe_ctx->ttu_regs.qos_level_low_wm,
1648                         pipe_ctx->ttu_regs.qos_level_high_wm,
1649                         pipe_ctx->ttu_regs.min_ttu_vblank,
1650                         pipe_ctx->ttu_regs.qos_level_flip,
1651                         pipe_ctx->ttu_regs.refcyc_per_req_delivery_l,
1652                         pipe_ctx->ttu_regs.qos_level_fixed_l,
1653                         pipe_ctx->ttu_regs.qos_ramp_disable_l,
1654                         pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_l,
1655                         pipe_ctx->ttu_regs.refcyc_per_req_delivery_c,
1656                         pipe_ctx->ttu_regs.qos_level_fixed_c,
1657                         pipe_ctx->ttu_regs.qos_ramp_disable_c,
1658                         pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_c
1659                         );
1660
1661         DC_LOG_BANDWIDTH_CALCS(core_dc->ctx->logger,
1662                         "\n============== DML DLG Output parameters [%d] ==============\n"
1663                         "refcyc_h_blank_end: %d, \n"
1664                         "dlg_vblank_end: %d, \n"
1665                         "min_dst_y_next_start: %d, \n"
1666                         "refcyc_per_htotal: %d, \n"
1667                         "refcyc_x_after_scaler: %d, \n"
1668                         "dst_y_after_scaler: %d, \n"
1669                         "dst_y_prefetch: %d, \n"
1670                         "dst_y_per_vm_vblank: %d, \n"
1671                         "dst_y_per_row_vblank: %d, \n"
1672                         "ref_freq_to_pix_freq: %d, \n"
1673                         "vratio_prefetch: %d, \n"
1674                         "refcyc_per_pte_group_vblank_l: %d, \n"
1675                         "refcyc_per_meta_chunk_vblank_l: %d, \n"
1676                         "dst_y_per_pte_row_nom_l: %d, \n"
1677                         "refcyc_per_pte_group_nom_l: %d, \n",
1678                         pipe_ctx->pipe_idx,
1679                         pipe_ctx->dlg_regs.refcyc_h_blank_end,
1680                         pipe_ctx->dlg_regs.dlg_vblank_end,
1681                         pipe_ctx->dlg_regs.min_dst_y_next_start,
1682                         pipe_ctx->dlg_regs.refcyc_per_htotal,
1683                         pipe_ctx->dlg_regs.refcyc_x_after_scaler,
1684                         pipe_ctx->dlg_regs.dst_y_after_scaler,
1685                         pipe_ctx->dlg_regs.dst_y_prefetch,
1686                         pipe_ctx->dlg_regs.dst_y_per_vm_vblank,
1687                         pipe_ctx->dlg_regs.dst_y_per_row_vblank,
1688                         pipe_ctx->dlg_regs.ref_freq_to_pix_freq,
1689                         pipe_ctx->dlg_regs.vratio_prefetch,
1690                         pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_l,
1691                         pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_l,
1692                         pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_l,
1693                         pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_l
1694                         );
1695
1696         DC_LOG_BANDWIDTH_CALCS(core_dc->ctx->logger,
1697                         "\ndst_y_per_meta_row_nom_l: %d, \n"
1698                         "refcyc_per_meta_chunk_nom_l: %d, \n"
1699                         "refcyc_per_line_delivery_pre_l: %d, \n"
1700                         "refcyc_per_line_delivery_l: %d, \n"
1701                         "vratio_prefetch_c: %d, \n"
1702                         "refcyc_per_pte_group_vblank_c: %d, \n"
1703                         "refcyc_per_meta_chunk_vblank_c: %d, \n"
1704                         "dst_y_per_pte_row_nom_c: %d, \n"
1705                         "refcyc_per_pte_group_nom_c: %d, \n"
1706                         "dst_y_per_meta_row_nom_c: %d, \n"
1707                         "refcyc_per_meta_chunk_nom_c: %d, \n"
1708                         "refcyc_per_line_delivery_pre_c: %d, \n"
1709                         "refcyc_per_line_delivery_c: %d \n"
1710                         "========================================================\n",
1711                         pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_l,
1712                         pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_l,
1713                         pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_l,
1714                         pipe_ctx->dlg_regs.refcyc_per_line_delivery_l,
1715                         pipe_ctx->dlg_regs.vratio_prefetch_c,
1716                         pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_c,
1717                         pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_c,
1718                         pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_c,
1719                         pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_c,
1720                         pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_c,
1721                         pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_c,
1722                         pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_c,
1723                         pipe_ctx->dlg_regs.refcyc_per_line_delivery_c
1724                         );
1725
1726         DC_LOG_BANDWIDTH_CALCS(core_dc->ctx->logger,
1727                         "\n============== DML RQ Output parameters [%d] ==============\n"
1728                         "chunk_size: %d \n"
1729                         "min_chunk_size: %d \n"
1730                         "meta_chunk_size: %d \n"
1731                         "min_meta_chunk_size: %d \n"
1732                         "dpte_group_size: %d \n"
1733                         "mpte_group_size: %d \n"
1734                         "swath_height: %d \n"
1735                         "pte_row_height_linear: %d \n"
1736                         "========================================================\n",
1737                         pipe_ctx->pipe_idx,
1738                         pipe_ctx->rq_regs.rq_regs_l.chunk_size,
1739                         pipe_ctx->rq_regs.rq_regs_l.min_chunk_size,
1740                         pipe_ctx->rq_regs.rq_regs_l.meta_chunk_size,
1741                         pipe_ctx->rq_regs.rq_regs_l.min_meta_chunk_size,
1742                         pipe_ctx->rq_regs.rq_regs_l.dpte_group_size,
1743                         pipe_ctx->rq_regs.rq_regs_l.mpte_group_size,
1744                         pipe_ctx->rq_regs.rq_regs_l.swath_height,
1745                         pipe_ctx->rq_regs.rq_regs_l.pte_row_height_linear
1746                         );
1747 }
1748 */
1749
1750 static void mmhub_read_vm_system_aperture_settings(struct dcn10_hubp *hubp1,
1751                 struct vm_system_aperture_param *apt,
1752                 struct dce_hwseq *hws)
1753 {
1754         PHYSICAL_ADDRESS_LOC physical_page_number;
1755         uint32_t logical_addr_low;
1756         uint32_t logical_addr_high;
1757
1758         REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
1759                         PHYSICAL_PAGE_NUMBER_MSB, &physical_page_number.high_part);
1760         REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
1761                         PHYSICAL_PAGE_NUMBER_LSB, &physical_page_number.low_part);
1762
1763         REG_GET(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1764                         LOGICAL_ADDR, &logical_addr_low);
1765
1766         REG_GET(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1767                         LOGICAL_ADDR, &logical_addr_high);
1768
1769         apt->sys_default.quad_part =  physical_page_number.quad_part << 12;
1770         apt->sys_low.quad_part =  (int64_t)logical_addr_low << 18;
1771         apt->sys_high.quad_part =  (int64_t)logical_addr_high << 18;
1772 }
1773
1774 /* Temporary read settings, future will get values from kmd directly */
1775 static void mmhub_read_vm_context0_settings(struct dcn10_hubp *hubp1,
1776                 struct vm_context0_param *vm0,
1777                 struct dce_hwseq *hws)
1778 {
1779         PHYSICAL_ADDRESS_LOC fb_base;
1780         PHYSICAL_ADDRESS_LOC fb_offset;
1781         uint32_t fb_base_value;
1782         uint32_t fb_offset_value;
1783
1784         REG_GET(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, &fb_base_value);
1785         REG_GET(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, &fb_offset_value);
1786
1787         REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
1788                         PAGE_DIRECTORY_ENTRY_HI32, &vm0->pte_base.high_part);
1789         REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
1790                         PAGE_DIRECTORY_ENTRY_LO32, &vm0->pte_base.low_part);
1791
1792         REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
1793                         LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_start.high_part);
1794         REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
1795                         LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_start.low_part);
1796
1797         REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
1798                         LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_end.high_part);
1799         REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
1800                         LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_end.low_part);
1801
1802         REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
1803                         PHYSICAL_PAGE_ADDR_HI4, &vm0->fault_default.high_part);
1804         REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
1805                         PHYSICAL_PAGE_ADDR_LO32, &vm0->fault_default.low_part);
1806
1807         /*
1808          * The values in VM_CONTEXT0_PAGE_TABLE_BASE_ADDR is in UMA space.
1809          * Therefore we need to do
1810          * DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
1811          * - DCHUBBUB_SDPIF_FB_OFFSET + DCHUBBUB_SDPIF_FB_BASE
1812          */
1813         fb_base.quad_part = (uint64_t)fb_base_value << 24;
1814         fb_offset.quad_part = (uint64_t)fb_offset_value << 24;
1815         vm0->pte_base.quad_part += fb_base.quad_part;
1816         vm0->pte_base.quad_part -= fb_offset.quad_part;
1817 }
1818
1819
1820 void dcn10_program_pte_vm(struct dce_hwseq *hws, struct hubp *hubp)
1821 {
1822         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
1823         struct vm_system_aperture_param apt = { {{ 0 } } };
1824         struct vm_context0_param vm0 = { { { 0 } } };
1825
1826         mmhub_read_vm_system_aperture_settings(hubp1, &apt, hws);
1827         mmhub_read_vm_context0_settings(hubp1, &vm0, hws);
1828
1829         hubp->funcs->hubp_set_vm_system_aperture_settings(hubp, &apt);
1830         hubp->funcs->hubp_set_vm_context0_settings(hubp, &vm0);
1831 }
1832
1833 static void dcn10_enable_plane(
1834         struct dc *dc,
1835         struct pipe_ctx *pipe_ctx,
1836         struct dc_state *context)
1837 {
1838         struct dce_hwseq *hws = dc->hwseq;
1839
1840         if (dc->debug.sanity_checks) {
1841                 dcn10_verify_allow_pstate_change_high(dc);
1842         }
1843
1844         undo_DEGVIDCN10_253_wa(dc);
1845
1846         power_on_plane(dc->hwseq,
1847                 pipe_ctx->plane_res.hubp->inst);
1848
1849         /* enable DCFCLK current DCHUB */
1850         pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);
1851
1852         /* make sure OPP_PIPE_CLOCK_EN = 1 */
1853         pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
1854                         pipe_ctx->stream_res.opp,
1855                         true);
1856
1857 /* TODO: enable/disable in dm as per update type.
1858         if (plane_state) {
1859                 DC_LOG_DC(dc->ctx->logger,
1860                                 "Pipe:%d 0x%x: addr hi:0x%x, "
1861                                 "addr low:0x%x, "
1862                                 "src: %d, %d, %d,"
1863                                 " %d; dst: %d, %d, %d, %d;\n",
1864                                 pipe_ctx->pipe_idx,
1865                                 plane_state,
1866                                 plane_state->address.grph.addr.high_part,
1867                                 plane_state->address.grph.addr.low_part,
1868                                 plane_state->src_rect.x,
1869                                 plane_state->src_rect.y,
1870                                 plane_state->src_rect.width,
1871                                 plane_state->src_rect.height,
1872                                 plane_state->dst_rect.x,
1873                                 plane_state->dst_rect.y,
1874                                 plane_state->dst_rect.width,
1875                                 plane_state->dst_rect.height);
1876
1877                 DC_LOG_DC(dc->ctx->logger,
1878                                 "Pipe %d: width, height, x, y         format:%d\n"
1879                                 "viewport:%d, %d, %d, %d\n"
1880                                 "recout:  %d, %d, %d, %d\n",
1881                                 pipe_ctx->pipe_idx,
1882                                 plane_state->format,
1883                                 pipe_ctx->plane_res.scl_data.viewport.width,
1884                                 pipe_ctx->plane_res.scl_data.viewport.height,
1885                                 pipe_ctx->plane_res.scl_data.viewport.x,
1886                                 pipe_ctx->plane_res.scl_data.viewport.y,
1887                                 pipe_ctx->plane_res.scl_data.recout.width,
1888                                 pipe_ctx->plane_res.scl_data.recout.height,
1889                                 pipe_ctx->plane_res.scl_data.recout.x,
1890                                 pipe_ctx->plane_res.scl_data.recout.y);
1891                 print_rq_dlg_ttu(dc, pipe_ctx);
1892         }
1893 */
1894         if (dc->config.gpu_vm_support)
1895                 dcn10_program_pte_vm(hws, pipe_ctx->plane_res.hubp);
1896
1897         if (dc->debug.sanity_checks) {
1898                 dcn10_verify_allow_pstate_change_high(dc);
1899         }
1900 }
1901
1902 static void dcn10_program_gamut_remap(struct pipe_ctx *pipe_ctx)
1903 {
1904         int i = 0;
1905         struct dpp_grph_csc_adjustment adjust;
1906         memset(&adjust, 0, sizeof(adjust));
1907         adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
1908
1909
1910         if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
1911                 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
1912                 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
1913                         adjust.temperature_matrix[i] =
1914                                 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
1915         }
1916
1917         pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp, &adjust);
1918 }
1919
1920
1921 static bool dcn10_is_rear_mpo_fix_required(struct pipe_ctx *pipe_ctx, enum dc_color_space colorspace)
1922 {
1923         if (pipe_ctx->plane_state && pipe_ctx->plane_state->layer_index > 0 && is_rgb_cspace(colorspace)) {
1924                 if (pipe_ctx->top_pipe) {
1925                         struct pipe_ctx *top = pipe_ctx->top_pipe;
1926
1927                         while (top->top_pipe)
1928                                 top = top->top_pipe; // Traverse to top pipe_ctx
1929                         if (top->plane_state && top->plane_state->layer_index == 0)
1930                                 return true; // Front MPO plane not hidden
1931                 }
1932         }
1933         return false;
1934 }
1935
1936 static void dcn10_set_csc_adjustment_rgb_mpo_fix(struct pipe_ctx *pipe_ctx, uint16_t *matrix)
1937 {
1938         // Override rear plane RGB bias to fix MPO brightness
1939         uint16_t rgb_bias = matrix[3];
1940
1941         matrix[3] = 0;
1942         matrix[7] = 0;
1943         matrix[11] = 0;
1944         pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, matrix);
1945         matrix[3] = rgb_bias;
1946         matrix[7] = rgb_bias;
1947         matrix[11] = rgb_bias;
1948 }
1949
1950 static void dcn10_program_output_csc(struct dc *dc,
1951                 struct pipe_ctx *pipe_ctx,
1952                 enum dc_color_space colorspace,
1953                 uint16_t *matrix,
1954                 int opp_id)
1955 {
1956         if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
1957                 if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment != NULL) {
1958
1959                         /* MPO is broken with RGB colorspaces when OCSC matrix
1960                          * brightness offset >= 0 on DCN1 due to OCSC before MPC
1961                          * Blending adds offsets from front + rear to rear plane
1962                          *
1963                          * Fix is to set RGB bias to 0 on rear plane, top plane
1964                          * black value pixels add offset instead of rear + front
1965                          */
1966
1967                         int16_t rgb_bias = matrix[3];
1968                         // matrix[3/7/11] are all the same offset value
1969
1970                         if (rgb_bias > 0 && dcn10_is_rear_mpo_fix_required(pipe_ctx, colorspace)) {
1971                                 dcn10_set_csc_adjustment_rgb_mpo_fix(pipe_ctx, matrix);
1972                         } else {
1973                                 pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, matrix);
1974                         }
1975                 }
1976         } else {
1977                 if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default != NULL)
1978                         pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default(pipe_ctx->plane_res.dpp, colorspace);
1979         }
1980 }
1981
1982 bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
1983 {
1984         if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible)
1985                 return true;
1986         if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
1987                 return true;
1988         return false;
1989 }
1990
1991 bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
1992 {
1993         if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible)
1994                 return true;
1995         if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
1996                 return true;
1997         return false;
1998 }
1999
2000 bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
2001 {
2002         if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible)
2003                 return true;
2004         if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
2005                 return true;
2006         if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
2007                 return true;
2008         return false;
2009 }
2010
2011 bool is_rgb_cspace(enum dc_color_space output_color_space)
2012 {
2013         switch (output_color_space) {
2014         case COLOR_SPACE_SRGB:
2015         case COLOR_SPACE_SRGB_LIMITED:
2016         case COLOR_SPACE_2020_RGB_FULLRANGE:
2017         case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
2018         case COLOR_SPACE_ADOBERGB:
2019                 return true;
2020         case COLOR_SPACE_YCBCR601:
2021         case COLOR_SPACE_YCBCR709:
2022         case COLOR_SPACE_YCBCR601_LIMITED:
2023         case COLOR_SPACE_YCBCR709_LIMITED:
2024         case COLOR_SPACE_2020_YCBCR:
2025                 return false;
2026         default:
2027                 /* Add a case to switch */
2028                 BREAK_TO_DEBUGGER();
2029                 return false;
2030         }
2031 }
2032
2033 void dcn10_get_surface_visual_confirm_color(
2034                 const struct pipe_ctx *pipe_ctx,
2035                 struct tg_color *color)
2036 {
2037         uint32_t color_value = MAX_TG_COLOR_VALUE;
2038
2039         switch (pipe_ctx->plane_res.scl_data.format) {
2040         case PIXEL_FORMAT_ARGB8888:
2041                 /* set boarder color to red */
2042                 color->color_r_cr = color_value;
2043                 break;
2044
2045         case PIXEL_FORMAT_ARGB2101010:
2046                 /* set boarder color to blue */
2047                 color->color_b_cb = color_value;
2048                 break;
2049         case PIXEL_FORMAT_420BPP8:
2050                 /* set boarder color to green */
2051                 color->color_g_y = color_value;
2052                 break;
2053         case PIXEL_FORMAT_420BPP10:
2054                 /* set boarder color to yellow */
2055                 color->color_g_y = color_value;
2056                 color->color_r_cr = color_value;
2057                 break;
2058         case PIXEL_FORMAT_FP16:
2059                 /* set boarder color to white */
2060                 color->color_r_cr = color_value;
2061                 color->color_b_cb = color_value;
2062                 color->color_g_y = color_value;
2063                 break;
2064         default:
2065                 break;
2066         }
2067 }
2068
2069 void dcn10_get_hdr_visual_confirm_color(
2070                 struct pipe_ctx *pipe_ctx,
2071                 struct tg_color *color)
2072 {
2073         uint32_t color_value = MAX_TG_COLOR_VALUE;
2074
2075         // Determine the overscan color based on the top-most (desktop) plane's context
2076         struct pipe_ctx *top_pipe_ctx  = pipe_ctx;
2077
2078         while (top_pipe_ctx->top_pipe != NULL)
2079                 top_pipe_ctx = top_pipe_ctx->top_pipe;
2080
2081         switch (top_pipe_ctx->plane_res.scl_data.format) {
2082         case PIXEL_FORMAT_ARGB2101010:
2083                 if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_PQ) {
2084                         /* HDR10, ARGB2101010 - set boarder color to red */
2085                         color->color_r_cr = color_value;
2086                 }
2087                 break;
2088         case PIXEL_FORMAT_FP16:
2089                 if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_PQ) {
2090                         /* HDR10, FP16 - set boarder color to blue */
2091                         color->color_b_cb = color_value;
2092                 } else if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22) {
2093                         /* FreeSync 2 HDR - set boarder color to green */
2094                         color->color_g_y = color_value;
2095                 }
2096                 break;
2097         default:
2098                 /* SDR - set boarder color to Gray */
2099                 color->color_r_cr = color_value/2;
2100                 color->color_b_cb = color_value/2;
2101                 color->color_g_y = color_value/2;
2102                 break;
2103         }
2104 }
2105
2106 static uint16_t fixed_point_to_int_frac(
2107         struct fixed31_32 arg,
2108         uint8_t integer_bits,
2109         uint8_t fractional_bits)
2110 {
2111         int32_t numerator;
2112         int32_t divisor = 1 << fractional_bits;
2113
2114         uint16_t result;
2115
2116         uint16_t d = (uint16_t)dc_fixpt_floor(
2117                 dc_fixpt_abs(
2118                         arg));
2119
2120         if (d <= (uint16_t)(1 << integer_bits) - (1 / (uint16_t)divisor))
2121                 numerator = (uint16_t)dc_fixpt_floor(
2122                         dc_fixpt_mul_int(
2123                                 arg,
2124                                 divisor));
2125         else {
2126                 numerator = dc_fixpt_floor(
2127                         dc_fixpt_sub(
2128                                 dc_fixpt_from_int(
2129                                         1LL << integer_bits),
2130                                 dc_fixpt_recip(
2131                                         dc_fixpt_from_int(
2132                                                 divisor))));
2133         }
2134
2135         if (numerator >= 0)
2136                 result = (uint16_t)numerator;
2137         else
2138                 result = (uint16_t)(
2139                 (1 << (integer_bits + fractional_bits + 1)) + numerator);
2140
2141         if ((result != 0) && dc_fixpt_lt(
2142                 arg, dc_fixpt_zero))
2143                 result |= 1 << (integer_bits + fractional_bits);
2144
2145         return result;
2146 }
2147
2148 void dcn10_build_prescale_params(struct  dc_bias_and_scale *bias_and_scale,
2149                 const struct dc_plane_state *plane_state)
2150 {
2151         if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
2152                         && plane_state->format != SURFACE_PIXEL_FORMAT_INVALID
2153                         && plane_state->input_csc_color_matrix.enable_adjustment
2154                         && plane_state->coeff_reduction_factor.value != 0) {
2155                 bias_and_scale->scale_blue = fixed_point_to_int_frac(
2156                         dc_fixpt_mul(plane_state->coeff_reduction_factor,
2157                                         dc_fixpt_from_fraction(256, 255)),
2158                                 2,
2159                                 13);
2160                 bias_and_scale->scale_red = bias_and_scale->scale_blue;
2161                 bias_and_scale->scale_green = bias_and_scale->scale_blue;
2162         } else {
2163                 bias_and_scale->scale_blue = 0x2000;
2164                 bias_and_scale->scale_red = 0x2000;
2165                 bias_and_scale->scale_green = 0x2000;
2166         }
2167 }
2168
2169 static void update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state)
2170 {
2171         struct dc_bias_and_scale bns_params = {0};
2172
2173         // program the input csc
2174         dpp->funcs->dpp_setup(dpp,
2175                         plane_state->format,
2176                         EXPANSION_MODE_ZERO,
2177                         plane_state->input_csc_color_matrix,
2178 #ifdef CONFIG_DRM_AMD_DC_DCN2_0
2179                         plane_state->color_space,
2180                         NULL);
2181 #else
2182                         plane_state->color_space);
2183 #endif
2184
2185         //set scale and bias registers
2186         dcn10_build_prescale_params(&bns_params, plane_state);
2187         if (dpp->funcs->dpp_program_bias_and_scale)
2188                 dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
2189 }
2190
2191 static void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
2192 {
2193         struct hubp *hubp = pipe_ctx->plane_res.hubp;
2194         struct mpcc_blnd_cfg blnd_cfg = {{0}};
2195         bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
2196         int mpcc_id;
2197         struct mpcc *new_mpcc;
2198         struct mpc *mpc = dc->res_pool->mpc;
2199         struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);
2200
2201         if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) {
2202                 dcn10_get_hdr_visual_confirm_color(
2203                                 pipe_ctx, &blnd_cfg.black_color);
2204         } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) {
2205                 dcn10_get_surface_visual_confirm_color(
2206                                 pipe_ctx, &blnd_cfg.black_color);
2207         } else {
2208                 color_space_to_black_color(
2209                                 dc, pipe_ctx->stream->output_color_space,
2210                                 &blnd_cfg.black_color);
2211         }
2212
2213         if (per_pixel_alpha)
2214                 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;
2215         else
2216                 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA;
2217
2218         blnd_cfg.overlap_only = false;
2219         blnd_cfg.global_gain = 0xff;
2220
2221         if (pipe_ctx->plane_state->global_alpha)
2222                 blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value;
2223         else
2224                 blnd_cfg.global_alpha = 0xff;
2225
2226         /* DCN1.0 has output CM before MPC which seems to screw with
2227          * pre-multiplied alpha.
2228          */
2229         blnd_cfg.pre_multiplied_alpha = is_rgb_cspace(
2230                         pipe_ctx->stream->output_color_space)
2231                                         && per_pixel_alpha;
2232
2233
2234         /*
2235          * TODO: remove hack
2236          * Note: currently there is a bug in init_hw such that
2237          * on resume from hibernate, BIOS sets up MPCC0, and
2238          * we do mpcc_remove but the mpcc cannot go to idle
2239          * after remove. This cause us to pick mpcc1 here,
2240          * which causes a pstate hang for yet unknown reason.
2241          */
2242         mpcc_id = hubp->inst;
2243
2244         /* If there is no full update, don't need to touch MPC tree*/
2245         if (!pipe_ctx->plane_state->update_flags.bits.full_update) {
2246                 mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id);
2247                 return;
2248         }
2249
2250         /* check if this MPCC is already being used */
2251         new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id);
2252         /* remove MPCC if being used */
2253         if (new_mpcc != NULL)
2254                 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc);
2255         else
2256                 if (dc->debug.sanity_checks)
2257                         mpc->funcs->assert_mpcc_idle_before_connect(
2258                                         dc->res_pool->mpc, mpcc_id);
2259
2260         /* Call MPC to insert new plane */
2261         new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,
2262                         mpc_tree_params,
2263                         &blnd_cfg,
2264                         NULL,
2265                         NULL,
2266                         hubp->inst,
2267                         mpcc_id);
2268
2269         ASSERT(new_mpcc != NULL);
2270
2271         hubp->opp_id = pipe_ctx->stream_res.opp->inst;
2272         hubp->mpcc_id = mpcc_id;
2273 }
2274
2275 static void update_scaler(struct pipe_ctx *pipe_ctx)
2276 {
2277         bool per_pixel_alpha =
2278                         pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
2279
2280         pipe_ctx->plane_res.scl_data.lb_params.alpha_en = per_pixel_alpha;
2281         pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
2282         /* scaler configuration */
2283         pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(
2284                         pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);
2285 }
2286
2287 void update_dchubp_dpp(
2288         struct dc *dc,
2289         struct pipe_ctx *pipe_ctx,
2290         struct dc_state *context)
2291 {
2292         struct hubp *hubp = pipe_ctx->plane_res.hubp;
2293         struct dpp *dpp = pipe_ctx->plane_res.dpp;
2294         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2295         struct plane_size size = plane_state->plane_size;
2296         unsigned int compat_level = 0;
2297
2298         /* depends on DML calculation, DPP clock value may change dynamically */
2299         /* If request max dpp clk is lower than current dispclk, no need to
2300          * divided by 2
2301          */
2302         if (plane_state->update_flags.bits.full_update) {
2303                 bool should_divided_by_2 = context->bw_ctx.bw.dcn.clk.dppclk_khz <=
2304                                 dc->clk_mgr->clks.dispclk_khz / 2;
2305
2306                 dpp->funcs->dpp_dppclk_control(
2307                                 dpp,
2308                                 should_divided_by_2,
2309                                 true);
2310
2311                 if (dc->res_pool->dccg)
2312                         dc->res_pool->dccg->funcs->update_dpp_dto(
2313                                         dc->res_pool->dccg,
2314                                         dpp->inst,
2315                                         pipe_ctx->plane_res.bw.dppclk_khz);
2316                 else
2317                         dc->clk_mgr->clks.dppclk_khz = should_divided_by_2 ?
2318                                                 dc->clk_mgr->clks.dispclk_khz / 2 :
2319                                                         dc->clk_mgr->clks.dispclk_khz;
2320         }
2321
2322         /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG
2323          * VTG is within DCHUBBUB which is commond block share by each pipe HUBP.
2324          * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG
2325          */
2326         if (plane_state->update_flags.bits.full_update) {
2327                 hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst);
2328
2329                 hubp->funcs->hubp_setup(
2330                         hubp,
2331                         &pipe_ctx->dlg_regs,
2332                         &pipe_ctx->ttu_regs,
2333                         &pipe_ctx->rq_regs,
2334                         &pipe_ctx->pipe_dlg_param);
2335                 hubp->funcs->hubp_setup_interdependent(
2336                         hubp,
2337                         &pipe_ctx->dlg_regs,
2338                         &pipe_ctx->ttu_regs);
2339         }
2340
2341         size.surface_size = pipe_ctx->plane_res.scl_data.viewport;
2342
2343         if (plane_state->update_flags.bits.full_update ||
2344                 plane_state->update_flags.bits.bpp_change)
2345                 update_dpp(dpp, plane_state);
2346
2347         if (plane_state->update_flags.bits.full_update ||
2348                 plane_state->update_flags.bits.per_pixel_alpha_change ||
2349                 plane_state->update_flags.bits.global_alpha_change)
2350                 dc->hwss.update_mpcc(dc, pipe_ctx);
2351
2352         if (plane_state->update_flags.bits.full_update ||
2353                 plane_state->update_flags.bits.per_pixel_alpha_change ||
2354                 plane_state->update_flags.bits.global_alpha_change ||
2355                 plane_state->update_flags.bits.scaling_change ||
2356                 plane_state->update_flags.bits.position_change) {
2357                 update_scaler(pipe_ctx);
2358         }
2359
2360         if (plane_state->update_flags.bits.full_update ||
2361                 plane_state->update_flags.bits.scaling_change ||
2362                 plane_state->update_flags.bits.position_change) {
2363                 hubp->funcs->mem_program_viewport(
2364                         hubp,
2365                         &pipe_ctx->plane_res.scl_data.viewport,
2366                         &pipe_ctx->plane_res.scl_data.viewport_c);
2367         }
2368
2369         if (pipe_ctx->stream->cursor_attributes.address.quad_part != 0) {
2370                 dc->hwss.set_cursor_position(pipe_ctx);
2371                 dc->hwss.set_cursor_attribute(pipe_ctx);
2372
2373                 if (dc->hwss.set_cursor_sdr_white_level)
2374                         dc->hwss.set_cursor_sdr_white_level(pipe_ctx);
2375         }
2376
2377         if (plane_state->update_flags.bits.full_update) {
2378                 /*gamut remap*/
2379                 dc->hwss.program_gamut_remap(pipe_ctx);
2380
2381                 dc->hwss.program_output_csc(dc,
2382                                 pipe_ctx,
2383                                 pipe_ctx->stream->output_color_space,
2384                                 pipe_ctx->stream->csc_color_matrix.matrix,
2385                                 pipe_ctx->stream_res.opp->inst);
2386         }
2387
2388         if (plane_state->update_flags.bits.full_update ||
2389                 plane_state->update_flags.bits.pixel_format_change ||
2390                 plane_state->update_flags.bits.horizontal_mirror_change ||
2391                 plane_state->update_flags.bits.rotation_change ||
2392                 plane_state->update_flags.bits.swizzle_change ||
2393                 plane_state->update_flags.bits.dcc_change ||
2394                 plane_state->update_flags.bits.bpp_change ||
2395                 plane_state->update_flags.bits.scaling_change ||
2396                 plane_state->update_flags.bits.plane_size_change) {
2397                 hubp->funcs->hubp_program_surface_config(
2398                         hubp,
2399                         plane_state->format,
2400                         &plane_state->tiling_info,
2401                         &size,
2402                         plane_state->rotation,
2403                         &plane_state->dcc,
2404                         plane_state->horizontal_mirror,
2405                         compat_level);
2406         }
2407
2408         hubp->power_gated = false;
2409
2410         dc->hwss.update_plane_addr(dc, pipe_ctx);
2411
2412         if (is_pipe_tree_visible(pipe_ctx))
2413                 hubp->funcs->set_blank(hubp, false);
2414 }
2415
2416 static void dcn10_blank_pixel_data(
2417                 struct dc *dc,
2418                 struct pipe_ctx *pipe_ctx,
2419                 bool blank)
2420 {
2421         enum dc_color_space color_space;
2422         struct tg_color black_color = {0};
2423         struct stream_resource *stream_res = &pipe_ctx->stream_res;
2424         struct dc_stream_state *stream = pipe_ctx->stream;
2425
2426         /* program otg blank color */
2427         color_space = stream->output_color_space;
2428         color_space_to_black_color(dc, color_space, &black_color);
2429
2430         /*
2431          * The way 420 is packed, 2 channels carry Y component, 1 channel
2432          * alternate between Cb and Cr, so both channels need the pixel
2433          * value for Y
2434          */
2435         if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
2436                 black_color.color_r_cr = black_color.color_g_y;
2437
2438
2439         if (stream_res->tg->funcs->set_blank_color)
2440                 stream_res->tg->funcs->set_blank_color(
2441                                 stream_res->tg,
2442                                 &black_color);
2443
2444         if (!blank) {
2445                 if (stream_res->tg->funcs->set_blank)
2446                         stream_res->tg->funcs->set_blank(stream_res->tg, blank);
2447                 if (stream_res->abm) {
2448                         stream_res->abm->funcs->set_pipe(stream_res->abm, stream_res->tg->inst + 1);
2449                         stream_res->abm->funcs->set_abm_level(stream_res->abm, stream->abm_level);
2450                 }
2451         } else if (blank) {
2452                 if (stream_res->abm)
2453                         stream_res->abm->funcs->set_abm_immediate_disable(stream_res->abm);
2454                 if (stream_res->tg->funcs->set_blank)
2455                         stream_res->tg->funcs->set_blank(stream_res->tg, blank);
2456         }
2457 }
2458
2459 void set_hdr_multiplier(struct pipe_ctx *pipe_ctx)
2460 {
2461         struct fixed31_32 multiplier = dc_fixpt_from_fraction(
2462                         pipe_ctx->plane_state->sdr_white_level, 80);
2463         uint32_t hw_mult = 0x1f000; // 1.0 default multiplier
2464         struct custom_float_format fmt;
2465
2466         fmt.exponenta_bits = 6;
2467         fmt.mantissa_bits = 12;
2468         fmt.sign = true;
2469
2470         if (pipe_ctx->plane_state->sdr_white_level > 80)
2471                 convert_to_custom_float_format(multiplier, &fmt, &hw_mult);
2472
2473         pipe_ctx->plane_res.dpp->funcs->dpp_set_hdr_multiplier(
2474                         pipe_ctx->plane_res.dpp, hw_mult);
2475 }
2476
2477 void dcn10_program_pipe(
2478                 struct dc *dc,
2479                 struct pipe_ctx *pipe_ctx,
2480                 struct dc_state *context)
2481 {
2482         if (pipe_ctx->plane_state->update_flags.bits.full_update)
2483                 dcn10_enable_plane(dc, pipe_ctx, context);
2484
2485         update_dchubp_dpp(dc, pipe_ctx, context);
2486
2487         set_hdr_multiplier(pipe_ctx);
2488
2489         if (pipe_ctx->plane_state->update_flags.bits.full_update ||
2490                         pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
2491                         pipe_ctx->plane_state->update_flags.bits.gamma_change)
2492                 dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state);
2493
2494         /* dcn10_translate_regamma_to_hw_format takes 750us to finish
2495          * only do gamma programming for full update.
2496          * TODO: This can be further optimized/cleaned up
2497          * Always call this for now since it does memcmp inside before
2498          * doing heavy calculation and programming
2499          */
2500         if (pipe_ctx->plane_state->update_flags.bits.full_update)
2501                 dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);
2502 }
2503
2504 static void program_all_pipe_in_tree(
2505                 struct dc *dc,
2506                 struct pipe_ctx *pipe_ctx,
2507                 struct dc_state *context)
2508 {
2509         if (pipe_ctx->top_pipe == NULL) {
2510                 bool blank = !is_pipe_tree_visible(pipe_ctx);
2511
2512                 pipe_ctx->stream_res.tg->funcs->program_global_sync(
2513                                 pipe_ctx->stream_res.tg,
2514                                 pipe_ctx->pipe_dlg_param.vready_offset,
2515                                 pipe_ctx->pipe_dlg_param.vstartup_start,
2516                                 pipe_ctx->pipe_dlg_param.vupdate_offset,
2517                                 pipe_ctx->pipe_dlg_param.vupdate_width);
2518
2519                 pipe_ctx->stream_res.tg->funcs->set_vtg_params(
2520                                 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
2521
2522                 if (dc->hwss.setup_vupdate_interrupt)
2523                         dc->hwss.setup_vupdate_interrupt(pipe_ctx);
2524
2525                 dc->hwss.blank_pixel_data(dc, pipe_ctx, blank);
2526         }
2527
2528         if (pipe_ctx->plane_state != NULL)
2529                 dcn10_program_pipe(dc, pipe_ctx, context);
2530
2531         if (pipe_ctx->bottom_pipe != NULL && pipe_ctx->bottom_pipe != pipe_ctx)
2532                 program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context);
2533 }
2534
2535 struct pipe_ctx *find_top_pipe_for_stream(
2536                 struct dc *dc,
2537                 struct dc_state *context,
2538                 const struct dc_stream_state *stream)
2539 {
2540         int i;
2541
2542         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2543                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2544                 struct pipe_ctx *old_pipe_ctx =
2545                                 &dc->current_state->res_ctx.pipe_ctx[i];
2546
2547                 if (!pipe_ctx->plane_state && !old_pipe_ctx->plane_state)
2548                         continue;
2549
2550                 if (pipe_ctx->stream != stream)
2551                         continue;
2552
2553                 if (!pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe)
2554                         return pipe_ctx;
2555         }
2556         return NULL;
2557 }
2558
2559 static void dcn10_apply_ctx_for_surface(
2560                 struct dc *dc,
2561                 const struct dc_stream_state *stream,
2562                 int num_planes,
2563                 struct dc_state *context)
2564 {
2565         int i;
2566         struct timing_generator *tg;
2567         uint32_t underflow_check_delay_us;
2568         bool removed_pipe[4] = { false };
2569         bool interdependent_update = false;
2570         struct pipe_ctx *top_pipe_to_program =
2571                         find_top_pipe_for_stream(dc, context, stream);
2572         DC_LOGGER_INIT(dc->ctx->logger);
2573
2574         if (!top_pipe_to_program)
2575                 return;
2576
2577         tg = top_pipe_to_program->stream_res.tg;
2578
2579         interdependent_update = top_pipe_to_program->plane_state &&
2580                 top_pipe_to_program->plane_state->update_flags.bits.full_update;
2581
2582         underflow_check_delay_us = dc->debug.underflow_assert_delay_us;
2583
2584         if (underflow_check_delay_us != 0xFFFFFFFF && dc->hwss.did_underflow_occur)
2585                 ASSERT(dc->hwss.did_underflow_occur(dc, top_pipe_to_program));
2586
2587         if (interdependent_update)
2588                 lock_all_pipes(dc, context, true);
2589         else
2590                 dcn10_pipe_control_lock(dc, top_pipe_to_program, true);
2591
2592         if (underflow_check_delay_us != 0xFFFFFFFF)
2593                 udelay(underflow_check_delay_us);
2594
2595         if (underflow_check_delay_us != 0xFFFFFFFF && dc->hwss.did_underflow_occur)
2596                 ASSERT(dc->hwss.did_underflow_occur(dc, top_pipe_to_program));
2597
2598         if (num_planes == 0) {
2599                 /* OTG blank before remove all front end */
2600                 dc->hwss.blank_pixel_data(dc, top_pipe_to_program, true);
2601         }
2602
2603         /* Disconnect unused mpcc */
2604         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2605                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2606                 struct pipe_ctx *old_pipe_ctx =
2607                                 &dc->current_state->res_ctx.pipe_ctx[i];
2608                 /*
2609                  * Powergate reused pipes that are not powergated
2610                  * fairly hacky right now, using opp_id as indicator
2611                  * TODO: After move dc_post to dc_update, this will
2612                  * be removed.
2613                  */
2614                 if (pipe_ctx->plane_state && !old_pipe_ctx->plane_state) {
2615                         if (old_pipe_ctx->stream_res.tg == tg &&
2616                             old_pipe_ctx->plane_res.hubp &&
2617                             old_pipe_ctx->plane_res.hubp->opp_id != OPP_ID_INVALID)
2618                                 dc->hwss.disable_plane(dc, old_pipe_ctx);
2619                 }
2620
2621                 if ((!pipe_ctx->plane_state ||
2622                      pipe_ctx->stream_res.tg != old_pipe_ctx->stream_res.tg) &&
2623                     old_pipe_ctx->plane_state &&
2624                     old_pipe_ctx->stream_res.tg == tg) {
2625
2626                         dc->hwss.plane_atomic_disconnect(dc, old_pipe_ctx);
2627                         removed_pipe[i] = true;
2628
2629                         DC_LOG_DC("Reset mpcc for pipe %d\n",
2630                                         old_pipe_ctx->pipe_idx);
2631                 }
2632         }
2633
2634         if (num_planes > 0)
2635                 program_all_pipe_in_tree(dc, top_pipe_to_program, context);
2636
2637 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
2638         /* Program secondary blending tree and writeback pipes */
2639         if ((stream->num_wb_info > 0) && (dc->hwss.program_all_writeback_pipes_in_tree))
2640                 dc->hwss.program_all_writeback_pipes_in_tree(dc, stream, context);
2641 #endif
2642         if (interdependent_update)
2643                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2644                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2645                         /* Skip inactive pipes and ones already updated */
2646                         if (!pipe_ctx->stream || pipe_ctx->stream == stream ||
2647                             !pipe_ctx->plane_state || !tg->funcs->is_tg_enabled(tg))
2648                                 continue;
2649
2650                         pipe_ctx->plane_res.hubp->funcs->hubp_setup_interdependent(
2651                                 pipe_ctx->plane_res.hubp,
2652                                 &pipe_ctx->dlg_regs,
2653                                 &pipe_ctx->ttu_regs);
2654                 }
2655
2656         if (interdependent_update)
2657                 lock_all_pipes(dc, context, false);
2658         else
2659                 dcn10_pipe_control_lock(dc, top_pipe_to_program, false);
2660
2661         if (num_planes == 0)
2662                 false_optc_underflow_wa(dc, stream, tg);
2663
2664         for (i = 0; i < dc->res_pool->pipe_count; i++)
2665                 if (removed_pipe[i])
2666                         dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
2667
2668         for (i = 0; i < dc->res_pool->pipe_count; i++)
2669                 if (removed_pipe[i]) {
2670                         dc->hwss.optimize_bandwidth(dc, context);
2671                         break;
2672                 }
2673
2674         if (dc->hwseq->wa.DEGVIDCN10_254)
2675                 hubbub1_wm_change_req_wa(dc->res_pool->hubbub);
2676 }
2677
2678 static void dcn10_stereo_hw_frame_pack_wa(struct dc *dc, struct dc_state *context)
2679 {
2680         uint8_t i;
2681
2682         for (i = 0; i < context->stream_count; i++) {
2683                 if (context->streams[i]->timing.timing_3d_format
2684                                 == TIMING_3D_FORMAT_HW_FRAME_PACKING) {
2685                         /*
2686                          * Disable stutter
2687                          */
2688                         hubbub1_allow_self_refresh_control(dc->res_pool->hubbub, false);
2689                         break;
2690                 }
2691         }
2692 }
2693
2694 static void dcn10_prepare_bandwidth(
2695                 struct dc *dc,
2696                 struct dc_state *context)
2697 {
2698         struct hubbub *hubbub = dc->res_pool->hubbub;
2699
2700         if (dc->debug.sanity_checks)
2701                 dcn10_verify_allow_pstate_change_high(dc);
2702
2703         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
2704                 if (context->stream_count == 0)
2705                         context->bw_ctx.bw.dcn.clk.phyclk_khz = 0;
2706
2707                 dc->clk_mgr->funcs->update_clocks(
2708                                 dc->clk_mgr,
2709                                 context,
2710                                 false);
2711         }
2712
2713         hubbub->funcs->program_watermarks(hubbub,
2714                         &context->bw_ctx.bw.dcn.watermarks,
2715                         dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
2716                         true);
2717         dcn10_stereo_hw_frame_pack_wa(dc, context);
2718
2719         if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE)
2720                 dcn_bw_notify_pplib_of_wm_ranges(dc);
2721
2722         if (dc->debug.sanity_checks)
2723                 dcn10_verify_allow_pstate_change_high(dc);
2724 }
2725
2726 static void dcn10_optimize_bandwidth(
2727                 struct dc *dc,
2728                 struct dc_state *context)
2729 {
2730         struct hubbub *hubbub = dc->res_pool->hubbub;
2731
2732         if (dc->debug.sanity_checks)
2733                 dcn10_verify_allow_pstate_change_high(dc);
2734
2735         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
2736                 if (context->stream_count == 0)
2737                         context->bw_ctx.bw.dcn.clk.phyclk_khz = 0;
2738
2739                 dc->clk_mgr->funcs->update_clocks(
2740                                 dc->clk_mgr,
2741                                 context,
2742                                 true);
2743         }
2744
2745         hubbub->funcs->program_watermarks(hubbub,
2746                         &context->bw_ctx.bw.dcn.watermarks,
2747                         dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
2748                         true);
2749         dcn10_stereo_hw_frame_pack_wa(dc, context);
2750
2751         if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE)
2752                 dcn_bw_notify_pplib_of_wm_ranges(dc);
2753
2754         if (dc->debug.sanity_checks)
2755                 dcn10_verify_allow_pstate_change_high(dc);
2756 }
2757
2758 static void dcn10_set_drr(struct pipe_ctx **pipe_ctx,
2759                 int num_pipes, unsigned int vmin, unsigned int vmax,
2760                 unsigned int vmid, unsigned int vmid_frame_number)
2761 {
2762         int i = 0;
2763         struct drr_params params = {0};
2764         // DRR set trigger event mapped to OTG_TRIG_A (bit 11) for manual control flow
2765         unsigned int event_triggers = 0x800;
2766
2767         params.vertical_total_max = vmax;
2768         params.vertical_total_min = vmin;
2769         params.vertical_total_mid = vmid;
2770         params.vertical_total_mid_frame_num = vmid_frame_number;
2771
2772         /* TODO: If multiple pipes are to be supported, you need
2773          * some GSL stuff. Static screen triggers may be programmed differently
2774          * as well.
2775          */
2776         for (i = 0; i < num_pipes; i++) {
2777                 pipe_ctx[i]->stream_res.tg->funcs->set_drr(
2778                         pipe_ctx[i]->stream_res.tg, &params);
2779                 if (vmax != 0 && vmin != 0)
2780                         pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control(
2781                                         pipe_ctx[i]->stream_res.tg,
2782                                         event_triggers);
2783         }
2784 }
2785
2786 static void dcn10_get_position(struct pipe_ctx **pipe_ctx,
2787                 int num_pipes,
2788                 struct crtc_position *position)
2789 {
2790         int i = 0;
2791
2792         /* TODO: handle pipes > 1
2793          */
2794         for (i = 0; i < num_pipes; i++)
2795                 pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);
2796 }
2797
2798 static void dcn10_set_static_screen_control(struct pipe_ctx **pipe_ctx,
2799                 int num_pipes, const struct dc_static_screen_events *events)
2800 {
2801         unsigned int i;
2802         unsigned int value = 0;
2803
2804         if (events->surface_update)
2805                 value |= 0x80;
2806         if (events->cursor_update)
2807                 value |= 0x2;
2808         if (events->force_trigger)
2809                 value |= 0x1;
2810
2811         for (i = 0; i < num_pipes; i++)
2812                 pipe_ctx[i]->stream_res.tg->funcs->
2813                         set_static_screen_control(pipe_ctx[i]->stream_res.tg, value);
2814 }
2815
2816 static void dcn10_config_stereo_parameters(
2817                 struct dc_stream_state *stream, struct crtc_stereo_flags *flags)
2818 {
2819         enum view_3d_format view_format = stream->view_format;
2820         enum dc_timing_3d_format timing_3d_format =\
2821                         stream->timing.timing_3d_format;
2822         bool non_stereo_timing = false;
2823
2824         if (timing_3d_format == TIMING_3D_FORMAT_NONE ||
2825                 timing_3d_format == TIMING_3D_FORMAT_SIDE_BY_SIDE ||
2826                 timing_3d_format == TIMING_3D_FORMAT_TOP_AND_BOTTOM)
2827                 non_stereo_timing = true;
2828
2829         if (non_stereo_timing == false &&
2830                 view_format == VIEW_3D_FORMAT_FRAME_SEQUENTIAL) {
2831
2832                 flags->PROGRAM_STEREO         = 1;
2833                 flags->PROGRAM_POLARITY       = 1;
2834                 if (timing_3d_format == TIMING_3D_FORMAT_INBAND_FA ||
2835                         timing_3d_format == TIMING_3D_FORMAT_DP_HDMI_INBAND_FA ||
2836                         timing_3d_format == TIMING_3D_FORMAT_SIDEBAND_FA) {
2837                         enum display_dongle_type dongle = \
2838                                         stream->link->ddc->dongle_type;
2839                         if (dongle == DISPLAY_DONGLE_DP_VGA_CONVERTER ||
2840                                 dongle == DISPLAY_DONGLE_DP_DVI_CONVERTER ||
2841                                 dongle == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
2842                                 flags->DISABLE_STEREO_DP_SYNC = 1;
2843                 }
2844                 flags->RIGHT_EYE_POLARITY =\
2845                                 stream->timing.flags.RIGHT_EYE_3D_POLARITY;
2846                 if (timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
2847                         flags->FRAME_PACKED = 1;
2848         }
2849
2850         return;
2851 }
2852
2853 static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc)
2854 {
2855         struct crtc_stereo_flags flags = { 0 };
2856         struct dc_stream_state *stream = pipe_ctx->stream;
2857
2858         dcn10_config_stereo_parameters(stream, &flags);
2859
2860         if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_SIDEBAND_FA) {
2861                 if (!dc_set_generic_gpio_for_stereo(true, dc->ctx->gpio_service))
2862                         dc_set_generic_gpio_for_stereo(false, dc->ctx->gpio_service);
2863         } else {
2864                 dc_set_generic_gpio_for_stereo(false, dc->ctx->gpio_service);
2865         }
2866
2867         pipe_ctx->stream_res.opp->funcs->opp_program_stereo(
2868                 pipe_ctx->stream_res.opp,
2869                 flags.PROGRAM_STEREO == 1 ? true:false,
2870                 &stream->timing);
2871
2872         pipe_ctx->stream_res.tg->funcs->program_stereo(
2873                 pipe_ctx->stream_res.tg,
2874                 &stream->timing,
2875                 &flags);
2876
2877         return;
2878 }
2879
2880 static struct hubp *get_hubp_by_inst(struct resource_pool *res_pool, int mpcc_inst)
2881 {
2882         int i;
2883
2884         for (i = 0; i < res_pool->pipe_count; i++) {
2885                 if (res_pool->hubps[i]->inst == mpcc_inst)
2886                         return res_pool->hubps[i];
2887         }
2888         ASSERT(false);
2889         return NULL;
2890 }
2891
2892 static void dcn10_wait_for_mpcc_disconnect(
2893                 struct dc *dc,
2894                 struct resource_pool *res_pool,
2895                 struct pipe_ctx *pipe_ctx)
2896 {
2897         int mpcc_inst;
2898
2899         if (dc->debug.sanity_checks) {
2900                 dcn10_verify_allow_pstate_change_high(dc);
2901         }
2902
2903         if (!pipe_ctx->stream_res.opp)
2904                 return;
2905
2906         for (mpcc_inst = 0; mpcc_inst < MAX_PIPES; mpcc_inst++) {
2907                 if (pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst]) {
2908                         struct hubp *hubp = get_hubp_by_inst(res_pool, mpcc_inst);
2909
2910                         res_pool->mpc->funcs->wait_for_idle(res_pool->mpc, mpcc_inst);
2911                         pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst] = false;
2912                         hubp->funcs->set_blank(hubp, true);
2913                 }
2914         }
2915
2916         if (dc->debug.sanity_checks) {
2917                 dcn10_verify_allow_pstate_change_high(dc);
2918         }
2919
2920 }
2921
2922 static bool dcn10_dummy_display_power_gating(
2923         struct dc *dc,
2924         uint8_t controller_id,
2925         struct dc_bios *dcb,
2926         enum pipe_gating_control power_gating)
2927 {
2928         return true;
2929 }
2930
2931 static void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx)
2932 {
2933         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2934         struct timing_generator *tg = pipe_ctx->stream_res.tg;
2935         bool flip_pending;
2936
2937         if (plane_state == NULL)
2938                 return;
2939
2940         flip_pending = pipe_ctx->plane_res.hubp->funcs->hubp_is_flip_pending(
2941                                         pipe_ctx->plane_res.hubp);
2942
2943         plane_state->status.is_flip_pending = plane_state->status.is_flip_pending || flip_pending;
2944
2945         if (!flip_pending)
2946                 plane_state->status.current_address = plane_state->status.requested_address;
2947
2948         if (plane_state->status.current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2949                         tg->funcs->is_stereo_left_eye) {
2950                 plane_state->status.is_right_eye =
2951                                 !tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);
2952         }
2953 }
2954
2955 static void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data)
2956 {
2957         struct hubbub *hubbub = hws->ctx->dc->res_pool->hubbub;
2958
2959         /* In DCN, this programming sequence is owned by the hubbub */
2960         hubbub->funcs->update_dchub(hubbub, dh_data);
2961 }
2962
2963 static void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)
2964 {
2965         struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;
2966         struct hubp *hubp = pipe_ctx->plane_res.hubp;
2967         struct dpp *dpp = pipe_ctx->plane_res.dpp;
2968         struct dc_cursor_mi_param param = {
2969                 .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10,
2970                 .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz,
2971                 .viewport = pipe_ctx->plane_res.scl_data.viewport,
2972                 .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz,
2973                 .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert,
2974                 .rotation = pipe_ctx->plane_state->rotation,
2975                 .mirror = pipe_ctx->plane_state->horizontal_mirror
2976         };
2977         uint32_t x_plane = pipe_ctx->plane_state->dst_rect.x;
2978         uint32_t y_plane = pipe_ctx->plane_state->dst_rect.y;
2979         uint32_t x_offset = min(x_plane, pos_cpy.x);
2980         uint32_t y_offset = min(y_plane, pos_cpy.y);
2981
2982         pos_cpy.x -= x_offset;
2983         pos_cpy.y -= y_offset;
2984         pos_cpy.x_hotspot += (x_plane - x_offset);
2985         pos_cpy.y_hotspot += (y_plane - y_offset);
2986
2987         if (pipe_ctx->plane_state->address.type
2988                         == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
2989                 pos_cpy.enable = false;
2990
2991         // Swap axis and mirror horizontally
2992         if (param.rotation == ROTATION_ANGLE_90) {
2993                 uint32_t temp_x = pos_cpy.x;
2994                 pos_cpy.x = pipe_ctx->plane_res.scl_data.viewport.width -
2995                                 (pos_cpy.y - pipe_ctx->plane_res.scl_data.viewport.x) + pipe_ctx->plane_res.scl_data.viewport.x;
2996                 pos_cpy.y = temp_x;
2997         }
2998         // Swap axis and mirror vertically
2999         else if (param.rotation == ROTATION_ANGLE_270) {
3000                 uint32_t temp_y = pos_cpy.y;
3001                 if (pos_cpy.x >  pipe_ctx->plane_res.scl_data.viewport.height) {
3002                         pos_cpy.x = pos_cpy.x - pipe_ctx->plane_res.scl_data.viewport.height;
3003                         pos_cpy.y = pipe_ctx->plane_res.scl_data.viewport.height - pos_cpy.x;
3004                 } else {
3005                         pos_cpy.y = 2 * pipe_ctx->plane_res.scl_data.viewport.height - pos_cpy.x;
3006                 }
3007                 pos_cpy.x = temp_y;
3008         }
3009         // Mirror horizontally and vertically
3010         else if (param.rotation == ROTATION_ANGLE_180) {
3011                 if (pos_cpy.x >= pipe_ctx->plane_res.scl_data.viewport.width + pipe_ctx->plane_res.scl_data.viewport.x) {
3012                         pos_cpy.x = 2 * pipe_ctx->plane_res.scl_data.viewport.width
3013                                         - pos_cpy.x + 2 * pipe_ctx->plane_res.scl_data.viewport.x;
3014                 } else {
3015                         uint32_t temp_x = pos_cpy.x;
3016                         pos_cpy.x = 2 * pipe_ctx->plane_res.scl_data.viewport.x - pos_cpy.x;
3017                         if (temp_x >= pipe_ctx->plane_res.scl_data.viewport.x + (int)hubp->curs_attr.width
3018                                         || pos_cpy.x <= (int)hubp->curs_attr.width + pipe_ctx->plane_state->src_rect.x) {
3019                                 pos_cpy.x = temp_x + pipe_ctx->plane_res.scl_data.viewport.width;
3020                         }
3021                 }
3022                 pos_cpy.y = pipe_ctx->plane_res.scl_data.viewport.height - pos_cpy.y;
3023         }
3024
3025         hubp->funcs->set_cursor_position(hubp, &pos_cpy, &param);
3026         dpp->funcs->set_cursor_position(dpp, &pos_cpy, &param, hubp->curs_attr.width, hubp->curs_attr.height);
3027 }
3028
3029 static void dcn10_set_cursor_attribute(struct pipe_ctx *pipe_ctx)
3030 {
3031         struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;
3032
3033         pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes(
3034                         pipe_ctx->plane_res.hubp, attributes);
3035         pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes(
3036                 pipe_ctx->plane_res.dpp, attributes);
3037 }
3038
3039 static void dcn10_set_cursor_sdr_white_level(struct pipe_ctx *pipe_ctx)
3040 {
3041         uint32_t sdr_white_level = pipe_ctx->stream->cursor_attributes.sdr_white_level;
3042         struct fixed31_32 multiplier;
3043         struct dpp_cursor_attributes opt_attr = { 0 };
3044         uint32_t hw_scale = 0x3c00; // 1.0 default multiplier
3045         struct custom_float_format fmt;
3046
3047         if (!pipe_ctx->plane_res.dpp->funcs->set_optional_cursor_attributes)
3048                 return;
3049
3050         fmt.exponenta_bits = 5;
3051         fmt.mantissa_bits = 10;
3052         fmt.sign = true;
3053
3054         if (sdr_white_level > 80) {
3055                 multiplier = dc_fixpt_from_fraction(sdr_white_level, 80);
3056                 convert_to_custom_float_format(multiplier, &fmt, &hw_scale);
3057         }
3058
3059         opt_attr.scale = hw_scale;
3060         opt_attr.bias = 0;
3061
3062         pipe_ctx->plane_res.dpp->funcs->set_optional_cursor_attributes(
3063                         pipe_ctx->plane_res.dpp, &opt_attr);
3064 }
3065
3066 /**
3067 * apply_front_porch_workaround  TODO FPGA still need?
3068 *
3069 * This is a workaround for a bug that has existed since R5xx and has not been
3070 * fixed keep Front porch at minimum 2 for Interlaced mode or 1 for progressive.
3071 */
3072 static void apply_front_porch_workaround(
3073         struct dc_crtc_timing *timing)
3074 {
3075         if (timing->flags.INTERLACE == 1) {
3076                 if (timing->v_front_porch < 2)
3077                         timing->v_front_porch = 2;
3078         } else {
3079                 if (timing->v_front_porch < 1)
3080                         timing->v_front_porch = 1;
3081         }
3082 }
3083
3084 int get_vupdate_offset_from_vsync(struct pipe_ctx *pipe_ctx)
3085 {
3086         const struct dc_crtc_timing *dc_crtc_timing = &pipe_ctx->stream->timing;
3087         struct dc_crtc_timing patched_crtc_timing;
3088         int vesa_sync_start;
3089         int asic_blank_end;
3090         int interlace_factor;
3091         int vertical_line_start;
3092
3093         patched_crtc_timing = *dc_crtc_timing;
3094         apply_front_porch_workaround(&patched_crtc_timing);
3095
3096         interlace_factor = patched_crtc_timing.flags.INTERLACE ? 2 : 1;
3097
3098         vesa_sync_start = patched_crtc_timing.v_addressable +
3099                         patched_crtc_timing.v_border_bottom +
3100                         patched_crtc_timing.v_front_porch;
3101
3102         asic_blank_end = (patched_crtc_timing.v_total -
3103                         vesa_sync_start -
3104                         patched_crtc_timing.v_border_top)
3105                         * interlace_factor;
3106
3107         vertical_line_start = asic_blank_end -
3108                         pipe_ctx->pipe_dlg_param.vstartup_start + 1;
3109
3110         return vertical_line_start;
3111 }
3112
3113 void lock_all_pipes(struct dc *dc,
3114         struct dc_state *context,
3115         bool lock)
3116 {
3117         struct pipe_ctx *pipe_ctx;
3118         struct timing_generator *tg;
3119         int i;
3120
3121         for (i = 0; i < dc->res_pool->pipe_count; i++) {
3122                 pipe_ctx = &context->res_ctx.pipe_ctx[i];
3123                 tg = pipe_ctx->stream_res.tg;
3124                 /*
3125                  * Only lock the top pipe's tg to prevent redundant
3126                  * (un)locking. Also skip if pipe is disabled.
3127                  */
3128                 if (pipe_ctx->top_pipe ||
3129                     !pipe_ctx->stream || !pipe_ctx->plane_state ||
3130                     !tg->funcs->is_tg_enabled(tg))
3131                         continue;
3132
3133                 if (lock)
3134                         tg->funcs->lock(tg);
3135                 else
3136                         tg->funcs->unlock(tg);
3137         }
3138 }
3139
3140 static void calc_vupdate_position(
3141                 struct pipe_ctx *pipe_ctx,
3142                 uint32_t *start_line,
3143                 uint32_t *end_line)
3144 {
3145         const struct dc_crtc_timing *dc_crtc_timing = &pipe_ctx->stream->timing;
3146         int vline_int_offset_from_vupdate =
3147                         pipe_ctx->stream->periodic_interrupt0.lines_offset;
3148         int vupdate_offset_from_vsync = get_vupdate_offset_from_vsync(pipe_ctx);
3149         int start_position;
3150
3151         if (vline_int_offset_from_vupdate > 0)
3152                 vline_int_offset_from_vupdate--;
3153         else if (vline_int_offset_from_vupdate < 0)
3154                 vline_int_offset_from_vupdate++;
3155
3156         start_position = vline_int_offset_from_vupdate + vupdate_offset_from_vsync;
3157
3158         if (start_position >= 0)
3159                 *start_line = start_position;
3160         else
3161                 *start_line = dc_crtc_timing->v_total + start_position - 1;
3162
3163         *end_line = *start_line + 2;
3164
3165         if (*end_line >= dc_crtc_timing->v_total)
3166                 *end_line = 2;
3167 }
3168
3169 static void cal_vline_position(
3170                 struct pipe_ctx *pipe_ctx,
3171                 enum vline_select vline,
3172                 uint32_t *start_line,
3173                 uint32_t *end_line)
3174 {
3175         enum vertical_interrupt_ref_point ref_point = INVALID_POINT;
3176
3177         if (vline == VLINE0)
3178                 ref_point = pipe_ctx->stream->periodic_interrupt0.ref_point;
3179         else if (vline == VLINE1)
3180                 ref_point = pipe_ctx->stream->periodic_interrupt1.ref_point;
3181
3182         switch (ref_point) {
3183         case START_V_UPDATE:
3184                 calc_vupdate_position(
3185                                 pipe_ctx,
3186                                 start_line,
3187                                 end_line);
3188                 break;
3189         case START_V_SYNC:
3190                 // Suppose to do nothing because vsync is 0;
3191                 break;
3192         default:
3193                 ASSERT(0);
3194                 break;
3195         }
3196 }
3197
3198 static void dcn10_setup_periodic_interrupt(
3199                 struct pipe_ctx *pipe_ctx,
3200                 enum vline_select vline)
3201 {
3202         struct timing_generator *tg = pipe_ctx->stream_res.tg;
3203
3204         if (vline == VLINE0) {
3205                 uint32_t start_line = 0;
3206                 uint32_t end_line = 0;
3207
3208                 cal_vline_position(pipe_ctx, vline, &start_line, &end_line);
3209
3210                 tg->funcs->setup_vertical_interrupt0(tg, start_line, end_line);
3211
3212         } else if (vline == VLINE1) {
3213                 pipe_ctx->stream_res.tg->funcs->setup_vertical_interrupt1(
3214                                 tg,
3215                                 pipe_ctx->stream->periodic_interrupt1.lines_offset);
3216         }
3217 }
3218
3219 static void dcn10_setup_vupdate_interrupt(struct pipe_ctx *pipe_ctx)
3220 {
3221         struct timing_generator *tg = pipe_ctx->stream_res.tg;
3222         int start_line = get_vupdate_offset_from_vsync(pipe_ctx);
3223
3224         if (start_line < 0) {
3225                 ASSERT(0);
3226                 start_line = 0;
3227         }
3228
3229         if (tg->funcs->setup_vertical_interrupt2)
3230                 tg->funcs->setup_vertical_interrupt2(tg, start_line);
3231 }
3232
3233 static void dcn10_unblank_stream(struct pipe_ctx *pipe_ctx,
3234                 struct dc_link_settings *link_settings)
3235 {
3236         struct encoder_unblank_param params = { { 0 } };
3237         struct dc_stream_state *stream = pipe_ctx->stream;
3238         struct dc_link *link = stream->link;
3239
3240         /* only 3 items below are used by unblank */
3241         params.timing = pipe_ctx->stream->timing;
3242
3243         params.link_settings.link_rate = link_settings->link_rate;
3244
3245         if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
3246                 if (params.timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
3247                         params.timing.pix_clk_100hz /= 2;
3248                 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, &params);
3249         }
3250
3251         if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
3252                 link->dc->hwss.edp_backlight_control(link, true);
3253         }
3254 }
3255
3256 static void dcn10_send_immediate_sdp_message(struct pipe_ctx *pipe_ctx,
3257                                 const uint8_t *custom_sdp_message,
3258                                 unsigned int sdp_message_size)
3259 {
3260         if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
3261                 pipe_ctx->stream_res.stream_enc->funcs->send_immediate_sdp_message(
3262                                 pipe_ctx->stream_res.stream_enc,
3263                                 custom_sdp_message,
3264                                 sdp_message_size);
3265         }
3266 }
3267 static enum dc_status dcn10_set_clock(struct dc *dc,
3268                         enum dc_clock_type clock_type,
3269                         uint32_t clk_khz,
3270                         uint32_t stepping)
3271 {
3272         struct dc_state *context = dc->current_state;
3273         struct dc_clock_config clock_cfg = {0};
3274         struct dc_clocks *current_clocks = &context->bw_ctx.bw.dcn.clk;
3275
3276         if (dc->clk_mgr && dc->clk_mgr->funcs->get_clock)
3277                                 dc->clk_mgr->funcs->get_clock(dc->clk_mgr,
3278                                                 context, clock_type, &clock_cfg);
3279
3280         if (!dc->clk_mgr->funcs->get_clock)
3281                 return DC_FAIL_UNSUPPORTED_1;
3282
3283         if (clk_khz > clock_cfg.max_clock_khz)
3284                 return DC_FAIL_CLK_EXCEED_MAX;
3285
3286         if (clk_khz < clock_cfg.min_clock_khz)
3287                 return DC_FAIL_CLK_BELOW_MIN;
3288
3289         if (clk_khz < clock_cfg.bw_requirequired_clock_khz)
3290                 return DC_FAIL_CLK_BELOW_CFG_REQUIRED;
3291
3292         /*update internal request clock for update clock use*/
3293         if (clock_type == DC_CLOCK_TYPE_DISPCLK)
3294                 current_clocks->dispclk_khz = clk_khz;
3295         else if (clock_type == DC_CLOCK_TYPE_DPPCLK)
3296                 current_clocks->dppclk_khz = clk_khz;
3297         else
3298                 return DC_ERROR_UNEXPECTED;
3299
3300         if (dc->clk_mgr && dc->clk_mgr->funcs->update_clocks)
3301                                 dc->clk_mgr->funcs->update_clocks(dc->clk_mgr,
3302                                 context, true);
3303         return DC_OK;
3304
3305 }
3306
3307 static void dcn10_get_clock(struct dc *dc,
3308                         enum dc_clock_type clock_type,
3309                         struct dc_clock_config *clock_cfg)
3310 {
3311         struct dc_state *context = dc->current_state;
3312
3313         if (dc->clk_mgr && dc->clk_mgr->funcs->get_clock)
3314                                 dc->clk_mgr->funcs->get_clock(dc->clk_mgr, context, clock_type, clock_cfg);
3315
3316 }
3317
3318 static const struct hw_sequencer_funcs dcn10_funcs = {
3319         .program_gamut_remap = dcn10_program_gamut_remap,
3320         .init_hw = dcn10_init_hw,
3321         .init_pipes = dcn10_init_pipes,
3322         .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
3323         .apply_ctx_for_surface = dcn10_apply_ctx_for_surface,
3324         .update_plane_addr = dcn10_update_plane_addr,
3325         .plane_atomic_disconnect = hwss1_plane_atomic_disconnect,
3326         .update_dchub = dcn10_update_dchub,
3327         .update_mpcc = dcn10_update_mpcc,
3328         .update_pending_status = dcn10_update_pending_status,
3329         .set_input_transfer_func = dcn10_set_input_transfer_func,
3330         .set_output_transfer_func = dcn10_set_output_transfer_func,
3331         .program_output_csc = dcn10_program_output_csc,
3332         .power_down = dce110_power_down,
3333         .enable_accelerated_mode = dce110_enable_accelerated_mode,
3334         .enable_timing_synchronization = dcn10_enable_timing_synchronization,
3335         .enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,
3336         .update_info_frame = dce110_update_info_frame,
3337         .send_immediate_sdp_message = dcn10_send_immediate_sdp_message,
3338         .enable_stream = dce110_enable_stream,
3339         .disable_stream = dce110_disable_stream,
3340         .unblank_stream = dcn10_unblank_stream,
3341         .blank_stream = dce110_blank_stream,
3342         .enable_audio_stream = dce110_enable_audio_stream,
3343         .disable_audio_stream = dce110_disable_audio_stream,
3344         .enable_display_power_gating = dcn10_dummy_display_power_gating,
3345         .disable_plane = dcn10_disable_plane,
3346         .blank_pixel_data = dcn10_blank_pixel_data,
3347         .pipe_control_lock = dcn10_pipe_control_lock,
3348         .prepare_bandwidth = dcn10_prepare_bandwidth,
3349         .optimize_bandwidth = dcn10_optimize_bandwidth,
3350         .reset_hw_ctx_wrap = dcn10_reset_hw_ctx_wrap,
3351         .enable_stream_timing = dcn10_enable_stream_timing,
3352         .set_drr = dcn10_set_drr,
3353         .get_position = dcn10_get_position,
3354         .set_static_screen_control = dcn10_set_static_screen_control,
3355         .setup_stereo = dcn10_setup_stereo,
3356         .set_avmute = dce110_set_avmute,
3357         .log_hw_state = dcn10_log_hw_state,
3358         .get_hw_state = dcn10_get_hw_state,
3359         .clear_status_bits = dcn10_clear_status_bits,
3360         .wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
3361         .edp_backlight_control = dce110_edp_backlight_control,
3362         .edp_power_control = dce110_edp_power_control,
3363         .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
3364         .set_cursor_position = dcn10_set_cursor_position,
3365         .set_cursor_attribute = dcn10_set_cursor_attribute,
3366         .set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,
3367         .disable_stream_gating = NULL,
3368         .enable_stream_gating = NULL,
3369         .setup_periodic_interrupt = dcn10_setup_periodic_interrupt,
3370         .setup_vupdate_interrupt = dcn10_setup_vupdate_interrupt,
3371         .set_clock = dcn10_set_clock,
3372         .get_clock = dcn10_get_clock,
3373         .did_underflow_occur = dcn10_did_underflow_occur,
3374         .init_blank = NULL,
3375         .disable_vga = dcn10_disable_vga,
3376         .bios_golden_init = dcn10_bios_golden_init,
3377         .plane_atomic_disable = dcn10_plane_atomic_disable,
3378         .plane_atomic_power_down = dcn10_plane_atomic_power_down,
3379         .enable_power_gating_plane = dcn10_enable_power_gating_plane,
3380         .dpp_pg_control = dcn10_dpp_pg_control,
3381         .hubp_pg_control = dcn10_hubp_pg_control,
3382         .dsc_pg_control = NULL,
3383 };
3384
3385
3386 void dcn10_hw_sequencer_construct(struct dc *dc)
3387 {
3388         dc->hwss = dcn10_funcs;
3389 }
3390