2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include "dm_services.h"
27 #include "core_types.h"
29 #include "custom_float.h"
30 #include "dcn10_hw_sequencer.h"
31 #include "dce110/dce110_hw_sequencer.h"
32 #include "dce/dce_hwseq.h"
35 #include "dcn10_optc.h"
36 #include "dcn10/dcn10_dpp.h"
37 #include "dcn10/dcn10_mpc.h"
38 #include "timing_generator.h"
42 #include "reg_helper.h"
43 #include "custom_float.h"
44 #include "dcn10_hubp.h"
45 #include "dcn10_hubbub.h"
46 #include "dcn10_cm_common.h"
54 #define FN(reg_name, field_name) \
55 hws->shifts->field_name, hws->masks->field_name
57 #define DTN_INFO_MICRO_SEC(ref_cycle) \
58 print_microsec(dc_ctx, ref_cycle)
60 void print_microsec(struct dc_context *dc_ctx, uint32_t ref_cycle)
62 static const uint32_t ref_clk_mhz = 48;
63 static const unsigned int frac = 10;
64 uint32_t us_x10 = (ref_cycle * frac) / ref_clk_mhz;
72 static void log_mpc_crc(struct dc *dc)
74 struct dc_context *dc_ctx = dc->ctx;
75 struct dce_hwseq *hws = dc->hwseq;
77 if (REG(MPC_CRC_RESULT_GB))
78 DTN_INFO("MPC_CRC_RESULT_GB:%d MPC_CRC_RESULT_C:%d MPC_CRC_RESULT_AR:%d\n",
79 REG_READ(MPC_CRC_RESULT_GB), REG_READ(MPC_CRC_RESULT_C), REG_READ(MPC_CRC_RESULT_AR));
80 if (REG(DPP_TOP0_DPP_CRC_VAL_B_A))
81 DTN_INFO("DPP_TOP0_DPP_CRC_VAL_B_A:%d DPP_TOP0_DPP_CRC_VAL_R_G:%d\n",
82 REG_READ(DPP_TOP0_DPP_CRC_VAL_B_A), REG_READ(DPP_TOP0_DPP_CRC_VAL_R_G));
85 void dcn10_log_hubbub_state(struct dc *dc)
87 struct dc_context *dc_ctx = dc->ctx;
88 struct dcn_hubbub_wm wm;
91 hubbub1_wm_read_state(dc->res_pool->hubbub, &wm);
93 DTN_INFO("HUBBUB WM: \t data_urgent \t pte_meta_urgent \t "
94 "sr_enter \t sr_exit \t dram_clk_change \n");
96 for (i = 0; i < 4; i++) {
97 struct dcn_hubbub_wm_set *s;
100 DTN_INFO("WM_Set[%d]:\t ", s->wm_set);
101 DTN_INFO_MICRO_SEC(s->data_urgent);
102 DTN_INFO_MICRO_SEC(s->pte_meta_urgent);
103 DTN_INFO_MICRO_SEC(s->sr_enter);
104 DTN_INFO_MICRO_SEC(s->sr_exit);
105 DTN_INFO_MICRO_SEC(s->dram_clk_chanage);
112 void dcn10_log_hw_state(struct dc *dc)
114 struct dc_context *dc_ctx = dc->ctx;
115 struct resource_pool *pool = dc->res_pool;
120 dcn10_log_hubbub_state(dc);
122 DTN_INFO("HUBP:\t format \t addr_hi \t width \t height \t "
123 "rotation \t mirror \t sw_mode \t "
124 "dcc_en \t blank_en \t ttu_dis \t underflow \t "
125 "min_ttu_vblank \t qos_low_wm \t qos_high_wm \n");
127 for (i = 0; i < pool->pipe_count; i++) {
128 struct hubp *hubp = pool->hubps[i];
129 struct dcn_hubp_state s;
131 hubp1_read_state(TO_DCN10_HUBP(hubp), &s);
133 DTN_INFO("[%d]:\t %xh \t %xh \t %d \t %d \t "
134 "%xh \t %xh \t %xh \t "
135 "%d \t %d \t %d \t %xh \t",
148 DTN_INFO_MICRO_SEC(s.min_ttu_vblank);
149 DTN_INFO_MICRO_SEC(s.qos_level_low_wm);
150 DTN_INFO_MICRO_SEC(s.qos_level_high_wm);
155 DTN_INFO("OTG:\t v_bs \t v_be \t v_ss \t v_se \t vpol \t vmax \t vmin \t "
156 "h_bs \t h_be \t h_ss \t h_se \t hpol \t htot \t vtot \t underflow\n");
158 for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
159 struct timing_generator *tg = pool->timing_generators[i];
160 struct dcn_otg_state s = {0};
162 optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s);
164 //only print if OTG master is enabled
165 if ((s.otg_enabled & 1) == 0)
168 DTN_INFO("[%d]:\t %d \t %d \t %d \t %d \t "
169 "%d \t %d \t %d \t %d \t %d \t %d \t "
170 "%d \t %d \t %d \t %d \t %d \t ",
186 s.underflow_occurred_status);
196 static void enable_dppclk(
197 struct dce_hwseq *hws,
199 uint32_t requested_pix_clk,
202 dm_logger_write(hws->ctx->logger, LOG_SURFACE,
203 "dppclk_rate_control for pipe %d programed to %d\n",
207 if (hws->shifts->DPPCLK_RATE_CONTROL)
208 REG_UPDATE_2(DPP_CONTROL[plane_id],
209 DPPCLK_RATE_CONTROL, dppclk_div,
210 DPP_CLOCK_ENABLE, 1);
212 REG_UPDATE(DPP_CONTROL[plane_id],
213 DPP_CLOCK_ENABLE, 1);
216 static void enable_power_gating_plane(
217 struct dce_hwseq *hws,
220 bool force_on = 1; /* disable power gating */
226 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on);
227 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on);
228 REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on);
229 REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on);
232 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on);
233 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on);
234 REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on);
235 REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);
238 static void disable_vga(
239 struct dce_hwseq *hws)
241 REG_WRITE(D1VGA_CONTROL, 0);
242 REG_WRITE(D2VGA_CONTROL, 0);
243 REG_WRITE(D3VGA_CONTROL, 0);
244 REG_WRITE(D4VGA_CONTROL, 0);
247 static void dpp_pg_control(
248 struct dce_hwseq *hws,
249 unsigned int dpp_inst,
252 uint32_t power_gate = power_on ? 0 : 1;
253 uint32_t pwr_status = power_on ? 0 : 2;
255 if (hws->ctx->dc->debug.disable_dpp_power_gate)
260 REG_UPDATE(DOMAIN1_PG_CONFIG,
261 DOMAIN1_POWER_GATE, power_gate);
263 REG_WAIT(DOMAIN1_PG_STATUS,
264 DOMAIN1_PGFSM_PWR_STATUS, pwr_status,
268 REG_UPDATE(DOMAIN3_PG_CONFIG,
269 DOMAIN3_POWER_GATE, power_gate);
271 REG_WAIT(DOMAIN3_PG_STATUS,
272 DOMAIN3_PGFSM_PWR_STATUS, pwr_status,
276 REG_UPDATE(DOMAIN5_PG_CONFIG,
277 DOMAIN5_POWER_GATE, power_gate);
279 REG_WAIT(DOMAIN5_PG_STATUS,
280 DOMAIN5_PGFSM_PWR_STATUS, pwr_status,
284 REG_UPDATE(DOMAIN7_PG_CONFIG,
285 DOMAIN7_POWER_GATE, power_gate);
287 REG_WAIT(DOMAIN7_PG_STATUS,
288 DOMAIN7_PGFSM_PWR_STATUS, pwr_status,
297 static void hubp_pg_control(
298 struct dce_hwseq *hws,
299 unsigned int hubp_inst,
302 uint32_t power_gate = power_on ? 0 : 1;
303 uint32_t pwr_status = power_on ? 0 : 2;
305 if (hws->ctx->dc->debug.disable_hubp_power_gate)
309 case 0: /* DCHUBP0 */
310 REG_UPDATE(DOMAIN0_PG_CONFIG,
311 DOMAIN0_POWER_GATE, power_gate);
313 REG_WAIT(DOMAIN0_PG_STATUS,
314 DOMAIN0_PGFSM_PWR_STATUS, pwr_status,
317 case 1: /* DCHUBP1 */
318 REG_UPDATE(DOMAIN2_PG_CONFIG,
319 DOMAIN2_POWER_GATE, power_gate);
321 REG_WAIT(DOMAIN2_PG_STATUS,
322 DOMAIN2_PGFSM_PWR_STATUS, pwr_status,
325 case 2: /* DCHUBP2 */
326 REG_UPDATE(DOMAIN4_PG_CONFIG,
327 DOMAIN4_POWER_GATE, power_gate);
329 REG_WAIT(DOMAIN4_PG_STATUS,
330 DOMAIN4_PGFSM_PWR_STATUS, pwr_status,
333 case 3: /* DCHUBP3 */
334 REG_UPDATE(DOMAIN6_PG_CONFIG,
335 DOMAIN6_POWER_GATE, power_gate);
337 REG_WAIT(DOMAIN6_PG_STATUS,
338 DOMAIN6_PGFSM_PWR_STATUS, pwr_status,
347 static void power_on_plane(
348 struct dce_hwseq *hws,
351 if (REG(DC_IP_REQUEST_CNTL)) {
352 REG_SET(DC_IP_REQUEST_CNTL, 0,
354 dpp_pg_control(hws, plane_id, true);
355 hubp_pg_control(hws, plane_id, true);
356 REG_SET(DC_IP_REQUEST_CNTL, 0,
358 dm_logger_write(hws->ctx->logger, LOG_DEBUG,
359 "Un-gated front end for pipe %d\n", plane_id);
363 static void undo_DEGVIDCN10_253_wa(struct dc *dc)
365 struct dce_hwseq *hws = dc->hwseq;
366 struct hubp *hubp = dc->res_pool->hubps[0];
368 if (!hws->wa_state.DEGVIDCN10_253_applied)
371 hubp->funcs->set_blank(hubp, true);
373 REG_SET(DC_IP_REQUEST_CNTL, 0,
376 hubp_pg_control(hws, 0, false);
377 REG_SET(DC_IP_REQUEST_CNTL, 0,
380 hws->wa_state.DEGVIDCN10_253_applied = false;
383 static void apply_DEGVIDCN10_253_wa(struct dc *dc)
385 struct dce_hwseq *hws = dc->hwseq;
386 struct hubp *hubp = dc->res_pool->hubps[0];
389 if (dc->debug.disable_stutter)
392 if (!hws->wa.DEGVIDCN10_253)
395 for (i = 0; i < dc->res_pool->pipe_count; i++) {
396 if (!dc->res_pool->hubps[i]->power_gated)
400 /* all pipe power gated, apply work around to enable stutter. */
402 REG_SET(DC_IP_REQUEST_CNTL, 0,
405 hubp_pg_control(hws, 0, true);
406 REG_SET(DC_IP_REQUEST_CNTL, 0,
409 hubp->funcs->set_hubp_blank_en(hubp, false);
410 hws->wa_state.DEGVIDCN10_253_applied = true;
413 static void bios_golden_init(struct dc *dc)
415 struct dc_bios *bp = dc->ctx->dc_bios;
418 /* initialize dcn global */
419 bp->funcs->enable_disp_power_gating(bp,
420 CONTROLLER_ID_D0, ASIC_PIPE_INIT);
422 for (i = 0; i < dc->res_pool->pipe_count; i++) {
423 /* initialize dcn per pipe */
424 bp->funcs->enable_disp_power_gating(bp,
425 CONTROLLER_ID_D0 + i, ASIC_PIPE_DISABLE);
429 static void false_optc_underflow_wa(
431 const struct dc_stream_state *stream,
432 struct timing_generator *tg)
437 if (!dc->hwseq->wa.false_optc_underflow)
440 underflow = tg->funcs->is_optc_underflow_occurred(tg);
442 for (i = 0; i < dc->res_pool->pipe_count; i++) {
443 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
445 if (old_pipe_ctx->stream != stream)
448 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, old_pipe_ctx);
451 tg->funcs->set_blank_data_double_buffer(tg, true);
453 if (tg->funcs->is_optc_underflow_occurred(tg) && !underflow)
454 tg->funcs->clear_optc_underflow(tg);
457 static enum dc_status dcn10_prog_pixclk_crtc_otg(
458 struct pipe_ctx *pipe_ctx,
459 struct dc_state *context,
462 struct dc_stream_state *stream = pipe_ctx->stream;
463 enum dc_color_space color_space;
464 struct tg_color black_color = {0};
466 /* by upper caller loop, pipe0 is parent pipe and be called first.
467 * back end is set up by for pipe0. Other children pipe share back end
468 * with pipe 0. No program is needed.
470 if (pipe_ctx->top_pipe != NULL)
473 /* TODO check if timing_changed, disable stream if timing changed */
475 /* HW program guide assume display already disable
476 * by unplug sequence. OTG assume stop.
478 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true);
480 if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
481 pipe_ctx->clock_source,
482 &pipe_ctx->stream_res.pix_clk_params,
483 &pipe_ctx->pll_settings)) {
485 return DC_ERROR_UNEXPECTED;
487 pipe_ctx->stream_res.tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset;
488 pipe_ctx->stream_res.tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start;
489 pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset;
490 pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_width = pipe_ctx->pipe_dlg_param.vupdate_width;
492 pipe_ctx->stream_res.tg->dlg_otg_param.signal = pipe_ctx->stream->signal;
494 pipe_ctx->stream_res.tg->funcs->program_timing(
495 pipe_ctx->stream_res.tg,
499 #if 0 /* move to after enable_crtc */
500 /* TODO: OPP FMT, ABM. etc. should be done here. */
501 /* or FPGA now. instance 0 only. TODO: move to opp.c */
503 inst_offset = reg_offsets[pipe_ctx->stream_res.tg->inst].fmt;
505 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
506 pipe_ctx->stream_res.opp,
507 &stream->bit_depth_params,
510 /* program otg blank color */
511 color_space = stream->output_color_space;
512 color_space_to_black_color(dc, color_space, &black_color);
514 if (pipe_ctx->stream_res.tg->funcs->set_blank_color)
515 pipe_ctx->stream_res.tg->funcs->set_blank_color(
516 pipe_ctx->stream_res.tg,
519 if (pipe_ctx->stream_res.tg->funcs->is_blanked &&
520 !pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg)) {
521 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);
522 hwss_wait_for_blank_complete(pipe_ctx->stream_res.tg);
523 false_optc_underflow_wa(dc, pipe_ctx->stream, pipe_ctx->stream_res.tg);
526 /* VTG is within DCHUB command block. DCFCLK is always on */
527 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {
529 return DC_ERROR_UNEXPECTED;
532 /* TODO program crtc source select for non-virtual signal*/
533 /* TODO program FMT */
534 /* TODO setup link_enc */
535 /* TODO set stream attributes */
536 /* TODO program audio */
537 /* TODO enable stream if timing changed */
538 /* TODO unblank stream if DP */
543 static void reset_back_end_for_pipe(
545 struct pipe_ctx *pipe_ctx,
546 struct dc_state *context)
550 if (pipe_ctx->stream_res.stream_enc == NULL) {
551 pipe_ctx->stream = NULL;
555 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
556 /* DPMS may already disable */
557 if (!pipe_ctx->stream->dpms_off)
558 core_link_disable_stream(pipe_ctx, FREE_ACQUIRED_RESOURCE);
561 /* by upper caller loop, parent pipe: pipe0, will be reset last.
562 * back end share by all pipes and will be disable only when disable
565 if (pipe_ctx->top_pipe == NULL) {
566 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
568 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
571 for (i = 0; i < dc->res_pool->pipe_count; i++)
572 if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx)
575 if (i == dc->res_pool->pipe_count)
578 pipe_ctx->stream = NULL;
579 dm_logger_write(dc->ctx->logger, LOG_DEBUG,
580 "Reset back end for pipe %d, tg:%d\n",
581 pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
584 static void dcn10_verify_allow_pstate_change_high(struct dc *dc)
586 static bool should_log_hw_state; /* prevent hw state log by default */
588 if (!hubbub1_verify_allow_pstate_change_high(dc->res_pool->hubbub)) {
589 if (should_log_hw_state) {
590 dcn10_log_hw_state(dc);
597 /* trigger HW to start disconnect plane from stream on the next vsync */
598 static void plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx)
600 int fe_idx = pipe_ctx->pipe_idx;
601 struct hubp *hubp = dc->res_pool->hubps[fe_idx];
602 struct mpc *mpc = dc->res_pool->mpc;
604 struct mpc_tree *mpc_tree_params;
605 struct mpcc *mpcc_to_remove = NULL;
607 /* look at tree rather than mi here to know if we already reset */
608 for (opp_id = 0; opp_id < dc->res_pool->pipe_count; opp_id++) {
609 struct output_pixel_processor *opp = dc->res_pool->opps[opp_id];
611 mpc_tree_params = &(opp->mpc_tree_params);
612 mpcc_to_remove = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, fe_idx);
613 if (mpcc_to_remove != NULL)
618 if (opp_id == dc->res_pool->pipe_count)
621 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, mpcc_to_remove);
622 dc->res_pool->opps[opp_id]->mpcc_disconnect_pending[fe_idx] = true;
624 dc->optimized_required = true;
626 if (hubp->funcs->hubp_disconnect)
627 hubp->funcs->hubp_disconnect(hubp);
629 if (dc->debug.sanity_checks)
630 dcn10_verify_allow_pstate_change_high(dc);
633 static void plane_atomic_power_down(struct dc *dc, int fe_idx)
635 struct dce_hwseq *hws = dc->hwseq;
636 struct dpp *dpp = dc->res_pool->dpps[fe_idx];
638 if (REG(DC_IP_REQUEST_CNTL)) {
639 REG_SET(DC_IP_REQUEST_CNTL, 0,
641 dpp_pg_control(hws, fe_idx, false);
642 hubp_pg_control(hws, fe_idx, false);
643 dpp->funcs->dpp_reset(dpp);
644 REG_SET(DC_IP_REQUEST_CNTL, 0,
646 dm_logger_write(dc->ctx->logger, LOG_DEBUG,
647 "Power gated front end %d\n", fe_idx);
651 /* disable HW used by plane.
652 * note: cannot disable until disconnect is complete
654 static void plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
656 int fe_idx = pipe_ctx->pipe_idx;
657 struct dce_hwseq *hws = dc->hwseq;
658 struct hubp *hubp = dc->res_pool->hubps[fe_idx];
659 int opp_id = hubp->opp_id;
661 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);
663 REG_UPDATE(HUBP_CLK_CNTL[fe_idx],
664 HUBP_CLOCK_ENABLE, 0);
665 REG_UPDATE(DPP_CONTROL[fe_idx],
666 DPP_CLOCK_ENABLE, 0);
668 if (opp_id != 0xf && dc->res_pool->opps[opp_id]->mpc_tree_params.opp_list == NULL)
669 REG_UPDATE(OPP_PIPE_CONTROL[opp_id],
670 OPP_PIPE_CLOCK_EN, 0);
672 hubp->power_gated = true;
673 dc->optimized_required = false; /* We're powering off, no need to optimize */
675 plane_atomic_power_down(dc, fe_idx);
677 pipe_ctx->stream = NULL;
678 memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res));
679 memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res));
680 pipe_ctx->top_pipe = NULL;
681 pipe_ctx->bottom_pipe = NULL;
682 pipe_ctx->plane_state = NULL;
685 static void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
687 if (dc->res_pool->hubps[pipe_ctx->pipe_idx]->power_gated)
690 plane_atomic_disable(dc, pipe_ctx);
692 apply_DEGVIDCN10_253_wa(dc);
694 dm_logger_write(dc->ctx->logger, LOG_DC,
695 "Power down front end %d\n",
699 static void dcn10_init_hw(struct dc *dc)
702 struct abm *abm = dc->res_pool->abm;
703 struct dmcu *dmcu = dc->res_pool->dmcu;
704 struct dce_hwseq *hws = dc->hwseq;
705 struct dc_bios *dcb = dc->ctx->dc_bios;
706 struct dc_state *context = dc->current_state;
708 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
709 REG_WRITE(REFCLK_CNTL, 0);
710 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
711 REG_WRITE(DIO_MEM_PWR_CTRL, 0);
713 if (!dc->debug.disable_clock_gate) {
714 /* enable all DCN clock gating */
715 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
717 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
719 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
722 enable_power_gating_plane(dc->hwseq, true);
725 /* end of FPGA. Below if real ASIC */
727 if (!dcb->funcs->is_accelerated_mode(dcb)) {
728 bios_golden_init(dc);
729 disable_vga(dc->hwseq);
732 for (i = 0; i < dc->link_count; i++) {
733 /* Power up AND update implementation according to the
734 * required signal (which may be different from the
735 * default signal on connector).
737 struct dc_link *link = dc->links[i];
739 if (link->link_enc->connector.id == CONNECTOR_ID_EDP)
740 dc->hwss.edp_power_control(link, true);
742 link->link_enc->funcs->hw_init(link->link_enc);
745 for (i = 0; i < dc->res_pool->pipe_count; i++) {
746 struct timing_generator *tg = dc->res_pool->timing_generators[i];
748 if (tg->funcs->is_tg_enabled(tg))
752 /* Blank controller using driver code instead of
755 for (i = 0; i < dc->res_pool->pipe_count; i++) {
756 struct timing_generator *tg = dc->res_pool->timing_generators[i];
758 if (tg->funcs->is_tg_enabled(tg)) {
759 tg->funcs->set_blank(tg, true);
760 hwss_wait_for_blank_complete(tg);
764 /* Reset all MPCC muxes */
765 dc->res_pool->mpc->funcs->mpc_init(dc->res_pool->mpc);
767 for (i = 0; i < dc->res_pool->pipe_count; i++) {
768 struct timing_generator *tg = dc->res_pool->timing_generators[i];
769 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
770 struct hubp *hubp = dc->res_pool->hubps[i];
772 pipe_ctx->stream_res.tg = tg;
773 pipe_ctx->pipe_idx = i;
775 pipe_ctx->plane_res.hubp = hubp;
778 hubp->power_gated = false;
780 dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
781 dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
782 dc->res_pool->opps[i]->mpcc_disconnect_pending[i] = true;
783 pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
785 plane_atomic_disconnect(dc, pipe_ctx);
788 for (i = 0; i < dc->res_pool->pipe_count; i++) {
789 struct timing_generator *tg = dc->res_pool->timing_generators[i];
791 if (tg->funcs->is_tg_enabled(tg))
792 tg->funcs->unlock(tg);
795 for (i = 0; i < dc->res_pool->pipe_count; i++) {
796 struct timing_generator *tg = dc->res_pool->timing_generators[i];
797 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
799 dcn10_disable_plane(dc, pipe_ctx);
801 pipe_ctx->stream_res.tg = NULL;
802 pipe_ctx->plane_res.hubp = NULL;
804 tg->funcs->tg_init(tg);
807 for (i = 0; i < dc->res_pool->audio_count; i++) {
808 struct audio *audio = dc->res_pool->audios[i];
810 audio->funcs->hw_init(audio);
814 abm->funcs->init_backlight(abm);
815 abm->funcs->abm_init(abm);
819 dmcu->funcs->dmcu_init(dmcu);
821 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/
822 REG_WRITE(DIO_MEM_PWR_CTRL, 0);
824 if (!dc->debug.disable_clock_gate) {
825 /* enable all DCN clock gating */
826 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
828 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
830 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
833 enable_power_gating_plane(dc->hwseq, true);
836 static void reset_hw_ctx_wrap(
838 struct dc_state *context)
843 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
844 struct pipe_ctx *pipe_ctx_old =
845 &dc->current_state->res_ctx.pipe_ctx[i];
846 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
848 if (!pipe_ctx_old->stream)
851 if (pipe_ctx_old->top_pipe)
854 if (!pipe_ctx->stream ||
855 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
856 struct clock_source *old_clk = pipe_ctx_old->clock_source;
858 reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
860 old_clk->funcs->cs_power_down(old_clk);
866 static bool patch_address_for_sbs_tb_stereo(
867 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr)
869 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
870 bool sec_split = pipe_ctx->top_pipe &&
871 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
872 if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
873 (pipe_ctx->stream->timing.timing_3d_format ==
874 TIMING_3D_FORMAT_SIDE_BY_SIDE ||
875 pipe_ctx->stream->timing.timing_3d_format ==
876 TIMING_3D_FORMAT_TOP_AND_BOTTOM)) {
877 *addr = plane_state->address.grph_stereo.left_addr;
878 plane_state->address.grph_stereo.left_addr =
879 plane_state->address.grph_stereo.right_addr;
882 if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE &&
883 plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) {
884 plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO;
885 plane_state->address.grph_stereo.right_addr =
886 plane_state->address.grph_stereo.left_addr;
894 static void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)
896 bool addr_patched = false;
897 PHYSICAL_ADDRESS_LOC addr;
898 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
900 if (plane_state == NULL)
902 addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);
903 pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(
904 pipe_ctx->plane_res.hubp,
905 &plane_state->address,
906 plane_state->flip_immediate);
907 plane_state->status.requested_address = plane_state->address;
909 pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;
912 static bool dcn10_set_input_transfer_func(struct pipe_ctx *pipe_ctx,
913 const struct dc_plane_state *plane_state)
915 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
916 const struct dc_transfer_func *tf = NULL;
919 if (dpp_base == NULL)
922 if (plane_state->in_transfer_func)
923 tf = plane_state->in_transfer_func;
925 if (plane_state->gamma_correction && dce_use_lut(plane_state))
926 dpp_base->funcs->dpp_program_input_lut(dpp_base, plane_state->gamma_correction);
929 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
930 else if (tf->type == TF_TYPE_PREDEFINED) {
932 case TRANSFER_FUNCTION_SRGB:
933 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_sRGB);
935 case TRANSFER_FUNCTION_BT709:
936 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_xvYCC);
938 case TRANSFER_FUNCTION_LINEAR:
939 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
941 case TRANSFER_FUNCTION_PQ:
946 } else if (tf->type == TF_TYPE_BYPASS) {
947 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
949 /*TF_TYPE_DISTRIBUTED_POINTS*/
961 dcn10_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
962 const struct dc_stream_state *stream)
964 struct dpp *dpp = pipe_ctx->plane_res.dpp;
969 dpp->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
971 if (stream->out_transfer_func &&
972 stream->out_transfer_func->type == TF_TYPE_PREDEFINED &&
973 stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB)
974 dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_SRGB);
976 /* dcn10_translate_regamma_to_hw_format takes 750us, only do it when full
979 else if (cm_helper_translate_curve_to_hw_format(
980 stream->out_transfer_func,
981 &dpp->regamma_params, false)) {
982 dpp->funcs->dpp_program_regamma_pwl(
984 &dpp->regamma_params, OPP_REGAMMA_USER);
986 dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_BYPASS);
991 static void dcn10_pipe_control_lock(
993 struct pipe_ctx *pipe,
996 struct hubp *hubp = NULL;
997 hubp = dc->res_pool->hubps[pipe->pipe_idx];
998 /* use TG master update lock to lock everything on the TG
999 * therefore only top pipe need to lock
1004 if (dc->debug.sanity_checks)
1005 dcn10_verify_allow_pstate_change_high(dc);
1008 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);
1010 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);
1012 if (dc->debug.sanity_checks)
1013 dcn10_verify_allow_pstate_change_high(dc);
1016 static bool wait_for_reset_trigger_to_occur(
1017 struct dc_context *dc_ctx,
1018 struct timing_generator *tg)
1022 /* To avoid endless loop we wait at most
1023 * frames_to_wait_on_triggered_reset frames for the reset to occur. */
1024 const uint32_t frames_to_wait_on_triggered_reset = 10;
1027 for (i = 0; i < frames_to_wait_on_triggered_reset; i++) {
1029 if (!tg->funcs->is_counter_moving(tg)) {
1030 DC_ERROR("TG counter is not moving!\n");
1034 if (tg->funcs->did_triggered_reset_occur(tg)) {
1036 /* usually occurs at i=1 */
1037 DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",
1042 /* Wait for one frame. */
1043 tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);
1044 tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
1048 DC_ERROR("GSL: Timeout on reset trigger!\n");
1053 static void dcn10_enable_timing_synchronization(
1057 struct pipe_ctx *grouped_pipes[])
1059 struct dc_context *dc_ctx = dc->ctx;
1062 DC_SYNC_INFO("Setting up OTG reset trigger\n");
1064 for (i = 1; i < group_size; i++)
1065 grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger(
1066 grouped_pipes[i]->stream_res.tg,
1067 grouped_pipes[0]->stream_res.tg->inst);
1069 DC_SYNC_INFO("Waiting for trigger\n");
1071 /* Need to get only check 1 pipe for having reset as all the others are
1072 * synchronized. Look at last pipe programmed to reset.
1075 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[1]->stream_res.tg);
1076 for (i = 1; i < group_size; i++)
1077 grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(
1078 grouped_pipes[i]->stream_res.tg);
1080 DC_SYNC_INFO("Sync complete\n");
1083 static void dcn10_enable_per_frame_crtc_position_reset(
1086 struct pipe_ctx *grouped_pipes[])
1088 struct dc_context *dc_ctx = dc->ctx;
1091 DC_SYNC_INFO("Setting up\n");
1092 for (i = 0; i < group_size; i++)
1093 grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset(
1094 grouped_pipes[i]->stream_res.tg,
1095 grouped_pipes[i]->stream->triggered_crtc_reset.event_source->status.primary_otg_inst,
1096 &grouped_pipes[i]->stream->triggered_crtc_reset);
1098 DC_SYNC_INFO("Waiting for trigger\n");
1100 for (i = 0; i < group_size; i++)
1101 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
1103 DC_SYNC_INFO("Multi-display sync is complete\n");
1106 /*static void print_rq_dlg_ttu(
1108 struct pipe_ctx *pipe_ctx)
1110 dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
1111 "\n============== DML TTU Output parameters [%d] ==============\n"
1112 "qos_level_low_wm: %d, \n"
1113 "qos_level_high_wm: %d, \n"
1114 "min_ttu_vblank: %d, \n"
1115 "qos_level_flip: %d, \n"
1116 "refcyc_per_req_delivery_l: %d, \n"
1117 "qos_level_fixed_l: %d, \n"
1118 "qos_ramp_disable_l: %d, \n"
1119 "refcyc_per_req_delivery_pre_l: %d, \n"
1120 "refcyc_per_req_delivery_c: %d, \n"
1121 "qos_level_fixed_c: %d, \n"
1122 "qos_ramp_disable_c: %d, \n"
1123 "refcyc_per_req_delivery_pre_c: %d\n"
1124 "=============================================================\n",
1126 pipe_ctx->ttu_regs.qos_level_low_wm,
1127 pipe_ctx->ttu_regs.qos_level_high_wm,
1128 pipe_ctx->ttu_regs.min_ttu_vblank,
1129 pipe_ctx->ttu_regs.qos_level_flip,
1130 pipe_ctx->ttu_regs.refcyc_per_req_delivery_l,
1131 pipe_ctx->ttu_regs.qos_level_fixed_l,
1132 pipe_ctx->ttu_regs.qos_ramp_disable_l,
1133 pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_l,
1134 pipe_ctx->ttu_regs.refcyc_per_req_delivery_c,
1135 pipe_ctx->ttu_regs.qos_level_fixed_c,
1136 pipe_ctx->ttu_regs.qos_ramp_disable_c,
1137 pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_c
1140 dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
1141 "\n============== DML DLG Output parameters [%d] ==============\n"
1142 "refcyc_h_blank_end: %d, \n"
1143 "dlg_vblank_end: %d, \n"
1144 "min_dst_y_next_start: %d, \n"
1145 "refcyc_per_htotal: %d, \n"
1146 "refcyc_x_after_scaler: %d, \n"
1147 "dst_y_after_scaler: %d, \n"
1148 "dst_y_prefetch: %d, \n"
1149 "dst_y_per_vm_vblank: %d, \n"
1150 "dst_y_per_row_vblank: %d, \n"
1151 "ref_freq_to_pix_freq: %d, \n"
1152 "vratio_prefetch: %d, \n"
1153 "refcyc_per_pte_group_vblank_l: %d, \n"
1154 "refcyc_per_meta_chunk_vblank_l: %d, \n"
1155 "dst_y_per_pte_row_nom_l: %d, \n"
1156 "refcyc_per_pte_group_nom_l: %d, \n",
1158 pipe_ctx->dlg_regs.refcyc_h_blank_end,
1159 pipe_ctx->dlg_regs.dlg_vblank_end,
1160 pipe_ctx->dlg_regs.min_dst_y_next_start,
1161 pipe_ctx->dlg_regs.refcyc_per_htotal,
1162 pipe_ctx->dlg_regs.refcyc_x_after_scaler,
1163 pipe_ctx->dlg_regs.dst_y_after_scaler,
1164 pipe_ctx->dlg_regs.dst_y_prefetch,
1165 pipe_ctx->dlg_regs.dst_y_per_vm_vblank,
1166 pipe_ctx->dlg_regs.dst_y_per_row_vblank,
1167 pipe_ctx->dlg_regs.ref_freq_to_pix_freq,
1168 pipe_ctx->dlg_regs.vratio_prefetch,
1169 pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_l,
1170 pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_l,
1171 pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_l,
1172 pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_l
1175 dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
1176 "\ndst_y_per_meta_row_nom_l: %d, \n"
1177 "refcyc_per_meta_chunk_nom_l: %d, \n"
1178 "refcyc_per_line_delivery_pre_l: %d, \n"
1179 "refcyc_per_line_delivery_l: %d, \n"
1180 "vratio_prefetch_c: %d, \n"
1181 "refcyc_per_pte_group_vblank_c: %d, \n"
1182 "refcyc_per_meta_chunk_vblank_c: %d, \n"
1183 "dst_y_per_pte_row_nom_c: %d, \n"
1184 "refcyc_per_pte_group_nom_c: %d, \n"
1185 "dst_y_per_meta_row_nom_c: %d, \n"
1186 "refcyc_per_meta_chunk_nom_c: %d, \n"
1187 "refcyc_per_line_delivery_pre_c: %d, \n"
1188 "refcyc_per_line_delivery_c: %d \n"
1189 "========================================================\n",
1190 pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_l,
1191 pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_l,
1192 pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_l,
1193 pipe_ctx->dlg_regs.refcyc_per_line_delivery_l,
1194 pipe_ctx->dlg_regs.vratio_prefetch_c,
1195 pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_c,
1196 pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_c,
1197 pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_c,
1198 pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_c,
1199 pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_c,
1200 pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_c,
1201 pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_c,
1202 pipe_ctx->dlg_regs.refcyc_per_line_delivery_c
1205 dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
1206 "\n============== DML RQ Output parameters [%d] ==============\n"
1208 "min_chunk_size: %d \n"
1209 "meta_chunk_size: %d \n"
1210 "min_meta_chunk_size: %d \n"
1211 "dpte_group_size: %d \n"
1212 "mpte_group_size: %d \n"
1213 "swath_height: %d \n"
1214 "pte_row_height_linear: %d \n"
1215 "========================================================\n",
1217 pipe_ctx->rq_regs.rq_regs_l.chunk_size,
1218 pipe_ctx->rq_regs.rq_regs_l.min_chunk_size,
1219 pipe_ctx->rq_regs.rq_regs_l.meta_chunk_size,
1220 pipe_ctx->rq_regs.rq_regs_l.min_meta_chunk_size,
1221 pipe_ctx->rq_regs.rq_regs_l.dpte_group_size,
1222 pipe_ctx->rq_regs.rq_regs_l.mpte_group_size,
1223 pipe_ctx->rq_regs.rq_regs_l.swath_height,
1224 pipe_ctx->rq_regs.rq_regs_l.pte_row_height_linear
1229 static void mmhub_read_vm_system_aperture_settings(struct dcn10_hubp *hubp1,
1230 struct vm_system_aperture_param *apt,
1231 struct dce_hwseq *hws)
1233 PHYSICAL_ADDRESS_LOC physical_page_number;
1234 uint32_t logical_addr_low;
1235 uint32_t logical_addr_high;
1237 REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
1238 PHYSICAL_PAGE_NUMBER_MSB, &physical_page_number.high_part);
1239 REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
1240 PHYSICAL_PAGE_NUMBER_LSB, &physical_page_number.low_part);
1242 REG_GET(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1243 LOGICAL_ADDR, &logical_addr_low);
1245 REG_GET(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1246 LOGICAL_ADDR, &logical_addr_high);
1248 apt->sys_default.quad_part = physical_page_number.quad_part << 12;
1249 apt->sys_low.quad_part = (int64_t)logical_addr_low << 18;
1250 apt->sys_high.quad_part = (int64_t)logical_addr_high << 18;
1253 /* Temporary read settings, future will get values from kmd directly */
1254 static void mmhub_read_vm_context0_settings(struct dcn10_hubp *hubp1,
1255 struct vm_context0_param *vm0,
1256 struct dce_hwseq *hws)
1258 PHYSICAL_ADDRESS_LOC fb_base;
1259 PHYSICAL_ADDRESS_LOC fb_offset;
1260 uint32_t fb_base_value;
1261 uint32_t fb_offset_value;
1263 REG_GET(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, &fb_base_value);
1264 REG_GET(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, &fb_offset_value);
1266 REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
1267 PAGE_DIRECTORY_ENTRY_HI32, &vm0->pte_base.high_part);
1268 REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
1269 PAGE_DIRECTORY_ENTRY_LO32, &vm0->pte_base.low_part);
1271 REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
1272 LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_start.high_part);
1273 REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
1274 LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_start.low_part);
1276 REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
1277 LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_end.high_part);
1278 REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
1279 LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_end.low_part);
1281 REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
1282 PHYSICAL_PAGE_ADDR_HI4, &vm0->fault_default.high_part);
1283 REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
1284 PHYSICAL_PAGE_ADDR_LO32, &vm0->fault_default.low_part);
1287 * The values in VM_CONTEXT0_PAGE_TABLE_BASE_ADDR is in UMA space.
1288 * Therefore we need to do
1289 * DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
1290 * - DCHUBBUB_SDPIF_FB_OFFSET + DCHUBBUB_SDPIF_FB_BASE
1292 fb_base.quad_part = (uint64_t)fb_base_value << 24;
1293 fb_offset.quad_part = (uint64_t)fb_offset_value << 24;
1294 vm0->pte_base.quad_part += fb_base.quad_part;
1295 vm0->pte_base.quad_part -= fb_offset.quad_part;
1299 static void dcn10_program_pte_vm(struct dce_hwseq *hws, struct hubp *hubp)
1301 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
1302 struct vm_system_aperture_param apt = { {{ 0 } } };
1303 struct vm_context0_param vm0 = { { { 0 } } };
1305 mmhub_read_vm_system_aperture_settings(hubp1, &apt, hws);
1306 mmhub_read_vm_context0_settings(hubp1, &vm0, hws);
1308 hubp->funcs->hubp_set_vm_system_aperture_settings(hubp, &apt);
1309 hubp->funcs->hubp_set_vm_context0_settings(hubp, &vm0);
1312 static void dcn10_enable_plane(
1314 struct pipe_ctx *pipe_ctx,
1315 struct dc_state *context)
1317 struct dce_hwseq *hws = dc->hwseq;
1319 if (dc->debug.sanity_checks) {
1320 dcn10_verify_allow_pstate_change_high(dc);
1323 undo_DEGVIDCN10_253_wa(dc);
1325 power_on_plane(dc->hwseq,
1326 pipe_ctx->pipe_idx);
1328 /* enable DCFCLK current DCHUB */
1329 REG_UPDATE(HUBP_CLK_CNTL[pipe_ctx->pipe_idx],
1330 HUBP_CLOCK_ENABLE, 1);
1332 /* make sure OPP_PIPE_CLOCK_EN = 1 */
1333 REG_UPDATE(OPP_PIPE_CONTROL[pipe_ctx->stream_res.tg->inst],
1334 OPP_PIPE_CLOCK_EN, 1);
1336 /* TODO: enable/disable in dm as per update type.
1338 dm_logger_write(dc->ctx->logger, LOG_DC,
1339 "Pipe:%d 0x%x: addr hi:0x%x, "
1342 " %d; dst: %d, %d, %d, %d;\n",
1345 plane_state->address.grph.addr.high_part,
1346 plane_state->address.grph.addr.low_part,
1347 plane_state->src_rect.x,
1348 plane_state->src_rect.y,
1349 plane_state->src_rect.width,
1350 plane_state->src_rect.height,
1351 plane_state->dst_rect.x,
1352 plane_state->dst_rect.y,
1353 plane_state->dst_rect.width,
1354 plane_state->dst_rect.height);
1356 dm_logger_write(dc->ctx->logger, LOG_DC,
1357 "Pipe %d: width, height, x, y format:%d\n"
1358 "viewport:%d, %d, %d, %d\n"
1359 "recout: %d, %d, %d, %d\n",
1361 plane_state->format,
1362 pipe_ctx->plane_res.scl_data.viewport.width,
1363 pipe_ctx->plane_res.scl_data.viewport.height,
1364 pipe_ctx->plane_res.scl_data.viewport.x,
1365 pipe_ctx->plane_res.scl_data.viewport.y,
1366 pipe_ctx->plane_res.scl_data.recout.width,
1367 pipe_ctx->plane_res.scl_data.recout.height,
1368 pipe_ctx->plane_res.scl_data.recout.x,
1369 pipe_ctx->plane_res.scl_data.recout.y);
1370 print_rq_dlg_ttu(dc, pipe_ctx);
1373 if (dc->config.gpu_vm_support)
1374 dcn10_program_pte_vm(hws, pipe_ctx->plane_res.hubp);
1376 if (dc->debug.sanity_checks) {
1377 dcn10_verify_allow_pstate_change_high(dc);
1381 static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
1383 struct dpp_grph_csc_adjustment adjust;
1384 memset(&adjust, 0, sizeof(adjust));
1385 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
1388 if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
1389 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
1390 adjust.temperature_matrix[0] =
1392 gamut_remap_matrix.matrix[0];
1393 adjust.temperature_matrix[1] =
1395 gamut_remap_matrix.matrix[1];
1396 adjust.temperature_matrix[2] =
1398 gamut_remap_matrix.matrix[2];
1399 adjust.temperature_matrix[3] =
1401 gamut_remap_matrix.matrix[4];
1402 adjust.temperature_matrix[4] =
1404 gamut_remap_matrix.matrix[5];
1405 adjust.temperature_matrix[5] =
1407 gamut_remap_matrix.matrix[6];
1408 adjust.temperature_matrix[6] =
1410 gamut_remap_matrix.matrix[8];
1411 adjust.temperature_matrix[7] =
1413 gamut_remap_matrix.matrix[9];
1414 adjust.temperature_matrix[8] =
1416 gamut_remap_matrix.matrix[10];
1419 pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp, &adjust);
1423 static void program_csc_matrix(struct pipe_ctx *pipe_ctx,
1424 enum dc_color_space colorspace,
1427 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
1428 if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment != NULL)
1429 pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, matrix);
1431 if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default != NULL)
1432 pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default(pipe_ctx->plane_res.dpp, colorspace);
1436 static void program_output_csc(struct dc *dc,
1437 struct pipe_ctx *pipe_ctx,
1438 enum dc_color_space colorspace,
1442 if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment != NULL)
1443 program_csc_matrix(pipe_ctx,
1448 static bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
1450 if (pipe_ctx->plane_state->visible)
1452 if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
1457 static bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
1459 if (pipe_ctx->plane_state->visible)
1461 if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
1466 static bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
1468 if (pipe_ctx->plane_state->visible)
1470 if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
1472 if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
1477 static bool is_rgb_cspace(enum dc_color_space output_color_space)
1479 switch (output_color_space) {
1480 case COLOR_SPACE_SRGB:
1481 case COLOR_SPACE_SRGB_LIMITED:
1482 case COLOR_SPACE_2020_RGB_FULLRANGE:
1483 case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
1484 case COLOR_SPACE_ADOBERGB:
1486 case COLOR_SPACE_YCBCR601:
1487 case COLOR_SPACE_YCBCR709:
1488 case COLOR_SPACE_YCBCR601_LIMITED:
1489 case COLOR_SPACE_YCBCR709_LIMITED:
1490 case COLOR_SPACE_2020_YCBCR:
1493 /* Add a case to switch */
1494 BREAK_TO_DEBUGGER();
1499 static void dcn10_get_surface_visual_confirm_color(
1500 const struct pipe_ctx *pipe_ctx,
1501 struct tg_color *color)
1503 uint32_t color_value = MAX_TG_COLOR_VALUE;
1505 switch (pipe_ctx->plane_res.scl_data.format) {
1506 case PIXEL_FORMAT_ARGB8888:
1507 /* set boarder color to red */
1508 color->color_r_cr = color_value;
1511 case PIXEL_FORMAT_ARGB2101010:
1512 /* set boarder color to blue */
1513 color->color_b_cb = color_value;
1515 case PIXEL_FORMAT_420BPP8:
1516 /* set boarder color to green */
1517 color->color_g_y = color_value;
1519 case PIXEL_FORMAT_420BPP10:
1520 /* set boarder color to yellow */
1521 color->color_g_y = color_value;
1522 color->color_r_cr = color_value;
1524 case PIXEL_FORMAT_FP16:
1525 /* set boarder color to white */
1526 color->color_r_cr = color_value;
1527 color->color_b_cb = color_value;
1528 color->color_g_y = color_value;
1535 static uint16_t fixed_point_to_int_frac(
1536 struct fixed31_32 arg,
1537 uint8_t integer_bits,
1538 uint8_t fractional_bits)
1541 int32_t divisor = 1 << fractional_bits;
1545 uint16_t d = (uint16_t)dal_fixed31_32_floor(
1549 if (d <= (uint16_t)(1 << integer_bits) - (1 / (uint16_t)divisor))
1550 numerator = (uint16_t)dal_fixed31_32_floor(
1551 dal_fixed31_32_mul_int(
1555 numerator = dal_fixed31_32_floor(
1557 dal_fixed31_32_from_int(
1558 1LL << integer_bits),
1559 dal_fixed31_32_recip(
1560 dal_fixed31_32_from_int(
1565 result = (uint16_t)numerator;
1567 result = (uint16_t)(
1568 (1 << (integer_bits + fractional_bits + 1)) + numerator);
1570 if ((result != 0) && dal_fixed31_32_lt(
1571 arg, dal_fixed31_32_zero))
1572 result |= 1 << (integer_bits + fractional_bits);
1577 void build_prescale_params(struct dc_bias_and_scale *bias_and_scale,
1578 const struct dc_plane_state *plane_state)
1580 if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
1581 && plane_state->format != SURFACE_PIXEL_FORMAT_INVALID
1582 && plane_state->input_csc_color_matrix.enable_adjustment
1583 && plane_state->coeff_reduction_factor.value != 0) {
1584 bias_and_scale->scale_blue = fixed_point_to_int_frac(
1585 dal_fixed31_32_mul(plane_state->coeff_reduction_factor,
1586 dal_fixed31_32_from_fraction(256, 255)),
1589 bias_and_scale->scale_red = bias_and_scale->scale_blue;
1590 bias_and_scale->scale_green = bias_and_scale->scale_blue;
1592 bias_and_scale->scale_blue = 0x2000;
1593 bias_and_scale->scale_red = 0x2000;
1594 bias_and_scale->scale_green = 0x2000;
1598 static void update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state)
1600 struct dc_bias_and_scale bns_params = {0};
1602 // program the input csc
1603 dpp->funcs->dpp_setup(dpp,
1604 plane_state->format,
1605 EXPANSION_MODE_ZERO,
1606 plane_state->input_csc_color_matrix,
1607 COLOR_SPACE_YCBCR601_LIMITED);
1609 //set scale and bias registers
1610 build_prescale_params(&bns_params, plane_state);
1611 if (dpp->funcs->dpp_program_bias_and_scale)
1612 dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
1615 static void update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
1617 struct hubp *hubp = pipe_ctx->plane_res.hubp;
1618 struct mpcc_blnd_cfg blnd_cfg;
1619 bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
1621 struct mpcc *new_mpcc;
1622 struct mpc *mpc = dc->res_pool->mpc;
1623 struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);
1625 /* TODO: proper fix once fpga works */
1627 if (dc->debug.surface_visual_confirm)
1628 dcn10_get_surface_visual_confirm_color(
1629 pipe_ctx, &blnd_cfg.black_color);
1631 color_space_to_black_color(
1632 dc, pipe_ctx->stream->output_color_space,
1633 &blnd_cfg.black_color);
1635 if (per_pixel_alpha)
1636 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;
1638 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA;
1640 blnd_cfg.overlap_only = false;
1641 blnd_cfg.global_alpha = 0xff;
1642 blnd_cfg.global_gain = 0xff;
1644 /* DCN1.0 has output CM before MPC which seems to screw with
1645 * pre-multiplied alpha.
1647 blnd_cfg.pre_multiplied_alpha = is_rgb_cspace(
1648 pipe_ctx->stream->output_color_space)
1653 * Note: currently there is a bug in init_hw such that
1654 * on resume from hibernate, BIOS sets up MPCC0, and
1655 * we do mpcc_remove but the mpcc cannot go to idle
1656 * after remove. This cause us to pick mpcc1 here,
1657 * which causes a pstate hang for yet unknown reason.
1659 mpcc_id = hubp->inst;
1661 /* check if this MPCC is already being used */
1662 new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id);
1663 /* remove MPCC if being used */
1664 if (new_mpcc != NULL)
1665 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc);
1667 if (dc->debug.sanity_checks)
1668 mpc->funcs->assert_mpcc_idle_before_connect(
1669 dc->res_pool->mpc, mpcc_id);
1671 /* Call MPC to insert new plane */
1672 new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,
1680 ASSERT(new_mpcc != NULL);
1682 hubp->opp_id = pipe_ctx->stream_res.opp->inst;
1683 hubp->mpcc_id = mpcc_id;
1686 static void update_scaler(struct pipe_ctx *pipe_ctx)
1688 bool per_pixel_alpha =
1689 pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
1691 /* TODO: proper fix once fpga works */
1693 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = per_pixel_alpha;
1694 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
1695 /* scaler configuration */
1696 pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(
1697 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);
1700 static void update_dchubp_dpp(
1702 struct pipe_ctx *pipe_ctx,
1703 struct dc_state *context)
1705 struct dce_hwseq *hws = dc->hwseq;
1706 struct hubp *hubp = pipe_ctx->plane_res.hubp;
1707 struct dpp *dpp = pipe_ctx->plane_res.dpp;
1708 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1709 union plane_size size = plane_state->plane_size;
1711 /* depends on DML calculation, DPP clock value may change dynamically */
1712 if (plane_state->update_flags.bits.full_update) {
1716 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk,
1717 context->bw.dcn.calc_clk.dppclk_div);
1718 dc->current_state->bw.dcn.cur_clk.dppclk_div =
1719 context->bw.dcn.calc_clk.dppclk_div;
1720 context->bw.dcn.cur_clk.dppclk_div = context->bw.dcn.calc_clk.dppclk_div;
1723 /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG
1724 * VTG is within DCHUBBUB which is commond block share by each pipe HUBP.
1725 * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG
1727 if (plane_state->update_flags.bits.full_update) {
1728 REG_UPDATE(DCHUBP_CNTL[pipe_ctx->pipe_idx], HUBP_VTG_SEL, pipe_ctx->stream_res.tg->inst);
1730 hubp->funcs->hubp_setup(
1732 &pipe_ctx->dlg_regs,
1733 &pipe_ctx->ttu_regs,
1735 &pipe_ctx->pipe_dlg_param);
1738 size.grph.surface_size = pipe_ctx->plane_res.scl_data.viewport;
1740 if (plane_state->update_flags.bits.full_update ||
1741 plane_state->update_flags.bits.bpp_change)
1742 update_dpp(dpp, plane_state);
1744 if (plane_state->update_flags.bits.full_update ||
1745 plane_state->update_flags.bits.per_pixel_alpha_change)
1746 update_mpcc(dc, pipe_ctx);
1748 if (plane_state->update_flags.bits.full_update ||
1749 plane_state->update_flags.bits.per_pixel_alpha_change ||
1750 plane_state->update_flags.bits.scaling_change ||
1751 plane_state->update_flags.bits.position_change) {
1752 update_scaler(pipe_ctx);
1755 if (plane_state->update_flags.bits.full_update ||
1756 plane_state->update_flags.bits.scaling_change ||
1757 plane_state->update_flags.bits.position_change) {
1758 hubp->funcs->mem_program_viewport(
1760 &pipe_ctx->plane_res.scl_data.viewport,
1761 &pipe_ctx->plane_res.scl_data.viewport_c);
1764 if (plane_state->update_flags.bits.full_update) {
1766 program_gamut_remap(pipe_ctx);
1768 program_output_csc(dc,
1770 pipe_ctx->stream->output_color_space,
1771 pipe_ctx->stream->csc_color_matrix.matrix,
1775 if (plane_state->update_flags.bits.full_update ||
1776 plane_state->update_flags.bits.horizontal_mirror_change ||
1777 plane_state->update_flags.bits.rotation_change ||
1778 plane_state->update_flags.bits.swizzle_change ||
1779 plane_state->update_flags.bits.dcc_change ||
1780 plane_state->update_flags.bits.bpp_change ||
1781 plane_state->update_flags.bits.scaling_change) {
1782 hubp->funcs->hubp_program_surface_config(
1784 plane_state->format,
1785 &plane_state->tiling_info,
1787 plane_state->rotation,
1789 plane_state->horizontal_mirror);
1792 hubp->power_gated = false;
1794 dc->hwss.update_plane_addr(dc, pipe_ctx);
1796 if (is_pipe_tree_visible(pipe_ctx))
1797 hubp->funcs->set_blank(hubp, false);
1801 static void program_all_pipe_in_tree(
1803 struct pipe_ctx *pipe_ctx,
1804 struct dc_state *context)
1807 if (pipe_ctx->top_pipe == NULL) {
1809 pipe_ctx->stream_res.tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset;
1810 pipe_ctx->stream_res.tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start;
1811 pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset;
1812 pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_width = pipe_ctx->pipe_dlg_param.vupdate_width;
1813 pipe_ctx->stream_res.tg->dlg_otg_param.signal = pipe_ctx->stream->signal;
1815 pipe_ctx->stream_res.tg->funcs->program_global_sync(
1816 pipe_ctx->stream_res.tg);
1818 if (pipe_ctx->stream_res.tg->funcs->set_blank)
1819 pipe_ctx->stream_res.tg->funcs->set_blank(
1820 pipe_ctx->stream_res.tg,
1821 !is_pipe_tree_visible(pipe_ctx));
1824 if (pipe_ctx->plane_state != NULL) {
1825 struct pipe_ctx *cur_pipe_ctx =
1826 &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
1828 if (pipe_ctx->plane_state->update_flags.bits.full_update)
1829 dcn10_enable_plane(dc, pipe_ctx, context);
1831 update_dchubp_dpp(dc, pipe_ctx, context);
1833 if (cur_pipe_ctx->plane_state != pipe_ctx->plane_state)
1834 dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state);
1836 /* dcn10_translate_regamma_to_hw_format takes 750us to finish
1837 * only do gamma programming for full update.
1838 * TODO: This can be further optimized/cleaned up
1839 * Always call this for now since it does memcmp inside before
1840 * doing heavy calculation and programming
1842 if (pipe_ctx->plane_state->update_flags.bits.full_update)
1843 dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);
1846 if (pipe_ctx->bottom_pipe != NULL && pipe_ctx->bottom_pipe != pipe_ctx)
1847 program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context);
1850 static void dcn10_pplib_apply_display_requirements(
1852 struct dc_state *context)
1854 struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
1856 pp_display_cfg->all_displays_in_sync = false;/*todo*/
1857 pp_display_cfg->nb_pstate_switch_disable = false;
1858 pp_display_cfg->min_engine_clock_khz = context->bw.dcn.cur_clk.dcfclk_khz;
1859 pp_display_cfg->min_memory_clock_khz = context->bw.dcn.cur_clk.fclk_khz;
1860 pp_display_cfg->min_engine_clock_deep_sleep_khz = context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz;
1861 pp_display_cfg->min_dcfc_deep_sleep_clock_khz = context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz;
1862 pp_display_cfg->avail_mclk_switch_time_us =
1863 context->bw.dcn.cur_clk.dram_ccm_us > 0 ? context->bw.dcn.cur_clk.dram_ccm_us : 0;
1864 pp_display_cfg->avail_mclk_switch_time_in_disp_active_us =
1865 context->bw.dcn.cur_clk.min_active_dram_ccm_us > 0 ? context->bw.dcn.cur_clk.min_active_dram_ccm_us : 0;
1866 pp_display_cfg->min_dcfclock_khz = context->bw.dcn.cur_clk.dcfclk_khz;
1867 pp_display_cfg->disp_clk_khz = context->bw.dcn.cur_clk.dispclk_khz;
1868 dce110_fill_display_configs(context, pp_display_cfg);
1870 if (memcmp(&dc->prev_display_config, pp_display_cfg, sizeof(
1871 struct dm_pp_display_configuration)) != 0)
1872 dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
1874 dc->prev_display_config = *pp_display_cfg;
1877 static void optimize_shared_resources(struct dc *dc)
1879 if (dc->current_state->stream_count == 0) {
1881 dcn10_pplib_apply_display_requirements(dc, dc->current_state);
1884 if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE)
1885 dcn_bw_notify_pplib_of_wm_ranges(dc);
1888 static void ready_shared_resources(struct dc *dc, struct dc_state *context)
1891 if (dc->current_state->stream_count == 0 &&
1892 context->stream_count != 0)
1893 dcn10_pplib_apply_display_requirements(dc, context);
1896 static struct pipe_ctx *find_top_pipe_for_stream(
1898 struct dc_state *context,
1899 const struct dc_stream_state *stream)
1903 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1904 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1905 struct pipe_ctx *old_pipe_ctx =
1906 &dc->current_state->res_ctx.pipe_ctx[i];
1908 if (!pipe_ctx->plane_state && !old_pipe_ctx->plane_state)
1911 if (pipe_ctx->stream != stream)
1914 if (!pipe_ctx->top_pipe)
1920 static void dcn10_apply_ctx_for_surface(
1922 const struct dc_stream_state *stream,
1924 struct dc_state *context)
1927 struct timing_generator *tg;
1928 struct output_pixel_processor *opp;
1929 bool removed_pipe[4] = { false };
1930 unsigned int ref_clk_mhz = dc->res_pool->ref_clock_inKhz/1000;
1931 bool program_water_mark = false;
1933 struct pipe_ctx *top_pipe_to_program =
1934 find_top_pipe_for_stream(dc, context, stream);
1936 if (!top_pipe_to_program)
1939 opp = top_pipe_to_program->stream_res.opp;
1941 tg = top_pipe_to_program->stream_res.tg;
1943 dcn10_pipe_control_lock(dc, top_pipe_to_program, true);
1945 if (num_planes == 0) {
1947 /* OTG blank before remove all front end */
1948 if (tg->funcs->set_blank)
1949 tg->funcs->set_blank(tg, true);
1952 /* Disconnect unused mpcc */
1953 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1954 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1955 struct pipe_ctx *old_pipe_ctx =
1956 &dc->current_state->res_ctx.pipe_ctx[i];
1958 * Powergate reused pipes that are not powergated
1959 * fairly hacky right now, using opp_id as indicator
1960 * TODO: After move dc_post to dc_update, this will
1963 if (pipe_ctx->plane_state && !old_pipe_ctx->plane_state) {
1964 if (old_pipe_ctx->stream_res.tg == tg &&
1965 old_pipe_ctx->plane_res.hubp &&
1966 old_pipe_ctx->plane_res.hubp->opp_id != 0xf) {
1967 dcn10_disable_plane(dc, pipe_ctx);
1969 * power down fe will unlock when calling reset, need
1970 * to lock it back here. Messy, need rework.
1972 pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg);
1976 if (!pipe_ctx->plane_state &&
1977 old_pipe_ctx->plane_state &&
1978 old_pipe_ctx->stream_res.tg == tg) {
1980 plane_atomic_disconnect(dc, old_pipe_ctx);
1981 removed_pipe[i] = true;
1983 dm_logger_write(dc->ctx->logger, LOG_DC,
1984 "Reset mpcc for pipe %d\n",
1985 old_pipe_ctx->pipe_idx);
1990 program_all_pipe_in_tree(dc, top_pipe_to_program, context);
1992 dcn10_pipe_control_lock(dc, top_pipe_to_program, false);
1994 if (num_planes == 0)
1995 false_optc_underflow_wa(dc, stream, tg);
1997 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1998 struct pipe_ctx *old_pipe_ctx =
1999 &dc->current_state->res_ctx.pipe_ctx[i];
2000 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2002 if (pipe_ctx->stream == stream &&
2003 pipe_ctx->plane_state &&
2004 pipe_ctx->plane_state->update_flags.bits.full_update)
2005 program_water_mark = true;
2007 if (removed_pipe[i])
2008 dcn10_disable_plane(dc, old_pipe_ctx);
2011 if (program_water_mark) {
2012 if (dc->debug.sanity_checks) {
2013 /* pstate stuck check after watermark update */
2014 dcn10_verify_allow_pstate_change_high(dc);
2017 /* watermark is for all pipes */
2018 hubbub1_program_watermarks(dc->res_pool->hubbub,
2019 &context->bw.dcn.watermarks, ref_clk_mhz);
2021 if (dc->debug.sanity_checks) {
2022 /* pstate stuck check after watermark update */
2023 dcn10_verify_allow_pstate_change_high(dc);
2026 /* dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS,
2027 "\n============== Watermark parameters ==============\n"
2028 "a.urgent_ns: %d \n"
2029 "a.cstate_enter_plus_exit: %d \n"
2030 "a.cstate_exit: %d \n"
2031 "a.pstate_change: %d \n"
2032 "a.pte_meta_urgent: %d \n"
2033 "b.urgent_ns: %d \n"
2034 "b.cstate_enter_plus_exit: %d \n"
2035 "b.cstate_exit: %d \n"
2036 "b.pstate_change: %d \n"
2037 "b.pte_meta_urgent: %d \n",
2038 context->bw.dcn.watermarks.a.urgent_ns,
2039 context->bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns,
2040 context->bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns,
2041 context->bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns,
2042 context->bw.dcn.watermarks.a.pte_meta_urgent_ns,
2043 context->bw.dcn.watermarks.b.urgent_ns,
2044 context->bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns,
2045 context->bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns,
2046 context->bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns,
2047 context->bw.dcn.watermarks.b.pte_meta_urgent_ns
2049 dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS,
2050 "\nc.urgent_ns: %d \n"
2051 "c.cstate_enter_plus_exit: %d \n"
2052 "c.cstate_exit: %d \n"
2053 "c.pstate_change: %d \n"
2054 "c.pte_meta_urgent: %d \n"
2055 "d.urgent_ns: %d \n"
2056 "d.cstate_enter_plus_exit: %d \n"
2057 "d.cstate_exit: %d \n"
2058 "d.pstate_change: %d \n"
2059 "d.pte_meta_urgent: %d \n"
2060 "========================================================\n",
2061 context->bw.dcn.watermarks.c.urgent_ns,
2062 context->bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns,
2063 context->bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns,
2064 context->bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns,
2065 context->bw.dcn.watermarks.c.pte_meta_urgent_ns,
2066 context->bw.dcn.watermarks.d.urgent_ns,
2067 context->bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns,
2068 context->bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns,
2069 context->bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns,
2070 context->bw.dcn.watermarks.d.pte_meta_urgent_ns
2075 static void dcn10_set_bandwidth(
2077 struct dc_state *context,
2078 bool decrease_allowed)
2080 struct pp_smu_display_requirement_rv *smu_req_cur =
2081 &dc->res_pool->pp_smu_req;
2082 struct pp_smu_display_requirement_rv smu_req = *smu_req_cur;
2083 struct pp_smu_funcs_rv *pp_smu = dc->res_pool->pp_smu;
2085 if (dc->debug.sanity_checks) {
2086 dcn10_verify_allow_pstate_change_high(dc);
2089 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
2092 if (decrease_allowed || context->bw.dcn.calc_clk.dispclk_khz
2093 > dc->current_state->bw.dcn.cur_clk.dispclk_khz) {
2094 dc->res_pool->display_clock->funcs->set_clock(
2095 dc->res_pool->display_clock,
2096 context->bw.dcn.calc_clk.dispclk_khz);
2097 dc->current_state->bw.dcn.cur_clk.dispclk_khz =
2098 context->bw.dcn.calc_clk.dispclk_khz;
2100 if (decrease_allowed || context->bw.dcn.calc_clk.dcfclk_khz
2101 > dc->current_state->bw.dcn.cur_clk.dcfclk_khz) {
2102 smu_req.hard_min_dcefclk_khz =
2103 context->bw.dcn.calc_clk.dcfclk_khz;
2105 if (decrease_allowed || context->bw.dcn.calc_clk.fclk_khz
2106 > dc->current_state->bw.dcn.cur_clk.fclk_khz) {
2107 smu_req.hard_min_fclk_khz = context->bw.dcn.calc_clk.fclk_khz;
2109 if (decrease_allowed || context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz
2110 > dc->current_state->bw.dcn.cur_clk.dcfclk_deep_sleep_khz) {
2111 dc->current_state->bw.dcn.calc_clk.dcfclk_deep_sleep_khz =
2112 context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz;
2113 context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz =
2114 context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz;
2117 smu_req.display_count = context->stream_count;
2119 if (pp_smu->set_display_requirement)
2120 pp_smu->set_display_requirement(&pp_smu->pp_smu, &smu_req);
2122 *smu_req_cur = smu_req;
2124 /* Decrease in freq is increase in period so opposite comparison for dram_ccm */
2125 if (decrease_allowed || context->bw.dcn.calc_clk.dram_ccm_us
2126 < dc->current_state->bw.dcn.cur_clk.dram_ccm_us) {
2127 dc->current_state->bw.dcn.calc_clk.dram_ccm_us =
2128 context->bw.dcn.calc_clk.dram_ccm_us;
2129 context->bw.dcn.cur_clk.dram_ccm_us =
2130 context->bw.dcn.calc_clk.dram_ccm_us;
2132 if (decrease_allowed || context->bw.dcn.calc_clk.min_active_dram_ccm_us
2133 < dc->current_state->bw.dcn.cur_clk.min_active_dram_ccm_us) {
2134 dc->current_state->bw.dcn.calc_clk.min_active_dram_ccm_us =
2135 context->bw.dcn.calc_clk.min_active_dram_ccm_us;
2136 context->bw.dcn.cur_clk.min_active_dram_ccm_us =
2137 context->bw.dcn.calc_clk.min_active_dram_ccm_us;
2139 dcn10_pplib_apply_display_requirements(dc, context);
2141 if (dc->debug.sanity_checks) {
2142 dcn10_verify_allow_pstate_change_high(dc);
2145 /* need to fix this function. not doing the right thing here */
2148 static void set_drr(struct pipe_ctx **pipe_ctx,
2149 int num_pipes, int vmin, int vmax)
2152 struct drr_params params = {0};
2154 params.vertical_total_max = vmax;
2155 params.vertical_total_min = vmin;
2157 /* TODO: If multiple pipes are to be supported, you need
2160 for (i = 0; i < num_pipes; i++) {
2161 pipe_ctx[i]->stream_res.tg->funcs->set_drr(pipe_ctx[i]->stream_res.tg, ¶ms);
2165 static void get_position(struct pipe_ctx **pipe_ctx,
2167 struct crtc_position *position)
2171 /* TODO: handle pipes > 1
2173 for (i = 0; i < num_pipes; i++)
2174 pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);
2177 static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
2178 int num_pipes, const struct dc_static_screen_events *events)
2181 unsigned int value = 0;
2183 if (events->surface_update)
2185 if (events->cursor_update)
2188 for (i = 0; i < num_pipes; i++)
2189 pipe_ctx[i]->stream_res.tg->funcs->
2190 set_static_screen_control(pipe_ctx[i]->stream_res.tg, value);
2193 static void set_plane_config(
2194 const struct dc *dc,
2195 struct pipe_ctx *pipe_ctx,
2196 struct resource_context *res_ctx)
2199 program_gamut_remap(pipe_ctx);
2202 static void dcn10_config_stereo_parameters(
2203 struct dc_stream_state *stream, struct crtc_stereo_flags *flags)
2205 enum view_3d_format view_format = stream->view_format;
2206 enum dc_timing_3d_format timing_3d_format =\
2207 stream->timing.timing_3d_format;
2208 bool non_stereo_timing = false;
2210 if (timing_3d_format == TIMING_3D_FORMAT_NONE ||
2211 timing_3d_format == TIMING_3D_FORMAT_SIDE_BY_SIDE ||
2212 timing_3d_format == TIMING_3D_FORMAT_TOP_AND_BOTTOM)
2213 non_stereo_timing = true;
2215 if (non_stereo_timing == false &&
2216 view_format == VIEW_3D_FORMAT_FRAME_SEQUENTIAL) {
2218 flags->PROGRAM_STEREO = 1;
2219 flags->PROGRAM_POLARITY = 1;
2220 if (timing_3d_format == TIMING_3D_FORMAT_INBAND_FA ||
2221 timing_3d_format == TIMING_3D_FORMAT_DP_HDMI_INBAND_FA ||
2222 timing_3d_format == TIMING_3D_FORMAT_SIDEBAND_FA) {
2223 enum display_dongle_type dongle = \
2224 stream->sink->link->ddc->dongle_type;
2225 if (dongle == DISPLAY_DONGLE_DP_VGA_CONVERTER ||
2226 dongle == DISPLAY_DONGLE_DP_DVI_CONVERTER ||
2227 dongle == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
2228 flags->DISABLE_STEREO_DP_SYNC = 1;
2230 flags->RIGHT_EYE_POLARITY =\
2231 stream->timing.flags.RIGHT_EYE_3D_POLARITY;
2232 if (timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
2233 flags->FRAME_PACKED = 1;
2239 static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc)
2241 struct crtc_stereo_flags flags = { 0 };
2242 struct dc_stream_state *stream = pipe_ctx->stream;
2244 dcn10_config_stereo_parameters(stream, &flags);
2246 pipe_ctx->stream_res.opp->funcs->opp_program_stereo(
2247 pipe_ctx->stream_res.opp,
2248 flags.PROGRAM_STEREO == 1 ? true:false,
2251 pipe_ctx->stream_res.tg->funcs->program_stereo(
2252 pipe_ctx->stream_res.tg,
2259 static void dcn10_wait_for_mpcc_disconnect(
2261 struct resource_pool *res_pool,
2262 struct pipe_ctx *pipe_ctx)
2266 if (dc->debug.sanity_checks) {
2267 dcn10_verify_allow_pstate_change_high(dc);
2270 if (!pipe_ctx->stream_res.opp)
2273 for (i = 0; i < MAX_PIPES; i++) {
2274 if (pipe_ctx->stream_res.opp->mpcc_disconnect_pending[i]) {
2275 res_pool->mpc->funcs->wait_for_idle(res_pool->mpc, i);
2276 pipe_ctx->stream_res.opp->mpcc_disconnect_pending[i] = false;
2277 res_pool->hubps[i]->funcs->set_blank(res_pool->hubps[i], true);
2278 /*dm_logger_write(dc->ctx->logger, LOG_ERROR,
2279 "[debug_mpo: wait_for_mpcc finished waiting on mpcc %d]\n",
2284 if (dc->debug.sanity_checks) {
2285 dcn10_verify_allow_pstate_change_high(dc);
2290 static bool dcn10_dummy_display_power_gating(
2292 uint8_t controller_id,
2293 struct dc_bios *dcb,
2294 enum pipe_gating_control power_gating)
2299 void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx)
2301 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2302 struct timing_generator *tg = pipe_ctx->stream_res.tg;
2304 if (plane_state == NULL)
2307 plane_state->status.is_flip_pending =
2308 pipe_ctx->plane_res.hubp->funcs->hubp_is_flip_pending(
2309 pipe_ctx->plane_res.hubp);
2311 plane_state->status.current_address = pipe_ctx->plane_res.hubp->current_address;
2312 if (pipe_ctx->plane_res.hubp->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2313 tg->funcs->is_stereo_left_eye) {
2314 plane_state->status.is_right_eye =
2315 !tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);
2319 void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data)
2321 if (hws->ctx->dc->res_pool->hubbub != NULL)
2322 hubbub1_update_dchub(hws->ctx->dc->res_pool->hubbub, dh_data);
2325 static const struct hw_sequencer_funcs dcn10_funcs = {
2326 .program_gamut_remap = program_gamut_remap,
2327 .program_csc_matrix = program_csc_matrix,
2328 .init_hw = dcn10_init_hw,
2329 .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
2330 .apply_ctx_for_surface = dcn10_apply_ctx_for_surface,
2331 .set_plane_config = set_plane_config,
2332 .update_plane_addr = dcn10_update_plane_addr,
2333 .update_dchub = dcn10_update_dchub,
2334 .update_pending_status = dcn10_update_pending_status,
2335 .set_input_transfer_func = dcn10_set_input_transfer_func,
2336 .set_output_transfer_func = dcn10_set_output_transfer_func,
2337 .power_down = dce110_power_down,
2338 .enable_accelerated_mode = dce110_enable_accelerated_mode,
2339 .enable_timing_synchronization = dcn10_enable_timing_synchronization,
2340 .enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,
2341 .update_info_frame = dce110_update_info_frame,
2342 .enable_stream = dce110_enable_stream,
2343 .disable_stream = dce110_disable_stream,
2344 .unblank_stream = dce110_unblank_stream,
2345 .enable_display_power_gating = dcn10_dummy_display_power_gating,
2346 .disable_plane = dcn10_disable_plane,
2347 .pipe_control_lock = dcn10_pipe_control_lock,
2348 .set_bandwidth = dcn10_set_bandwidth,
2349 .reset_hw_ctx_wrap = reset_hw_ctx_wrap,
2350 .prog_pixclk_crtc_otg = dcn10_prog_pixclk_crtc_otg,
2352 .get_position = get_position,
2353 .set_static_screen_control = set_static_screen_control,
2354 .setup_stereo = dcn10_setup_stereo,
2355 .set_avmute = dce110_set_avmute,
2356 .log_hw_state = dcn10_log_hw_state,
2357 .wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
2358 .ready_shared_resources = ready_shared_resources,
2359 .optimize_shared_resources = optimize_shared_resources,
2360 .pplib_apply_display_requirements =
2361 dcn10_pplib_apply_display_requirements,
2362 .edp_backlight_control = hwss_edp_backlight_control,
2363 .edp_power_control = hwss_edp_power_control,
2364 .edp_wait_for_hpd_ready = hwss_edp_wait_for_hpd_ready,
2368 void dcn10_hw_sequencer_construct(struct dc *dc)
2370 dc->hwss = dcn10_funcs;