drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27 #include "core_types.h"
  28 #include "resource.h"
  29 #include "custom_float.h"
  30 #include "dcn10_hw_sequencer.h"
  31 #include "dce110/dce110_hw_sequencer.h"
  32 #include "dce/dce_hwseq.h"
  33 #include "abm.h"
  34 #include "dmcu.h"
  35 #include "dcn10_optc.h"
  36 #include "dcn10/dcn10_dpp.h"
  37 #include "dcn10/dcn10_mpc.h"
  38 #include "timing_generator.h"
  39 #include "opp.h"
  40 #include "ipp.h"
  41 #include "mpc.h"
  42 #include "reg_helper.h"
  43 #include "custom_float.h"
  44 #include "dcn10_hubp.h"
  45 #include "dcn10_hubbub.h"
  46 #include "dcn10_cm_common.h"
  47
  48 #define DC_LOGGER \
  49         ctx->logger
  50 #define CTX \
  51         hws->ctx
  52 #define REG(reg)\
  53         hws->regs->reg
  54
  55 #undef FN
  56 #define FN(reg_name, field_name) \
  57         hws->shifts->field_name, hws->masks->field_name
  58
  59 #define DTN_INFO_MICRO_SEC(ref_cycle) \
  60         print_microsec(dc_ctx, ref_cycle)
  61
  62 void print_microsec(struct dc_context *dc_ctx, uint32_t ref_cycle)
  63 {
  64         static const uint32_t ref_clk_mhz = 48;
  65         static const unsigned int frac = 10;
  66         uint32_t us_x10 = (ref_cycle * frac) / ref_clk_mhz;
  67
  68         DTN_INFO("%d.%d \t ",
  69                         us_x10 / frac,
  70                         us_x10 % frac);
  71 }
  72
  73
  74 static void log_mpc_crc(struct dc *dc)
  75 {
  76         struct dc_context *dc_ctx = dc->ctx;
  77         struct dce_hwseq *hws = dc->hwseq;
  78
  79         if (REG(MPC_CRC_RESULT_GB))
  80                 DTN_INFO("MPC_CRC_RESULT_GB:%d MPC_CRC_RESULT_C:%d MPC_CRC_RESULT_AR:%d\n",
  81                 REG_READ(MPC_CRC_RESULT_GB), REG_READ(MPC_CRC_RESULT_C), REG_READ(MPC_CRC_RESULT_AR));
  82         if (REG(DPP_TOP0_DPP_CRC_VAL_B_A))
  83                 DTN_INFO("DPP_TOP0_DPP_CRC_VAL_B_A:%d DPP_TOP0_DPP_CRC_VAL_R_G:%d\n",
  84                 REG_READ(DPP_TOP0_DPP_CRC_VAL_B_A), REG_READ(DPP_TOP0_DPP_CRC_VAL_R_G));
  85 }
  86
  87 void dcn10_log_hubbub_state(struct dc *dc)
  88 {
  89         struct dc_context *dc_ctx = dc->ctx;
  90         struct dcn_hubbub_wm wm;
  91         int i;
  92
  93         hubbub1_wm_read_state(dc->res_pool->hubbub, &wm);
  94
  95         DTN_INFO("HUBBUB WM: \t data_urgent \t pte_meta_urgent \t "
  96                         "sr_enter \t sr_exit \t dram_clk_change \n");
  97
  98         for (i = 0; i < 4; i++) {
  99                 struct dcn_hubbub_wm_set *s;
 100
 101                 s = &wm.sets[i];
 102                 DTN_INFO("WM_Set[%d]:\t ", s->wm_set);
 103                 DTN_INFO_MICRO_SEC(s->data_urgent);
 104                 DTN_INFO_MICRO_SEC(s->pte_meta_urgent);
 105                 DTN_INFO_MICRO_SEC(s->sr_enter);
 106                 DTN_INFO_MICRO_SEC(s->sr_exit);
 107                 DTN_INFO_MICRO_SEC(s->dram_clk_chanage);
 108                 DTN_INFO("\n");
 109         }
 110
 111         DTN_INFO("\n");
 112 }
 113
 114 void dcn10_log_hw_state(struct dc *dc)
 115 {
 116         struct dc_context *dc_ctx = dc->ctx;
 117         struct resource_pool *pool = dc->res_pool;
 118         int i;
 119
 120         DTN_INFO_BEGIN();
 121
 122         dcn10_log_hubbub_state(dc);
 123
 124         DTN_INFO("HUBP:\t format \t addr_hi \t width \t height \t "
 125                         "rotation \t mirror \t  sw_mode \t "
 126                         "dcc_en \t blank_en \t ttu_dis \t underflow \t "
 127                         "min_ttu_vblank \t qos_low_wm \t qos_high_wm \n");
 128
 129         for (i = 0; i < pool->pipe_count; i++) {
 130                 struct hubp *hubp = pool->hubps[i];
 131                 struct dcn_hubp_state s;
 132
 133                 hubp1_read_state(TO_DCN10_HUBP(hubp), &s);
 134
 135                 DTN_INFO("[%d]:\t %xh \t %xh \t %d \t %d \t "
 136                                 "%xh \t %xh \t %xh \t "
 137                                 "%d \t %d \t %d \t %xh \t",
 138                                 hubp->inst,
 139                                 s.pixel_format,
 140                                 s.inuse_addr_hi,
 141                                 s.viewport_width,
 142                                 s.viewport_height,
 143                                 s.rotation_angle,
 144                                 s.h_mirror_en,
 145                                 s.sw_mode,
 146                                 s.dcc_en,
 147                                 s.blank_en,
 148                                 s.ttu_disable,
 149                                 s.underflow_status);
 150                 DTN_INFO_MICRO_SEC(s.min_ttu_vblank);
 151                 DTN_INFO_MICRO_SEC(s.qos_level_low_wm);
 152                 DTN_INFO_MICRO_SEC(s.qos_level_high_wm);
 153                 DTN_INFO("\n");
 154         }
 155         DTN_INFO("\n");
 156
 157         DTN_INFO("OTG:\t v_bs \t v_be \t v_ss \t v_se \t vpol \t vmax \t vmin \t "
 158                         "h_bs \t h_be \t h_ss \t h_se \t hpol \t htot \t vtot \t underflow\n");
 159
 160         for (i = 0; i < pool->timing_generator_count; i++) {
 161                 struct timing_generator *tg = pool->timing_generators[i];
 162                 struct dcn_otg_state s = {0};
 163
 164                 optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s);
 165
 166                 //only print if OTG master is enabled
 167                 if ((s.otg_enabled & 1) == 0)
 168                         continue;
 169
 170                 DTN_INFO("[%d]:\t %d \t %d \t %d \t %d \t "
 171                                 "%d \t %d \t %d \t %d \t %d \t %d \t "
 172                                 "%d \t %d \t %d \t %d \t %d \t ",
 173                                 tg->inst,
 174                                 s.v_blank_start,
 175                                 s.v_blank_end,
 176                                 s.v_sync_a_start,
 177                                 s.v_sync_a_end,
 178                                 s.v_sync_a_pol,
 179                                 s.v_total_max,
 180                                 s.v_total_min,
 181                                 s.h_blank_start,
 182                                 s.h_blank_end,
 183                                 s.h_sync_a_start,
 184                                 s.h_sync_a_end,
 185                                 s.h_sync_a_pol,
 186                                 s.h_total,
 187                                 s.v_total,
 188                                 s.underflow_occurred_status);
 189                 DTN_INFO("\n");
 190         }
 191         DTN_INFO("\n");
 192
 193         log_mpc_crc(dc);
 194
 195         DTN_INFO_END();
 196 }
 197
 198 static void enable_power_gating_plane(
 199         struct dce_hwseq *hws,
 200         bool enable)
 201 {
 202         bool force_on = 1; /* disable power gating */
 203
 204         if (enable)
 205                 force_on = 0;
 206
 207         /* DCHUBP0/1/2/3 */
 208         REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on);
 209         REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on);
 210         REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on);
 211         REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on);
 212
 213         /* DPP0/1/2/3 */
 214         REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on);
 215         REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on);
 216         REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on);
 217         REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);
 218 }
 219
 220 static void disable_vga(
 221         struct dce_hwseq *hws)
 222 {
 223         REG_WRITE(D1VGA_CONTROL, 0);
 224         REG_WRITE(D2VGA_CONTROL, 0);
 225         REG_WRITE(D3VGA_CONTROL, 0);
 226         REG_WRITE(D4VGA_CONTROL, 0);
 227
 228         /* HW Engineer's Notes:
 229          *  During switch from vga->extended, if we set the VGA_TEST_ENABLE and
 230          *  then hit the VGA_TEST_RENDER_START, then the DCHUBP timing gets updated correctly.
 231          *
 232          *  Then vBIOS will have it poll for the VGA_TEST_RENDER_DONE and unset
 233          *  VGA_TEST_ENABLE, to leave it in the same state as before.
 234          */
 235         REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_ENABLE, 1);
 236         REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_RENDER_START, 1);
 237 }
 238
 239 static void dpp_pg_control(
 240                 struct dce_hwseq *hws,
 241                 unsigned int dpp_inst,
 242                 bool power_on)
 243 {
 244         uint32_t power_gate = power_on ? 0 : 1;
 245         uint32_t pwr_status = power_on ? 0 : 2;
 246
 247         if (hws->ctx->dc->debug.disable_dpp_power_gate)
 248                 return;
 249
 250         switch (dpp_inst) {
 251         case 0: /* DPP0 */
 252                 REG_UPDATE(DOMAIN1_PG_CONFIG,
 253                                 DOMAIN1_POWER_GATE, power_gate);
 254
 255                 REG_WAIT(DOMAIN1_PG_STATUS,
 256                                 DOMAIN1_PGFSM_PWR_STATUS, pwr_status,
 257                                 1, 1000);
 258                 break;
 259         case 1: /* DPP1 */
 260                 REG_UPDATE(DOMAIN3_PG_CONFIG,
 261                                 DOMAIN3_POWER_GATE, power_gate);
 262
 263                 REG_WAIT(DOMAIN3_PG_STATUS,
 264                                 DOMAIN3_PGFSM_PWR_STATUS, pwr_status,
 265                                 1, 1000);
 266                 break;
 267         case 2: /* DPP2 */
 268                 REG_UPDATE(DOMAIN5_PG_CONFIG,
 269                                 DOMAIN5_POWER_GATE, power_gate);
 270
 271                 REG_WAIT(DOMAIN5_PG_STATUS,
 272                                 DOMAIN5_PGFSM_PWR_STATUS, pwr_status,
 273                                 1, 1000);
 274                 break;
 275         case 3: /* DPP3 */
 276                 REG_UPDATE(DOMAIN7_PG_CONFIG,
 277                                 DOMAIN7_POWER_GATE, power_gate);
 278
 279                 REG_WAIT(DOMAIN7_PG_STATUS,
 280                                 DOMAIN7_PGFSM_PWR_STATUS, pwr_status,
 281                                 1, 1000);
 282                 break;
 283         default:
 284                 BREAK_TO_DEBUGGER();
 285                 break;
 286         }
 287 }
 288
 289 static void hubp_pg_control(
 290                 struct dce_hwseq *hws,
 291                 unsigned int hubp_inst,
 292                 bool power_on)
 293 {
 294         uint32_t power_gate = power_on ? 0 : 1;
 295         uint32_t pwr_status = power_on ? 0 : 2;
 296
 297         if (hws->ctx->dc->debug.disable_hubp_power_gate)
 298                 return;
 299
 300         switch (hubp_inst) {
 301         case 0: /* DCHUBP0 */
 302                 REG_UPDATE(DOMAIN0_PG_CONFIG,
 303                                 DOMAIN0_POWER_GATE, power_gate);
 304
 305                 REG_WAIT(DOMAIN0_PG_STATUS,
 306                                 DOMAIN0_PGFSM_PWR_STATUS, pwr_status,
 307                                 1, 1000);
 308                 break;
 309         case 1: /* DCHUBP1 */
 310                 REG_UPDATE(DOMAIN2_PG_CONFIG,
 311                                 DOMAIN2_POWER_GATE, power_gate);
 312
 313                 REG_WAIT(DOMAIN2_PG_STATUS,
 314                                 DOMAIN2_PGFSM_PWR_STATUS, pwr_status,
 315                                 1, 1000);
 316                 break;
 317         case 2: /* DCHUBP2 */
 318                 REG_UPDATE(DOMAIN4_PG_CONFIG,
 319                                 DOMAIN4_POWER_GATE, power_gate);
 320
 321                 REG_WAIT(DOMAIN4_PG_STATUS,
 322                                 DOMAIN4_PGFSM_PWR_STATUS, pwr_status,
 323                                 1, 1000);
 324                 break;
 325         case 3: /* DCHUBP3 */
 326                 REG_UPDATE(DOMAIN6_PG_CONFIG,
 327                                 DOMAIN6_POWER_GATE, power_gate);
 328
 329                 REG_WAIT(DOMAIN6_PG_STATUS,
 330                                 DOMAIN6_PGFSM_PWR_STATUS, pwr_status,
 331                                 1, 1000);
 332                 break;
 333         default:
 334                 BREAK_TO_DEBUGGER();
 335                 break;
 336         }
 337 }
 338
 339 static void power_on_plane(
 340         struct dce_hwseq *hws,
 341         int plane_id)
 342 {
 343         struct dc_context *ctx = hws->ctx;
 344         if (REG(DC_IP_REQUEST_CNTL)) {
 345                 REG_SET(DC_IP_REQUEST_CNTL, 0,
 346                                 IP_REQUEST_EN, 1);
 347                 dpp_pg_control(hws, plane_id, true);
 348                 hubp_pg_control(hws, plane_id, true);
 349                 REG_SET(DC_IP_REQUEST_CNTL, 0,
 350                                 IP_REQUEST_EN, 0);
 351                 DC_LOG_DEBUG(
 352                                 "Un-gated front end for pipe %d\n", plane_id);
 353         }
 354 }
 355
 356 static void undo_DEGVIDCN10_253_wa(struct dc *dc)
 357 {
 358         struct dce_hwseq *hws = dc->hwseq;
 359         struct hubp *hubp = dc->res_pool->hubps[0];
 360
 361         if (!hws->wa_state.DEGVIDCN10_253_applied)
 362                 return;
 363
 364         hubp->funcs->set_blank(hubp, true);
 365
 366         REG_SET(DC_IP_REQUEST_CNTL, 0,
 367                         IP_REQUEST_EN, 1);
 368
 369         hubp_pg_control(hws, 0, false);
 370         REG_SET(DC_IP_REQUEST_CNTL, 0,
 371                         IP_REQUEST_EN, 0);
 372
 373         hws->wa_state.DEGVIDCN10_253_applied = false;
 374 }
 375
 376 static void apply_DEGVIDCN10_253_wa(struct dc *dc)
 377 {
 378         struct dce_hwseq *hws = dc->hwseq;
 379         struct hubp *hubp = dc->res_pool->hubps[0];
 380         int i;
 381
 382         if (dc->debug.disable_stutter)
 383                 return;
 384
 385         if (!hws->wa.DEGVIDCN10_253)
 386                 return;
 387
 388         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 389                 if (!dc->res_pool->hubps[i]->power_gated)
 390                         return;
 391         }
 392
 393         /* all pipe power gated, apply work around to enable stutter. */
 394
 395         REG_SET(DC_IP_REQUEST_CNTL, 0,
 396                         IP_REQUEST_EN, 1);
 397
 398         hubp_pg_control(hws, 0, true);
 399         REG_SET(DC_IP_REQUEST_CNTL, 0,
 400                         IP_REQUEST_EN, 0);
 401
 402         hubp->funcs->set_hubp_blank_en(hubp, false);
 403         hws->wa_state.DEGVIDCN10_253_applied = true;
 404 }
 405
 406 static void bios_golden_init(struct dc *dc)
 407 {
 408         struct dc_bios *bp = dc->ctx->dc_bios;
 409         int i;
 410
 411         /* initialize dcn global */
 412         bp->funcs->enable_disp_power_gating(bp,
 413                         CONTROLLER_ID_D0, ASIC_PIPE_INIT);
 414
 415         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 416                 /* initialize dcn per pipe */
 417                 bp->funcs->enable_disp_power_gating(bp,
 418                                 CONTROLLER_ID_D0 + i, ASIC_PIPE_DISABLE);
 419         }
 420 }
 421
 422 static void false_optc_underflow_wa(
 423                 struct dc *dc,
 424                 const struct dc_stream_state *stream,
 425                 struct timing_generator *tg)
 426 {
 427         int i;
 428         bool underflow;
 429
 430         if (!dc->hwseq->wa.false_optc_underflow)
 431                 return;
 432
 433         underflow = tg->funcs->is_optc_underflow_occurred(tg);
 434
 435         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 436                 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
 437
 438                 if (old_pipe_ctx->stream != stream)
 439                         continue;
 440
 441                 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, old_pipe_ctx);
 442         }
 443
 444         tg->funcs->set_blank_data_double_buffer(tg, true);
 445
 446         if (tg->funcs->is_optc_underflow_occurred(tg) && !underflow)
 447                 tg->funcs->clear_optc_underflow(tg);
 448 }
 449
 450 static enum dc_status dcn10_prog_pixclk_crtc_otg(
 451                 struct pipe_ctx *pipe_ctx,
 452                 struct dc_state *context,
 453                 struct dc *dc)
 454 {
 455         struct dc_stream_state *stream = pipe_ctx->stream;
 456         enum dc_color_space color_space;
 457         struct tg_color black_color = {0};
 458
 459         /* by upper caller loop, pipe0 is parent pipe and be called first.
 460          * back end is set up by for pipe0. Other children pipe share back end
 461          * with pipe 0. No program is needed.
 462          */
 463         if (pipe_ctx->top_pipe != NULL)
 464                 return DC_OK;
 465
 466         /* TODO check if timing_changed, disable stream if timing changed */
 467
 468         /* HW program guide assume display already disable
 469          * by unplug sequence. OTG assume stop.
 470          */
 471         pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true);
 472
 473         if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
 474                         pipe_ctx->clock_source,
 475                         &pipe_ctx->stream_res.pix_clk_params,
 476                         &pipe_ctx->pll_settings)) {
 477                 BREAK_TO_DEBUGGER();
 478                 return DC_ERROR_UNEXPECTED;
 479         }
 480         pipe_ctx->stream_res.tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset;
 481         pipe_ctx->stream_res.tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start;
 482         pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset;
 483         pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_width = pipe_ctx->pipe_dlg_param.vupdate_width;
 484
 485         pipe_ctx->stream_res.tg->dlg_otg_param.signal =  pipe_ctx->stream->signal;
 486
 487         pipe_ctx->stream_res.tg->funcs->program_timing(
 488                         pipe_ctx->stream_res.tg,
 489                         &stream->timing,
 490                         true);
 491
 492 #if 0 /* move to after enable_crtc */
 493         /* TODO: OPP FMT, ABM. etc. should be done here. */
 494         /* or FPGA now. instance 0 only. TODO: move to opp.c */
 495
 496         inst_offset = reg_offsets[pipe_ctx->stream_res.tg->inst].fmt;
 497
 498         pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
 499                                 pipe_ctx->stream_res.opp,
 500                                 &stream->bit_depth_params,
 501                                 &stream->clamping);
 502 #endif
 503         /* program otg blank color */
 504         color_space = stream->output_color_space;
 505         color_space_to_black_color(dc, color_space, &black_color);
 506
 507         if (pipe_ctx->stream_res.tg->funcs->set_blank_color)
 508                 pipe_ctx->stream_res.tg->funcs->set_blank_color(
 509                                 pipe_ctx->stream_res.tg,
 510                                 &black_color);
 511
 512         if (pipe_ctx->stream_res.tg->funcs->is_blanked &&
 513                         !pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg)) {
 514                 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);
 515                 hwss_wait_for_blank_complete(pipe_ctx->stream_res.tg);
 516                 false_optc_underflow_wa(dc, pipe_ctx->stream, pipe_ctx->stream_res.tg);
 517         }
 518
 519         /* VTG is  within DCHUB command block. DCFCLK is always on */
 520         if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {
 521                 BREAK_TO_DEBUGGER();
 522                 return DC_ERROR_UNEXPECTED;
 523         }
 524
 525         /* TODO program crtc source select for non-virtual signal*/
 526         /* TODO program FMT */
 527         /* TODO setup link_enc */
 528         /* TODO set stream attributes */
 529         /* TODO program audio */
 530         /* TODO enable stream if timing changed */
 531         /* TODO unblank stream if DP */
 532
 533         return DC_OK;
 534 }
 535
 536 static void reset_back_end_for_pipe(
 537                 struct dc *dc,
 538                 struct pipe_ctx *pipe_ctx,
 539                 struct dc_state *context)
 540 {
 541         int i;
 542         struct dc_context *ctx = dc->ctx;
 543         if (pipe_ctx->stream_res.stream_enc == NULL) {
 544                 pipe_ctx->stream = NULL;
 545                 return;
 546         }
 547
 548         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
 549                 /* DPMS may already disable */
 550                 if (!pipe_ctx->stream->dpms_off)
 551                         core_link_disable_stream(pipe_ctx, FREE_ACQUIRED_RESOURCE);
 552                 else if (pipe_ctx->stream_res.audio) {
 553                         /*
 554                          * if stream is already disabled outside of commit streams path,
 555                          * audio disable was skipped. Need to do it here
 556                          */
 557                         pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
 558
 559                         if (dc->caps.dynamic_audio == true) {
 560                                 /*we have to dynamic arbitrate the audio endpoints*/
 561                                 pipe_ctx->stream_res.audio = NULL;
 562                                 /*we free the resource, need reset is_audio_acquired*/
 563                                 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, pipe_ctx->stream_res.audio, false);
 564                         }
 565
 566                 }
 567
 568         }
 569
 570         /* by upper caller loop, parent pipe: pipe0, will be reset last.
 571          * back end share by all pipes and will be disable only when disable
 572          * parent pipe.
 573          */
 574         if (pipe_ctx->top_pipe == NULL) {
 575                 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
 576
 577                 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
 578         }
 579
 580         for (i = 0; i < dc->res_pool->pipe_count; i++)
 581                 if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx)
 582                         break;
 583
 584         if (i == dc->res_pool->pipe_count)
 585                 return;
 586
 587         pipe_ctx->stream = NULL;
 588         DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n",
 589                                         pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
 590 }
 591
 592 static void dcn10_verify_allow_pstate_change_high(struct dc *dc)
 593 {
 594         static bool should_log_hw_state; /* prevent hw state log by default */
 595
 596         if (!hubbub1_verify_allow_pstate_change_high(dc->res_pool->hubbub)) {
 597                 if (should_log_hw_state) {
 598                         dcn10_log_hw_state(dc);
 599                 }
 600
 601                 BREAK_TO_DEBUGGER();
 602         }
 603 }
 604
 605 /* trigger HW to start disconnect plane from stream on the next vsync */
 606 static void plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx)
 607 {
 608         struct hubp *hubp = pipe_ctx->plane_res.hubp;
 609         int dpp_id = pipe_ctx->plane_res.dpp->inst;
 610         struct mpc *mpc = dc->res_pool->mpc;
 611         struct mpc_tree *mpc_tree_params;
 612         struct mpcc *mpcc_to_remove = NULL;
 613         struct output_pixel_processor *opp = pipe_ctx->stream_res.opp;
 614
 615         mpc_tree_params = &(opp->mpc_tree_params);
 616         mpcc_to_remove = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, dpp_id);
 617
 618         /*Already reset*/
 619         if (mpcc_to_remove == NULL)
 620                 return;
 621
 622         mpc->funcs->remove_mpcc(mpc, mpc_tree_params, mpcc_to_remove);
 623         opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
 624
 625         dc->optimized_required = true;
 626
 627         if (hubp->funcs->hubp_disconnect)
 628                 hubp->funcs->hubp_disconnect(hubp);
 629
 630         if (dc->debug.sanity_checks)
 631                 dcn10_verify_allow_pstate_change_high(dc);
 632 }
 633
 634 static void plane_atomic_power_down(struct dc *dc, struct pipe_ctx *pipe_ctx)
 635 {
 636         struct dce_hwseq *hws = dc->hwseq;
 637         struct dpp *dpp = pipe_ctx->plane_res.dpp;
 638         struct dc_context *ctx = dc->ctx;
 639
 640         if (REG(DC_IP_REQUEST_CNTL)) {
 641                 REG_SET(DC_IP_REQUEST_CNTL, 0,
 642                                 IP_REQUEST_EN, 1);
 643                 dpp_pg_control(hws, dpp->inst, false);
 644                 hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, false);
 645                 dpp->funcs->dpp_reset(dpp);
 646                 REG_SET(DC_IP_REQUEST_CNTL, 0,
 647                                 IP_REQUEST_EN, 0);
 648                 DC_LOG_DEBUG(
 649                                 "Power gated front end %d\n", pipe_ctx->pipe_idx);
 650         }
 651 }
 652
 653 /* disable HW used by plane.
 654  * note:  cannot disable until disconnect is complete
 655  */
 656 static void plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
 657 {
 658         struct hubp *hubp = pipe_ctx->plane_res.hubp;
 659         struct dpp *dpp = pipe_ctx->plane_res.dpp;
 660         int opp_id = hubp->opp_id;
 661
 662         dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);
 663
 664         hubp->funcs->hubp_clk_cntl(hubp, false);
 665
 666         dpp->funcs->dpp_dppclk_control(dpp, false, false);
 667
 668         if (opp_id != 0xf && pipe_ctx->stream_res.opp->mpc_tree_params.opp_list == NULL)
 669                 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
 670                                 pipe_ctx->stream_res.opp,
 671                                 false);
 672
 673         hubp->power_gated = true;
 674         dc->optimized_required = false; /* We're powering off, no need to optimize */
 675
 676         plane_atomic_power_down(dc, pipe_ctx);
 677
 678         pipe_ctx->stream = NULL;
 679         memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res));
 680         memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res));
 681         pipe_ctx->top_pipe = NULL;
 682         pipe_ctx->bottom_pipe = NULL;
 683         pipe_ctx->plane_state = NULL;
 684 }
 685
 686 static void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
 687 {
 688         struct dc_context *ctx = dc->ctx;
 689
 690         if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)
 691                 return;
 692
 693         plane_atomic_disable(dc, pipe_ctx);
 694
 695         apply_DEGVIDCN10_253_wa(dc);
 696
 697         DC_LOG_DC("Power down front end %d\n",
 698                                         pipe_ctx->pipe_idx);
 699 }
 700
 701 static void dcn10_init_hw(struct dc *dc)
 702 {
 703         int i;
 704         struct abm *abm = dc->res_pool->abm;
 705         struct dmcu *dmcu = dc->res_pool->dmcu;
 706         struct dce_hwseq *hws = dc->hwseq;
 707         struct dc_bios *dcb = dc->ctx->dc_bios;
 708         struct dc_state  *context = dc->current_state;
 709
 710         if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
 711                 REG_WRITE(REFCLK_CNTL, 0);
 712                 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
 713                 REG_WRITE(DIO_MEM_PWR_CTRL, 0);
 714
 715                 if (!dc->debug.disable_clock_gate) {
 716                         /* enable all DCN clock gating */
 717                         REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
 718
 719                         REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
 720
 721                         REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
 722                 }
 723
 724                 enable_power_gating_plane(dc->hwseq, true);
 725         } else {
 726
 727                 if (!dcb->funcs->is_accelerated_mode(dcb)) {
 728                         bios_golden_init(dc);
 729                         disable_vga(dc->hwseq);
 730                 }
 731
 732                 for (i = 0; i < dc->link_count; i++) {
 733                         /* Power up AND update implementation according to the
 734                          * required signal (which may be different from the
 735                          * default signal on connector).
 736                          */
 737                         struct dc_link *link = dc->links[i];
 738
 739                         if (link->link_enc->connector.id == CONNECTOR_ID_EDP)
 740                                 dc->hwss.edp_power_control(link, true);
 741
 742                         link->link_enc->funcs->hw_init(link->link_enc);
 743                 }
 744         }
 745
 746         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 747                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
 748
 749                 if (tg->funcs->is_tg_enabled(tg))
 750                         tg->funcs->lock(tg);
 751         }
 752
 753         /* Blank controller using driver code instead of
 754          * command table.
 755          */
 756         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 757                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
 758
 759                 if (tg->funcs->is_tg_enabled(tg)) {
 760                         tg->funcs->set_blank(tg, true);
 761                         hwss_wait_for_blank_complete(tg);
 762                 }
 763         }
 764
 765         /* Reset all MPCC muxes */
 766         dc->res_pool->mpc->funcs->mpc_init(dc->res_pool->mpc);
 767
 768         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 769                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
 770                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
 771                 struct hubp *hubp = dc->res_pool->hubps[i];
 772                 struct dpp *dpp = dc->res_pool->dpps[i];
 773
 774                 pipe_ctx->stream_res.tg = tg;
 775                 pipe_ctx->pipe_idx = i;
 776
 777                 pipe_ctx->plane_res.hubp = hubp;
 778                 pipe_ctx->plane_res.dpp = dpp;
 779                 pipe_ctx->plane_res.mpcc_inst = dpp->inst;
 780                 hubp->mpcc_id = dpp->inst;
 781                 hubp->opp_id = 0xf;
 782                 hubp->power_gated = false;
 783
 784                 dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
 785                 dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
 786                 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
 787                 pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
 788
 789                 plane_atomic_disconnect(dc, pipe_ctx);
 790         }
 791
 792         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 793                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
 794
 795                 if (tg->funcs->is_tg_enabled(tg))
 796                         tg->funcs->unlock(tg);
 797         }
 798
 799         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 800                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
 801                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
 802
 803                 dcn10_disable_plane(dc, pipe_ctx);
 804
 805                 pipe_ctx->stream_res.tg = NULL;
 806                 pipe_ctx->plane_res.hubp = NULL;
 807
 808                 tg->funcs->tg_init(tg);
 809         }
 810
 811         /* end of FPGA. Below if real ASIC */
 812         if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
 813                 return;
 814
 815         for (i = 0; i < dc->res_pool->audio_count; i++) {
 816                 struct audio *audio = dc->res_pool->audios[i];
 817
 818                 audio->funcs->hw_init(audio);
 819         }
 820
 821         if (abm != NULL) {
 822                 abm->funcs->init_backlight(abm);
 823                 abm->funcs->abm_init(abm);
 824         }
 825
 826         if (dmcu != NULL)
 827                 dmcu->funcs->dmcu_init(dmcu);
 828
 829         /* power AFMT HDMI memory TODO: may move to dis/en output save power*/
 830         REG_WRITE(DIO_MEM_PWR_CTRL, 0);
 831
 832         if (!dc->debug.disable_clock_gate) {
 833                 /* enable all DCN clock gating */
 834                 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
 835
 836                 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
 837
 838                 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
 839         }
 840
 841         enable_power_gating_plane(dc->hwseq, true);
 842 }
 843
 844 static void reset_hw_ctx_wrap(
 845                 struct dc *dc,
 846                 struct dc_state *context)
 847 {
 848         int i;
 849
 850         /* Reset Back End*/
 851         for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
 852                 struct pipe_ctx *pipe_ctx_old =
 853                         &dc->current_state->res_ctx.pipe_ctx[i];
 854                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
 855
 856                 if (!pipe_ctx_old->stream)
 857                         continue;
 858
 859                 if (pipe_ctx_old->top_pipe)
 860                         continue;
 861
 862                 if (!pipe_ctx->stream ||
 863                                 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
 864                         struct clock_source *old_clk = pipe_ctx_old->clock_source;
 865
 866                         reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
 867                         if (old_clk)
 868                                 old_clk->funcs->cs_power_down(old_clk);
 869                 }
 870         }
 871
 872 }
 873
 874 static bool patch_address_for_sbs_tb_stereo(
 875                 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr)
 876 {
 877         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
 878         bool sec_split = pipe_ctx->top_pipe &&
 879                         pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
 880         if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
 881                 (pipe_ctx->stream->timing.timing_3d_format ==
 882                  TIMING_3D_FORMAT_SIDE_BY_SIDE ||
 883                  pipe_ctx->stream->timing.timing_3d_format ==
 884                  TIMING_3D_FORMAT_TOP_AND_BOTTOM)) {
 885                 *addr = plane_state->address.grph_stereo.left_addr;
 886                 plane_state->address.grph_stereo.left_addr =
 887                 plane_state->address.grph_stereo.right_addr;
 888                 return true;
 889         } else {
 890                 if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE &&
 891                         plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) {
 892                         plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO;
 893                         plane_state->address.grph_stereo.right_addr =
 894                         plane_state->address.grph_stereo.left_addr;
 895                 }
 896         }
 897         return false;
 898 }
 899
 900
 901
 902 static void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)
 903 {
 904         bool addr_patched = false;
 905         PHYSICAL_ADDRESS_LOC addr;
 906         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
 907
 908         if (plane_state == NULL)
 909                 return;
 910         addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);
 911         pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(
 912                         pipe_ctx->plane_res.hubp,
 913                         &plane_state->address,
 914                         plane_state->flip_immediate);
 915         plane_state->status.requested_address = plane_state->address;
 916         if (addr_patched)
 917                 pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;
 918 }
 919
 920 static bool dcn10_set_input_transfer_func(struct pipe_ctx *pipe_ctx,
 921                                           const struct dc_plane_state *plane_state)
 922 {
 923         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
 924         const struct dc_transfer_func *tf = NULL;
 925         bool result = true;
 926
 927         if (dpp_base == NULL)
 928                 return false;
 929
 930         if (plane_state->in_transfer_func)
 931                 tf = plane_state->in_transfer_func;
 932
 933         if (plane_state->gamma_correction &&
 934                 plane_state->gamma_correction->is_identity)
 935                 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
 936         else if (plane_state->gamma_correction && dce_use_lut(plane_state->format))
 937                 dpp_base->funcs->dpp_program_input_lut(dpp_base, plane_state->gamma_correction);
 938
 939         if (tf == NULL)
 940                 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
 941         else if (tf->type == TF_TYPE_PREDEFINED) {
 942                 switch (tf->tf) {
 943                 case TRANSFER_FUNCTION_SRGB:
 944                         dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_sRGB);
 945                         break;
 946                 case TRANSFER_FUNCTION_BT709:
 947                         dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_xvYCC);
 948                         break;
 949                 case TRANSFER_FUNCTION_LINEAR:
 950                         dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
 951                         break;
 952                 case TRANSFER_FUNCTION_PQ:
 953                 default:
 954                         result = false;
 955                         break;
 956                 }
 957         } else if (tf->type == TF_TYPE_BYPASS) {
 958                 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
 959         } else {
 960                 /*TF_TYPE_DISTRIBUTED_POINTS*/
 961                 result = false;
 962         }
 963
 964         return result;
 965 }
 966
 967
 968
 969
 970
 971 static bool
 972 dcn10_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
 973                                const struct dc_stream_state *stream)
 974 {
 975         struct dpp *dpp = pipe_ctx->plane_res.dpp;
 976
 977         if (dpp == NULL)
 978                 return false;
 979
 980         dpp->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
 981
 982         if (stream->out_transfer_func &&
 983             stream->out_transfer_func->type == TF_TYPE_PREDEFINED &&
 984             stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB)
 985                 dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_SRGB);
 986
 987         /* dcn10_translate_regamma_to_hw_format takes 750us, only do it when full
 988          * update.
 989          */
 990         else if (cm_helper_translate_curve_to_hw_format(
 991                         stream->out_transfer_func,
 992                         &dpp->regamma_params, false)) {
 993                 dpp->funcs->dpp_program_regamma_pwl(
 994                                 dpp,
 995                                 &dpp->regamma_params, OPP_REGAMMA_USER);
 996         } else
 997                 dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_BYPASS);
 998
 999         return true;
1000 }
1001
1002 static void dcn10_pipe_control_lock(
1003         struct dc *dc,
1004         struct pipe_ctx *pipe,
1005         bool lock)
1006 {
1007         /* use TG master update lock to lock everything on the TG
1008          * therefore only top pipe need to lock
1009          */
1010         if (pipe->top_pipe)
1011                 return;
1012
1013         if (dc->debug.sanity_checks)
1014                 dcn10_verify_allow_pstate_change_high(dc);
1015
1016         if (lock)
1017                 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);
1018         else
1019                 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);
1020
1021         if (dc->debug.sanity_checks)
1022                 dcn10_verify_allow_pstate_change_high(dc);
1023 }
1024
1025 static bool wait_for_reset_trigger_to_occur(
1026         struct dc_context *dc_ctx,
1027         struct timing_generator *tg)
1028 {
1029         bool rc = false;
1030
1031         /* To avoid endless loop we wait at most
1032          * frames_to_wait_on_triggered_reset frames for the reset to occur. */
1033         const uint32_t frames_to_wait_on_triggered_reset = 10;
1034         int i;
1035
1036         for (i = 0; i < frames_to_wait_on_triggered_reset; i++) {
1037
1038                 if (!tg->funcs->is_counter_moving(tg)) {
1039                         DC_ERROR("TG counter is not moving!\n");
1040                         break;
1041                 }
1042
1043                 if (tg->funcs->did_triggered_reset_occur(tg)) {
1044                         rc = true;
1045                         /* usually occurs at i=1 */
1046                         DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",
1047                                         i);
1048                         break;
1049                 }
1050
1051                 /* Wait for one frame. */
1052                 tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);
1053                 tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
1054         }
1055
1056         if (false == rc)
1057                 DC_ERROR("GSL: Timeout on reset trigger!\n");
1058
1059         return rc;
1060 }
1061
1062 static void dcn10_enable_timing_synchronization(
1063         struct dc *dc,
1064         int group_index,
1065         int group_size,
1066         struct pipe_ctx *grouped_pipes[])
1067 {
1068         struct dc_context *dc_ctx = dc->ctx;
1069         int i;
1070
1071         DC_SYNC_INFO("Setting up OTG reset trigger\n");
1072
1073         for (i = 1; i < group_size; i++)
1074                 grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger(
1075                                 grouped_pipes[i]->stream_res.tg,
1076                                 grouped_pipes[0]->stream_res.tg->inst);
1077
1078         DC_SYNC_INFO("Waiting for trigger\n");
1079
1080         /* Need to get only check 1 pipe for having reset as all the others are
1081          * synchronized. Look at last pipe programmed to reset.
1082          */
1083
1084         wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[1]->stream_res.tg);
1085         for (i = 1; i < group_size; i++)
1086                 grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(
1087                                 grouped_pipes[i]->stream_res.tg);
1088
1089         DC_SYNC_INFO("Sync complete\n");
1090 }
1091
1092 static void dcn10_enable_per_frame_crtc_position_reset(
1093         struct dc *dc,
1094         int group_size,
1095         struct pipe_ctx *grouped_pipes[])
1096 {
1097         struct dc_context *dc_ctx = dc->ctx;
1098         int i;
1099
1100         DC_SYNC_INFO("Setting up\n");
1101         for (i = 0; i < group_size; i++)
1102                 grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset(
1103                                 grouped_pipes[i]->stream_res.tg,
1104                                 grouped_pipes[i]->stream->triggered_crtc_reset.event_source->status.primary_otg_inst,
1105                                 &grouped_pipes[i]->stream->triggered_crtc_reset);
1106
1107         DC_SYNC_INFO("Waiting for trigger\n");
1108
1109         for (i = 0; i < group_size; i++)
1110                 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
1111
1112         DC_SYNC_INFO("Multi-display sync is complete\n");
1113 }
1114
1115 /*static void print_rq_dlg_ttu(
1116                 struct dc *core_dc,
1117                 struct pipe_ctx *pipe_ctx)
1118 {
1119         DC_LOG_BANDWIDTH_CALCS(core_dc->ctx->logger,
1120                         "\n============== DML TTU Output parameters [%d] ==============\n"
1121                         "qos_level_low_wm: %d, \n"
1122                         "qos_level_high_wm: %d, \n"
1123                         "min_ttu_vblank: %d, \n"
1124                         "qos_level_flip: %d, \n"
1125                         "refcyc_per_req_delivery_l: %d, \n"
1126                         "qos_level_fixed_l: %d, \n"
1127                         "qos_ramp_disable_l: %d, \n"
1128                         "refcyc_per_req_delivery_pre_l: %d, \n"
1129                         "refcyc_per_req_delivery_c: %d, \n"
1130                         "qos_level_fixed_c: %d, \n"
1131                         "qos_ramp_disable_c: %d, \n"
1132                         "refcyc_per_req_delivery_pre_c: %d\n"
1133                         "=============================================================\n",
1134                         pipe_ctx->pipe_idx,
1135                         pipe_ctx->ttu_regs.qos_level_low_wm,
1136                         pipe_ctx->ttu_regs.qos_level_high_wm,
1137                         pipe_ctx->ttu_regs.min_ttu_vblank,
1138                         pipe_ctx->ttu_regs.qos_level_flip,
1139                         pipe_ctx->ttu_regs.refcyc_per_req_delivery_l,
1140                         pipe_ctx->ttu_regs.qos_level_fixed_l,
1141                         pipe_ctx->ttu_regs.qos_ramp_disable_l,
1142                         pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_l,
1143                         pipe_ctx->ttu_regs.refcyc_per_req_delivery_c,
1144                         pipe_ctx->ttu_regs.qos_level_fixed_c,
1145                         pipe_ctx->ttu_regs.qos_ramp_disable_c,
1146                         pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_c
1147                         );
1148
1149         DC_LOG_BANDWIDTH_CALCS(core_dc->ctx->logger,
1150                         "\n============== DML DLG Output parameters [%d] ==============\n"
1151                         "refcyc_h_blank_end: %d, \n"
1152                         "dlg_vblank_end: %d, \n"
1153                         "min_dst_y_next_start: %d, \n"
1154                         "refcyc_per_htotal: %d, \n"
1155                         "refcyc_x_after_scaler: %d, \n"
1156                         "dst_y_after_scaler: %d, \n"
1157                         "dst_y_prefetch: %d, \n"
1158                         "dst_y_per_vm_vblank: %d, \n"
1159                         "dst_y_per_row_vblank: %d, \n"
1160                         "ref_freq_to_pix_freq: %d, \n"
1161                         "vratio_prefetch: %d, \n"
1162                         "refcyc_per_pte_group_vblank_l: %d, \n"
1163                         "refcyc_per_meta_chunk_vblank_l: %d, \n"
1164                         "dst_y_per_pte_row_nom_l: %d, \n"
1165                         "refcyc_per_pte_group_nom_l: %d, \n",
1166                         pipe_ctx->pipe_idx,
1167                         pipe_ctx->dlg_regs.refcyc_h_blank_end,
1168                         pipe_ctx->dlg_regs.dlg_vblank_end,
1169                         pipe_ctx->dlg_regs.min_dst_y_next_start,
1170                         pipe_ctx->dlg_regs.refcyc_per_htotal,
1171                         pipe_ctx->dlg_regs.refcyc_x_after_scaler,
1172                         pipe_ctx->dlg_regs.dst_y_after_scaler,
1173                         pipe_ctx->dlg_regs.dst_y_prefetch,
1174                         pipe_ctx->dlg_regs.dst_y_per_vm_vblank,
1175                         pipe_ctx->dlg_regs.dst_y_per_row_vblank,
1176                         pipe_ctx->dlg_regs.ref_freq_to_pix_freq,
1177                         pipe_ctx->dlg_regs.vratio_prefetch,
1178                         pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_l,
1179                         pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_l,
1180                         pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_l,
1181                         pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_l
1182                         );
1183
1184         DC_LOG_BANDWIDTH_CALCS(core_dc->ctx->logger,
1185                         "\ndst_y_per_meta_row_nom_l: %d, \n"
1186                         "refcyc_per_meta_chunk_nom_l: %d, \n"
1187                         "refcyc_per_line_delivery_pre_l: %d, \n"
1188                         "refcyc_per_line_delivery_l: %d, \n"
1189                         "vratio_prefetch_c: %d, \n"
1190                         "refcyc_per_pte_group_vblank_c: %d, \n"
1191                         "refcyc_per_meta_chunk_vblank_c: %d, \n"
1192                         "dst_y_per_pte_row_nom_c: %d, \n"
1193                         "refcyc_per_pte_group_nom_c: %d, \n"
1194                         "dst_y_per_meta_row_nom_c: %d, \n"
1195                         "refcyc_per_meta_chunk_nom_c: %d, \n"
1196                         "refcyc_per_line_delivery_pre_c: %d, \n"
1197                         "refcyc_per_line_delivery_c: %d \n"
1198                         "========================================================\n",
1199                         pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_l,
1200                         pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_l,
1201                         pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_l,
1202                         pipe_ctx->dlg_regs.refcyc_per_line_delivery_l,
1203                         pipe_ctx->dlg_regs.vratio_prefetch_c,
1204                         pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_c,
1205                         pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_c,
1206                         pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_c,
1207                         pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_c,
1208                         pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_c,
1209                         pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_c,
1210                         pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_c,
1211                         pipe_ctx->dlg_regs.refcyc_per_line_delivery_c
1212                         );
1213
1214         DC_LOG_BANDWIDTH_CALCS(core_dc->ctx->logger,
1215                         "\n============== DML RQ Output parameters [%d] ==============\n"
1216                         "chunk_size: %d \n"
1217                         "min_chunk_size: %d \n"
1218                         "meta_chunk_size: %d \n"
1219                         "min_meta_chunk_size: %d \n"
1220                         "dpte_group_size: %d \n"
1221                         "mpte_group_size: %d \n"
1222                         "swath_height: %d \n"
1223                         "pte_row_height_linear: %d \n"
1224                         "========================================================\n",
1225                         pipe_ctx->pipe_idx,
1226                         pipe_ctx->rq_regs.rq_regs_l.chunk_size,
1227                         pipe_ctx->rq_regs.rq_regs_l.min_chunk_size,
1228                         pipe_ctx->rq_regs.rq_regs_l.meta_chunk_size,
1229                         pipe_ctx->rq_regs.rq_regs_l.min_meta_chunk_size,
1230                         pipe_ctx->rq_regs.rq_regs_l.dpte_group_size,
1231                         pipe_ctx->rq_regs.rq_regs_l.mpte_group_size,
1232                         pipe_ctx->rq_regs.rq_regs_l.swath_height,
1233                         pipe_ctx->rq_regs.rq_regs_l.pte_row_height_linear
1234                         );
1235 }
1236 */
1237
1238 static void mmhub_read_vm_system_aperture_settings(struct dcn10_hubp *hubp1,
1239                 struct vm_system_aperture_param *apt,
1240                 struct dce_hwseq *hws)
1241 {
1242         PHYSICAL_ADDRESS_LOC physical_page_number;
1243         uint32_t logical_addr_low;
1244         uint32_t logical_addr_high;
1245
1246         REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
1247                         PHYSICAL_PAGE_NUMBER_MSB, &physical_page_number.high_part);
1248         REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
1249                         PHYSICAL_PAGE_NUMBER_LSB, &physical_page_number.low_part);
1250
1251         REG_GET(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1252                         LOGICAL_ADDR, &logical_addr_low);
1253
1254         REG_GET(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1255                         LOGICAL_ADDR, &logical_addr_high);
1256
1257         apt->sys_default.quad_part =  physical_page_number.quad_part << 12;
1258         apt->sys_low.quad_part =  (int64_t)logical_addr_low << 18;
1259         apt->sys_high.quad_part =  (int64_t)logical_addr_high << 18;
1260 }
1261
1262 /* Temporary read settings, future will get values from kmd directly */
1263 static void mmhub_read_vm_context0_settings(struct dcn10_hubp *hubp1,
1264                 struct vm_context0_param *vm0,
1265                 struct dce_hwseq *hws)
1266 {
1267         PHYSICAL_ADDRESS_LOC fb_base;
1268         PHYSICAL_ADDRESS_LOC fb_offset;
1269         uint32_t fb_base_value;
1270         uint32_t fb_offset_value;
1271
1272         REG_GET(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, &fb_base_value);
1273         REG_GET(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, &fb_offset_value);
1274
1275         REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
1276                         PAGE_DIRECTORY_ENTRY_HI32, &vm0->pte_base.high_part);
1277         REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
1278                         PAGE_DIRECTORY_ENTRY_LO32, &vm0->pte_base.low_part);
1279
1280         REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
1281                         LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_start.high_part);
1282         REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
1283                         LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_start.low_part);
1284
1285         REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
1286                         LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_end.high_part);
1287         REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
1288                         LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_end.low_part);
1289
1290         REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
1291                         PHYSICAL_PAGE_ADDR_HI4, &vm0->fault_default.high_part);
1292         REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
1293                         PHYSICAL_PAGE_ADDR_LO32, &vm0->fault_default.low_part);
1294
1295         /*
1296          * The values in VM_CONTEXT0_PAGE_TABLE_BASE_ADDR is in UMA space.
1297          * Therefore we need to do
1298          * DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
1299          * - DCHUBBUB_SDPIF_FB_OFFSET + DCHUBBUB_SDPIF_FB_BASE
1300          */
1301         fb_base.quad_part = (uint64_t)fb_base_value << 24;
1302         fb_offset.quad_part = (uint64_t)fb_offset_value << 24;
1303         vm0->pte_base.quad_part += fb_base.quad_part;
1304         vm0->pte_base.quad_part -= fb_offset.quad_part;
1305 }
1306
1307
1308 static void dcn10_program_pte_vm(struct dce_hwseq *hws, struct hubp *hubp)
1309 {
1310         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
1311         struct vm_system_aperture_param apt = { {{ 0 } } };
1312         struct vm_context0_param vm0 = { { { 0 } } };
1313
1314         mmhub_read_vm_system_aperture_settings(hubp1, &apt, hws);
1315         mmhub_read_vm_context0_settings(hubp1, &vm0, hws);
1316
1317         hubp->funcs->hubp_set_vm_system_aperture_settings(hubp, &apt);
1318         hubp->funcs->hubp_set_vm_context0_settings(hubp, &vm0);
1319 }
1320
1321 static void dcn10_enable_plane(
1322         struct dc *dc,
1323         struct pipe_ctx *pipe_ctx,
1324         struct dc_state *context)
1325 {
1326         struct dce_hwseq *hws = dc->hwseq;
1327
1328         if (dc->debug.sanity_checks) {
1329                 dcn10_verify_allow_pstate_change_high(dc);
1330         }
1331
1332         undo_DEGVIDCN10_253_wa(dc);
1333
1334         power_on_plane(dc->hwseq,
1335                 pipe_ctx->plane_res.hubp->inst);
1336
1337         /* enable DCFCLK current DCHUB */
1338         pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);
1339
1340         /* make sure OPP_PIPE_CLOCK_EN = 1 */
1341         pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
1342                         pipe_ctx->stream_res.opp,
1343                         true);
1344
1345 /* TODO: enable/disable in dm as per update type.
1346         if (plane_state) {
1347                 DC_LOG_DC(dc->ctx->logger,
1348                                 "Pipe:%d 0x%x: addr hi:0x%x, "
1349                                 "addr low:0x%x, "
1350                                 "src: %d, %d, %d,"
1351                                 " %d; dst: %d, %d, %d, %d;\n",
1352                                 pipe_ctx->pipe_idx,
1353                                 plane_state,
1354                                 plane_state->address.grph.addr.high_part,
1355                                 plane_state->address.grph.addr.low_part,
1356                                 plane_state->src_rect.x,
1357                                 plane_state->src_rect.y,
1358                                 plane_state->src_rect.width,
1359                                 plane_state->src_rect.height,
1360                                 plane_state->dst_rect.x,
1361                                 plane_state->dst_rect.y,
1362                                 plane_state->dst_rect.width,
1363                                 plane_state->dst_rect.height);
1364
1365                 DC_LOG_DC(dc->ctx->logger,
1366                                 "Pipe %d: width, height, x, y         format:%d\n"
1367                                 "viewport:%d, %d, %d, %d\n"
1368                                 "recout:  %d, %d, %d, %d\n",
1369                                 pipe_ctx->pipe_idx,
1370                                 plane_state->format,
1371                                 pipe_ctx->plane_res.scl_data.viewport.width,
1372                                 pipe_ctx->plane_res.scl_data.viewport.height,
1373                                 pipe_ctx->plane_res.scl_data.viewport.x,
1374                                 pipe_ctx->plane_res.scl_data.viewport.y,
1375                                 pipe_ctx->plane_res.scl_data.recout.width,
1376                                 pipe_ctx->plane_res.scl_data.recout.height,
1377                                 pipe_ctx->plane_res.scl_data.recout.x,
1378                                 pipe_ctx->plane_res.scl_data.recout.y);
1379                 print_rq_dlg_ttu(dc, pipe_ctx);
1380         }
1381 */
1382         if (dc->config.gpu_vm_support)
1383                 dcn10_program_pte_vm(hws, pipe_ctx->plane_res.hubp);
1384
1385         if (dc->debug.sanity_checks) {
1386                 dcn10_verify_allow_pstate_change_high(dc);
1387         }
1388 }
1389
1390 static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
1391 {
1392         int i = 0;
1393         struct dpp_grph_csc_adjustment adjust;
1394         memset(&adjust, 0, sizeof(adjust));
1395         adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
1396
1397
1398         if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
1399                 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
1400                 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
1401                         adjust.temperature_matrix[i] =
1402                                 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
1403         }
1404
1405         pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp, &adjust);
1406 }
1407
1408
1409 static void program_csc_matrix(struct pipe_ctx *pipe_ctx,
1410                 enum dc_color_space colorspace,
1411                 uint16_t *matrix)
1412 {
1413         if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
1414                         if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment != NULL)
1415                                 pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, matrix);
1416         } else {
1417                 if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default != NULL)
1418                         pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default(pipe_ctx->plane_res.dpp, colorspace);
1419         }
1420 }
1421
1422 static void program_output_csc(struct dc *dc,
1423                 struct pipe_ctx *pipe_ctx,
1424                 enum dc_color_space colorspace,
1425                 uint16_t *matrix,
1426                 int opp_id)
1427 {
1428         if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment != NULL)
1429                 program_csc_matrix(pipe_ctx,
1430                                 colorspace,
1431                                 matrix);
1432 }
1433
1434 static bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
1435 {
1436         if (pipe_ctx->plane_state->visible)
1437                 return true;
1438         if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
1439                 return true;
1440         return false;
1441 }
1442
1443 static bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
1444 {
1445         if (pipe_ctx->plane_state->visible)
1446                 return true;
1447         if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
1448                 return true;
1449         return false;
1450 }
1451
1452 static bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
1453 {
1454         if (pipe_ctx->plane_state->visible)
1455                 return true;
1456         if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
1457                 return true;
1458         if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
1459                 return true;
1460         return false;
1461 }
1462
1463 bool is_rgb_cspace(enum dc_color_space output_color_space)
1464 {
1465         switch (output_color_space) {
1466         case COLOR_SPACE_SRGB:
1467         case COLOR_SPACE_SRGB_LIMITED:
1468         case COLOR_SPACE_2020_RGB_FULLRANGE:
1469         case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
1470         case COLOR_SPACE_ADOBERGB:
1471                 return true;
1472         case COLOR_SPACE_YCBCR601:
1473         case COLOR_SPACE_YCBCR709:
1474         case COLOR_SPACE_YCBCR601_LIMITED:
1475         case COLOR_SPACE_YCBCR709_LIMITED:
1476         case COLOR_SPACE_2020_YCBCR:
1477                 return false;
1478         default:
1479                 /* Add a case to switch */
1480                 BREAK_TO_DEBUGGER();
1481                 return false;
1482         }
1483 }
1484
1485 static void dcn10_get_surface_visual_confirm_color(
1486                 const struct pipe_ctx *pipe_ctx,
1487                 struct tg_color *color)
1488 {
1489         uint32_t color_value = MAX_TG_COLOR_VALUE;
1490
1491         switch (pipe_ctx->plane_res.scl_data.format) {
1492         case PIXEL_FORMAT_ARGB8888:
1493                 /* set boarder color to red */
1494                 color->color_r_cr = color_value;
1495                 break;
1496
1497         case PIXEL_FORMAT_ARGB2101010:
1498                 /* set boarder color to blue */
1499                 color->color_b_cb = color_value;
1500                 break;
1501         case PIXEL_FORMAT_420BPP8:
1502                 /* set boarder color to green */
1503                 color->color_g_y = color_value;
1504                 break;
1505         case PIXEL_FORMAT_420BPP10:
1506                 /* set boarder color to yellow */
1507                 color->color_g_y = color_value;
1508                 color->color_r_cr = color_value;
1509                 break;
1510         case PIXEL_FORMAT_FP16:
1511                 /* set boarder color to white */
1512                 color->color_r_cr = color_value;
1513                 color->color_b_cb = color_value;
1514                 color->color_g_y = color_value;
1515                 break;
1516         default:
1517                 break;
1518         }
1519 }
1520
1521 static uint16_t fixed_point_to_int_frac(
1522         struct fixed31_32 arg,
1523         uint8_t integer_bits,
1524         uint8_t fractional_bits)
1525 {
1526         int32_t numerator;
1527         int32_t divisor = 1 << fractional_bits;
1528
1529         uint16_t result;
1530
1531         uint16_t d = (uint16_t)dal_fixed31_32_floor(
1532                 dal_fixed31_32_abs(
1533                         arg));
1534
1535         if (d <= (uint16_t)(1 << integer_bits) - (1 / (uint16_t)divisor))
1536                 numerator = (uint16_t)dal_fixed31_32_floor(
1537                         dal_fixed31_32_mul_int(
1538                                 arg,
1539                                 divisor));
1540         else {
1541                 numerator = dal_fixed31_32_floor(
1542                         dal_fixed31_32_sub(
1543                                 dal_fixed31_32_from_int(
1544                                         1LL << integer_bits),
1545                                 dal_fixed31_32_recip(
1546                                         dal_fixed31_32_from_int(
1547                                                 divisor))));
1548         }
1549
1550         if (numerator >= 0)
1551                 result = (uint16_t)numerator;
1552         else
1553                 result = (uint16_t)(
1554                 (1 << (integer_bits + fractional_bits + 1)) + numerator);
1555
1556         if ((result != 0) && dal_fixed31_32_lt(
1557                 arg, dal_fixed31_32_zero))
1558                 result |= 1 << (integer_bits + fractional_bits);
1559
1560         return result;
1561 }
1562
1563 void build_prescale_params(struct  dc_bias_and_scale *bias_and_scale,
1564                 const struct dc_plane_state *plane_state)
1565 {
1566         if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
1567                         && plane_state->format != SURFACE_PIXEL_FORMAT_INVALID
1568                         && plane_state->input_csc_color_matrix.enable_adjustment
1569                         && plane_state->coeff_reduction_factor.value != 0) {
1570                 bias_and_scale->scale_blue = fixed_point_to_int_frac(
1571                         dal_fixed31_32_mul(plane_state->coeff_reduction_factor,
1572                                         dal_fixed31_32_from_fraction(256, 255)),
1573                                 2,
1574                                 13);
1575                 bias_and_scale->scale_red = bias_and_scale->scale_blue;
1576                 bias_and_scale->scale_green = bias_and_scale->scale_blue;
1577         } else {
1578                 bias_and_scale->scale_blue = 0x2000;
1579                 bias_and_scale->scale_red = 0x2000;
1580                 bias_and_scale->scale_green = 0x2000;
1581         }
1582 }
1583
1584 static void update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state)
1585 {
1586         struct dc_bias_and_scale bns_params = {0};
1587
1588         // program the input csc
1589         dpp->funcs->dpp_setup(dpp,
1590                         plane_state->format,
1591                         EXPANSION_MODE_ZERO,
1592                         plane_state->input_csc_color_matrix,
1593                         COLOR_SPACE_YCBCR601_LIMITED);
1594
1595         //set scale and bias registers
1596         build_prescale_params(&bns_params, plane_state);
1597         if (dpp->funcs->dpp_program_bias_and_scale)
1598                 dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
1599 }
1600
1601
1602 static void update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
1603 {
1604         struct hubp *hubp = pipe_ctx->plane_res.hubp;
1605         struct mpcc_blnd_cfg blnd_cfg;
1606         bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
1607         int mpcc_id;
1608         struct mpcc *new_mpcc;
1609         struct mpc *mpc = dc->res_pool->mpc;
1610         struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);
1611
1612         /* TODO: proper fix once fpga works */
1613
1614         if (dc->debug.surface_visual_confirm)
1615                 dcn10_get_surface_visual_confirm_color(
1616                                 pipe_ctx, &blnd_cfg.black_color);
1617         else
1618                 color_space_to_black_color(
1619                         dc, pipe_ctx->stream->output_color_space,
1620                         &blnd_cfg.black_color);
1621
1622         if (per_pixel_alpha)
1623                 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;
1624         else
1625                 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA;
1626
1627         blnd_cfg.overlap_only = false;
1628         blnd_cfg.global_alpha = 0xff;
1629         blnd_cfg.global_gain = 0xff;
1630
1631         /* DCN1.0 has output CM before MPC which seems to screw with
1632          * pre-multiplied alpha.
1633          */
1634         blnd_cfg.pre_multiplied_alpha = is_rgb_cspace(
1635                         pipe_ctx->stream->output_color_space)
1636                                         && per_pixel_alpha;
1637
1638         /*
1639          * TODO: remove hack
1640          * Note: currently there is a bug in init_hw such that
1641          * on resume from hibernate, BIOS sets up MPCC0, and
1642          * we do mpcc_remove but the mpcc cannot go to idle
1643          * after remove. This cause us to pick mpcc1 here,
1644          * which causes a pstate hang for yet unknown reason.
1645          */
1646         mpcc_id = hubp->inst;
1647
1648         /* check if this MPCC is already being used */
1649         new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id);
1650         /* remove MPCC if being used */
1651         if (new_mpcc != NULL)
1652                 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc);
1653         else
1654                 if (dc->debug.sanity_checks)
1655                         mpc->funcs->assert_mpcc_idle_before_connect(
1656                                         dc->res_pool->mpc, mpcc_id);
1657
1658         /* Call MPC to insert new plane */
1659         new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,
1660                         mpc_tree_params,
1661                         &blnd_cfg,
1662                         NULL,
1663                         NULL,
1664                         hubp->inst,
1665                         mpcc_id);
1666
1667         ASSERT(new_mpcc != NULL);
1668
1669         hubp->opp_id = pipe_ctx->stream_res.opp->inst;
1670         hubp->mpcc_id = mpcc_id;
1671 }
1672
1673 static void update_scaler(struct pipe_ctx *pipe_ctx)
1674 {
1675         bool per_pixel_alpha =
1676                         pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
1677
1678         /* TODO: proper fix once fpga works */
1679
1680         pipe_ctx->plane_res.scl_data.lb_params.alpha_en = per_pixel_alpha;
1681         pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
1682         /* scaler configuration */
1683         pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(
1684                         pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);
1685 }
1686
1687 static void update_dchubp_dpp(
1688         struct dc *dc,
1689         struct pipe_ctx *pipe_ctx,
1690         struct dc_state *context)
1691 {
1692         struct hubp *hubp = pipe_ctx->plane_res.hubp;
1693         struct dpp *dpp = pipe_ctx->plane_res.dpp;
1694         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1695         union plane_size size = plane_state->plane_size;
1696
1697         /* depends on DML calculation, DPP clock value may change dynamically */
1698         if (plane_state->update_flags.bits.full_update) {
1699                 dpp->funcs->dpp_dppclk_control(
1700                                 dpp,
1701                                 context->bw.dcn.calc_clk.max_dppclk_khz <
1702                                                 context->bw.dcn.calc_clk.dispclk_khz,
1703                                 true);
1704
1705                 dc->current_state->bw.dcn.cur_clk.max_dppclk_khz =
1706                                 context->bw.dcn.calc_clk.max_dppclk_khz;
1707                 context->bw.dcn.cur_clk.max_dppclk_khz = context->bw.dcn.calc_clk.max_dppclk_khz;
1708         }
1709
1710         /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG
1711          * VTG is within DCHUBBUB which is commond block share by each pipe HUBP.
1712          * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG
1713          */
1714         if (plane_state->update_flags.bits.full_update) {
1715                 hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst);
1716
1717                 hubp->funcs->hubp_setup(
1718                         hubp,
1719                         &pipe_ctx->dlg_regs,
1720                         &pipe_ctx->ttu_regs,
1721                         &pipe_ctx->rq_regs,
1722                         &pipe_ctx->pipe_dlg_param);
1723         }
1724
1725         size.grph.surface_size = pipe_ctx->plane_res.scl_data.viewport;
1726
1727         if (plane_state->update_flags.bits.full_update ||
1728                 plane_state->update_flags.bits.bpp_change)
1729                 update_dpp(dpp, plane_state);
1730
1731         if (plane_state->update_flags.bits.full_update ||
1732                 plane_state->update_flags.bits.per_pixel_alpha_change)
1733                 update_mpcc(dc, pipe_ctx);
1734
1735         if (plane_state->update_flags.bits.full_update ||
1736                 plane_state->update_flags.bits.per_pixel_alpha_change ||
1737                 plane_state->update_flags.bits.scaling_change ||
1738                 plane_state->update_flags.bits.position_change) {
1739                 update_scaler(pipe_ctx);
1740         }
1741
1742         if (plane_state->update_flags.bits.full_update ||
1743                 plane_state->update_flags.bits.scaling_change ||
1744                 plane_state->update_flags.bits.position_change) {
1745                 hubp->funcs->mem_program_viewport(
1746                         hubp,
1747                         &pipe_ctx->plane_res.scl_data.viewport,
1748                         &pipe_ctx->plane_res.scl_data.viewport_c);
1749         }
1750
1751         if (pipe_ctx->stream->cursor_attributes.address.quad_part != 0) {
1752                 dc->hwss.set_cursor_position(pipe_ctx);
1753                 dc->hwss.set_cursor_attribute(pipe_ctx);
1754         }
1755
1756         if (plane_state->update_flags.bits.full_update) {
1757                 /*gamut remap*/
1758                 program_gamut_remap(pipe_ctx);
1759
1760                 program_output_csc(dc,
1761                                 pipe_ctx,
1762                                 pipe_ctx->stream->output_color_space,
1763                                 pipe_ctx->stream->csc_color_matrix.matrix,
1764                                 hubp->opp_id);
1765         }
1766
1767         if (plane_state->update_flags.bits.full_update ||
1768                 plane_state->update_flags.bits.pixel_format_change ||
1769                 plane_state->update_flags.bits.horizontal_mirror_change ||
1770                 plane_state->update_flags.bits.rotation_change ||
1771                 plane_state->update_flags.bits.swizzle_change ||
1772                 plane_state->update_flags.bits.dcc_change ||
1773                 plane_state->update_flags.bits.bpp_change ||
1774                 plane_state->update_flags.bits.scaling_change) {
1775                 hubp->funcs->hubp_program_surface_config(
1776                         hubp,
1777                         plane_state->format,
1778                         &plane_state->tiling_info,
1779                         &size,
1780                         plane_state->rotation,
1781                         &plane_state->dcc,
1782                         plane_state->horizontal_mirror);
1783         }
1784
1785         hubp->power_gated = false;
1786
1787         dc->hwss.update_plane_addr(dc, pipe_ctx);
1788
1789         if (is_pipe_tree_visible(pipe_ctx))
1790                 hubp->funcs->set_blank(hubp, false);
1791 }
1792
1793 static void dcn10_otg_blank(
1794                 struct dc *dc,
1795                 struct stream_resource stream_res,
1796                 struct dc_stream_state *stream,
1797                 bool blank)
1798 {
1799         enum dc_color_space color_space;
1800         struct tg_color black_color = {0};
1801
1802         /* program otg blank color */
1803         color_space = stream->output_color_space;
1804         color_space_to_black_color(dc, color_space, &black_color);
1805
1806         if (stream_res.tg->funcs->set_blank_color)
1807                 stream_res.tg->funcs->set_blank_color(
1808                                 stream_res.tg,
1809                                 &black_color);
1810
1811         if (!blank) {
1812                 if (stream_res.tg->funcs->set_blank)
1813                         stream_res.tg->funcs->set_blank(stream_res.tg, blank);
1814                 if (stream_res.abm)
1815                         stream_res.abm->funcs->set_abm_level(stream_res.abm, stream->abm_level);
1816         } else if (blank) {
1817                 if (stream_res.abm)
1818                         stream_res.abm->funcs->set_abm_immediate_disable(stream_res.abm);
1819                 if (stream_res.tg->funcs->set_blank)
1820                         stream_res.tg->funcs->set_blank(stream_res.tg, blank);
1821         }
1822 }
1823
1824 static void program_all_pipe_in_tree(
1825                 struct dc *dc,
1826                 struct pipe_ctx *pipe_ctx,
1827                 struct dc_state *context)
1828 {
1829         if (pipe_ctx->top_pipe == NULL) {
1830                 bool blank = !is_pipe_tree_visible(pipe_ctx);
1831
1832                 pipe_ctx->stream_res.tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset;
1833                 pipe_ctx->stream_res.tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start;
1834                 pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset;
1835                 pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_width = pipe_ctx->pipe_dlg_param.vupdate_width;
1836                 pipe_ctx->stream_res.tg->dlg_otg_param.signal =  pipe_ctx->stream->signal;
1837
1838                 pipe_ctx->stream_res.tg->funcs->program_global_sync(
1839                                 pipe_ctx->stream_res.tg);
1840
1841                 dcn10_otg_blank(dc, pipe_ctx->stream_res,
1842                                 pipe_ctx->stream, blank);
1843         }
1844
1845         if (pipe_ctx->plane_state != NULL) {
1846                 if (pipe_ctx->plane_state->update_flags.bits.full_update)
1847                         dcn10_enable_plane(dc, pipe_ctx, context);
1848
1849                 update_dchubp_dpp(dc, pipe_ctx, context);
1850
1851                 if (pipe_ctx->plane_state->update_flags.bits.full_update ||
1852                                 pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
1853                                 pipe_ctx->plane_state->update_flags.bits.gamma_change)
1854                         dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state);
1855
1856                 /* dcn10_translate_regamma_to_hw_format takes 750us to finish
1857                  * only do gamma programming for full update.
1858                  * TODO: This can be further optimized/cleaned up
1859                  * Always call this for now since it does memcmp inside before
1860                  * doing heavy calculation and programming
1861                  */
1862                 if (pipe_ctx->plane_state->update_flags.bits.full_update)
1863                         dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);
1864         }
1865
1866         if (pipe_ctx->bottom_pipe != NULL && pipe_ctx->bottom_pipe != pipe_ctx) {
1867                 program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context);
1868         }
1869 }
1870
1871 static void dcn10_pplib_apply_display_requirements(
1872         struct dc *dc,
1873         struct dc_state *context)
1874 {
1875         struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
1876
1877         pp_display_cfg->all_displays_in_sync = false;/*todo*/
1878         pp_display_cfg->nb_pstate_switch_disable = false;
1879         pp_display_cfg->min_engine_clock_khz = context->bw.dcn.cur_clk.dcfclk_khz;
1880         pp_display_cfg->min_memory_clock_khz = context->bw.dcn.cur_clk.fclk_khz;
1881         pp_display_cfg->min_engine_clock_deep_sleep_khz = context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz;
1882         pp_display_cfg->min_dcfc_deep_sleep_clock_khz = context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz;
1883         pp_display_cfg->avail_mclk_switch_time_us =
1884                         context->bw.dcn.cur_clk.dram_ccm_us > 0 ? context->bw.dcn.cur_clk.dram_ccm_us : 0;
1885         pp_display_cfg->avail_mclk_switch_time_in_disp_active_us =
1886                         context->bw.dcn.cur_clk.min_active_dram_ccm_us > 0 ? context->bw.dcn.cur_clk.min_active_dram_ccm_us : 0;
1887         pp_display_cfg->min_dcfclock_khz = context->bw.dcn.cur_clk.dcfclk_khz;
1888         pp_display_cfg->disp_clk_khz = context->bw.dcn.cur_clk.dispclk_khz;
1889         dce110_fill_display_configs(context, pp_display_cfg);
1890
1891         if (memcmp(&dc->prev_display_config, pp_display_cfg, sizeof(
1892                         struct dm_pp_display_configuration)) !=  0)
1893                 dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
1894
1895         dc->prev_display_config = *pp_display_cfg;
1896 }
1897
1898 static void optimize_shared_resources(struct dc *dc)
1899 {
1900         if (dc->current_state->stream_count == 0) {
1901                 /* S0i2 message */
1902                 dcn10_pplib_apply_display_requirements(dc, dc->current_state);
1903         }
1904
1905         if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE)
1906                 dcn_bw_notify_pplib_of_wm_ranges(dc);
1907 }
1908
1909 static void ready_shared_resources(struct dc *dc, struct dc_state *context)
1910 {
1911         /* S0i2 message */
1912         if (dc->current_state->stream_count == 0 &&
1913                         context->stream_count != 0)
1914                 dcn10_pplib_apply_display_requirements(dc, context);
1915 }
1916
1917 static struct pipe_ctx *find_top_pipe_for_stream(
1918                 struct dc *dc,
1919                 struct dc_state *context,
1920                 const struct dc_stream_state *stream)
1921 {
1922         int i;
1923
1924         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1925                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1926                 struct pipe_ctx *old_pipe_ctx =
1927                                 &dc->current_state->res_ctx.pipe_ctx[i];
1928
1929                 if (!pipe_ctx->plane_state && !old_pipe_ctx->plane_state)
1930                         continue;
1931
1932                 if (pipe_ctx->stream != stream)
1933                         continue;
1934
1935                 if (!pipe_ctx->top_pipe)
1936                         return pipe_ctx;
1937         }
1938         return NULL;
1939 }
1940
1941 static void dcn10_apply_ctx_for_surface(
1942                 struct dc *dc,
1943                 const struct dc_stream_state *stream,
1944                 int num_planes,
1945                 struct dc_state *context)
1946 {
1947         int i;
1948         struct timing_generator *tg;
1949         bool removed_pipe[4] = { false };
1950         unsigned int ref_clk_mhz = dc->res_pool->ref_clock_inKhz/1000;
1951         bool program_water_mark = false;
1952         struct dc_context *ctx = dc->ctx;
1953         struct pipe_ctx *top_pipe_to_program =
1954                         find_top_pipe_for_stream(dc, context, stream);
1955
1956         if (!top_pipe_to_program)
1957                 return;
1958
1959         tg = top_pipe_to_program->stream_res.tg;
1960
1961         dcn10_pipe_control_lock(dc, top_pipe_to_program, true);
1962
1963         if (num_planes == 0) {
1964                 /* OTG blank before remove all front end */
1965                 dcn10_otg_blank(dc, top_pipe_to_program->stream_res, top_pipe_to_program->stream, true);
1966         }
1967
1968         /* Disconnect unused mpcc */
1969         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1970                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1971                 struct pipe_ctx *old_pipe_ctx =
1972                                 &dc->current_state->res_ctx.pipe_ctx[i];
1973                 /*
1974                  * Powergate reused pipes that are not powergated
1975                  * fairly hacky right now, using opp_id as indicator
1976                  * TODO: After move dc_post to dc_update, this will
1977                  * be removed.
1978                  */
1979                 if (pipe_ctx->plane_state && !old_pipe_ctx->plane_state) {
1980                         if (old_pipe_ctx->stream_res.tg == tg &&
1981                                 old_pipe_ctx->plane_res.hubp &&
1982                                 old_pipe_ctx->plane_res.hubp->opp_id != 0xf) {
1983                                 dcn10_disable_plane(dc, old_pipe_ctx);
1984                                 /*
1985                                  * power down fe will unlock when calling reset, need
1986                                  * to lock it back here. Messy, need rework.
1987                                  */
1988                                 pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg);
1989                         }
1990                 }
1991
1992                 if (!pipe_ctx->plane_state &&
1993                         old_pipe_ctx->plane_state &&
1994                         old_pipe_ctx->stream_res.tg == tg) {
1995
1996                         plane_atomic_disconnect(dc, old_pipe_ctx);
1997                         removed_pipe[i] = true;
1998
1999                         DC_LOG_DC(
2000                                         "Reset mpcc for pipe %d\n",
2001                                         old_pipe_ctx->pipe_idx);
2002                 }
2003         }
2004
2005         if (num_planes > 0)
2006                 program_all_pipe_in_tree(dc, top_pipe_to_program, context);
2007
2008         dcn10_pipe_control_lock(dc, top_pipe_to_program, false);
2009
2010         if (num_planes == 0)
2011                 false_optc_underflow_wa(dc, stream, tg);
2012
2013         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2014                 struct pipe_ctx *old_pipe_ctx =
2015                                 &dc->current_state->res_ctx.pipe_ctx[i];
2016                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2017
2018                 if (pipe_ctx->stream == stream &&
2019                                 pipe_ctx->plane_state &&
2020                         pipe_ctx->plane_state->update_flags.bits.full_update)
2021                         program_water_mark = true;
2022
2023                 if (removed_pipe[i])
2024                         dcn10_disable_plane(dc, old_pipe_ctx);
2025         }
2026
2027         if (program_water_mark) {
2028                 if (dc->debug.sanity_checks) {
2029                         /* pstate stuck check after watermark update */
2030                         dcn10_verify_allow_pstate_change_high(dc);
2031                 }
2032
2033                 /* watermark is for all pipes */
2034                 hubbub1_program_watermarks(dc->res_pool->hubbub,
2035                                 &context->bw.dcn.watermarks, ref_clk_mhz);
2036
2037                 if (dc->debug.sanity_checks) {
2038                         /* pstate stuck check after watermark update */
2039                         dcn10_verify_allow_pstate_change_high(dc);
2040                 }
2041         }
2042 /*      DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger,
2043                         "\n============== Watermark parameters ==============\n"
2044                         "a.urgent_ns: %d \n"
2045                         "a.cstate_enter_plus_exit: %d \n"
2046                         "a.cstate_exit: %d \n"
2047                         "a.pstate_change: %d \n"
2048                         "a.pte_meta_urgent: %d \n"
2049                         "b.urgent_ns: %d \n"
2050                         "b.cstate_enter_plus_exit: %d \n"
2051                         "b.cstate_exit: %d \n"
2052                         "b.pstate_change: %d \n"
2053                         "b.pte_meta_urgent: %d \n",
2054                         context->bw.dcn.watermarks.a.urgent_ns,
2055                         context->bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns,
2056                         context->bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns,
2057                         context->bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns,
2058                         context->bw.dcn.watermarks.a.pte_meta_urgent_ns,
2059                         context->bw.dcn.watermarks.b.urgent_ns,
2060                         context->bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns,
2061                         context->bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns,
2062                         context->bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns,
2063                         context->bw.dcn.watermarks.b.pte_meta_urgent_ns
2064                         );
2065         DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger,
2066                         "\nc.urgent_ns: %d \n"
2067                         "c.cstate_enter_plus_exit: %d \n"
2068                         "c.cstate_exit: %d \n"
2069                         "c.pstate_change: %d \n"
2070                         "c.pte_meta_urgent: %d \n"
2071                         "d.urgent_ns: %d \n"
2072                         "d.cstate_enter_plus_exit: %d \n"
2073                         "d.cstate_exit: %d \n"
2074                         "d.pstate_change: %d \n"
2075                         "d.pte_meta_urgent: %d \n"
2076                         "========================================================\n",
2077                         context->bw.dcn.watermarks.c.urgent_ns,
2078                         context->bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns,
2079                         context->bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns,
2080                         context->bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns,
2081                         context->bw.dcn.watermarks.c.pte_meta_urgent_ns,
2082                         context->bw.dcn.watermarks.d.urgent_ns,
2083                         context->bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns,
2084                         context->bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns,
2085                         context->bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns,
2086                         context->bw.dcn.watermarks.d.pte_meta_urgent_ns
2087                         );
2088 */
2089 }
2090
2091 static void dcn10_set_bandwidth(
2092                 struct dc *dc,
2093                 struct dc_state *context,
2094                 bool decrease_allowed)
2095 {
2096         struct pp_smu_display_requirement_rv *smu_req_cur =
2097                         &dc->res_pool->pp_smu_req;
2098         struct pp_smu_display_requirement_rv smu_req = *smu_req_cur;
2099         struct pp_smu_funcs_rv *pp_smu = dc->res_pool->pp_smu;
2100
2101         if (dc->debug.sanity_checks) {
2102                 dcn10_verify_allow_pstate_change_high(dc);
2103         }
2104
2105         if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
2106                 return;
2107
2108         if (decrease_allowed || context->bw.dcn.calc_clk.dispclk_khz
2109                         > dc->current_state->bw.dcn.cur_clk.dispclk_khz) {
2110                 dc->res_pool->display_clock->funcs->set_clock(
2111                                 dc->res_pool->display_clock,
2112                                 context->bw.dcn.calc_clk.dispclk_khz);
2113                 context->bw.dcn.cur_clk.dispclk_khz =
2114                                 context->bw.dcn.calc_clk.dispclk_khz;
2115         }
2116         if (decrease_allowed || context->bw.dcn.calc_clk.dcfclk_khz
2117                         > dc->current_state->bw.dcn.cur_clk.dcfclk_khz) {
2118                 context->bw.dcn.cur_clk.dcfclk_khz =
2119                                 context->bw.dcn.calc_clk.dcfclk_khz;
2120                 smu_req.hard_min_dcefclk_khz =
2121                                 context->bw.dcn.calc_clk.dcfclk_khz;
2122         }
2123         if (decrease_allowed || context->bw.dcn.calc_clk.fclk_khz
2124                         > dc->current_state->bw.dcn.cur_clk.fclk_khz) {
2125                 context->bw.dcn.cur_clk.fclk_khz =
2126                                 context->bw.dcn.calc_clk.fclk_khz;
2127                 smu_req.hard_min_fclk_khz = context->bw.dcn.calc_clk.fclk_khz;
2128         }
2129         if (decrease_allowed || context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz
2130                         > dc->current_state->bw.dcn.cur_clk.dcfclk_deep_sleep_khz) {
2131                 context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz =
2132                                 context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz;
2133         }
2134
2135         smu_req.display_count = context->stream_count;
2136
2137         if (pp_smu->set_display_requirement)
2138                 pp_smu->set_display_requirement(&pp_smu->pp_smu, &smu_req);
2139
2140         *smu_req_cur = smu_req;
2141
2142         /* Decrease in freq is increase in period so opposite comparison for dram_ccm */
2143         if (decrease_allowed || context->bw.dcn.calc_clk.dram_ccm_us
2144                         < dc->current_state->bw.dcn.cur_clk.dram_ccm_us) {
2145                 context->bw.dcn.cur_clk.dram_ccm_us =
2146                                 context->bw.dcn.calc_clk.dram_ccm_us;
2147         }
2148         if (decrease_allowed || context->bw.dcn.calc_clk.min_active_dram_ccm_us
2149                         < dc->current_state->bw.dcn.cur_clk.min_active_dram_ccm_us) {
2150                 context->bw.dcn.cur_clk.min_active_dram_ccm_us =
2151                                 context->bw.dcn.calc_clk.min_active_dram_ccm_us;
2152         }
2153         dcn10_pplib_apply_display_requirements(dc, context);
2154
2155         if (dc->debug.sanity_checks) {
2156                 dcn10_verify_allow_pstate_change_high(dc);
2157         }
2158
2159         /* need to fix this function.  not doing the right thing here */
2160 }
2161
2162 static void set_drr(struct pipe_ctx **pipe_ctx,
2163                 int num_pipes, int vmin, int vmax)
2164 {
2165         int i = 0;
2166         struct drr_params params = {0};
2167
2168         params.vertical_total_max = vmax;
2169         params.vertical_total_min = vmin;
2170
2171         /* TODO: If multiple pipes are to be supported, you need
2172          * some GSL stuff
2173          */
2174         for (i = 0; i < num_pipes; i++) {
2175                 pipe_ctx[i]->stream_res.tg->funcs->set_drr(pipe_ctx[i]->stream_res.tg, &params);
2176         }
2177 }
2178
2179 static void get_position(struct pipe_ctx **pipe_ctx,
2180                 int num_pipes,
2181                 struct crtc_position *position)
2182 {
2183         int i = 0;
2184
2185         /* TODO: handle pipes > 1
2186          */
2187         for (i = 0; i < num_pipes; i++)
2188                 pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);
2189 }
2190
2191 static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
2192                 int num_pipes, const struct dc_static_screen_events *events)
2193 {
2194         unsigned int i;
2195         unsigned int value = 0;
2196
2197         if (events->surface_update)
2198                 value |= 0x80;
2199         if (events->cursor_update)
2200                 value |= 0x2;
2201         if (events->force_trigger)
2202                 value |= 0x1;
2203
2204         for (i = 0; i < num_pipes; i++)
2205                 pipe_ctx[i]->stream_res.tg->funcs->
2206                         set_static_screen_control(pipe_ctx[i]->stream_res.tg, value);
2207 }
2208
2209 static void set_plane_config(
2210         const struct dc *dc,
2211         struct pipe_ctx *pipe_ctx,
2212         struct resource_context *res_ctx)
2213 {
2214         /* TODO */
2215         program_gamut_remap(pipe_ctx);
2216 }
2217
2218 static void dcn10_config_stereo_parameters(
2219                 struct dc_stream_state *stream, struct crtc_stereo_flags *flags)
2220 {
2221         enum view_3d_format view_format = stream->view_format;
2222         enum dc_timing_3d_format timing_3d_format =\
2223                         stream->timing.timing_3d_format;
2224         bool non_stereo_timing = false;
2225
2226         if (timing_3d_format == TIMING_3D_FORMAT_NONE ||
2227                 timing_3d_format == TIMING_3D_FORMAT_SIDE_BY_SIDE ||
2228                 timing_3d_format == TIMING_3D_FORMAT_TOP_AND_BOTTOM)
2229                 non_stereo_timing = true;
2230
2231         if (non_stereo_timing == false &&
2232                 view_format == VIEW_3D_FORMAT_FRAME_SEQUENTIAL) {
2233
2234                 flags->PROGRAM_STEREO         = 1;
2235                 flags->PROGRAM_POLARITY       = 1;
2236                 if (timing_3d_format == TIMING_3D_FORMAT_INBAND_FA ||
2237                         timing_3d_format == TIMING_3D_FORMAT_DP_HDMI_INBAND_FA ||
2238                         timing_3d_format == TIMING_3D_FORMAT_SIDEBAND_FA) {
2239                         enum display_dongle_type dongle = \
2240                                         stream->sink->link->ddc->dongle_type;
2241                         if (dongle == DISPLAY_DONGLE_DP_VGA_CONVERTER ||
2242                                 dongle == DISPLAY_DONGLE_DP_DVI_CONVERTER ||
2243                                 dongle == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
2244                                 flags->DISABLE_STEREO_DP_SYNC = 1;
2245                 }
2246                 flags->RIGHT_EYE_POLARITY =\
2247                                 stream->timing.flags.RIGHT_EYE_3D_POLARITY;
2248                 if (timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
2249                         flags->FRAME_PACKED = 1;
2250         }
2251
2252         return;
2253 }
2254
2255 static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc)
2256 {
2257         struct crtc_stereo_flags flags = { 0 };
2258         struct dc_stream_state *stream = pipe_ctx->stream;
2259
2260         dcn10_config_stereo_parameters(stream, &flags);
2261
2262         pipe_ctx->stream_res.opp->funcs->opp_program_stereo(
2263                 pipe_ctx->stream_res.opp,
2264                 flags.PROGRAM_STEREO == 1 ? true:false,
2265                 &stream->timing);
2266
2267         pipe_ctx->stream_res.tg->funcs->program_stereo(
2268                 pipe_ctx->stream_res.tg,
2269                 &stream->timing,
2270                 &flags);
2271
2272         return;
2273 }
2274
2275 static struct hubp *get_hubp_by_inst(struct resource_pool *res_pool, int mpcc_inst)
2276 {
2277         int i;
2278
2279         for (i = 0; i < res_pool->pipe_count; i++) {
2280                 if (res_pool->hubps[i]->inst == mpcc_inst)
2281                         return res_pool->hubps[i];
2282         }
2283         ASSERT(false);
2284         return NULL;
2285 }
2286
2287 static void dcn10_wait_for_mpcc_disconnect(
2288                 struct dc *dc,
2289                 struct resource_pool *res_pool,
2290                 struct pipe_ctx *pipe_ctx)
2291 {
2292         int mpcc_inst;
2293
2294         if (dc->debug.sanity_checks) {
2295                 dcn10_verify_allow_pstate_change_high(dc);
2296         }
2297
2298         if (!pipe_ctx->stream_res.opp)
2299                 return;
2300
2301         for (mpcc_inst = 0; mpcc_inst < MAX_PIPES; mpcc_inst++) {
2302                 if (pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst]) {
2303                         struct hubp *hubp = get_hubp_by_inst(res_pool, mpcc_inst);
2304
2305                         res_pool->mpc->funcs->wait_for_idle(res_pool->mpc, mpcc_inst);
2306                         pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst] = false;
2307                         hubp->funcs->set_blank(hubp, true);
2308                         /*DC_LOG_ERROR(dc->ctx->logger,
2309                                         "[debug_mpo: wait_for_mpcc finished waiting on mpcc %d]\n",
2310                                         i);*/
2311                 }
2312         }
2313
2314         if (dc->debug.sanity_checks) {
2315                 dcn10_verify_allow_pstate_change_high(dc);
2316         }
2317
2318 }
2319
2320 static bool dcn10_dummy_display_power_gating(
2321         struct dc *dc,
2322         uint8_t controller_id,
2323         struct dc_bios *dcb,
2324         enum pipe_gating_control power_gating)
2325 {
2326         return true;
2327 }
2328
2329 static void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx)
2330 {
2331         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2332         struct timing_generator *tg = pipe_ctx->stream_res.tg;
2333
2334         if (plane_state == NULL)
2335                 return;
2336
2337         plane_state->status.is_flip_pending =
2338                         pipe_ctx->plane_res.hubp->funcs->hubp_is_flip_pending(
2339                                         pipe_ctx->plane_res.hubp);
2340
2341         plane_state->status.current_address = pipe_ctx->plane_res.hubp->current_address;
2342         if (pipe_ctx->plane_res.hubp->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2343                         tg->funcs->is_stereo_left_eye) {
2344                 plane_state->status.is_right_eye =
2345                                 !tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);
2346         }
2347 }
2348
2349 static void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data)
2350 {
2351         if (hws->ctx->dc->res_pool->hubbub != NULL)
2352                 hubbub1_update_dchub(hws->ctx->dc->res_pool->hubbub, dh_data);
2353 }
2354
2355 static void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)
2356 {
2357         struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;
2358         struct hubp *hubp = pipe_ctx->plane_res.hubp;
2359         struct dpp *dpp = pipe_ctx->plane_res.dpp;
2360         struct dc_cursor_mi_param param = {
2361                 .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_khz,
2362                 .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clock_inKhz,
2363                 .viewport_x_start = pipe_ctx->plane_res.scl_data.viewport.x,
2364                 .viewport_width = pipe_ctx->plane_res.scl_data.viewport.width,
2365                 .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz
2366         };
2367
2368         if (pipe_ctx->plane_state->address.type
2369                         == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
2370                 pos_cpy.enable = false;
2371
2372         if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)
2373                 pos_cpy.enable = false;
2374
2375         hubp->funcs->set_cursor_position(hubp, &pos_cpy, &param);
2376         dpp->funcs->set_cursor_position(dpp, &pos_cpy, &param, hubp->curs_attr.width);
2377 }
2378
2379 static void dcn10_set_cursor_attribute(struct pipe_ctx *pipe_ctx)
2380 {
2381         struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;
2382
2383         pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes(
2384                         pipe_ctx->plane_res.hubp, attributes);
2385         pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes(
2386                 pipe_ctx->plane_res.dpp, attributes->color_format);
2387 }
2388
2389 static const struct hw_sequencer_funcs dcn10_funcs = {
2390         .program_gamut_remap = program_gamut_remap,
2391         .program_csc_matrix = program_csc_matrix,
2392         .init_hw = dcn10_init_hw,
2393         .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
2394         .apply_ctx_for_surface = dcn10_apply_ctx_for_surface,
2395         .set_plane_config = set_plane_config,
2396         .update_plane_addr = dcn10_update_plane_addr,
2397         .update_dchub = dcn10_update_dchub,
2398         .update_pending_status = dcn10_update_pending_status,
2399         .set_input_transfer_func = dcn10_set_input_transfer_func,
2400         .set_output_transfer_func = dcn10_set_output_transfer_func,
2401         .power_down = dce110_power_down,
2402         .enable_accelerated_mode = dce110_enable_accelerated_mode,
2403         .enable_timing_synchronization = dcn10_enable_timing_synchronization,
2404         .enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,
2405         .update_info_frame = dce110_update_info_frame,
2406         .enable_stream = dce110_enable_stream,
2407         .disable_stream = dce110_disable_stream,
2408         .unblank_stream = dce110_unblank_stream,
2409         .blank_stream = dce110_blank_stream,
2410         .enable_display_power_gating = dcn10_dummy_display_power_gating,
2411         .disable_plane = dcn10_disable_plane,
2412         .pipe_control_lock = dcn10_pipe_control_lock,
2413         .set_bandwidth = dcn10_set_bandwidth,
2414         .reset_hw_ctx_wrap = reset_hw_ctx_wrap,
2415         .prog_pixclk_crtc_otg = dcn10_prog_pixclk_crtc_otg,
2416         .set_drr = set_drr,
2417         .get_position = get_position,
2418         .set_static_screen_control = set_static_screen_control,
2419         .setup_stereo = dcn10_setup_stereo,
2420         .set_avmute = dce110_set_avmute,
2421         .log_hw_state = dcn10_log_hw_state,
2422         .wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
2423         .ready_shared_resources = ready_shared_resources,
2424         .optimize_shared_resources = optimize_shared_resources,
2425         .pplib_apply_display_requirements =
2426                         dcn10_pplib_apply_display_requirements,
2427         .edp_backlight_control = hwss_edp_backlight_control,
2428         .edp_power_control = hwss_edp_power_control,
2429         .edp_wait_for_hpd_ready = hwss_edp_wait_for_hpd_ready,
2430         .set_cursor_position = dcn10_set_cursor_position,
2431         .set_cursor_attribute = dcn10_set_cursor_attribute
2432 };
2433
2434
2435 void dcn10_hw_sequencer_construct(struct dc *dc)
2436 {
2437         dc->hwss = dcn10_funcs;
2438 }
2439