drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27 #include "core_types.h"
  28 #include "resource.h"
  29 #include "custom_float.h"
  30 #include "dcn10_hw_sequencer.h"
  31 #include "dce110/dce110_hw_sequencer.h"
  32 #include "dce/dce_hwseq.h"
  33 #include "abm.h"
  34 #include "dmcu.h"
  35 #include "dcn10/dcn10_timing_generator.h"
  36 #include "dcn10/dcn10_dpp.h"
  37 #include "dcn10/dcn10_mpc.h"
  38 #include "timing_generator.h"
  39 #include "opp.h"
  40 #include "ipp.h"
  41 #include "mpc.h"
  42 #include "reg_helper.h"
  43 #include "custom_float.h"
  44 #include "dcn10_hubp.h"
  45 #include "dcn10_hubbub.h"
  46
  47 #define CTX \
  48         hws->ctx
  49 #define REG(reg)\
  50         hws->regs->reg
  51
  52 #undef FN
  53 #define FN(reg_name, field_name) \
  54         hws->shifts->field_name, hws->masks->field_name
  55
  56 #define DTN_INFO_MICRO_SEC(ref_cycle) \
  57         print_microsec(dc_ctx, ref_cycle)
  58
  59 void print_microsec(struct dc_context *dc_ctx, uint32_t ref_cycle)
  60 {
  61         static const uint32_t ref_clk_mhz = 48;
  62         static const unsigned int frac = 10;
  63         uint32_t us_x10 = (ref_cycle * frac) / ref_clk_mhz;
  64
  65         DTN_INFO("%d.%d \t ",
  66                         us_x10 / frac,
  67                         us_x10 % frac);
  68 }
  69
  70
  71 static void log_mpc_crc(struct dc *dc)
  72 {
  73         struct dc_context *dc_ctx = dc->ctx;
  74         struct dce_hwseq *hws = dc->hwseq;
  75
  76         if (REG(MPC_CRC_RESULT_GB))
  77                 DTN_INFO("MPC_CRC_RESULT_GB:%d MPC_CRC_RESULT_C:%d MPC_CRC_RESULT_AR:%d\n",
  78                 REG_READ(MPC_CRC_RESULT_GB), REG_READ(MPC_CRC_RESULT_C), REG_READ(MPC_CRC_RESULT_AR));
  79         if (REG(DPP_TOP0_DPP_CRC_VAL_B_A))
  80                 DTN_INFO("DPP_TOP0_DPP_CRC_VAL_B_A:%d DPP_TOP0_DPP_CRC_VAL_R_G:%d\n",
  81                 REG_READ(DPP_TOP0_DPP_CRC_VAL_B_A), REG_READ(DPP_TOP0_DPP_CRC_VAL_R_G));
  82 }
  83
  84 void dcn10_log_hubbub_state(struct dc *dc)
  85 {
  86         struct dc_context *dc_ctx = dc->ctx;
  87         struct dcn_hubbub_wm wm;
  88         int i;
  89
  90         hubbub1_wm_read_state(dc->res_pool->hubbub, &wm);
  91
  92         DTN_INFO("HUBBUB WM: \t data_urgent \t pte_meta_urgent \t "
  93                         "sr_enter \t sr_exit \t dram_clk_change \n");
  94
  95         for (i = 0; i < 4; i++) {
  96                 struct dcn_hubbub_wm_set *s;
  97
  98                 s = &wm.sets[i];
  99                 DTN_INFO("WM_Set[%d]:\t ", s->wm_set);
 100                 DTN_INFO_MICRO_SEC(s->data_urgent);
 101                 DTN_INFO_MICRO_SEC(s->pte_meta_urgent);
 102                 DTN_INFO_MICRO_SEC(s->sr_enter);
 103                 DTN_INFO_MICRO_SEC(s->sr_exit);
 104                 DTN_INFO_MICRO_SEC(s->dram_clk_chanage);
 105                 DTN_INFO("\n");
 106         }
 107
 108         DTN_INFO("\n");
 109 }
 110
 111 void dcn10_log_hw_state(struct dc *dc)
 112 {
 113         struct dc_context *dc_ctx = dc->ctx;
 114         struct resource_pool *pool = dc->res_pool;
 115         int i;
 116
 117         DTN_INFO_BEGIN();
 118
 119         dcn10_log_hubbub_state(dc);
 120
 121         DTN_INFO("HUBP:\t format \t addr_hi \t width \t height \t "
 122                         "rotation \t mirror \t  sw_mode \t "
 123                         "dcc_en \t blank_en \t ttu_dis \t underflow \t "
 124                         "min_ttu_vblank \t qos_low_wm \t qos_high_wm \n");
 125
 126         for (i = 0; i < pool->pipe_count; i++) {
 127                 struct hubp *hubp = pool->hubps[i];
 128                 struct dcn_hubp_state s;
 129
 130                 hubp1_read_state(TO_DCN10_HUBP(hubp), &s);
 131
 132                 DTN_INFO("[%d]:\t %xh \t %xh \t %d \t %d \t "
 133                                 "%xh \t %xh \t %xh \t "
 134                                 "%d \t %d \t %d \t %xh \t",
 135                                 i,
 136                                 s.pixel_format,
 137                                 s.inuse_addr_hi,
 138                                 s.viewport_width,
 139                                 s.viewport_height,
 140                                 s.rotation_angle,
 141                                 s.h_mirror_en,
 142                                 s.sw_mode,
 143                                 s.dcc_en,
 144                                 s.blank_en,
 145                                 s.ttu_disable,
 146                                 s.underflow_status);
 147                 DTN_INFO_MICRO_SEC(s.min_ttu_vblank);
 148                 DTN_INFO_MICRO_SEC(s.qos_level_low_wm);
 149                 DTN_INFO_MICRO_SEC(s.qos_level_high_wm);
 150                 DTN_INFO("\n");
 151         }
 152         DTN_INFO("\n");
 153
 154         DTN_INFO("OTG:\t v_bs \t v_be \t v_ss \t v_se \t vpol \t vmax \t vmin \t "
 155                         "h_bs \t h_be \t h_ss \t h_se \t hpol \t htot \t vtot \t underflow\n");
 156
 157         for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
 158                 struct timing_generator *tg = pool->timing_generators[i];
 159                 struct dcn_otg_state s = {0};
 160
 161                 tgn10_read_otg_state(DCN10TG_FROM_TG(tg), &s);
 162
 163                 //only print if OTG master is enabled
 164                 if ((s.otg_enabled & 1) == 0)
 165                         continue;
 166
 167                 DTN_INFO("[%d]:\t %d \t %d \t %d \t %d \t "
 168                                 "%d \t %d \t %d \t %d \t %d \t %d \t "
 169                                 "%d \t %d \t %d \t %d \t %d \t ",
 170                                 i,
 171                                 s.v_blank_start,
 172                                 s.v_blank_end,
 173                                 s.v_sync_a_start,
 174                                 s.v_sync_a_end,
 175                                 s.v_sync_a_pol,
 176                                 s.v_total_max,
 177                                 s.v_total_min,
 178                                 s.h_blank_start,
 179                                 s.h_blank_end,
 180                                 s.h_sync_a_start,
 181                                 s.h_sync_a_end,
 182                                 s.h_sync_a_pol,
 183                                 s.h_total,
 184                                 s.v_total,
 185                                 s.underflow_occurred_status);
 186                 DTN_INFO("\n");
 187         }
 188         DTN_INFO("\n");
 189
 190         log_mpc_crc(dc);
 191
 192         DTN_INFO_END();
 193 }
 194
 195 static void enable_dppclk(
 196         struct dce_hwseq *hws,
 197         uint8_t plane_id,
 198         uint32_t requested_pix_clk,
 199         bool dppclk_div)
 200 {
 201         dm_logger_write(hws->ctx->logger, LOG_SURFACE,
 202                         "dppclk_rate_control for pipe %d programed to %d\n",
 203                         plane_id,
 204                         dppclk_div);
 205
 206         if (hws->shifts->DPPCLK_RATE_CONTROL)
 207                 REG_UPDATE_2(DPP_CONTROL[plane_id],
 208                         DPPCLK_RATE_CONTROL, dppclk_div,
 209                         DPP_CLOCK_ENABLE, 1);
 210         else
 211                 REG_UPDATE(DPP_CONTROL[plane_id],
 212                         DPP_CLOCK_ENABLE, 1);
 213 }
 214
 215 static void enable_power_gating_plane(
 216         struct dce_hwseq *hws,
 217         bool enable)
 218 {
 219         bool force_on = 1; /* disable power gating */
 220
 221         if (enable)
 222                 force_on = 0;
 223
 224         /* DCHUBP0/1/2/3 */
 225         REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on);
 226         REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on);
 227         REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on);
 228         REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on);
 229
 230         /* DPP0/1/2/3 */
 231         REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on);
 232         REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on);
 233         REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on);
 234         REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);
 235 }
 236
 237 static void disable_vga(
 238         struct dce_hwseq *hws)
 239 {
 240         REG_WRITE(D1VGA_CONTROL, 0);
 241         REG_WRITE(D2VGA_CONTROL, 0);
 242         REG_WRITE(D3VGA_CONTROL, 0);
 243         REG_WRITE(D4VGA_CONTROL, 0);
 244 }
 245
 246 static void dpp_pg_control(
 247                 struct dce_hwseq *hws,
 248                 unsigned int dpp_inst,
 249                 bool power_on)
 250 {
 251         uint32_t power_gate = power_on ? 0 : 1;
 252         uint32_t pwr_status = power_on ? 0 : 2;
 253
 254         if (hws->ctx->dc->debug.disable_dpp_power_gate)
 255                 return;
 256
 257         switch (dpp_inst) {
 258         case 0: /* DPP0 */
 259                 REG_UPDATE(DOMAIN1_PG_CONFIG,
 260                                 DOMAIN1_POWER_GATE, power_gate);
 261
 262                 REG_WAIT(DOMAIN1_PG_STATUS,
 263                                 DOMAIN1_PGFSM_PWR_STATUS, pwr_status,
 264                                 1, 1000);
 265                 break;
 266         case 1: /* DPP1 */
 267                 REG_UPDATE(DOMAIN3_PG_CONFIG,
 268                                 DOMAIN3_POWER_GATE, power_gate);
 269
 270                 REG_WAIT(DOMAIN3_PG_STATUS,
 271                                 DOMAIN3_PGFSM_PWR_STATUS, pwr_status,
 272                                 1, 1000);
 273                 break;
 274         case 2: /* DPP2 */
 275                 REG_UPDATE(DOMAIN5_PG_CONFIG,
 276                                 DOMAIN5_POWER_GATE, power_gate);
 277
 278                 REG_WAIT(DOMAIN5_PG_STATUS,
 279                                 DOMAIN5_PGFSM_PWR_STATUS, pwr_status,
 280                                 1, 1000);
 281                 break;
 282         case 3: /* DPP3 */
 283                 REG_UPDATE(DOMAIN7_PG_CONFIG,
 284                                 DOMAIN7_POWER_GATE, power_gate);
 285
 286                 REG_WAIT(DOMAIN7_PG_STATUS,
 287                                 DOMAIN7_PGFSM_PWR_STATUS, pwr_status,
 288                                 1, 1000);
 289                 break;
 290         default:
 291                 BREAK_TO_DEBUGGER();
 292                 break;
 293         }
 294 }
 295
 296 static void hubp_pg_control(
 297                 struct dce_hwseq *hws,
 298                 unsigned int hubp_inst,
 299                 bool power_on)
 300 {
 301         uint32_t power_gate = power_on ? 0 : 1;
 302         uint32_t pwr_status = power_on ? 0 : 2;
 303
 304         if (hws->ctx->dc->debug.disable_hubp_power_gate)
 305                 return;
 306
 307         switch (hubp_inst) {
 308         case 0: /* DCHUBP0 */
 309                 REG_UPDATE(DOMAIN0_PG_CONFIG,
 310                                 DOMAIN0_POWER_GATE, power_gate);
 311
 312                 REG_WAIT(DOMAIN0_PG_STATUS,
 313                                 DOMAIN0_PGFSM_PWR_STATUS, pwr_status,
 314                                 1, 1000);
 315                 break;
 316         case 1: /* DCHUBP1 */
 317                 REG_UPDATE(DOMAIN2_PG_CONFIG,
 318                                 DOMAIN2_POWER_GATE, power_gate);
 319
 320                 REG_WAIT(DOMAIN2_PG_STATUS,
 321                                 DOMAIN2_PGFSM_PWR_STATUS, pwr_status,
 322                                 1, 1000);
 323                 break;
 324         case 2: /* DCHUBP2 */
 325                 REG_UPDATE(DOMAIN4_PG_CONFIG,
 326                                 DOMAIN4_POWER_GATE, power_gate);
 327
 328                 REG_WAIT(DOMAIN4_PG_STATUS,
 329                                 DOMAIN4_PGFSM_PWR_STATUS, pwr_status,
 330                                 1, 1000);
 331                 break;
 332         case 3: /* DCHUBP3 */
 333                 REG_UPDATE(DOMAIN6_PG_CONFIG,
 334                                 DOMAIN6_POWER_GATE, power_gate);
 335
 336                 REG_WAIT(DOMAIN6_PG_STATUS,
 337                                 DOMAIN6_PGFSM_PWR_STATUS, pwr_status,
 338                                 1, 1000);
 339                 break;
 340         default:
 341                 BREAK_TO_DEBUGGER();
 342                 break;
 343         }
 344 }
 345
 346 static void power_on_plane(
 347         struct dce_hwseq *hws,
 348         int plane_id)
 349 {
 350         if (REG(DC_IP_REQUEST_CNTL)) {
 351                 REG_SET(DC_IP_REQUEST_CNTL, 0,
 352                                 IP_REQUEST_EN, 1);
 353                 dpp_pg_control(hws, plane_id, true);
 354                 hubp_pg_control(hws, plane_id, true);
 355                 REG_SET(DC_IP_REQUEST_CNTL, 0,
 356                                 IP_REQUEST_EN, 0);
 357                 dm_logger_write(hws->ctx->logger, LOG_DEBUG,
 358                                 "Un-gated front end for pipe %d\n", plane_id);
 359         }
 360 }
 361
 362 static void undo_DEGVIDCN10_253_wa(struct dc *dc)
 363 {
 364         struct dce_hwseq *hws = dc->hwseq;
 365         struct hubp *hubp = dc->res_pool->hubps[0];
 366
 367         if (!hws->wa_state.DEGVIDCN10_253_applied)
 368                 return;
 369
 370         hubp->funcs->set_blank(hubp, true);
 371
 372         REG_SET(DC_IP_REQUEST_CNTL, 0,
 373                         IP_REQUEST_EN, 1);
 374
 375         hubp_pg_control(hws, 0, false);
 376         REG_SET(DC_IP_REQUEST_CNTL, 0,
 377                         IP_REQUEST_EN, 0);
 378
 379         hws->wa_state.DEGVIDCN10_253_applied = false;
 380 }
 381
 382 static void apply_DEGVIDCN10_253_wa(struct dc *dc)
 383 {
 384         struct dce_hwseq *hws = dc->hwseq;
 385         struct hubp *hubp = dc->res_pool->hubps[0];
 386         int i;
 387
 388         if (dc->debug.disable_stutter)
 389                 return;
 390
 391         if (!hws->wa.DEGVIDCN10_253)
 392                 return;
 393
 394         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 395                 if (!dc->res_pool->hubps[i]->power_gated)
 396                         return;
 397         }
 398
 399         /* all pipe power gated, apply work around to enable stutter. */
 400
 401         REG_SET(DC_IP_REQUEST_CNTL, 0,
 402                         IP_REQUEST_EN, 1);
 403
 404         hubp_pg_control(hws, 0, true);
 405         REG_SET(DC_IP_REQUEST_CNTL, 0,
 406                         IP_REQUEST_EN, 0);
 407
 408         hubp->funcs->set_hubp_blank_en(hubp, false);
 409         hws->wa_state.DEGVIDCN10_253_applied = true;
 410 }
 411
 412 static void bios_golden_init(struct dc *dc)
 413 {
 414         struct dc_bios *bp = dc->ctx->dc_bios;
 415         int i;
 416
 417         /* initialize dcn global */
 418         bp->funcs->enable_disp_power_gating(bp,
 419                         CONTROLLER_ID_D0, ASIC_PIPE_INIT);
 420
 421         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 422                 /* initialize dcn per pipe */
 423                 bp->funcs->enable_disp_power_gating(bp,
 424                                 CONTROLLER_ID_D0 + i, ASIC_PIPE_DISABLE);
 425         }
 426 }
 427
 428 static void false_optc_underflow_wa(
 429                 struct dc *dc,
 430                 const struct dc_stream_state *stream,
 431                 struct timing_generator *tg)
 432 {
 433         int i;
 434         bool underflow;
 435
 436         if (!dc->hwseq->wa.false_optc_underflow)
 437                 return;
 438
 439         underflow = tg->funcs->is_optc_underflow_occurred(tg);
 440
 441         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 442                 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
 443
 444                 if (old_pipe_ctx->stream != stream)
 445                         continue;
 446
 447                 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, old_pipe_ctx);
 448         }
 449
 450         tg->funcs->set_blank_data_double_buffer(tg, true);
 451
 452         if (tg->funcs->is_optc_underflow_occurred(tg) && !underflow)
 453                 tg->funcs->clear_optc_underflow(tg);
 454 }
 455
 456 static enum dc_status dcn10_prog_pixclk_crtc_otg(
 457                 struct pipe_ctx *pipe_ctx,
 458                 struct dc_state *context,
 459                 struct dc *dc)
 460 {
 461         struct dc_stream_state *stream = pipe_ctx->stream;
 462         enum dc_color_space color_space;
 463         struct tg_color black_color = {0};
 464         bool enableStereo    = stream->timing.timing_3d_format == TIMING_3D_FORMAT_NONE ?
 465                         false:true;
 466         bool rightEyePolarity = stream->timing.flags.RIGHT_EYE_3D_POLARITY;
 467
 468         /* by upper caller loop, pipe0 is parent pipe and be called first.
 469          * back end is set up by for pipe0. Other children pipe share back end
 470          * with pipe 0. No program is needed.
 471          */
 472         if (pipe_ctx->top_pipe != NULL)
 473                 return DC_OK;
 474
 475         /* TODO check if timing_changed, disable stream if timing changed */
 476
 477         /* HW program guide assume display already disable
 478          * by unplug sequence. OTG assume stop.
 479          */
 480         pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true);
 481
 482         if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
 483                         pipe_ctx->clock_source,
 484                         &pipe_ctx->stream_res.pix_clk_params,
 485                         &pipe_ctx->pll_settings)) {
 486                 BREAK_TO_DEBUGGER();
 487                 return DC_ERROR_UNEXPECTED;
 488         }
 489         pipe_ctx->stream_res.tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset;
 490         pipe_ctx->stream_res.tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start;
 491         pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset;
 492         pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_width = pipe_ctx->pipe_dlg_param.vupdate_width;
 493
 494         pipe_ctx->stream_res.tg->dlg_otg_param.signal =  pipe_ctx->stream->signal;
 495
 496         pipe_ctx->stream_res.tg->funcs->program_timing(
 497                         pipe_ctx->stream_res.tg,
 498                         &stream->timing,
 499                         true);
 500
 501         pipe_ctx->stream_res.opp->funcs->opp_set_stereo_polarity(
 502                                 pipe_ctx->stream_res.opp,
 503                                 enableStereo,
 504                                 rightEyePolarity);
 505
 506 #if 0 /* move to after enable_crtc */
 507         /* TODO: OPP FMT, ABM. etc. should be done here. */
 508         /* or FPGA now. instance 0 only. TODO: move to opp.c */
 509
 510         inst_offset = reg_offsets[pipe_ctx->stream_res.tg->inst].fmt;
 511
 512         pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
 513                                 pipe_ctx->stream_res.opp,
 514                                 &stream->bit_depth_params,
 515                                 &stream->clamping);
 516 #endif
 517         /* program otg blank color */
 518         color_space = stream->output_color_space;
 519         color_space_to_black_color(dc, color_space, &black_color);
 520         pipe_ctx->stream_res.tg->funcs->set_blank_color(
 521                         pipe_ctx->stream_res.tg,
 522                         &black_color);
 523
 524         if (!pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg)) {
 525                 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);
 526                 hwss_wait_for_blank_complete(pipe_ctx->stream_res.tg);
 527                 false_optc_underflow_wa(dc, pipe_ctx->stream, pipe_ctx->stream_res.tg);
 528         }
 529
 530         /* VTG is  within DCHUB command block. DCFCLK is always on */
 531         if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {
 532                 BREAK_TO_DEBUGGER();
 533                 return DC_ERROR_UNEXPECTED;
 534         }
 535
 536         /* TODO program crtc source select for non-virtual signal*/
 537         /* TODO program FMT */
 538         /* TODO setup link_enc */
 539         /* TODO set stream attributes */
 540         /* TODO program audio */
 541         /* TODO enable stream if timing changed */
 542         /* TODO unblank stream if DP */
 543
 544         return DC_OK;
 545 }
 546
 547 static void reset_back_end_for_pipe(
 548                 struct dc *dc,
 549                 struct pipe_ctx *pipe_ctx,
 550                 struct dc_state *context)
 551 {
 552         int i;
 553
 554         if (pipe_ctx->stream_res.stream_enc == NULL) {
 555                 pipe_ctx->stream = NULL;
 556                 return;
 557         }
 558
 559         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
 560                 /* DPMS may already disable */
 561                 if (!pipe_ctx->stream->dpms_off)
 562                         core_link_disable_stream(pipe_ctx, FREE_ACQUIRED_RESOURCE);
 563         }
 564
 565         /* by upper caller loop, parent pipe: pipe0, will be reset last.
 566          * back end share by all pipes and will be disable only when disable
 567          * parent pipe.
 568          */
 569         if (pipe_ctx->top_pipe == NULL) {
 570                 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
 571
 572                 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
 573         }
 574
 575         for (i = 0; i < dc->res_pool->pipe_count; i++)
 576                 if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx)
 577                         break;
 578
 579         if (i == dc->res_pool->pipe_count)
 580                 return;
 581
 582         pipe_ctx->stream = NULL;
 583         dm_logger_write(dc->ctx->logger, LOG_DEBUG,
 584                                         "Reset back end for pipe %d, tg:%d\n",
 585                                         pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
 586 }
 587
 588 static void dcn10_verify_allow_pstate_change_high(struct dc *dc)
 589 {
 590         static bool should_log_hw_state; /* prevent hw state log by default */
 591
 592         if (!hubbub1_verify_allow_pstate_change_high(dc->res_pool->hubbub)) {
 593                 if (should_log_hw_state) {
 594                         dcn10_log_hw_state(dc);
 595                 }
 596
 597                 BREAK_TO_DEBUGGER();
 598         }
 599 }
 600
 601 /* trigger HW to start disconnect plane from stream on the next vsync */
 602 static void plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx)
 603 {
 604         int fe_idx = pipe_ctx->pipe_idx;
 605         struct hubp *hubp = dc->res_pool->hubps[fe_idx];
 606         struct mpc *mpc = dc->res_pool->mpc;
 607         int opp_id;
 608         struct mpc_tree *mpc_tree_params;
 609         struct mpcc *mpcc_to_remove = NULL;
 610
 611         /* look at tree rather than mi here to know if we already reset */
 612         for (opp_id = 0; opp_id < dc->res_pool->pipe_count; opp_id++) {
 613                 struct output_pixel_processor *opp = dc->res_pool->opps[opp_id];
 614
 615                 mpc_tree_params = &(opp->mpc_tree_params);
 616                 mpcc_to_remove = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, fe_idx);
 617                 if (mpcc_to_remove != NULL)
 618                         break;
 619         }
 620
 621         /*Already reset*/
 622         if (opp_id == dc->res_pool->pipe_count)
 623                 return;
 624
 625         mpc->funcs->remove_mpcc(mpc, mpc_tree_params, mpcc_to_remove);
 626         dc->res_pool->opps[opp_id]->mpcc_disconnect_pending[fe_idx] = true;
 627
 628         dc->optimized_required = true;
 629
 630         if (hubp->funcs->hubp_disconnect)
 631                 hubp->funcs->hubp_disconnect(hubp);
 632
 633         if (dc->debug.sanity_checks)
 634                 dcn10_verify_allow_pstate_change_high(dc);
 635 }
 636
 637 static void plane_atomic_power_down(struct dc *dc, int fe_idx)
 638 {
 639         struct dce_hwseq *hws = dc->hwseq;
 640         struct dpp *dpp = dc->res_pool->dpps[fe_idx];
 641
 642         if (REG(DC_IP_REQUEST_CNTL)) {
 643                 REG_SET(DC_IP_REQUEST_CNTL, 0,
 644                                 IP_REQUEST_EN, 1);
 645                 dpp_pg_control(hws, fe_idx, false);
 646                 hubp_pg_control(hws, fe_idx, false);
 647                 dpp->funcs->dpp_reset(dpp);
 648                 REG_SET(DC_IP_REQUEST_CNTL, 0,
 649                                 IP_REQUEST_EN, 0);
 650                 dm_logger_write(dc->ctx->logger, LOG_DEBUG,
 651                                 "Power gated front end %d\n", fe_idx);
 652         }
 653 }
 654
 655 /* disable HW used by plane.
 656  * note:  cannot disable until disconnect is complete
 657  */
 658 static void plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
 659 {
 660         int fe_idx = pipe_ctx->pipe_idx;
 661         struct dce_hwseq *hws = dc->hwseq;
 662         struct hubp *hubp = dc->res_pool->hubps[fe_idx];
 663         int opp_id = hubp->opp_id;
 664
 665         dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);
 666
 667         REG_UPDATE(HUBP_CLK_CNTL[fe_idx],
 668                         HUBP_CLOCK_ENABLE, 0);
 669         REG_UPDATE(DPP_CONTROL[fe_idx],
 670                         DPP_CLOCK_ENABLE, 0);
 671
 672         if (opp_id != 0xf && dc->res_pool->opps[opp_id]->mpc_tree_params.opp_list == NULL)
 673                 REG_UPDATE(OPP_PIPE_CONTROL[opp_id],
 674                                 OPP_PIPE_CLOCK_EN, 0);
 675
 676         hubp->power_gated = true;
 677         dc->optimized_required = false; /* We're powering off, no need to optimize */
 678
 679         plane_atomic_power_down(dc, fe_idx);
 680
 681         pipe_ctx->stream = NULL;
 682         memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res));
 683         memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res));
 684         pipe_ctx->top_pipe = NULL;
 685         pipe_ctx->bottom_pipe = NULL;
 686         pipe_ctx->plane_state = NULL;
 687 }
 688
 689 static void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
 690 {
 691         if (dc->res_pool->hubps[pipe_ctx->pipe_idx]->power_gated)
 692                 return;
 693
 694         plane_atomic_disable(dc, pipe_ctx);
 695
 696         apply_DEGVIDCN10_253_wa(dc);
 697
 698         dm_logger_write(dc->ctx->logger, LOG_DC,
 699                                         "Power down front end %d\n",
 700                                         pipe_ctx->pipe_idx);
 701 }
 702
 703 static void dcn10_init_hw(struct dc *dc)
 704 {
 705         int i, opp_id;
 706         struct abm *abm = dc->res_pool->abm;
 707         struct dmcu *dmcu = dc->res_pool->dmcu;
 708         struct dce_hwseq *hws = dc->hwseq;
 709         struct dc_bios *dcb = dc->ctx->dc_bios;
 710         struct dc_state  *context = dc->current_state;
 711
 712         if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
 713                 REG_WRITE(REFCLK_CNTL, 0);
 714                 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
 715                 REG_WRITE(DIO_MEM_PWR_CTRL, 0);
 716
 717                 if (!dc->debug.disable_clock_gate) {
 718                         /* enable all DCN clock gating */
 719                         REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
 720
 721                         REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
 722
 723                         REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
 724                 }
 725
 726                 enable_power_gating_plane(dc->hwseq, true);
 727                 return;
 728         }
 729         /* end of FPGA. Below if real ASIC */
 730
 731         if (!dcb->funcs->is_accelerated_mode(dcb)) {
 732                 bios_golden_init(dc);
 733                 disable_vga(dc->hwseq);
 734         }
 735
 736         for (i = 0; i < dc->link_count; i++) {
 737                 /* Power up AND update implementation according to the
 738                  * required signal (which may be different from the
 739                  * default signal on connector).
 740                  */
 741                 struct dc_link *link = dc->links[i];
 742
 743                 if (link->link_enc->connector.id == CONNECTOR_ID_EDP)
 744                         dc->hwss.edp_power_control(link, true);
 745
 746                 link->link_enc->funcs->hw_init(link->link_enc);
 747         }
 748
 749         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 750                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
 751
 752                 if (tg->funcs->is_tg_enabled(tg))
 753                         tg->funcs->lock(tg);
 754         }
 755
 756         /* Blank controller using driver code instead of
 757          * command table.
 758          */
 759         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 760                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
 761
 762                 if (tg->funcs->is_tg_enabled(tg)) {
 763                         tg->funcs->set_blank(tg, true);
 764                         hwss_wait_for_blank_complete(tg);
 765                 }
 766         }
 767
 768         /* Initialize MPC tree based on HW values */
 769         for (opp_id = 0; opp_id < dc->res_pool->pipe_count; opp_id++) {
 770                 struct output_pixel_processor *opp = dc->res_pool->opps[opp_id];
 771                 struct mpc_tree *mpc_tree_params = &(opp->mpc_tree_params);
 772
 773                 dc->res_pool->mpc->funcs->init_mpcc_list_from_hw(dc->res_pool->mpc, mpc_tree_params);
 774         }
 775
 776         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 777                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
 778                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
 779                 struct hubp *hubp = dc->res_pool->hubps[i];
 780
 781                 pipe_ctx->stream_res.tg = tg;
 782                 pipe_ctx->pipe_idx = i;
 783
 784                 pipe_ctx->plane_res.hubp = hubp;
 785                 hubp->mpcc_id = i;
 786                 hubp->opp_id = dc->res_pool->mpc->funcs->get_opp_id(dc->res_pool->mpc, i);
 787                 hubp->power_gated = false;
 788
 789                 if (hubp->opp_id != 0xf)
 790                         pipe_ctx->stream_res.opp = dc->res_pool->opps[hubp->opp_id];
 791
 792                 plane_atomic_disconnect(dc, pipe_ctx);
 793         }
 794
 795         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 796                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
 797
 798                 if (tg->funcs->is_tg_enabled(tg))
 799                         tg->funcs->unlock(tg);
 800         }
 801
 802         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 803                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
 804                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
 805
 806                 dcn10_disable_plane(dc, pipe_ctx);
 807
 808                 pipe_ctx->stream_res.tg = NULL;
 809                 pipe_ctx->plane_res.hubp = NULL;
 810
 811                 tg->funcs->tg_init(tg);
 812         }
 813
 814         for (i = 0; i < dc->res_pool->audio_count; i++) {
 815                 struct audio *audio = dc->res_pool->audios[i];
 816
 817                 audio->funcs->hw_init(audio);
 818         }
 819
 820         if (abm != NULL) {
 821                 abm->funcs->init_backlight(abm);
 822                 abm->funcs->abm_init(abm);
 823         }
 824
 825         if (dmcu != NULL)
 826                 dmcu->funcs->dmcu_init(dmcu);
 827
 828         /* power AFMT HDMI memory TODO: may move to dis/en output save power*/
 829         REG_WRITE(DIO_MEM_PWR_CTRL, 0);
 830
 831         if (!dc->debug.disable_clock_gate) {
 832                 /* enable all DCN clock gating */
 833                 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
 834
 835                 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
 836
 837                 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
 838         }
 839
 840         enable_power_gating_plane(dc->hwseq, true);
 841 }
 842
 843 static void reset_hw_ctx_wrap(
 844                 struct dc *dc,
 845                 struct dc_state *context)
 846 {
 847         int i;
 848
 849         /* Reset Back End*/
 850         for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
 851                 struct pipe_ctx *pipe_ctx_old =
 852                         &dc->current_state->res_ctx.pipe_ctx[i];
 853                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
 854
 855                 if (!pipe_ctx_old->stream)
 856                         continue;
 857
 858                 if (pipe_ctx_old->top_pipe)
 859                         continue;
 860
 861                 if (!pipe_ctx->stream ||
 862                                 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
 863                         struct clock_source *old_clk = pipe_ctx_old->clock_source;
 864
 865                         reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
 866                         if (old_clk)
 867                                 old_clk->funcs->cs_power_down(old_clk);
 868                 }
 869         }
 870
 871 }
 872
 873 static bool patch_address_for_sbs_tb_stereo(
 874                 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr)
 875 {
 876         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
 877         bool sec_split = pipe_ctx->top_pipe &&
 878                         pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
 879         if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
 880                 (pipe_ctx->stream->timing.timing_3d_format ==
 881                  TIMING_3D_FORMAT_SIDE_BY_SIDE ||
 882                  pipe_ctx->stream->timing.timing_3d_format ==
 883                  TIMING_3D_FORMAT_TOP_AND_BOTTOM)) {
 884                 *addr = plane_state->address.grph_stereo.left_addr;
 885                 plane_state->address.grph_stereo.left_addr =
 886                 plane_state->address.grph_stereo.right_addr;
 887                 return true;
 888         } else {
 889                 if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE &&
 890                         plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) {
 891                         plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO;
 892                         plane_state->address.grph_stereo.right_addr =
 893                         plane_state->address.grph_stereo.left_addr;
 894                 }
 895         }
 896         return false;
 897 }
 898
 899
 900
 901 static void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)
 902 {
 903         bool addr_patched = false;
 904         PHYSICAL_ADDRESS_LOC addr;
 905         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
 906
 907         if (plane_state == NULL)
 908                 return;
 909         addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);
 910         pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(
 911                         pipe_ctx->plane_res.hubp,
 912                         &plane_state->address,
 913                         plane_state->flip_immediate);
 914         plane_state->status.requested_address = plane_state->address;
 915         if (addr_patched)
 916                 pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;
 917 }
 918
 919 static bool dcn10_set_input_transfer_func(struct pipe_ctx *pipe_ctx,
 920                                           const struct dc_plane_state *plane_state)
 921 {
 922         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
 923         const struct dc_transfer_func *tf = NULL;
 924         bool result = true;
 925
 926         if (dpp_base == NULL)
 927                 return false;
 928
 929         if (plane_state->in_transfer_func)
 930                 tf = plane_state->in_transfer_func;
 931
 932         if (plane_state->gamma_correction && dce_use_lut(plane_state))
 933                 dpp_base->funcs->dpp_program_input_lut(dpp_base, plane_state->gamma_correction);
 934
 935         if (tf == NULL)
 936                 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
 937         else if (tf->type == TF_TYPE_PREDEFINED) {
 938                 switch (tf->tf) {
 939                 case TRANSFER_FUNCTION_SRGB:
 940                         dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_sRGB);
 941                         break;
 942                 case TRANSFER_FUNCTION_BT709:
 943                         dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_xvYCC);
 944                         break;
 945                 case TRANSFER_FUNCTION_LINEAR:
 946                         dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
 947                         break;
 948                 case TRANSFER_FUNCTION_PQ:
 949                 default:
 950                         result = false;
 951                         break;
 952                 }
 953         } else if (tf->type == TF_TYPE_BYPASS) {
 954                 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
 955         } else {
 956                 /*TF_TYPE_DISTRIBUTED_POINTS*/
 957                 result = false;
 958         }
 959
 960         return result;
 961 }
 962 /*modify the method to handle rgb for arr_points*/
 963 static bool convert_to_custom_float(
 964                 struct pwl_result_data *rgb_resulted,
 965                 struct curve_points *arr_points,
 966                 uint32_t hw_points_num)
 967 {
 968         struct custom_float_format fmt;
 969
 970         struct pwl_result_data *rgb = rgb_resulted;
 971
 972         uint32_t i = 0;
 973
 974         fmt.exponenta_bits = 6;
 975         fmt.mantissa_bits = 12;
 976         fmt.sign = false;
 977
 978         if (!convert_to_custom_float_format(arr_points[0].x, &fmt,
 979                                             &arr_points[0].custom_float_x)) {
 980                 BREAK_TO_DEBUGGER();
 981                 return false;
 982         }
 983
 984         if (!convert_to_custom_float_format(arr_points[0].offset, &fmt,
 985                                             &arr_points[0].custom_float_offset)) {
 986                 BREAK_TO_DEBUGGER();
 987                 return false;
 988         }
 989
 990         if (!convert_to_custom_float_format(arr_points[0].slope, &fmt,
 991                                             &arr_points[0].custom_float_slope)) {
 992                 BREAK_TO_DEBUGGER();
 993                 return false;
 994         }
 995
 996         fmt.mantissa_bits = 10;
 997         fmt.sign = false;
 998
 999         if (!convert_to_custom_float_format(arr_points[1].x, &fmt,
1000                                             &arr_points[1].custom_float_x)) {
1001                 BREAK_TO_DEBUGGER();
1002                 return false;
1003         }
1004
1005         if (!convert_to_custom_float_format(arr_points[1].y, &fmt,
1006                                             &arr_points[1].custom_float_y)) {
1007                 BREAK_TO_DEBUGGER();
1008                 return false;
1009         }
1010
1011         if (!convert_to_custom_float_format(arr_points[1].slope, &fmt,
1012                                             &arr_points[1].custom_float_slope)) {
1013                 BREAK_TO_DEBUGGER();
1014                 return false;
1015         }
1016
1017         fmt.mantissa_bits = 12;
1018         fmt.sign = true;
1019
1020         while (i != hw_points_num) {
1021                 if (!convert_to_custom_float_format(rgb->red, &fmt,
1022                                                     &rgb->red_reg)) {
1023                         BREAK_TO_DEBUGGER();
1024                         return false;
1025                 }
1026
1027                 if (!convert_to_custom_float_format(rgb->green, &fmt,
1028                                                     &rgb->green_reg)) {
1029                         BREAK_TO_DEBUGGER();
1030                         return false;
1031                 }
1032
1033                 if (!convert_to_custom_float_format(rgb->blue, &fmt,
1034                                                     &rgb->blue_reg)) {
1035                         BREAK_TO_DEBUGGER();
1036                         return false;
1037                 }
1038
1039                 if (!convert_to_custom_float_format(rgb->delta_red, &fmt,
1040                                                     &rgb->delta_red_reg)) {
1041                         BREAK_TO_DEBUGGER();
1042                         return false;
1043                 }
1044
1045                 if (!convert_to_custom_float_format(rgb->delta_green, &fmt,
1046                                                     &rgb->delta_green_reg)) {
1047                         BREAK_TO_DEBUGGER();
1048                         return false;
1049                 }
1050
1051                 if (!convert_to_custom_float_format(rgb->delta_blue, &fmt,
1052                                                     &rgb->delta_blue_reg)) {
1053                         BREAK_TO_DEBUGGER();
1054                         return false;
1055                 }
1056
1057                 ++rgb;
1058                 ++i;
1059         }
1060
1061         return true;
1062 }
1063 #define MAX_REGIONS_NUMBER 34
1064 #define MAX_LOW_POINT      25
1065 #define NUMBER_SEGMENTS    32
1066
1067 static bool
1068 dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf,
1069                                      struct pwl_params *regamma_params)
1070 {
1071         struct curve_points *arr_points;
1072         struct pwl_result_data *rgb_resulted;
1073         struct pwl_result_data *rgb;
1074         struct pwl_result_data *rgb_plus_1;
1075         struct fixed31_32 y_r;
1076         struct fixed31_32 y_g;
1077         struct fixed31_32 y_b;
1078         struct fixed31_32 y1_min;
1079         struct fixed31_32 y3_max;
1080
1081         int32_t segment_start, segment_end;
1082         int32_t i;
1083         uint32_t j, k, seg_distr[MAX_REGIONS_NUMBER], increment, start_index, hw_points;
1084
1085         if (output_tf == NULL || regamma_params == NULL || output_tf->type == TF_TYPE_BYPASS)
1086                 return false;
1087
1088         PERF_TRACE();
1089
1090         arr_points = regamma_params->arr_points;
1091         rgb_resulted = regamma_params->rgb_resulted;
1092         hw_points = 0;
1093
1094         memset(regamma_params, 0, sizeof(struct pwl_params));
1095         memset(seg_distr, 0, sizeof(seg_distr));
1096
1097         if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
1098                 /* 32 segments
1099                  * segments are from 2^-25 to 2^7
1100                  */
1101                 for (i = 0; i < 32 ; i++)
1102                         seg_distr[i] = 3;
1103
1104                 segment_start = -25;
1105                 segment_end   = 7;
1106         } else {
1107                 /* 10 segments
1108                  * segment is from 2^-10 to 2^0
1109                  * There are less than 256 points, for optimization
1110                  */
1111                 seg_distr[0] = 3;
1112                 seg_distr[1] = 4;
1113                 seg_distr[2] = 4;
1114                 seg_distr[3] = 4;
1115                 seg_distr[4] = 4;
1116                 seg_distr[5] = 4;
1117                 seg_distr[6] = 4;
1118                 seg_distr[7] = 4;
1119                 seg_distr[8] = 5;
1120                 seg_distr[9] = 5;
1121
1122                 segment_start = -10;
1123                 segment_end = 0;
1124         }
1125
1126         for (i = segment_end - segment_start; i < MAX_REGIONS_NUMBER ; i++)
1127                 seg_distr[i] = -1;
1128
1129         for (k = 0; k < MAX_REGIONS_NUMBER; k++) {
1130                 if (seg_distr[k] != -1)
1131                         hw_points += (1 << seg_distr[k]);
1132         }
1133
1134         j = 0;
1135         for (k = 0; k < (segment_end - segment_start); k++) {
1136                 increment = NUMBER_SEGMENTS / (1 << seg_distr[k]);
1137                 start_index = (segment_start + k + MAX_LOW_POINT) * NUMBER_SEGMENTS;
1138                 for (i = start_index; i < start_index + NUMBER_SEGMENTS; i += increment) {
1139                         if (j == hw_points - 1)
1140                                 break;
1141                         rgb_resulted[j].red = output_tf->tf_pts.red[i];
1142                         rgb_resulted[j].green = output_tf->tf_pts.green[i];
1143                         rgb_resulted[j].blue = output_tf->tf_pts.blue[i];
1144                         j++;
1145                 }
1146         }
1147
1148         /* last point */
1149         start_index = (segment_end + MAX_LOW_POINT) * NUMBER_SEGMENTS;
1150         rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index];
1151         rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index];
1152         rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index];
1153
1154         arr_points[0].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
1155                                              dal_fixed31_32_from_int(segment_start));
1156         arr_points[1].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
1157                                              dal_fixed31_32_from_int(segment_end));
1158
1159         y_r = rgb_resulted[0].red;
1160         y_g = rgb_resulted[0].green;
1161         y_b = rgb_resulted[0].blue;
1162
1163         y1_min = dal_fixed31_32_min(y_r, dal_fixed31_32_min(y_g, y_b));
1164
1165         arr_points[0].y = y1_min;
1166         arr_points[0].slope = dal_fixed31_32_div(arr_points[0].y, arr_points[0].x);
1167         y_r = rgb_resulted[hw_points - 1].red;
1168         y_g = rgb_resulted[hw_points - 1].green;
1169         y_b = rgb_resulted[hw_points - 1].blue;
1170
1171         /* see comment above, m_arrPoints[1].y should be the Y value for the
1172          * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1)
1173          */
1174         y3_max = dal_fixed31_32_max(y_r, dal_fixed31_32_max(y_g, y_b));
1175
1176         arr_points[1].y = y3_max;
1177
1178         arr_points[1].slope = dal_fixed31_32_zero;
1179
1180         if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
1181                 /* for PQ, we want to have a straight line from last HW X point,
1182                  * and the slope to be such that we hit 1.0 at 10000 nits.
1183                  */
1184                 const struct fixed31_32 end_value =
1185                                 dal_fixed31_32_from_int(125);
1186
1187                 arr_points[1].slope = dal_fixed31_32_div(
1188                         dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y),
1189                         dal_fixed31_32_sub(end_value, arr_points[1].x));
1190         }
1191
1192         regamma_params->hw_points_num = hw_points;
1193
1194         i = 1;
1195         for (k = 0; k < MAX_REGIONS_NUMBER && i < MAX_REGIONS_NUMBER; k++) {
1196                 if (seg_distr[k] != -1) {
1197                         regamma_params->arr_curve_points[k].segments_num =
1198                                         seg_distr[k];
1199                         regamma_params->arr_curve_points[i].offset =
1200                                         regamma_params->arr_curve_points[k].offset + (1 << seg_distr[k]);
1201                 }
1202                 i++;
1203         }
1204
1205         if (seg_distr[k] != -1)
1206                 regamma_params->arr_curve_points[k].segments_num = seg_distr[k];
1207
1208         rgb = rgb_resulted;
1209         rgb_plus_1 = rgb_resulted + 1;
1210
1211         i = 1;
1212
1213         while (i != hw_points + 1) {
1214                 if (dal_fixed31_32_lt(rgb_plus_1->red, rgb->red))
1215                         rgb_plus_1->red = rgb->red;
1216                 if (dal_fixed31_32_lt(rgb_plus_1->green, rgb->green))
1217                         rgb_plus_1->green = rgb->green;
1218                 if (dal_fixed31_32_lt(rgb_plus_1->blue, rgb->blue))
1219                         rgb_plus_1->blue = rgb->blue;
1220
1221                 rgb->delta_red = dal_fixed31_32_sub(rgb_plus_1->red, rgb->red);
1222                 rgb->delta_green = dal_fixed31_32_sub(rgb_plus_1->green, rgb->green);
1223                 rgb->delta_blue = dal_fixed31_32_sub(rgb_plus_1->blue, rgb->blue);
1224
1225                 ++rgb_plus_1;
1226                 ++rgb;
1227                 ++i;
1228         }
1229
1230         convert_to_custom_float(rgb_resulted, arr_points, hw_points);
1231
1232         PERF_TRACE();
1233
1234         return true;
1235 }
1236
1237 static bool
1238 dcn10_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
1239                                const struct dc_stream_state *stream)
1240 {
1241         struct dpp *dpp = pipe_ctx->plane_res.dpp;
1242
1243         if (dpp == NULL)
1244                 return false;
1245
1246         dpp->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
1247
1248         if (stream->out_transfer_func &&
1249             stream->out_transfer_func->type == TF_TYPE_PREDEFINED &&
1250             stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB)
1251                 dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_SRGB);
1252
1253         /* dcn10_translate_regamma_to_hw_format takes 750us, only do it when full
1254          * update.
1255          */
1256         else if (dcn10_translate_regamma_to_hw_format(
1257                         stream->out_transfer_func,
1258                         &dpp->regamma_params)) {
1259                 dpp->funcs->dpp_program_regamma_pwl(
1260                                 dpp,
1261                                 &dpp->regamma_params, OPP_REGAMMA_USER);
1262         } else
1263                 dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_BYPASS);
1264
1265         return true;
1266 }
1267
1268 static void dcn10_pipe_control_lock(
1269         struct dc *dc,
1270         struct pipe_ctx *pipe,
1271         bool lock)
1272 {
1273         struct hubp *hubp = NULL;
1274         hubp = dc->res_pool->hubps[pipe->pipe_idx];
1275         /* use TG master update lock to lock everything on the TG
1276          * therefore only top pipe need to lock
1277          */
1278         if (pipe->top_pipe)
1279                 return;
1280
1281         if (dc->debug.sanity_checks)
1282                 dcn10_verify_allow_pstate_change_high(dc);
1283
1284         if (lock)
1285                 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);
1286         else
1287                 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);
1288
1289         if (dc->debug.sanity_checks)
1290                 dcn10_verify_allow_pstate_change_high(dc);
1291 }
1292
1293 static bool wait_for_reset_trigger_to_occur(
1294         struct dc_context *dc_ctx,
1295         struct timing_generator *tg)
1296 {
1297         bool rc = false;
1298
1299         /* To avoid endless loop we wait at most
1300          * frames_to_wait_on_triggered_reset frames for the reset to occur. */
1301         const uint32_t frames_to_wait_on_triggered_reset = 10;
1302         int i;
1303
1304         for (i = 0; i < frames_to_wait_on_triggered_reset; i++) {
1305
1306                 if (!tg->funcs->is_counter_moving(tg)) {
1307                         DC_ERROR("TG counter is not moving!\n");
1308                         break;
1309                 }
1310
1311                 if (tg->funcs->did_triggered_reset_occur(tg)) {
1312                         rc = true;
1313                         /* usually occurs at i=1 */
1314                         DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",
1315                                         i);
1316                         break;
1317                 }
1318
1319                 /* Wait for one frame. */
1320                 tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);
1321                 tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
1322         }
1323
1324         if (false == rc)
1325                 DC_ERROR("GSL: Timeout on reset trigger!\n");
1326
1327         return rc;
1328 }
1329
1330 static void dcn10_enable_timing_synchronization(
1331         struct dc *dc,
1332         int group_index,
1333         int group_size,
1334         struct pipe_ctx *grouped_pipes[])
1335 {
1336         struct dc_context *dc_ctx = dc->ctx;
1337         int i;
1338
1339         DC_SYNC_INFO("Setting up OTG reset trigger\n");
1340
1341         for (i = 1; i < group_size; i++)
1342                 grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger(
1343                                 grouped_pipes[i]->stream_res.tg,
1344                                 grouped_pipes[0]->stream_res.tg->inst);
1345
1346         DC_SYNC_INFO("Waiting for trigger\n");
1347
1348         /* Need to get only check 1 pipe for having reset as all the others are
1349          * synchronized. Look at last pipe programmed to reset.
1350          */
1351
1352         wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[1]->stream_res.tg);
1353         for (i = 1; i < group_size; i++)
1354                 grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(
1355                                 grouped_pipes[i]->stream_res.tg);
1356
1357         DC_SYNC_INFO("Sync complete\n");
1358 }
1359
1360 static void dcn10_enable_per_frame_crtc_position_reset(
1361         struct dc *dc,
1362         int group_size,
1363         struct pipe_ctx *grouped_pipes[])
1364 {
1365         struct dc_context *dc_ctx = dc->ctx;
1366         int i;
1367
1368         DC_SYNC_INFO("Setting up\n");
1369         for (i = 0; i < group_size; i++)
1370                 grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset(
1371                                 grouped_pipes[i]->stream_res.tg,
1372                                 grouped_pipes[i]->stream->triggered_crtc_reset.event_source->status.primary_otg_inst,
1373                                 &grouped_pipes[i]->stream->triggered_crtc_reset);
1374
1375         DC_SYNC_INFO("Waiting for trigger\n");
1376
1377         for (i = 1; i < group_size; i++)
1378                 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
1379
1380         DC_SYNC_INFO("Multi-display sync is complete\n");
1381 }
1382
1383 /*static void print_rq_dlg_ttu(
1384                 struct dc *core_dc,
1385                 struct pipe_ctx *pipe_ctx)
1386 {
1387         dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
1388                         "\n============== DML TTU Output parameters [%d] ==============\n"
1389                         "qos_level_low_wm: %d, \n"
1390                         "qos_level_high_wm: %d, \n"
1391                         "min_ttu_vblank: %d, \n"
1392                         "qos_level_flip: %d, \n"
1393                         "refcyc_per_req_delivery_l: %d, \n"
1394                         "qos_level_fixed_l: %d, \n"
1395                         "qos_ramp_disable_l: %d, \n"
1396                         "refcyc_per_req_delivery_pre_l: %d, \n"
1397                         "refcyc_per_req_delivery_c: %d, \n"
1398                         "qos_level_fixed_c: %d, \n"
1399                         "qos_ramp_disable_c: %d, \n"
1400                         "refcyc_per_req_delivery_pre_c: %d\n"
1401                         "=============================================================\n",
1402                         pipe_ctx->pipe_idx,
1403                         pipe_ctx->ttu_regs.qos_level_low_wm,
1404                         pipe_ctx->ttu_regs.qos_level_high_wm,
1405                         pipe_ctx->ttu_regs.min_ttu_vblank,
1406                         pipe_ctx->ttu_regs.qos_level_flip,
1407                         pipe_ctx->ttu_regs.refcyc_per_req_delivery_l,
1408                         pipe_ctx->ttu_regs.qos_level_fixed_l,
1409                         pipe_ctx->ttu_regs.qos_ramp_disable_l,
1410                         pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_l,
1411                         pipe_ctx->ttu_regs.refcyc_per_req_delivery_c,
1412                         pipe_ctx->ttu_regs.qos_level_fixed_c,
1413                         pipe_ctx->ttu_regs.qos_ramp_disable_c,
1414                         pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_c
1415                         );
1416
1417         dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
1418                         "\n============== DML DLG Output parameters [%d] ==============\n"
1419                         "refcyc_h_blank_end: %d, \n"
1420                         "dlg_vblank_end: %d, \n"
1421                         "min_dst_y_next_start: %d, \n"
1422                         "refcyc_per_htotal: %d, \n"
1423                         "refcyc_x_after_scaler: %d, \n"
1424                         "dst_y_after_scaler: %d, \n"
1425                         "dst_y_prefetch: %d, \n"
1426                         "dst_y_per_vm_vblank: %d, \n"
1427                         "dst_y_per_row_vblank: %d, \n"
1428                         "ref_freq_to_pix_freq: %d, \n"
1429                         "vratio_prefetch: %d, \n"
1430                         "refcyc_per_pte_group_vblank_l: %d, \n"
1431                         "refcyc_per_meta_chunk_vblank_l: %d, \n"
1432                         "dst_y_per_pte_row_nom_l: %d, \n"
1433                         "refcyc_per_pte_group_nom_l: %d, \n",
1434                         pipe_ctx->pipe_idx,
1435                         pipe_ctx->dlg_regs.refcyc_h_blank_end,
1436                         pipe_ctx->dlg_regs.dlg_vblank_end,
1437                         pipe_ctx->dlg_regs.min_dst_y_next_start,
1438                         pipe_ctx->dlg_regs.refcyc_per_htotal,
1439                         pipe_ctx->dlg_regs.refcyc_x_after_scaler,
1440                         pipe_ctx->dlg_regs.dst_y_after_scaler,
1441                         pipe_ctx->dlg_regs.dst_y_prefetch,
1442                         pipe_ctx->dlg_regs.dst_y_per_vm_vblank,
1443                         pipe_ctx->dlg_regs.dst_y_per_row_vblank,
1444                         pipe_ctx->dlg_regs.ref_freq_to_pix_freq,
1445                         pipe_ctx->dlg_regs.vratio_prefetch,
1446                         pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_l,
1447                         pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_l,
1448                         pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_l,
1449                         pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_l
1450                         );
1451
1452         dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
1453                         "\ndst_y_per_meta_row_nom_l: %d, \n"
1454                         "refcyc_per_meta_chunk_nom_l: %d, \n"
1455                         "refcyc_per_line_delivery_pre_l: %d, \n"
1456                         "refcyc_per_line_delivery_l: %d, \n"
1457                         "vratio_prefetch_c: %d, \n"
1458                         "refcyc_per_pte_group_vblank_c: %d, \n"
1459                         "refcyc_per_meta_chunk_vblank_c: %d, \n"
1460                         "dst_y_per_pte_row_nom_c: %d, \n"
1461                         "refcyc_per_pte_group_nom_c: %d, \n"
1462                         "dst_y_per_meta_row_nom_c: %d, \n"
1463                         "refcyc_per_meta_chunk_nom_c: %d, \n"
1464                         "refcyc_per_line_delivery_pre_c: %d, \n"
1465                         "refcyc_per_line_delivery_c: %d \n"
1466                         "========================================================\n",
1467                         pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_l,
1468                         pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_l,
1469                         pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_l,
1470                         pipe_ctx->dlg_regs.refcyc_per_line_delivery_l,
1471                         pipe_ctx->dlg_regs.vratio_prefetch_c,
1472                         pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_c,
1473                         pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_c,
1474                         pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_c,
1475                         pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_c,
1476                         pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_c,
1477                         pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_c,
1478                         pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_c,
1479                         pipe_ctx->dlg_regs.refcyc_per_line_delivery_c
1480                         );
1481
1482         dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
1483                         "\n============== DML RQ Output parameters [%d] ==============\n"
1484                         "chunk_size: %d \n"
1485                         "min_chunk_size: %d \n"
1486                         "meta_chunk_size: %d \n"
1487                         "min_meta_chunk_size: %d \n"
1488                         "dpte_group_size: %d \n"
1489                         "mpte_group_size: %d \n"
1490                         "swath_height: %d \n"
1491                         "pte_row_height_linear: %d \n"
1492                         "========================================================\n",
1493                         pipe_ctx->pipe_idx,
1494                         pipe_ctx->rq_regs.rq_regs_l.chunk_size,
1495                         pipe_ctx->rq_regs.rq_regs_l.min_chunk_size,
1496                         pipe_ctx->rq_regs.rq_regs_l.meta_chunk_size,
1497                         pipe_ctx->rq_regs.rq_regs_l.min_meta_chunk_size,
1498                         pipe_ctx->rq_regs.rq_regs_l.dpte_group_size,
1499                         pipe_ctx->rq_regs.rq_regs_l.mpte_group_size,
1500                         pipe_ctx->rq_regs.rq_regs_l.swath_height,
1501                         pipe_ctx->rq_regs.rq_regs_l.pte_row_height_linear
1502                         );
1503 }
1504 */
1505
1506 static void mmhub_read_vm_system_aperture_settings(struct dcn10_hubp *hubp1,
1507                 struct vm_system_aperture_param *apt,
1508                 struct dce_hwseq *hws)
1509 {
1510         PHYSICAL_ADDRESS_LOC physical_page_number;
1511         uint32_t logical_addr_low;
1512         uint32_t logical_addr_high;
1513
1514         REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
1515                         PHYSICAL_PAGE_NUMBER_MSB, &physical_page_number.high_part);
1516         REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
1517                         PHYSICAL_PAGE_NUMBER_LSB, &physical_page_number.low_part);
1518
1519         REG_GET(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1520                         LOGICAL_ADDR, &logical_addr_low);
1521
1522         REG_GET(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1523                         LOGICAL_ADDR, &logical_addr_high);
1524
1525         apt->sys_default.quad_part =  physical_page_number.quad_part << 12;
1526         apt->sys_low.quad_part =  (int64_t)logical_addr_low << 18;
1527         apt->sys_high.quad_part =  (int64_t)logical_addr_high << 18;
1528 }
1529
1530 /* Temporary read settings, future will get values from kmd directly */
1531 static void mmhub_read_vm_context0_settings(struct dcn10_hubp *hubp1,
1532                 struct vm_context0_param *vm0,
1533                 struct dce_hwseq *hws)
1534 {
1535         PHYSICAL_ADDRESS_LOC fb_base;
1536         PHYSICAL_ADDRESS_LOC fb_offset;
1537         uint32_t fb_base_value;
1538         uint32_t fb_offset_value;
1539
1540         REG_GET(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, &fb_base_value);
1541         REG_GET(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, &fb_offset_value);
1542
1543         REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
1544                         PAGE_DIRECTORY_ENTRY_HI32, &vm0->pte_base.high_part);
1545         REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
1546                         PAGE_DIRECTORY_ENTRY_LO32, &vm0->pte_base.low_part);
1547
1548         REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
1549                         LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_start.high_part);
1550         REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
1551                         LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_start.low_part);
1552
1553         REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
1554                         LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_end.high_part);
1555         REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
1556                         LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_end.low_part);
1557
1558         REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
1559                         PHYSICAL_PAGE_ADDR_HI4, &vm0->fault_default.high_part);
1560         REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
1561                         PHYSICAL_PAGE_ADDR_LO32, &vm0->fault_default.low_part);
1562
1563         /*
1564          * The values in VM_CONTEXT0_PAGE_TABLE_BASE_ADDR is in UMA space.
1565          * Therefore we need to do
1566          * DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
1567          * - DCHUBBUB_SDPIF_FB_OFFSET + DCHUBBUB_SDPIF_FB_BASE
1568          */
1569         fb_base.quad_part = (uint64_t)fb_base_value << 24;
1570         fb_offset.quad_part = (uint64_t)fb_offset_value << 24;
1571         vm0->pte_base.quad_part += fb_base.quad_part;
1572         vm0->pte_base.quad_part -= fb_offset.quad_part;
1573 }
1574
1575
1576 static void dcn10_program_pte_vm(struct dce_hwseq *hws, struct hubp *hubp)
1577 {
1578         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
1579         struct vm_system_aperture_param apt = { {{ 0 } } };
1580         struct vm_context0_param vm0 = { { { 0 } } };
1581
1582         mmhub_read_vm_system_aperture_settings(hubp1, &apt, hws);
1583         mmhub_read_vm_context0_settings(hubp1, &vm0, hws);
1584
1585         hubp->funcs->hubp_set_vm_system_aperture_settings(hubp, &apt);
1586         hubp->funcs->hubp_set_vm_context0_settings(hubp, &vm0);
1587 }
1588
1589 static void dcn10_enable_plane(
1590         struct dc *dc,
1591         struct pipe_ctx *pipe_ctx,
1592         struct dc_state *context)
1593 {
1594         struct dce_hwseq *hws = dc->hwseq;
1595
1596         if (dc->debug.sanity_checks) {
1597                 dcn10_verify_allow_pstate_change_high(dc);
1598         }
1599
1600         undo_DEGVIDCN10_253_wa(dc);
1601
1602         power_on_plane(dc->hwseq,
1603                 pipe_ctx->pipe_idx);
1604
1605         /* enable DCFCLK current DCHUB */
1606         REG_UPDATE(HUBP_CLK_CNTL[pipe_ctx->pipe_idx],
1607                         HUBP_CLOCK_ENABLE, 1);
1608
1609         /* make sure OPP_PIPE_CLOCK_EN = 1 */
1610         REG_UPDATE(OPP_PIPE_CONTROL[pipe_ctx->stream_res.tg->inst],
1611                         OPP_PIPE_CLOCK_EN, 1);
1612         /*TODO: REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, 0x1f);*/
1613
1614 /* TODO: enable/disable in dm as per update type.
1615         if (plane_state) {
1616                 dm_logger_write(dc->ctx->logger, LOG_DC,
1617                                 "Pipe:%d 0x%x: addr hi:0x%x, "
1618                                 "addr low:0x%x, "
1619                                 "src: %d, %d, %d,"
1620                                 " %d; dst: %d, %d, %d, %d;\n",
1621                                 pipe_ctx->pipe_idx,
1622                                 plane_state,
1623                                 plane_state->address.grph.addr.high_part,
1624                                 plane_state->address.grph.addr.low_part,
1625                                 plane_state->src_rect.x,
1626                                 plane_state->src_rect.y,
1627                                 plane_state->src_rect.width,
1628                                 plane_state->src_rect.height,
1629                                 plane_state->dst_rect.x,
1630                                 plane_state->dst_rect.y,
1631                                 plane_state->dst_rect.width,
1632                                 plane_state->dst_rect.height);
1633
1634                 dm_logger_write(dc->ctx->logger, LOG_DC,
1635                                 "Pipe %d: width, height, x, y         format:%d\n"
1636                                 "viewport:%d, %d, %d, %d\n"
1637                                 "recout:  %d, %d, %d, %d\n",
1638                                 pipe_ctx->pipe_idx,
1639                                 plane_state->format,
1640                                 pipe_ctx->plane_res.scl_data.viewport.width,
1641                                 pipe_ctx->plane_res.scl_data.viewport.height,
1642                                 pipe_ctx->plane_res.scl_data.viewport.x,
1643                                 pipe_ctx->plane_res.scl_data.viewport.y,
1644                                 pipe_ctx->plane_res.scl_data.recout.width,
1645                                 pipe_ctx->plane_res.scl_data.recout.height,
1646                                 pipe_ctx->plane_res.scl_data.recout.x,
1647                                 pipe_ctx->plane_res.scl_data.recout.y);
1648                 print_rq_dlg_ttu(dc, pipe_ctx);
1649         }
1650 */
1651         if (dc->config.gpu_vm_support)
1652                 dcn10_program_pte_vm(hws, pipe_ctx->plane_res.hubp);
1653
1654         if (dc->debug.sanity_checks) {
1655                 dcn10_verify_allow_pstate_change_high(dc);
1656         }
1657 }
1658
1659 static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
1660 {
1661         struct dpp_grph_csc_adjustment adjust;
1662         memset(&adjust, 0, sizeof(adjust));
1663         adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
1664
1665
1666         if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
1667                 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
1668                 adjust.temperature_matrix[0] =
1669                                 pipe_ctx->stream->
1670                                 gamut_remap_matrix.matrix[0];
1671                 adjust.temperature_matrix[1] =
1672                                 pipe_ctx->stream->
1673                                 gamut_remap_matrix.matrix[1];
1674                 adjust.temperature_matrix[2] =
1675                                 pipe_ctx->stream->
1676                                 gamut_remap_matrix.matrix[2];
1677                 adjust.temperature_matrix[3] =
1678                                 pipe_ctx->stream->
1679                                 gamut_remap_matrix.matrix[4];
1680                 adjust.temperature_matrix[4] =
1681                                 pipe_ctx->stream->
1682                                 gamut_remap_matrix.matrix[5];
1683                 adjust.temperature_matrix[5] =
1684                                 pipe_ctx->stream->
1685                                 gamut_remap_matrix.matrix[6];
1686                 adjust.temperature_matrix[6] =
1687                                 pipe_ctx->stream->
1688                                 gamut_remap_matrix.matrix[8];
1689                 adjust.temperature_matrix[7] =
1690                                 pipe_ctx->stream->
1691                                 gamut_remap_matrix.matrix[9];
1692                 adjust.temperature_matrix[8] =
1693                                 pipe_ctx->stream->
1694                                 gamut_remap_matrix.matrix[10];
1695         }
1696
1697         pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp, &adjust);
1698 }
1699
1700
1701 static void program_csc_matrix(struct pipe_ctx *pipe_ctx,
1702                 enum dc_color_space colorspace,
1703                 uint16_t *matrix)
1704 {
1705         int i;
1706         struct out_csc_color_matrix tbl_entry;
1707
1708         if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
1709                         enum dc_color_space color_space =
1710                                 pipe_ctx->stream->output_color_space;
1711
1712                         //uint16_t matrix[12];
1713                         for (i = 0; i < 12; i++)
1714                                 tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i];
1715
1716                         tbl_entry.color_space = color_space;
1717                         //tbl_entry.regval = matrix;
1718
1719                         if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment != NULL)
1720                                 pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, &tbl_entry);
1721         } else {
1722                 if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default != NULL)
1723                         pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default(pipe_ctx->plane_res.dpp, colorspace);
1724         }
1725 }
1726
1727 static void program_output_csc(struct dc *dc,
1728                 struct pipe_ctx *pipe_ctx,
1729                 enum dc_color_space colorspace,
1730                 uint16_t *matrix,
1731                 int opp_id)
1732 {
1733         if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment != NULL)
1734                 program_csc_matrix(pipe_ctx,
1735                                 colorspace,
1736                                 matrix);
1737 }
1738
1739 static bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
1740 {
1741         if (pipe_ctx->plane_state->visible)
1742                 return true;
1743         if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
1744                 return true;
1745         return false;
1746 }
1747
1748 static bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
1749 {
1750         if (pipe_ctx->plane_state->visible)
1751                 return true;
1752         if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
1753                 return true;
1754         return false;
1755 }
1756
1757 static bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
1758 {
1759         if (pipe_ctx->plane_state->visible)
1760                 return true;
1761         if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
1762                 return true;
1763         if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
1764                 return true;
1765         return false;
1766 }
1767
1768 static bool is_rgb_cspace(enum dc_color_space output_color_space)
1769 {
1770         switch (output_color_space) {
1771         case COLOR_SPACE_SRGB:
1772         case COLOR_SPACE_SRGB_LIMITED:
1773         case COLOR_SPACE_2020_RGB_FULLRANGE:
1774         case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
1775         case COLOR_SPACE_ADOBERGB:
1776                 return true;
1777         case COLOR_SPACE_YCBCR601:
1778         case COLOR_SPACE_YCBCR709:
1779         case COLOR_SPACE_YCBCR601_LIMITED:
1780         case COLOR_SPACE_YCBCR709_LIMITED:
1781         case COLOR_SPACE_2020_YCBCR:
1782                 return false;
1783         default:
1784                 /* Add a case to switch */
1785                 BREAK_TO_DEBUGGER();
1786                 return false;
1787         }
1788 }
1789
1790 static void dcn10_get_surface_visual_confirm_color(
1791                 const struct pipe_ctx *pipe_ctx,
1792                 struct tg_color *color)
1793 {
1794         uint32_t color_value = MAX_TG_COLOR_VALUE;
1795
1796         switch (pipe_ctx->plane_res.scl_data.format) {
1797         case PIXEL_FORMAT_ARGB8888:
1798                 /* set boarder color to red */
1799                 color->color_r_cr = color_value;
1800                 break;
1801
1802         case PIXEL_FORMAT_ARGB2101010:
1803                 /* set boarder color to blue */
1804                 color->color_b_cb = color_value;
1805                 break;
1806         case PIXEL_FORMAT_420BPP8:
1807                 /* set boarder color to green */
1808                 color->color_g_y = color_value;
1809                 break;
1810         case PIXEL_FORMAT_420BPP10:
1811                 /* set boarder color to yellow */
1812                 color->color_g_y = color_value;
1813                 color->color_r_cr = color_value;
1814                 break;
1815         case PIXEL_FORMAT_FP16:
1816                 /* set boarder color to white */
1817                 color->color_r_cr = color_value;
1818                 color->color_b_cb = color_value;
1819                 color->color_g_y = color_value;
1820                 break;
1821         default:
1822                 break;
1823         }
1824 }
1825
1826 static uint16_t fixed_point_to_int_frac(
1827         struct fixed31_32 arg,
1828         uint8_t integer_bits,
1829         uint8_t fractional_bits)
1830 {
1831         int32_t numerator;
1832         int32_t divisor = 1 << fractional_bits;
1833
1834         uint16_t result;
1835
1836         uint16_t d = (uint16_t)dal_fixed31_32_floor(
1837                 dal_fixed31_32_abs(
1838                         arg));
1839
1840         if (d <= (uint16_t)(1 << integer_bits) - (1 / (uint16_t)divisor))
1841                 numerator = (uint16_t)dal_fixed31_32_floor(
1842                         dal_fixed31_32_mul_int(
1843                                 arg,
1844                                 divisor));
1845         else {
1846                 numerator = dal_fixed31_32_floor(
1847                         dal_fixed31_32_sub(
1848                                 dal_fixed31_32_from_int(
1849                                         1LL << integer_bits),
1850                                 dal_fixed31_32_recip(
1851                                         dal_fixed31_32_from_int(
1852                                                 divisor))));
1853         }
1854
1855         if (numerator >= 0)
1856                 result = (uint16_t)numerator;
1857         else
1858                 result = (uint16_t)(
1859                 (1 << (integer_bits + fractional_bits + 1)) + numerator);
1860
1861         if ((result != 0) && dal_fixed31_32_lt(
1862                 arg, dal_fixed31_32_zero))
1863                 result |= 1 << (integer_bits + fractional_bits);
1864
1865         return result;
1866 }
1867
1868 void build_prescale_params(struct  dc_bias_and_scale *bias_and_scale,
1869                 const struct dc_plane_state *plane_state)
1870 {
1871         if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
1872                         && plane_state->format != SURFACE_PIXEL_FORMAT_INVALID
1873                         && plane_state->input_csc_color_matrix.enable_adjustment
1874                         && plane_state->coeff_reduction_factor.value != 0) {
1875                 bias_and_scale->scale_blue = fixed_point_to_int_frac(
1876                         dal_fixed31_32_mul(plane_state->coeff_reduction_factor,
1877                                         dal_fixed31_32_from_fraction(256, 255)),
1878                                 2,
1879                                 13);
1880                 bias_and_scale->scale_red = bias_and_scale->scale_blue;
1881                 bias_and_scale->scale_green = bias_and_scale->scale_blue;
1882         } else {
1883                 bias_and_scale->scale_blue = 0x2000;
1884                 bias_and_scale->scale_red = 0x2000;
1885                 bias_and_scale->scale_green = 0x2000;
1886         }
1887 }
1888
1889 static void update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state)
1890 {
1891         struct dc_bias_and_scale bns_params = {0};
1892
1893         // program the input csc
1894         dpp->funcs->dpp_setup(dpp,
1895                         plane_state->format,
1896                         EXPANSION_MODE_ZERO,
1897                         plane_state->input_csc_color_matrix,
1898                         COLOR_SPACE_YCBCR601_LIMITED);
1899
1900         //set scale and bias registers
1901         build_prescale_params(&bns_params, plane_state);
1902         if (dpp->funcs->dpp_program_bias_and_scale)
1903                 dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
1904 }
1905
1906 static void update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
1907 {
1908         struct hubp *hubp = pipe_ctx->plane_res.hubp;
1909         struct mpcc_blnd_cfg blnd_cfg;
1910         bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
1911         int mpcc_id;
1912         struct mpcc *new_mpcc;
1913         struct mpc *mpc = dc->res_pool->mpc;
1914         struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);
1915
1916         /* TODO: proper fix once fpga works */
1917
1918         if (dc->debug.surface_visual_confirm)
1919                 dcn10_get_surface_visual_confirm_color(
1920                                 pipe_ctx, &blnd_cfg.black_color);
1921         else
1922                 color_space_to_black_color(
1923                         dc, pipe_ctx->stream->output_color_space,
1924                         &blnd_cfg.black_color);
1925
1926         if (per_pixel_alpha)
1927                 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;
1928         else
1929                 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA;
1930
1931         blnd_cfg.overlap_only = false;
1932         blnd_cfg.global_alpha = 0xff;
1933         blnd_cfg.global_gain = 0xff;
1934
1935         /* DCN1.0 has output CM before MPC which seems to screw with
1936          * pre-multiplied alpha.
1937          */
1938         blnd_cfg.pre_multiplied_alpha = is_rgb_cspace(
1939                         pipe_ctx->stream->output_color_space)
1940                                         && per_pixel_alpha;
1941
1942         /*
1943          * TODO: remove hack
1944          * Note: currently there is a bug in init_hw such that
1945          * on resume from hibernate, BIOS sets up MPCC0, and
1946          * we do mpcc_remove but the mpcc cannot go to idle
1947          * after remove. This cause us to pick mpcc1 here,
1948          * which causes a pstate hang for yet unknown reason.
1949          */
1950         mpcc_id = hubp->inst;
1951
1952         /* check if this MPCC is already being used */
1953         new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id);
1954         /* remove MPCC if being used */
1955         if (new_mpcc != NULL)
1956                 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc);
1957         else
1958                 if (dc->debug.sanity_checks)
1959                         mpc->funcs->assert_mpcc_idle_before_connect(
1960                                         dc->res_pool->mpc, mpcc_id);
1961
1962         /* Call MPC to insert new plane */
1963         new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,
1964                         mpc_tree_params,
1965                         &blnd_cfg,
1966                         NULL,
1967                         NULL,
1968                         hubp->inst,
1969                         mpcc_id);
1970
1971         ASSERT(new_mpcc != NULL);
1972
1973         hubp->opp_id = pipe_ctx->stream_res.opp->inst;
1974         hubp->mpcc_id = mpcc_id;
1975 }
1976
1977 static void update_scaler(struct pipe_ctx *pipe_ctx)
1978 {
1979         bool per_pixel_alpha =
1980                         pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
1981
1982         /* TODO: proper fix once fpga works */
1983
1984         pipe_ctx->plane_res.scl_data.lb_params.alpha_en = per_pixel_alpha;
1985         pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
1986         /* scaler configuration */
1987         pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(
1988                         pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);
1989 }
1990
1991 static void update_dchubp_dpp(
1992         struct dc *dc,
1993         struct pipe_ctx *pipe_ctx,
1994         struct dc_state *context)
1995 {
1996         struct dce_hwseq *hws = dc->hwseq;
1997         struct hubp *hubp = pipe_ctx->plane_res.hubp;
1998         struct dpp *dpp = pipe_ctx->plane_res.dpp;
1999         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2000         union plane_size size = plane_state->plane_size;
2001
2002         /* depends on DML calculation, DPP clock value may change dynamically */
2003         if (pipe_ctx->plane_state->update_flags.raw != 0) {
2004                 enable_dppclk(
2005                         dc->hwseq,
2006                         pipe_ctx->pipe_idx,
2007                         pipe_ctx->stream_res.pix_clk_params.requested_pix_clk,
2008                         context->bw.dcn.calc_clk.dppclk_div);
2009                 dc->current_state->bw.dcn.cur_clk.dppclk_div =
2010                                 context->bw.dcn.calc_clk.dppclk_div;
2011                 context->bw.dcn.cur_clk.dppclk_div = context->bw.dcn.calc_clk.dppclk_div;
2012         }
2013
2014         /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG
2015          * VTG is within DCHUBBUB which is commond block share by each pipe HUBP.
2016          * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG
2017          */
2018         if (plane_state->update_flags.bits.full_update) {
2019                 REG_UPDATE(DCHUBP_CNTL[pipe_ctx->pipe_idx], HUBP_VTG_SEL, pipe_ctx->stream_res.tg->inst);
2020
2021                 hubp->funcs->hubp_setup(
2022                         hubp,
2023                         &pipe_ctx->dlg_regs,
2024                         &pipe_ctx->ttu_regs,
2025                         &pipe_ctx->rq_regs,
2026                         &pipe_ctx->pipe_dlg_param);
2027         }
2028
2029         size.grph.surface_size = pipe_ctx->plane_res.scl_data.viewport;
2030
2031         if (plane_state->update_flags.bits.full_update ||
2032                 plane_state->update_flags.bits.bpp_change)
2033                 update_dpp(dpp, plane_state);
2034
2035         if (plane_state->update_flags.bits.full_update ||
2036                 plane_state->update_flags.bits.per_pixel_alpha_change)
2037                 update_mpcc(dc, pipe_ctx);
2038
2039         if (plane_state->update_flags.bits.full_update ||
2040                 plane_state->update_flags.bits.per_pixel_alpha_change ||
2041                 plane_state->update_flags.bits.scaling_change ||
2042                 plane_state->update_flags.bits.position_change) {
2043                 update_scaler(pipe_ctx);
2044         }
2045
2046         if (plane_state->update_flags.bits.full_update ||
2047                 plane_state->update_flags.bits.scaling_change) {
2048                 hubp->funcs->mem_program_viewport(
2049                         hubp,
2050                         &pipe_ctx->plane_res.scl_data.viewport,
2051                         &pipe_ctx->plane_res.scl_data.viewport_c);
2052         }
2053
2054         if (plane_state->update_flags.bits.full_update) {
2055                 /*gamut remap*/
2056                 program_gamut_remap(pipe_ctx);
2057
2058                 program_output_csc(dc,
2059                                 pipe_ctx,
2060                                 pipe_ctx->stream->output_color_space,
2061                                 pipe_ctx->stream->csc_color_matrix.matrix,
2062                                 hubp->opp_id);
2063         }
2064
2065         if (plane_state->update_flags.bits.full_update ||
2066                 plane_state->update_flags.bits.horizontal_mirror_change ||
2067                 plane_state->update_flags.bits.rotation_change ||
2068                 plane_state->update_flags.bits.swizzle_change ||
2069                 plane_state->update_flags.bits.bpp_change) {
2070                 hubp->funcs->hubp_program_surface_config(
2071                         hubp,
2072                         plane_state->format,
2073                         &plane_state->tiling_info,
2074                         &size,
2075                         plane_state->rotation,
2076                         &plane_state->dcc,
2077                         plane_state->horizontal_mirror);
2078         }
2079
2080         hubp->power_gated = false;
2081
2082         dc->hwss.update_plane_addr(dc, pipe_ctx);
2083
2084         if (is_pipe_tree_visible(pipe_ctx))
2085                 hubp->funcs->set_blank(hubp, false);
2086 }
2087
2088
2089 static void program_all_pipe_in_tree(
2090                 struct dc *dc,
2091                 struct pipe_ctx *pipe_ctx,
2092                 struct dc_state *context)
2093 {
2094         if (pipe_ctx->top_pipe == NULL) {
2095
2096                 pipe_ctx->stream_res.tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset;
2097                 pipe_ctx->stream_res.tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start;
2098                 pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset;
2099                 pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_width = pipe_ctx->pipe_dlg_param.vupdate_width;
2100                 pipe_ctx->stream_res.tg->dlg_otg_param.signal =  pipe_ctx->stream->signal;
2101
2102                 pipe_ctx->stream_res.tg->funcs->program_global_sync(
2103                                 pipe_ctx->stream_res.tg);
2104                 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, !is_pipe_tree_visible(pipe_ctx));
2105         }
2106
2107         if (pipe_ctx->plane_state != NULL) {
2108                 struct pipe_ctx *cur_pipe_ctx =
2109                                 &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
2110
2111                 if (pipe_ctx->plane_state->update_flags.bits.full_update)
2112                         dcn10_enable_plane(dc, pipe_ctx, context);
2113
2114                 update_dchubp_dpp(dc, pipe_ctx, context);
2115
2116                 if (cur_pipe_ctx->plane_state != pipe_ctx->plane_state)
2117                         dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state);
2118
2119                 /* dcn10_translate_regamma_to_hw_format takes 750us to finish
2120                  * only do gamma programming for full update.
2121                  * TODO: This can be further optimized/cleaned up
2122                  * Always call this for now since it does memcmp inside before
2123                  * doing heavy calculation and programming
2124                  */
2125                 if (pipe_ctx->plane_state->update_flags.bits.full_update)
2126                         dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);
2127         }
2128
2129         if (pipe_ctx->bottom_pipe != NULL && pipe_ctx->bottom_pipe != pipe_ctx)
2130                 program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context);
2131 }
2132
2133 static void dcn10_pplib_apply_display_requirements(
2134         struct dc *dc,
2135         struct dc_state *context)
2136 {
2137         struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
2138
2139         pp_display_cfg->all_displays_in_sync = false;/*todo*/
2140         pp_display_cfg->nb_pstate_switch_disable = false;
2141         pp_display_cfg->min_engine_clock_khz = context->bw.dcn.cur_clk.dcfclk_khz;
2142         pp_display_cfg->min_memory_clock_khz = context->bw.dcn.cur_clk.fclk_khz;
2143         pp_display_cfg->min_engine_clock_deep_sleep_khz = context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz;
2144         pp_display_cfg->min_dcfc_deep_sleep_clock_khz = context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz;
2145         pp_display_cfg->avail_mclk_switch_time_us =
2146                         context->bw.dcn.cur_clk.dram_ccm_us > 0 ? context->bw.dcn.cur_clk.dram_ccm_us : 0;
2147         pp_display_cfg->avail_mclk_switch_time_in_disp_active_us =
2148                         context->bw.dcn.cur_clk.min_active_dram_ccm_us > 0 ? context->bw.dcn.cur_clk.min_active_dram_ccm_us : 0;
2149         pp_display_cfg->min_dcfclock_khz = context->bw.dcn.cur_clk.dcfclk_khz;
2150         pp_display_cfg->disp_clk_khz = context->bw.dcn.cur_clk.dispclk_khz;
2151         dce110_fill_display_configs(context, pp_display_cfg);
2152
2153         if (memcmp(&dc->prev_display_config, pp_display_cfg, sizeof(
2154                         struct dm_pp_display_configuration)) !=  0)
2155                 dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
2156
2157         dc->prev_display_config = *pp_display_cfg;
2158 }
2159
2160 static void optimize_shared_resources(struct dc *dc)
2161 {
2162         if (dc->current_state->stream_count == 0) {
2163                 /* S0i2 message */
2164                 dcn10_pplib_apply_display_requirements(dc, dc->current_state);
2165         }
2166
2167         if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE)
2168                 dcn_bw_notify_pplib_of_wm_ranges(dc);
2169 }
2170
2171 static void ready_shared_resources(struct dc *dc, struct dc_state *context)
2172 {
2173         /* S0i2 message */
2174         if (dc->current_state->stream_count == 0 &&
2175                         context->stream_count != 0)
2176                 dcn10_pplib_apply_display_requirements(dc, context);
2177 }
2178
2179 static struct pipe_ctx *find_top_pipe_for_stream(
2180                 struct dc *dc,
2181                 struct dc_state *context,
2182                 const struct dc_stream_state *stream)
2183 {
2184         int i;
2185
2186         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2187                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2188                 struct pipe_ctx *old_pipe_ctx =
2189                                 &dc->current_state->res_ctx.pipe_ctx[i];
2190
2191                 if (!pipe_ctx->plane_state && !old_pipe_ctx->plane_state)
2192                         continue;
2193
2194                 if (pipe_ctx->stream != stream)
2195                         continue;
2196
2197                 if (!pipe_ctx->top_pipe)
2198                         return pipe_ctx;
2199         }
2200         return NULL;
2201 }
2202
2203 static void dcn10_apply_ctx_for_surface(
2204                 struct dc *dc,
2205                 const struct dc_stream_state *stream,
2206                 int num_planes,
2207                 struct dc_state *context)
2208 {
2209         int i;
2210         struct timing_generator *tg;
2211         bool removed_pipe[4] = { false };
2212         unsigned int ref_clk_mhz = dc->res_pool->ref_clock_inKhz/1000;
2213         bool program_water_mark = false;
2214
2215         struct pipe_ctx *top_pipe_to_program =
2216                         find_top_pipe_for_stream(dc, context, stream);
2217
2218         if (!top_pipe_to_program)
2219                 return;
2220
2221         tg = top_pipe_to_program->stream_res.tg;
2222
2223         tg->funcs->lock(tg);
2224
2225         if (num_planes == 0) {
2226
2227                 /* OTG blank before remove all front end */
2228                 tg->funcs->set_blank(tg, true);
2229         }
2230
2231         /* Disconnect unused mpcc */
2232         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2233                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2234                 struct pipe_ctx *old_pipe_ctx =
2235                                 &dc->current_state->res_ctx.pipe_ctx[i];
2236                 /*
2237                  * Powergate reused pipes that are not powergated
2238                  * fairly hacky right now, using opp_id as indicator
2239                  * TODO: After move dc_post to dc_update, this will
2240                  * be removed.
2241                  */
2242                 if (pipe_ctx->plane_state && !old_pipe_ctx->plane_state) {
2243                         if (old_pipe_ctx->stream_res.tg == tg &&
2244                                 old_pipe_ctx->plane_res.hubp &&
2245                                 old_pipe_ctx->plane_res.hubp->opp_id != 0xf) {
2246                                 dcn10_disable_plane(dc, pipe_ctx);
2247                                 /*
2248                                  * power down fe will unlock when calling reset, need
2249                                  * to lock it back here. Messy, need rework.
2250                                  */
2251                                 pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg);
2252                         }
2253                 }
2254
2255                 if (!pipe_ctx->plane_state &&
2256                         old_pipe_ctx->plane_state &&
2257                         old_pipe_ctx->stream_res.tg == tg) {
2258
2259                         plane_atomic_disconnect(dc, old_pipe_ctx);
2260                         removed_pipe[i] = true;
2261
2262                         dm_logger_write(dc->ctx->logger, LOG_DC,
2263                                         "Reset mpcc for pipe %d\n",
2264                                         old_pipe_ctx->pipe_idx);
2265                 }
2266         }
2267
2268         if (num_planes > 0) {
2269                 program_all_pipe_in_tree(dc, top_pipe_to_program, context);
2270
2271                 /* TODO: this is a hack w/a for switching from mpo to pipe split */
2272                 if (stream->cursor_attributes.address.quad_part != 0) {
2273                         struct dc_cursor_position position = { 0 };
2274
2275                         dc_stream_set_cursor_position(
2276                                 (struct dc_stream_state *)stream,
2277                                 &position);
2278                         dc_stream_set_cursor_attributes(
2279                                 (struct dc_stream_state *)stream,
2280                                 &stream->cursor_attributes);
2281                 }
2282         }
2283
2284         tg->funcs->unlock(tg);
2285
2286         if (num_planes == 0)
2287                 false_optc_underflow_wa(dc, stream, tg);
2288
2289         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2290                 struct pipe_ctx *old_pipe_ctx =
2291                                 &dc->current_state->res_ctx.pipe_ctx[i];
2292                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2293
2294                 if (pipe_ctx->stream == stream &&
2295                                 pipe_ctx->plane_state &&
2296                         pipe_ctx->plane_state->update_flags.bits.full_update)
2297                         program_water_mark = true;
2298
2299                 if (removed_pipe[i] && num_planes == 0)
2300                         dcn10_disable_plane(dc, old_pipe_ctx);
2301         }
2302
2303         if (program_water_mark) {
2304                 if (dc->debug.sanity_checks) {
2305                         /* pstate stuck check after watermark update */
2306                         dcn10_verify_allow_pstate_change_high(dc);
2307                 }
2308                 /* watermark is for all pipes */
2309                 hubbub1_program_watermarks(dc->res_pool->hubbub,
2310                                 &context->bw.dcn.watermarks, ref_clk_mhz);
2311
2312                 if (dc->debug.sanity_checks) {
2313                         /* pstate stuck check after watermark update */
2314                         dcn10_verify_allow_pstate_change_high(dc);
2315                 }
2316         }
2317 /*      dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS,
2318                         "\n============== Watermark parameters ==============\n"
2319                         "a.urgent_ns: %d \n"
2320                         "a.cstate_enter_plus_exit: %d \n"
2321                         "a.cstate_exit: %d \n"
2322                         "a.pstate_change: %d \n"
2323                         "a.pte_meta_urgent: %d \n"
2324                         "b.urgent_ns: %d \n"
2325                         "b.cstate_enter_plus_exit: %d \n"
2326                         "b.cstate_exit: %d \n"
2327                         "b.pstate_change: %d \n"
2328                         "b.pte_meta_urgent: %d \n",
2329                         context->bw.dcn.watermarks.a.urgent_ns,
2330                         context->bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns,
2331                         context->bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns,
2332                         context->bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns,
2333                         context->bw.dcn.watermarks.a.pte_meta_urgent_ns,
2334                         context->bw.dcn.watermarks.b.urgent_ns,
2335                         context->bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns,
2336                         context->bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns,
2337                         context->bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns,
2338                         context->bw.dcn.watermarks.b.pte_meta_urgent_ns
2339                         );
2340         dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS,
2341                         "\nc.urgent_ns: %d \n"
2342                         "c.cstate_enter_plus_exit: %d \n"
2343                         "c.cstate_exit: %d \n"
2344                         "c.pstate_change: %d \n"
2345                         "c.pte_meta_urgent: %d \n"
2346                         "d.urgent_ns: %d \n"
2347                         "d.cstate_enter_plus_exit: %d \n"
2348                         "d.cstate_exit: %d \n"
2349                         "d.pstate_change: %d \n"
2350                         "d.pte_meta_urgent: %d \n"
2351                         "========================================================\n",
2352                         context->bw.dcn.watermarks.c.urgent_ns,
2353                         context->bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns,
2354                         context->bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns,
2355                         context->bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns,
2356                         context->bw.dcn.watermarks.c.pte_meta_urgent_ns,
2357                         context->bw.dcn.watermarks.d.urgent_ns,
2358                         context->bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns,
2359                         context->bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns,
2360                         context->bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns,
2361                         context->bw.dcn.watermarks.d.pte_meta_urgent_ns
2362                         );
2363 */
2364 }
2365
2366 static void dcn10_set_bandwidth(
2367                 struct dc *dc,
2368                 struct dc_state *context,
2369                 bool decrease_allowed)
2370 {
2371         struct pp_smu_display_requirement_rv *smu_req_cur =
2372                         &dc->res_pool->pp_smu_req;
2373         struct pp_smu_display_requirement_rv smu_req = *smu_req_cur;
2374         struct pp_smu_funcs_rv *pp_smu = dc->res_pool->pp_smu;
2375
2376         if (dc->debug.sanity_checks) {
2377                 dcn10_verify_allow_pstate_change_high(dc);
2378         }
2379
2380         if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
2381                 return;
2382
2383         if (decrease_allowed || context->bw.dcn.calc_clk.dispclk_khz
2384                         > dc->current_state->bw.dcn.cur_clk.dispclk_khz) {
2385                 dc->res_pool->display_clock->funcs->set_clock(
2386                                 dc->res_pool->display_clock,
2387                                 context->bw.dcn.calc_clk.dispclk_khz);
2388                 dc->current_state->bw.dcn.cur_clk.dispclk_khz =
2389                                 context->bw.dcn.calc_clk.dispclk_khz;
2390         }
2391         if (decrease_allowed || context->bw.dcn.calc_clk.dcfclk_khz
2392                         > dc->current_state->bw.dcn.cur_clk.dcfclk_khz) {
2393                 smu_req.hard_min_dcefclk_khz =
2394                                 context->bw.dcn.calc_clk.dcfclk_khz;
2395         }
2396         if (decrease_allowed || context->bw.dcn.calc_clk.fclk_khz
2397                         > dc->current_state->bw.dcn.cur_clk.fclk_khz) {
2398                 smu_req.hard_min_fclk_khz = context->bw.dcn.calc_clk.fclk_khz;
2399         }
2400         if (decrease_allowed || context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz
2401                         > dc->current_state->bw.dcn.cur_clk.dcfclk_deep_sleep_khz) {
2402                 dc->current_state->bw.dcn.calc_clk.dcfclk_deep_sleep_khz =
2403                                 context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz;
2404                 context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz =
2405                                 context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz;
2406         }
2407
2408         smu_req.display_count = context->stream_count;
2409
2410         if (pp_smu->set_display_requirement)
2411                 pp_smu->set_display_requirement(&pp_smu->pp_smu, &smu_req);
2412
2413         *smu_req_cur = smu_req;
2414
2415         /* Decrease in freq is increase in period so opposite comparison for dram_ccm */
2416         if (decrease_allowed || context->bw.dcn.calc_clk.dram_ccm_us
2417                         < dc->current_state->bw.dcn.cur_clk.dram_ccm_us) {
2418                 dc->current_state->bw.dcn.calc_clk.dram_ccm_us =
2419                                 context->bw.dcn.calc_clk.dram_ccm_us;
2420                 context->bw.dcn.cur_clk.dram_ccm_us =
2421                                 context->bw.dcn.calc_clk.dram_ccm_us;
2422         }
2423         if (decrease_allowed || context->bw.dcn.calc_clk.min_active_dram_ccm_us
2424                         < dc->current_state->bw.dcn.cur_clk.min_active_dram_ccm_us) {
2425                 dc->current_state->bw.dcn.calc_clk.min_active_dram_ccm_us =
2426                                 context->bw.dcn.calc_clk.min_active_dram_ccm_us;
2427                 context->bw.dcn.cur_clk.min_active_dram_ccm_us =
2428                                 context->bw.dcn.calc_clk.min_active_dram_ccm_us;
2429         }
2430         dcn10_pplib_apply_display_requirements(dc, context);
2431
2432         if (dc->debug.sanity_checks) {
2433                 dcn10_verify_allow_pstate_change_high(dc);
2434         }
2435
2436         /* need to fix this function.  not doing the right thing here */
2437 }
2438
2439 static void set_drr(struct pipe_ctx **pipe_ctx,
2440                 int num_pipes, int vmin, int vmax)
2441 {
2442         int i = 0;
2443         struct drr_params params = {0};
2444
2445         params.vertical_total_max = vmax;
2446         params.vertical_total_min = vmin;
2447
2448         /* TODO: If multiple pipes are to be supported, you need
2449          * some GSL stuff
2450          */
2451         for (i = 0; i < num_pipes; i++) {
2452                 pipe_ctx[i]->stream_res.tg->funcs->set_drr(pipe_ctx[i]->stream_res.tg, &params);
2453         }
2454 }
2455
2456 static void get_position(struct pipe_ctx **pipe_ctx,
2457                 int num_pipes,
2458                 struct crtc_position *position)
2459 {
2460         int i = 0;
2461
2462         /* TODO: handle pipes > 1
2463          */
2464         for (i = 0; i < num_pipes; i++)
2465                 pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);
2466 }
2467
2468 static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
2469                 int num_pipes, const struct dc_static_screen_events *events)
2470 {
2471         unsigned int i;
2472         unsigned int value = 0;
2473
2474         if (events->surface_update)
2475                 value |= 0x80;
2476         if (events->cursor_update)
2477                 value |= 0x2;
2478
2479         for (i = 0; i < num_pipes; i++)
2480                 pipe_ctx[i]->stream_res.tg->funcs->
2481                         set_static_screen_control(pipe_ctx[i]->stream_res.tg, value);
2482 }
2483
2484 static void set_plane_config(
2485         const struct dc *dc,
2486         struct pipe_ctx *pipe_ctx,
2487         struct resource_context *res_ctx)
2488 {
2489         /* TODO */
2490         program_gamut_remap(pipe_ctx);
2491 }
2492
2493 static void dcn10_config_stereo_parameters(
2494                 struct dc_stream_state *stream, struct crtc_stereo_flags *flags)
2495 {
2496         enum view_3d_format view_format = stream->view_format;
2497         enum dc_timing_3d_format timing_3d_format =\
2498                         stream->timing.timing_3d_format;
2499         bool non_stereo_timing = false;
2500
2501         if (timing_3d_format == TIMING_3D_FORMAT_NONE ||
2502                 timing_3d_format == TIMING_3D_FORMAT_SIDE_BY_SIDE ||
2503                 timing_3d_format == TIMING_3D_FORMAT_TOP_AND_BOTTOM)
2504                 non_stereo_timing = true;
2505
2506         if (non_stereo_timing == false &&
2507                 view_format == VIEW_3D_FORMAT_FRAME_SEQUENTIAL) {
2508
2509                 flags->PROGRAM_STEREO         = 1;
2510                 flags->PROGRAM_POLARITY       = 1;
2511                 if (timing_3d_format == TIMING_3D_FORMAT_INBAND_FA ||
2512                         timing_3d_format == TIMING_3D_FORMAT_DP_HDMI_INBAND_FA ||
2513                         timing_3d_format == TIMING_3D_FORMAT_SIDEBAND_FA) {
2514                         enum display_dongle_type dongle = \
2515                                         stream->sink->link->ddc->dongle_type;
2516                         if (dongle == DISPLAY_DONGLE_DP_VGA_CONVERTER ||
2517                                 dongle == DISPLAY_DONGLE_DP_DVI_CONVERTER ||
2518                                 dongle == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
2519                                 flags->DISABLE_STEREO_DP_SYNC = 1;
2520                 }
2521                 flags->RIGHT_EYE_POLARITY =\
2522                                 stream->timing.flags.RIGHT_EYE_3D_POLARITY;
2523                 if (timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
2524                         flags->FRAME_PACKED = 1;
2525         }
2526
2527         return;
2528 }
2529
2530 static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc)
2531 {
2532         struct crtc_stereo_flags flags = { 0 };
2533         struct dc_stream_state *stream = pipe_ctx->stream;
2534
2535         dcn10_config_stereo_parameters(stream, &flags);
2536
2537         pipe_ctx->stream_res.opp->funcs->opp_set_stereo_polarity(
2538                 pipe_ctx->stream_res.opp,
2539                 flags.PROGRAM_STEREO == 1 ? true:false,
2540                 stream->timing.flags.RIGHT_EYE_3D_POLARITY == 1 ? true:false);
2541
2542         pipe_ctx->stream_res.tg->funcs->program_stereo(
2543                 pipe_ctx->stream_res.tg,
2544                 &stream->timing,
2545                 &flags);
2546
2547         return;
2548 }
2549
2550 static void dcn10_wait_for_mpcc_disconnect(
2551                 struct dc *dc,
2552                 struct resource_pool *res_pool,
2553                 struct pipe_ctx *pipe_ctx)
2554 {
2555         int i;
2556
2557         if (dc->debug.sanity_checks) {
2558                 dcn10_verify_allow_pstate_change_high(dc);
2559         }
2560
2561         if (!pipe_ctx->stream_res.opp)
2562                 return;
2563
2564         for (i = 0; i < MAX_PIPES; i++) {
2565                 if (pipe_ctx->stream_res.opp->mpcc_disconnect_pending[i]) {
2566                         res_pool->mpc->funcs->wait_for_idle(res_pool->mpc, i);
2567                         pipe_ctx->stream_res.opp->mpcc_disconnect_pending[i] = false;
2568                         res_pool->hubps[i]->funcs->set_blank(res_pool->hubps[i], true);
2569                         /*dm_logger_write(dc->ctx->logger, LOG_ERROR,
2570                                         "[debug_mpo: wait_for_mpcc finished waiting on mpcc %d]\n",
2571                                         i);*/
2572                 }
2573         }
2574
2575         if (dc->debug.sanity_checks) {
2576                 dcn10_verify_allow_pstate_change_high(dc);
2577         }
2578
2579 }
2580
2581 static bool dcn10_dummy_display_power_gating(
2582         struct dc *dc,
2583         uint8_t controller_id,
2584         struct dc_bios *dcb,
2585         enum pipe_gating_control power_gating)
2586 {
2587         return true;
2588 }
2589
2590 void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx)
2591 {
2592         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2593         struct timing_generator *tg = pipe_ctx->stream_res.tg;
2594
2595         if (plane_state == NULL)
2596                 return;
2597
2598         plane_state->status.is_flip_pending =
2599                         pipe_ctx->plane_res.hubp->funcs->hubp_is_flip_pending(
2600                                         pipe_ctx->plane_res.hubp);
2601
2602         plane_state->status.current_address = pipe_ctx->plane_res.hubp->current_address;
2603         if (pipe_ctx->plane_res.hubp->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2604                         tg->funcs->is_stereo_left_eye) {
2605                 plane_state->status.is_right_eye =
2606                                 !tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);
2607         }
2608 }
2609
2610 void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data)
2611 {
2612         if (hws->ctx->dc->res_pool->hubbub != NULL)
2613                 hubbub1_update_dchub(hws->ctx->dc->res_pool->hubbub, dh_data);
2614 }
2615
2616 static const struct hw_sequencer_funcs dcn10_funcs = {
2617         .program_gamut_remap = program_gamut_remap,
2618         .program_csc_matrix = program_csc_matrix,
2619         .init_hw = dcn10_init_hw,
2620         .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
2621         .apply_ctx_for_surface = dcn10_apply_ctx_for_surface,
2622         .set_plane_config = set_plane_config,
2623         .update_plane_addr = dcn10_update_plane_addr,
2624         .update_dchub = dcn10_update_dchub,
2625         .update_pending_status = dcn10_update_pending_status,
2626         .set_input_transfer_func = dcn10_set_input_transfer_func,
2627         .set_output_transfer_func = dcn10_set_output_transfer_func,
2628         .power_down = dce110_power_down,
2629         .enable_accelerated_mode = dce110_enable_accelerated_mode,
2630         .enable_timing_synchronization = dcn10_enable_timing_synchronization,
2631         .enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,
2632         .update_info_frame = dce110_update_info_frame,
2633         .enable_stream = dce110_enable_stream,
2634         .disable_stream = dce110_disable_stream,
2635         .unblank_stream = dce110_unblank_stream,
2636         .enable_display_power_gating = dcn10_dummy_display_power_gating,
2637         .disable_plane = dcn10_disable_plane,
2638         .pipe_control_lock = dcn10_pipe_control_lock,
2639         .set_bandwidth = dcn10_set_bandwidth,
2640         .reset_hw_ctx_wrap = reset_hw_ctx_wrap,
2641         .prog_pixclk_crtc_otg = dcn10_prog_pixclk_crtc_otg,
2642         .set_drr = set_drr,
2643         .get_position = get_position,
2644         .set_static_screen_control = set_static_screen_control,
2645         .setup_stereo = dcn10_setup_stereo,
2646         .set_avmute = dce110_set_avmute,
2647         .log_hw_state = dcn10_log_hw_state,
2648         .wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
2649         .ready_shared_resources = ready_shared_resources,
2650         .optimize_shared_resources = optimize_shared_resources,
2651         .pplib_apply_display_requirements =
2652                         dcn10_pplib_apply_display_requirements,
2653         .edp_backlight_control = hwss_edp_backlight_control,
2654         .edp_power_control = hwss_edp_power_control
2655 };
2656
2657
2658 void dcn10_hw_sequencer_construct(struct dc *dc)
2659 {
2660         dc->hwss = dcn10_funcs;
2661 }
2662