2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include "dm_services.h"
27 #include "core_types.h"
29 #include "custom_float.h"
30 #include "dcn10_hw_sequencer.h"
31 #include "dce110/dce110_hw_sequencer.h"
32 #include "dce/dce_hwseq.h"
35 #include "dcn10_optc.h"
36 #include "dcn10/dcn10_dpp.h"
37 #include "dcn10/dcn10_mpc.h"
38 #include "timing_generator.h"
42 #include "reg_helper.h"
43 #include "dcn10_hubp.h"
44 #include "dcn10_hubbub.h"
45 #include "dcn10_cm_common.h"
46 #include "dc_link_dp.h"
51 #define DC_LOGGER_INIT(logger)
59 #define FN(reg_name, field_name) \
60 hws->shifts->field_name, hws->masks->field_name
62 /*print is 17 wide, first two characters are spaces*/
63 #define DTN_INFO_MICRO_SEC(ref_cycle) \
64 print_microsec(dc_ctx, log_ctx, ref_cycle)
66 void print_microsec(struct dc_context *dc_ctx,
67 struct dc_log_buffer_ctx *log_ctx,
70 const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000;
71 static const unsigned int frac = 1000;
72 uint32_t us_x10 = (ref_cycle * frac) / ref_clk_mhz;
74 DTN_INFO(" %11d.%03d",
79 static void log_mpc_crc(struct dc *dc,
80 struct dc_log_buffer_ctx *log_ctx)
82 struct dc_context *dc_ctx = dc->ctx;
83 struct dce_hwseq *hws = dc->hwseq;
85 if (REG(MPC_CRC_RESULT_GB))
86 DTN_INFO("MPC_CRC_RESULT_GB:%d MPC_CRC_RESULT_C:%d MPC_CRC_RESULT_AR:%d\n",
87 REG_READ(MPC_CRC_RESULT_GB), REG_READ(MPC_CRC_RESULT_C), REG_READ(MPC_CRC_RESULT_AR));
88 if (REG(DPP_TOP0_DPP_CRC_VAL_B_A))
89 DTN_INFO("DPP_TOP0_DPP_CRC_VAL_B_A:%d DPP_TOP0_DPP_CRC_VAL_R_G:%d\n",
90 REG_READ(DPP_TOP0_DPP_CRC_VAL_B_A), REG_READ(DPP_TOP0_DPP_CRC_VAL_R_G));
93 void dcn10_log_hubbub_state(struct dc *dc, struct dc_log_buffer_ctx *log_ctx)
95 struct dc_context *dc_ctx = dc->ctx;
96 struct dcn_hubbub_wm wm;
99 memset(&wm, 0, sizeof(struct dcn_hubbub_wm));
100 dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm);
102 DTN_INFO("HUBBUB WM: data_urgent pte_meta_urgent"
103 " sr_enter sr_exit dram_clk_change\n");
105 for (i = 0; i < 4; i++) {
106 struct dcn_hubbub_wm_set *s;
109 DTN_INFO("WM_Set[%d]:", s->wm_set);
110 DTN_INFO_MICRO_SEC(s->data_urgent);
111 DTN_INFO_MICRO_SEC(s->pte_meta_urgent);
112 DTN_INFO_MICRO_SEC(s->sr_enter);
113 DTN_INFO_MICRO_SEC(s->sr_exit);
114 DTN_INFO_MICRO_SEC(s->dram_clk_chanage);
121 static void dcn10_log_hubp_states(struct dc *dc, void *log_ctx)
123 struct dc_context *dc_ctx = dc->ctx;
124 struct resource_pool *pool = dc->res_pool;
127 DTN_INFO("HUBP: format addr_hi width height"
128 " rot mir sw_mode dcc_en blank_en ttu_dis underflow"
129 " min_ttu_vblank qos_low_wm qos_high_wm\n");
130 for (i = 0; i < pool->pipe_count; i++) {
131 struct hubp *hubp = pool->hubps[i];
132 struct dcn_hubp_state *s = &(TO_DCN10_HUBP(hubp)->state);
134 hubp->funcs->hubp_read_state(hubp);
137 DTN_INFO("[%2d]: %5xh %6xh %5d %6d %2xh %2xh %6xh"
150 s->underflow_status);
151 DTN_INFO_MICRO_SEC(s->min_ttu_vblank);
152 DTN_INFO_MICRO_SEC(s->qos_level_low_wm);
153 DTN_INFO_MICRO_SEC(s->qos_level_high_wm);
158 DTN_INFO("\n=========RQ========\n");
159 DTN_INFO("HUBP: drq_exp_m prq_exp_m mrq_exp_m crq_exp_m plane1_ba L:chunk_s min_chu_s meta_ch_s"
160 " min_m_c_s dpte_gr_s mpte_gr_s swath_hei pte_row_h C:chunk_s min_chu_s meta_ch_s"
161 " min_m_c_s dpte_gr_s mpte_gr_s swath_hei pte_row_h\n");
162 for (i = 0; i < pool->pipe_count; i++) {
163 struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);
164 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;
167 DTN_INFO("[%2d]: %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh\n",
168 pool->hubps[i]->inst, rq_regs->drq_expansion_mode, rq_regs->prq_expansion_mode, rq_regs->mrq_expansion_mode,
169 rq_regs->crq_expansion_mode, rq_regs->plane1_base_address, rq_regs->rq_regs_l.chunk_size,
170 rq_regs->rq_regs_l.min_chunk_size, rq_regs->rq_regs_l.meta_chunk_size,
171 rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs->rq_regs_l.dpte_group_size,
172 rq_regs->rq_regs_l.mpte_group_size, rq_regs->rq_regs_l.swath_height,
173 rq_regs->rq_regs_l.pte_row_height_linear, rq_regs->rq_regs_c.chunk_size, rq_regs->rq_regs_c.min_chunk_size,
174 rq_regs->rq_regs_c.meta_chunk_size, rq_regs->rq_regs_c.min_meta_chunk_size,
175 rq_regs->rq_regs_c.dpte_group_size, rq_regs->rq_regs_c.mpte_group_size,
176 rq_regs->rq_regs_c.swath_height, rq_regs->rq_regs_c.pte_row_height_linear);
179 DTN_INFO("========DLG========\n");
180 DTN_INFO("HUBP: rc_hbe dlg_vbe min_d_y_n rc_per_ht rc_x_a_s "
181 " dst_y_a_s dst_y_pf dst_y_vvb dst_y_rvb dst_y_vfl dst_y_rfl rf_pix_fq"
182 " vratio_pf vrat_pf_c rc_pg_vbl rc_pg_vbc rc_mc_vbl rc_mc_vbc rc_pg_fll"
183 " rc_pg_flc rc_mc_fll rc_mc_flc pr_nom_l pr_nom_c rc_pg_nl rc_pg_nc "
184 " mr_nom_l mr_nom_c rc_mc_nl rc_mc_nc rc_ld_pl rc_ld_pc rc_ld_l "
185 " rc_ld_c cha_cur0 ofst_cur1 cha_cur1 vr_af_vc0 ddrq_limt x_rt_dlay"
186 " x_rp_dlay x_rr_sfl\n");
187 for (i = 0; i < pool->pipe_count; i++) {
188 struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);
189 struct _vcs_dpi_display_dlg_regs_st *dlg_regs = &s->dlg_attr;
192 DTN_INFO("[%2d]: %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh"
193 "% 8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh"
194 " %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh\n",
195 pool->hubps[i]->inst, dlg_regs->refcyc_h_blank_end, dlg_regs->dlg_vblank_end, dlg_regs->min_dst_y_next_start,
196 dlg_regs->refcyc_per_htotal, dlg_regs->refcyc_x_after_scaler, dlg_regs->dst_y_after_scaler,
197 dlg_regs->dst_y_prefetch, dlg_regs->dst_y_per_vm_vblank, dlg_regs->dst_y_per_row_vblank,
198 dlg_regs->dst_y_per_vm_flip, dlg_regs->dst_y_per_row_flip, dlg_regs->ref_freq_to_pix_freq,
199 dlg_regs->vratio_prefetch, dlg_regs->vratio_prefetch_c, dlg_regs->refcyc_per_pte_group_vblank_l,
200 dlg_regs->refcyc_per_pte_group_vblank_c, dlg_regs->refcyc_per_meta_chunk_vblank_l,
201 dlg_regs->refcyc_per_meta_chunk_vblank_c, dlg_regs->refcyc_per_pte_group_flip_l,
202 dlg_regs->refcyc_per_pte_group_flip_c, dlg_regs->refcyc_per_meta_chunk_flip_l,
203 dlg_regs->refcyc_per_meta_chunk_flip_c, dlg_regs->dst_y_per_pte_row_nom_l,
204 dlg_regs->dst_y_per_pte_row_nom_c, dlg_regs->refcyc_per_pte_group_nom_l,
205 dlg_regs->refcyc_per_pte_group_nom_c, dlg_regs->dst_y_per_meta_row_nom_l,
206 dlg_regs->dst_y_per_meta_row_nom_c, dlg_regs->refcyc_per_meta_chunk_nom_l,
207 dlg_regs->refcyc_per_meta_chunk_nom_c, dlg_regs->refcyc_per_line_delivery_pre_l,
208 dlg_regs->refcyc_per_line_delivery_pre_c, dlg_regs->refcyc_per_line_delivery_l,
209 dlg_regs->refcyc_per_line_delivery_c, dlg_regs->chunk_hdl_adjust_cur0, dlg_regs->dst_y_offset_cur1,
210 dlg_regs->chunk_hdl_adjust_cur1, dlg_regs->vready_after_vcount0, dlg_regs->dst_y_delta_drq_limit,
211 dlg_regs->xfc_reg_transfer_delay, dlg_regs->xfc_reg_precharge_delay,
212 dlg_regs->xfc_reg_remote_surface_flip_latency);
215 DTN_INFO("========TTU========\n");
216 DTN_INFO("HUBP: qos_ll_wm qos_lh_wm mn_ttu_vb qos_l_flp rc_rd_p_l rc_rd_l rc_rd_p_c"
217 " rc_rd_c rc_rd_c0 rc_rd_pc0 rc_rd_c1 rc_rd_pc1 qos_lf_l qos_rds_l"
218 " qos_lf_c qos_rds_c qos_lf_c0 qos_rds_c0 qos_lf_c1 qos_rds_c1\n");
219 for (i = 0; i < pool->pipe_count; i++) {
220 struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);
221 struct _vcs_dpi_display_ttu_regs_st *ttu_regs = &s->ttu_attr;
224 DTN_INFO("[%2d]: %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh\n",
225 pool->hubps[i]->inst, ttu_regs->qos_level_low_wm, ttu_regs->qos_level_high_wm, ttu_regs->min_ttu_vblank,
226 ttu_regs->qos_level_flip, ttu_regs->refcyc_per_req_delivery_pre_l, ttu_regs->refcyc_per_req_delivery_l,
227 ttu_regs->refcyc_per_req_delivery_pre_c, ttu_regs->refcyc_per_req_delivery_c, ttu_regs->refcyc_per_req_delivery_cur0,
228 ttu_regs->refcyc_per_req_delivery_pre_cur0, ttu_regs->refcyc_per_req_delivery_cur1,
229 ttu_regs->refcyc_per_req_delivery_pre_cur1, ttu_regs->qos_level_fixed_l, ttu_regs->qos_ramp_disable_l,
230 ttu_regs->qos_level_fixed_c, ttu_regs->qos_ramp_disable_c, ttu_regs->qos_level_fixed_cur0,
231 ttu_regs->qos_ramp_disable_cur0, ttu_regs->qos_level_fixed_cur1, ttu_regs->qos_ramp_disable_cur1);
236 void dcn10_log_hw_state(struct dc *dc,
237 struct dc_log_buffer_ctx *log_ctx)
239 struct dc_context *dc_ctx = dc->ctx;
240 struct resource_pool *pool = dc->res_pool;
245 dcn10_log_hubbub_state(dc, log_ctx);
247 dcn10_log_hubp_states(dc, log_ctx);
249 DTN_INFO("DPP: IGAM format IGAM mode DGAM mode RGAM mode"
250 " GAMUT mode C11 C12 C13 C14 C21 C22 C23 C24 "
251 "C31 C32 C33 C34\n");
252 for (i = 0; i < pool->pipe_count; i++) {
253 struct dpp *dpp = pool->dpps[i];
254 struct dcn_dpp_state s = {0};
256 dpp->funcs->dpp_read_state(dpp, &s);
261 DTN_INFO("[%2d]: %11xh %-11s %-11s %-11s"
262 "%8x %08xh %08xh %08xh %08xh %08xh %08xh",
265 (s.igam_lut_mode == 0) ? "BypassFixed" :
266 ((s.igam_lut_mode == 1) ? "BypassFloat" :
267 ((s.igam_lut_mode == 2) ? "RAM" :
268 ((s.igam_lut_mode == 3) ? "RAM" :
270 (s.dgam_lut_mode == 0) ? "Bypass" :
271 ((s.dgam_lut_mode == 1) ? "sRGB" :
272 ((s.dgam_lut_mode == 2) ? "Ycc" :
273 ((s.dgam_lut_mode == 3) ? "RAM" :
274 ((s.dgam_lut_mode == 4) ? "RAM" :
276 (s.rgam_lut_mode == 0) ? "Bypass" :
277 ((s.rgam_lut_mode == 1) ? "sRGB" :
278 ((s.rgam_lut_mode == 2) ? "Ycc" :
279 ((s.rgam_lut_mode == 3) ? "RAM" :
280 ((s.rgam_lut_mode == 4) ? "RAM" :
283 s.gamut_remap_c11_c12,
284 s.gamut_remap_c13_c14,
285 s.gamut_remap_c21_c22,
286 s.gamut_remap_c23_c24,
287 s.gamut_remap_c31_c32,
288 s.gamut_remap_c33_c34);
293 DTN_INFO("MPCC: OPP DPP MPCCBOT MODE ALPHA_MODE PREMULT OVERLAP_ONLY IDLE\n");
294 for (i = 0; i < pool->pipe_count; i++) {
295 struct mpcc_state s = {0};
297 pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s);
299 DTN_INFO("[%2d]: %2xh %2xh %6xh %4d %10d %7d %12d %4d\n",
300 i, s.opp_id, s.dpp_id, s.bot_mpcc_id,
301 s.mode, s.alpha_mode, s.pre_multiplied_alpha, s.overlap_only,
306 DTN_INFO("OTG: v_bs v_be v_ss v_se vpol vmax vmin vmax_sel vmin_sel"
307 " h_bs h_be h_ss h_se hpol htot vtot underflow\n");
309 for (i = 0; i < pool->timing_generator_count; i++) {
310 struct timing_generator *tg = pool->timing_generators[i];
311 struct dcn_otg_state s = {0};
313 optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s);
315 //only print if OTG master is enabled
316 if ((s.otg_enabled & 1) == 0)
319 DTN_INFO("[%d]: %5d %5d %5d %5d %5d %5d %5d %9d %9d %5d %5d %5d"
320 " %5d %5d %5d %5d %9d\n",
338 s.underflow_occurred_status);
340 // Clear underflow for debug purposes
341 // We want to keep underflow sticky bit on for the longevity tests outside of test environment.
342 // This function is called only from Windows or Diags test environment, hence it's safe to clear
343 // it from here without affecting the original intent.
344 tg->funcs->clear_optc_underflow(tg);
348 DTN_INFO("\nCALCULATED Clocks: dcfclk_khz:%d dcfclk_deep_sleep_khz:%d dispclk_khz:%d\n"
349 "dppclk_khz:%d max_supported_dppclk_khz:%d fclk_khz:%d socclk_khz:%d\n\n",
350 dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_khz,
351 dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz,
352 dc->current_state->bw_ctx.bw.dcn.clk.dispclk_khz,
353 dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz,
354 dc->current_state->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz,
355 dc->current_state->bw_ctx.bw.dcn.clk.fclk_khz,
356 dc->current_state->bw_ctx.bw.dcn.clk.socclk_khz);
358 log_mpc_crc(dc, log_ctx);
363 static void enable_power_gating_plane(
364 struct dce_hwseq *hws,
367 bool force_on = 1; /* disable power gating */
373 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on);
374 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on);
375 REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on);
376 REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on);
379 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on);
380 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on);
381 REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on);
382 REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);
385 static void disable_vga(
386 struct dce_hwseq *hws)
388 unsigned int in_vga1_mode = 0;
389 unsigned int in_vga2_mode = 0;
390 unsigned int in_vga3_mode = 0;
391 unsigned int in_vga4_mode = 0;
393 REG_GET(D1VGA_CONTROL, D1VGA_MODE_ENABLE, &in_vga1_mode);
394 REG_GET(D2VGA_CONTROL, D2VGA_MODE_ENABLE, &in_vga2_mode);
395 REG_GET(D3VGA_CONTROL, D3VGA_MODE_ENABLE, &in_vga3_mode);
396 REG_GET(D4VGA_CONTROL, D4VGA_MODE_ENABLE, &in_vga4_mode);
398 if (in_vga1_mode == 0 && in_vga2_mode == 0 &&
399 in_vga3_mode == 0 && in_vga4_mode == 0)
402 REG_WRITE(D1VGA_CONTROL, 0);
403 REG_WRITE(D2VGA_CONTROL, 0);
404 REG_WRITE(D3VGA_CONTROL, 0);
405 REG_WRITE(D4VGA_CONTROL, 0);
407 /* HW Engineer's Notes:
408 * During switch from vga->extended, if we set the VGA_TEST_ENABLE and
409 * then hit the VGA_TEST_RENDER_START, then the DCHUBP timing gets updated correctly.
411 * Then vBIOS will have it poll for the VGA_TEST_RENDER_DONE and unset
412 * VGA_TEST_ENABLE, to leave it in the same state as before.
414 REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_ENABLE, 1);
415 REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_RENDER_START, 1);
418 static void dpp_pg_control(
419 struct dce_hwseq *hws,
420 unsigned int dpp_inst,
423 uint32_t power_gate = power_on ? 0 : 1;
424 uint32_t pwr_status = power_on ? 0 : 2;
426 if (hws->ctx->dc->debug.disable_dpp_power_gate)
428 if (REG(DOMAIN1_PG_CONFIG) == 0)
433 REG_UPDATE(DOMAIN1_PG_CONFIG,
434 DOMAIN1_POWER_GATE, power_gate);
436 REG_WAIT(DOMAIN1_PG_STATUS,
437 DOMAIN1_PGFSM_PWR_STATUS, pwr_status,
441 REG_UPDATE(DOMAIN3_PG_CONFIG,
442 DOMAIN3_POWER_GATE, power_gate);
444 REG_WAIT(DOMAIN3_PG_STATUS,
445 DOMAIN3_PGFSM_PWR_STATUS, pwr_status,
449 REG_UPDATE(DOMAIN5_PG_CONFIG,
450 DOMAIN5_POWER_GATE, power_gate);
452 REG_WAIT(DOMAIN5_PG_STATUS,
453 DOMAIN5_PGFSM_PWR_STATUS, pwr_status,
457 REG_UPDATE(DOMAIN7_PG_CONFIG,
458 DOMAIN7_POWER_GATE, power_gate);
460 REG_WAIT(DOMAIN7_PG_STATUS,
461 DOMAIN7_PGFSM_PWR_STATUS, pwr_status,
470 static void hubp_pg_control(
471 struct dce_hwseq *hws,
472 unsigned int hubp_inst,
475 uint32_t power_gate = power_on ? 0 : 1;
476 uint32_t pwr_status = power_on ? 0 : 2;
478 if (hws->ctx->dc->debug.disable_hubp_power_gate)
480 if (REG(DOMAIN0_PG_CONFIG) == 0)
484 case 0: /* DCHUBP0 */
485 REG_UPDATE(DOMAIN0_PG_CONFIG,
486 DOMAIN0_POWER_GATE, power_gate);
488 REG_WAIT(DOMAIN0_PG_STATUS,
489 DOMAIN0_PGFSM_PWR_STATUS, pwr_status,
492 case 1: /* DCHUBP1 */
493 REG_UPDATE(DOMAIN2_PG_CONFIG,
494 DOMAIN2_POWER_GATE, power_gate);
496 REG_WAIT(DOMAIN2_PG_STATUS,
497 DOMAIN2_PGFSM_PWR_STATUS, pwr_status,
500 case 2: /* DCHUBP2 */
501 REG_UPDATE(DOMAIN4_PG_CONFIG,
502 DOMAIN4_POWER_GATE, power_gate);
504 REG_WAIT(DOMAIN4_PG_STATUS,
505 DOMAIN4_PGFSM_PWR_STATUS, pwr_status,
508 case 3: /* DCHUBP3 */
509 REG_UPDATE(DOMAIN6_PG_CONFIG,
510 DOMAIN6_POWER_GATE, power_gate);
512 REG_WAIT(DOMAIN6_PG_STATUS,
513 DOMAIN6_PGFSM_PWR_STATUS, pwr_status,
522 static void power_on_plane(
523 struct dce_hwseq *hws,
526 DC_LOGGER_INIT(hws->ctx->logger);
527 if (REG(DC_IP_REQUEST_CNTL)) {
528 REG_SET(DC_IP_REQUEST_CNTL, 0,
530 dpp_pg_control(hws, plane_id, true);
531 hubp_pg_control(hws, plane_id, true);
532 REG_SET(DC_IP_REQUEST_CNTL, 0,
535 "Un-gated front end for pipe %d\n", plane_id);
539 static void undo_DEGVIDCN10_253_wa(struct dc *dc)
541 struct dce_hwseq *hws = dc->hwseq;
542 struct hubp *hubp = dc->res_pool->hubps[0];
544 if (!hws->wa_state.DEGVIDCN10_253_applied)
547 hubp->funcs->set_blank(hubp, true);
549 REG_SET(DC_IP_REQUEST_CNTL, 0,
552 hubp_pg_control(hws, 0, false);
553 REG_SET(DC_IP_REQUEST_CNTL, 0,
556 hws->wa_state.DEGVIDCN10_253_applied = false;
559 static void apply_DEGVIDCN10_253_wa(struct dc *dc)
561 struct dce_hwseq *hws = dc->hwseq;
562 struct hubp *hubp = dc->res_pool->hubps[0];
565 if (dc->debug.disable_stutter)
568 if (!hws->wa.DEGVIDCN10_253)
571 for (i = 0; i < dc->res_pool->pipe_count; i++) {
572 if (!dc->res_pool->hubps[i]->power_gated)
576 /* all pipe power gated, apply work around to enable stutter. */
578 REG_SET(DC_IP_REQUEST_CNTL, 0,
581 hubp_pg_control(hws, 0, true);
582 REG_SET(DC_IP_REQUEST_CNTL, 0,
585 hubp->funcs->set_hubp_blank_en(hubp, false);
586 hws->wa_state.DEGVIDCN10_253_applied = true;
589 static void bios_golden_init(struct dc *dc)
591 struct dc_bios *bp = dc->ctx->dc_bios;
594 /* initialize dcn global */
595 bp->funcs->enable_disp_power_gating(bp,
596 CONTROLLER_ID_D0, ASIC_PIPE_INIT);
598 for (i = 0; i < dc->res_pool->pipe_count; i++) {
599 /* initialize dcn per pipe */
600 bp->funcs->enable_disp_power_gating(bp,
601 CONTROLLER_ID_D0 + i, ASIC_PIPE_DISABLE);
605 static void false_optc_underflow_wa(
607 const struct dc_stream_state *stream,
608 struct timing_generator *tg)
613 if (!dc->hwseq->wa.false_optc_underflow)
616 underflow = tg->funcs->is_optc_underflow_occurred(tg);
618 for (i = 0; i < dc->res_pool->pipe_count; i++) {
619 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
621 if (old_pipe_ctx->stream != stream)
624 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, old_pipe_ctx);
627 tg->funcs->set_blank_data_double_buffer(tg, true);
629 if (tg->funcs->is_optc_underflow_occurred(tg) && !underflow)
630 tg->funcs->clear_optc_underflow(tg);
633 static enum dc_status dcn10_enable_stream_timing(
634 struct pipe_ctx *pipe_ctx,
635 struct dc_state *context,
638 struct dc_stream_state *stream = pipe_ctx->stream;
639 enum dc_color_space color_space;
640 struct tg_color black_color = {0};
642 /* by upper caller loop, pipe0 is parent pipe and be called first.
643 * back end is set up by for pipe0. Other children pipe share back end
644 * with pipe 0. No program is needed.
646 if (pipe_ctx->top_pipe != NULL)
649 /* TODO check if timing_changed, disable stream if timing changed */
651 /* HW program guide assume display already disable
652 * by unplug sequence. OTG assume stop.
654 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true);
656 if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
657 pipe_ctx->clock_source,
658 &pipe_ctx->stream_res.pix_clk_params,
659 &pipe_ctx->pll_settings)) {
661 return DC_ERROR_UNEXPECTED;
664 pipe_ctx->stream_res.tg->funcs->program_timing(
665 pipe_ctx->stream_res.tg,
667 pipe_ctx->pipe_dlg_param.vready_offset,
668 pipe_ctx->pipe_dlg_param.vstartup_start,
669 pipe_ctx->pipe_dlg_param.vupdate_offset,
670 pipe_ctx->pipe_dlg_param.vupdate_width,
671 pipe_ctx->stream->signal,
674 #if 0 /* move to after enable_crtc */
675 /* TODO: OPP FMT, ABM. etc. should be done here. */
676 /* or FPGA now. instance 0 only. TODO: move to opp.c */
678 inst_offset = reg_offsets[pipe_ctx->stream_res.tg->inst].fmt;
680 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
681 pipe_ctx->stream_res.opp,
682 &stream->bit_depth_params,
685 /* program otg blank color */
686 color_space = stream->output_color_space;
687 color_space_to_black_color(dc, color_space, &black_color);
689 if (pipe_ctx->stream_res.tg->funcs->set_blank_color)
690 pipe_ctx->stream_res.tg->funcs->set_blank_color(
691 pipe_ctx->stream_res.tg,
694 if (pipe_ctx->stream_res.tg->funcs->is_blanked &&
695 !pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg)) {
696 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);
697 hwss_wait_for_blank_complete(pipe_ctx->stream_res.tg);
698 false_optc_underflow_wa(dc, pipe_ctx->stream, pipe_ctx->stream_res.tg);
701 /* VTG is within DCHUB command block. DCFCLK is always on */
702 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {
704 return DC_ERROR_UNEXPECTED;
707 /* TODO program crtc source select for non-virtual signal*/
708 /* TODO program FMT */
709 /* TODO setup link_enc */
710 /* TODO set stream attributes */
711 /* TODO program audio */
712 /* TODO enable stream if timing changed */
713 /* TODO unblank stream if DP */
718 static void dcn10_reset_back_end_for_pipe(
720 struct pipe_ctx *pipe_ctx,
721 struct dc_state *context)
724 DC_LOGGER_INIT(dc->ctx->logger);
725 if (pipe_ctx->stream_res.stream_enc == NULL) {
726 pipe_ctx->stream = NULL;
730 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
731 /* DPMS may already disable */
732 if (!pipe_ctx->stream->dpms_off)
733 core_link_disable_stream(pipe_ctx, FREE_ACQUIRED_RESOURCE);
734 else if (pipe_ctx->stream_res.audio) {
735 dc->hwss.disable_audio_stream(pipe_ctx, FREE_ACQUIRED_RESOURCE);
740 /* by upper caller loop, parent pipe: pipe0, will be reset last.
741 * back end share by all pipes and will be disable only when disable
744 if (pipe_ctx->top_pipe == NULL) {
745 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
747 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
750 for (i = 0; i < dc->res_pool->pipe_count; i++)
751 if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx)
754 if (i == dc->res_pool->pipe_count)
757 pipe_ctx->stream = NULL;
758 DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n",
759 pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
762 static bool dcn10_hw_wa_force_recovery(struct dc *dc)
766 bool need_recover = true;
768 if (!dc->debug.recovery_enabled)
771 for (i = 0; i < dc->res_pool->pipe_count; i++) {
772 struct pipe_ctx *pipe_ctx =
773 &dc->current_state->res_ctx.pipe_ctx[i];
774 if (pipe_ctx != NULL) {
775 hubp = pipe_ctx->plane_res.hubp;
776 if (hubp != NULL && hubp->funcs->hubp_get_underflow_status) {
777 if (hubp->funcs->hubp_get_underflow_status(hubp) != 0) {
778 /* one pipe underflow, we will reset all the pipes*/
787 DCHUBP_CNTL:HUBP_BLANK_EN=1
788 DCHUBBUB_SOFT_RESET:DCHUBBUB_GLOBAL_SOFT_RESET=1
789 DCHUBP_CNTL:HUBP_DISABLE=1
790 DCHUBP_CNTL:HUBP_DISABLE=0
791 DCHUBBUB_SOFT_RESET:DCHUBBUB_GLOBAL_SOFT_RESET=0
792 DCSURF_PRIMARY_SURFACE_ADDRESS
793 DCHUBP_CNTL:HUBP_BLANK_EN=0
796 for (i = 0; i < dc->res_pool->pipe_count; i++) {
797 struct pipe_ctx *pipe_ctx =
798 &dc->current_state->res_ctx.pipe_ctx[i];
799 if (pipe_ctx != NULL) {
800 hubp = pipe_ctx->plane_res.hubp;
801 /*DCHUBP_CNTL:HUBP_BLANK_EN=1*/
802 if (hubp != NULL && hubp->funcs->set_hubp_blank_en)
803 hubp->funcs->set_hubp_blank_en(hubp, true);
806 /*DCHUBBUB_SOFT_RESET:DCHUBBUB_GLOBAL_SOFT_RESET=1*/
807 hubbub1_soft_reset(dc->res_pool->hubbub, true);
809 for (i = 0; i < dc->res_pool->pipe_count; i++) {
810 struct pipe_ctx *pipe_ctx =
811 &dc->current_state->res_ctx.pipe_ctx[i];
812 if (pipe_ctx != NULL) {
813 hubp = pipe_ctx->plane_res.hubp;
814 /*DCHUBP_CNTL:HUBP_DISABLE=1*/
815 if (hubp != NULL && hubp->funcs->hubp_disable_control)
816 hubp->funcs->hubp_disable_control(hubp, true);
819 for (i = 0; i < dc->res_pool->pipe_count; i++) {
820 struct pipe_ctx *pipe_ctx =
821 &dc->current_state->res_ctx.pipe_ctx[i];
822 if (pipe_ctx != NULL) {
823 hubp = pipe_ctx->plane_res.hubp;
824 /*DCHUBP_CNTL:HUBP_DISABLE=0*/
825 if (hubp != NULL && hubp->funcs->hubp_disable_control)
826 hubp->funcs->hubp_disable_control(hubp, true);
829 /*DCHUBBUB_SOFT_RESET:DCHUBBUB_GLOBAL_SOFT_RESET=0*/
830 hubbub1_soft_reset(dc->res_pool->hubbub, false);
831 for (i = 0; i < dc->res_pool->pipe_count; i++) {
832 struct pipe_ctx *pipe_ctx =
833 &dc->current_state->res_ctx.pipe_ctx[i];
834 if (pipe_ctx != NULL) {
835 hubp = pipe_ctx->plane_res.hubp;
836 /*DCHUBP_CNTL:HUBP_BLANK_EN=0*/
837 if (hubp != NULL && hubp->funcs->set_hubp_blank_en)
838 hubp->funcs->set_hubp_blank_en(hubp, true);
846 void dcn10_verify_allow_pstate_change_high(struct dc *dc)
848 static bool should_log_hw_state; /* prevent hw state log by default */
850 if (!hubbub1_verify_allow_pstate_change_high(dc->res_pool->hubbub)) {
851 if (should_log_hw_state) {
852 dcn10_log_hw_state(dc, NULL);
855 if (dcn10_hw_wa_force_recovery(dc)) {
857 if (!hubbub1_verify_allow_pstate_change_high(dc->res_pool->hubbub))
863 /* trigger HW to start disconnect plane from stream on the next vsync */
864 void hwss1_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx)
866 struct hubp *hubp = pipe_ctx->plane_res.hubp;
867 int dpp_id = pipe_ctx->plane_res.dpp->inst;
868 struct mpc *mpc = dc->res_pool->mpc;
869 struct mpc_tree *mpc_tree_params;
870 struct mpcc *mpcc_to_remove = NULL;
871 struct output_pixel_processor *opp = pipe_ctx->stream_res.opp;
873 mpc_tree_params = &(opp->mpc_tree_params);
874 mpcc_to_remove = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, dpp_id);
877 if (mpcc_to_remove == NULL)
880 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, mpcc_to_remove);
882 opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
884 dc->optimized_required = true;
886 if (hubp->funcs->hubp_disconnect)
887 hubp->funcs->hubp_disconnect(hubp);
889 if (dc->debug.sanity_checks)
890 dcn10_verify_allow_pstate_change_high(dc);
893 static void plane_atomic_power_down(struct dc *dc,
897 struct dce_hwseq *hws = dc->hwseq;
898 DC_LOGGER_INIT(dc->ctx->logger);
900 if (REG(DC_IP_REQUEST_CNTL)) {
901 REG_SET(DC_IP_REQUEST_CNTL, 0,
903 dpp_pg_control(hws, dpp->inst, false);
904 hubp_pg_control(hws, hubp->inst, false);
905 dpp->funcs->dpp_reset(dpp);
906 REG_SET(DC_IP_REQUEST_CNTL, 0,
909 "Power gated front end %d\n", hubp->inst);
913 /* disable HW used by plane.
914 * note: cannot disable until disconnect is complete
916 static void plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
918 struct hubp *hubp = pipe_ctx->plane_res.hubp;
919 struct dpp *dpp = pipe_ctx->plane_res.dpp;
920 int opp_id = hubp->opp_id;
922 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);
924 hubp->funcs->hubp_clk_cntl(hubp, false);
926 dpp->funcs->dpp_dppclk_control(dpp, false, false);
928 if (opp_id != 0xf && pipe_ctx->stream_res.opp->mpc_tree_params.opp_list == NULL)
929 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
930 pipe_ctx->stream_res.opp,
933 hubp->power_gated = true;
934 dc->optimized_required = false; /* We're powering off, no need to optimize */
936 plane_atomic_power_down(dc,
937 pipe_ctx->plane_res.dpp,
938 pipe_ctx->plane_res.hubp);
940 pipe_ctx->stream = NULL;
941 memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res));
942 memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res));
943 pipe_ctx->top_pipe = NULL;
944 pipe_ctx->bottom_pipe = NULL;
945 pipe_ctx->plane_state = NULL;
948 static void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
950 DC_LOGGER_INIT(dc->ctx->logger);
952 if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)
955 plane_atomic_disable(dc, pipe_ctx);
957 apply_DEGVIDCN10_253_wa(dc);
959 DC_LOG_DC("Power down front end %d\n",
963 static void dcn10_init_pipes(struct dc *dc, struct dc_state *context)
966 bool can_apply_seamless_boot = false;
968 for (i = 0; i < context->stream_count; i++) {
969 if (context->streams[i]->apply_seamless_boot_optimization) {
970 can_apply_seamless_boot = true;
975 for (i = 0; i < dc->res_pool->pipe_count; i++) {
976 struct timing_generator *tg = dc->res_pool->timing_generators[i];
977 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
979 /* There is assumption that pipe_ctx is not mapping irregularly
980 * to non-preferred front end. If pipe_ctx->stream is not NULL,
981 * we will use the pipe, so don't disable
983 if (pipe_ctx->stream != NULL && can_apply_seamless_boot)
986 /* Blank controller using driver code instead of
989 if (tg->funcs->is_tg_enabled(tg)) {
991 tg->funcs->set_blank(tg, true);
992 hwss_wait_for_blank_complete(tg);
996 /* Cannot reset the MPC mux if seamless boot */
997 if (!can_apply_seamless_boot)
998 dc->res_pool->mpc->funcs->mpc_init(dc->res_pool->mpc);
1000 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1001 struct timing_generator *tg = dc->res_pool->timing_generators[i];
1002 struct hubp *hubp = dc->res_pool->hubps[i];
1003 struct dpp *dpp = dc->res_pool->dpps[i];
1004 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1006 /* There is assumption that pipe_ctx is not mapping irregularly
1007 * to non-preferred front end. If pipe_ctx->stream is not NULL,
1008 * we will use the pipe, so don't disable
1010 if (can_apply_seamless_boot &&
1011 pipe_ctx->stream != NULL &&
1012 pipe_ctx->stream_res.tg->funcs->is_tg_enabled(
1013 pipe_ctx->stream_res.tg))
1016 /* Disable on the current state so the new one isn't cleared. */
1017 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
1019 dpp->funcs->dpp_reset(dpp);
1021 pipe_ctx->stream_res.tg = tg;
1022 pipe_ctx->pipe_idx = i;
1024 pipe_ctx->plane_res.hubp = hubp;
1025 pipe_ctx->plane_res.dpp = dpp;
1026 pipe_ctx->plane_res.mpcc_inst = dpp->inst;
1027 hubp->mpcc_id = dpp->inst;
1029 hubp->power_gated = false;
1031 dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
1032 dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
1033 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
1034 pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
1036 hwss1_plane_atomic_disconnect(dc, pipe_ctx);
1038 if (tg->funcs->is_tg_enabled(tg))
1039 tg->funcs->unlock(tg);
1041 dcn10_disable_plane(dc, pipe_ctx);
1043 pipe_ctx->stream_res.tg = NULL;
1044 pipe_ctx->plane_res.hubp = NULL;
1046 tg->funcs->tg_init(tg);
1050 static void dcn10_init_hw(struct dc *dc)
1053 struct abm *abm = dc->res_pool->abm;
1054 struct dmcu *dmcu = dc->res_pool->dmcu;
1055 struct dce_hwseq *hws = dc->hwseq;
1056 struct dc_bios *dcb = dc->ctx->dc_bios;
1058 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
1059 REG_WRITE(REFCLK_CNTL, 0);
1060 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
1061 REG_WRITE(DIO_MEM_PWR_CTRL, 0);
1063 if (!dc->debug.disable_clock_gate) {
1064 /* enable all DCN clock gating */
1065 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
1067 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
1069 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
1072 enable_power_gating_plane(dc->hwseq, true);
1074 /* end of FPGA. Below if real ASIC */
1078 if (!dcb->funcs->is_accelerated_mode(dcb)) {
1079 bool allow_self_fresh_force_enable =
1080 hububu1_is_allow_self_refresh_enabled(
1081 dc->res_pool->hubbub);
1083 bios_golden_init(dc);
1085 /* WA for making DF sleep when idle after resume from S0i3.
1086 * DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE is set to 1 by
1087 * command table, if DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE = 0
1088 * before calling command table and it changed to 1 after,
1089 * it should be set back to 0.
1091 if (allow_self_fresh_force_enable == false &&
1092 hububu1_is_allow_self_refresh_enabled(dc->res_pool->hubbub))
1093 hubbub1_allow_self_refresh_control(dc->res_pool->hubbub, true);
1095 disable_vga(dc->hwseq);
1098 for (i = 0; i < dc->link_count; i++) {
1099 /* Power up AND update implementation according to the
1100 * required signal (which may be different from the
1101 * default signal on connector).
1103 struct dc_link *link = dc->links[i];
1105 if (link->link_enc->connector.id == CONNECTOR_ID_EDP)
1106 dc->hwss.edp_power_control(link, true);
1108 link->link_enc->funcs->hw_init(link->link_enc);
1110 /* Check for enabled DIG to identify enabled display */
1111 if (link->link_enc->funcs->is_dig_enabled &&
1112 link->link_enc->funcs->is_dig_enabled(link->link_enc))
1113 link->link_status.link_active = true;
1116 /* If taking control over from VBIOS, we may want to optimize our first
1117 * mode set, so we need to skip powering down pipes until we know which
1118 * pipes we want to use.
1119 * Otherwise, if taking control is not possible, we need to power
1122 if (dcb->funcs->is_accelerated_mode(dcb) || dc->config.power_down_display_on_boot) {
1123 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1124 struct hubp *hubp = dc->res_pool->hubps[i];
1125 struct dpp *dpp = dc->res_pool->dpps[i];
1127 hubp->funcs->hubp_init(hubp);
1128 dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
1129 plane_atomic_power_down(dc, dpp, hubp);
1132 apply_DEGVIDCN10_253_wa(dc);
1135 for (i = 0; i < dc->res_pool->audio_count; i++) {
1136 struct audio *audio = dc->res_pool->audios[i];
1138 audio->funcs->hw_init(audio);
1142 abm->funcs->init_backlight(abm);
1143 abm->funcs->abm_init(abm);
1147 dmcu->funcs->dmcu_init(dmcu);
1149 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/
1150 REG_WRITE(DIO_MEM_PWR_CTRL, 0);
1152 if (!dc->debug.disable_clock_gate) {
1153 /* enable all DCN clock gating */
1154 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
1156 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
1158 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
1161 enable_power_gating_plane(dc->hwseq, true);
1163 memset(&dc->clk_mgr->clks, 0, sizeof(dc->clk_mgr->clks));
1166 static void dcn10_reset_hw_ctx_wrap(
1168 struct dc_state *context)
1173 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
1174 struct pipe_ctx *pipe_ctx_old =
1175 &dc->current_state->res_ctx.pipe_ctx[i];
1176 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1178 if (!pipe_ctx_old->stream)
1181 if (pipe_ctx_old->top_pipe)
1184 if (!pipe_ctx->stream ||
1185 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
1186 struct clock_source *old_clk = pipe_ctx_old->clock_source;
1188 dcn10_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
1189 if (dc->hwss.enable_stream_gating)
1190 dc->hwss.enable_stream_gating(dc, pipe_ctx);
1192 old_clk->funcs->cs_power_down(old_clk);
1197 static bool patch_address_for_sbs_tb_stereo(
1198 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr)
1200 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1201 bool sec_split = pipe_ctx->top_pipe &&
1202 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
1203 if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
1204 (pipe_ctx->stream->timing.timing_3d_format ==
1205 TIMING_3D_FORMAT_SIDE_BY_SIDE ||
1206 pipe_ctx->stream->timing.timing_3d_format ==
1207 TIMING_3D_FORMAT_TOP_AND_BOTTOM)) {
1208 *addr = plane_state->address.grph_stereo.left_addr;
1209 plane_state->address.grph_stereo.left_addr =
1210 plane_state->address.grph_stereo.right_addr;
1213 if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE &&
1214 plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) {
1215 plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO;
1216 plane_state->address.grph_stereo.right_addr =
1217 plane_state->address.grph_stereo.left_addr;
1225 static void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)
1227 bool addr_patched = false;
1228 PHYSICAL_ADDRESS_LOC addr;
1229 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1231 if (plane_state == NULL)
1234 addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);
1236 pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(
1237 pipe_ctx->plane_res.hubp,
1238 &plane_state->address,
1239 plane_state->flip_immediate,
1242 plane_state->status.requested_address = plane_state->address;
1244 if (plane_state->flip_immediate)
1245 plane_state->status.current_address = plane_state->address;
1248 pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;
1251 static bool dcn10_set_input_transfer_func(struct pipe_ctx *pipe_ctx,
1252 const struct dc_plane_state *plane_state)
1254 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
1255 const struct dc_transfer_func *tf = NULL;
1258 if (dpp_base == NULL)
1261 if (plane_state->in_transfer_func)
1262 tf = plane_state->in_transfer_func;
1264 if (plane_state->gamma_correction &&
1265 !dpp_base->ctx->dc->debug.always_use_regamma
1266 && !plane_state->gamma_correction->is_identity
1267 && dce_use_lut(plane_state->format))
1268 dpp_base->funcs->dpp_program_input_lut(dpp_base, plane_state->gamma_correction);
1271 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
1272 else if (tf->type == TF_TYPE_PREDEFINED) {
1274 case TRANSFER_FUNCTION_SRGB:
1275 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_sRGB);
1277 case TRANSFER_FUNCTION_BT709:
1278 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_xvYCC);
1280 case TRANSFER_FUNCTION_LINEAR:
1281 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
1283 case TRANSFER_FUNCTION_PQ:
1288 } else if (tf->type == TF_TYPE_BYPASS) {
1289 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
1291 cm_helper_translate_curve_to_degamma_hw_format(tf,
1292 &dpp_base->degamma_params);
1293 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base,
1294 &dpp_base->degamma_params);
1306 dcn10_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
1307 const struct dc_stream_state *stream)
1309 struct dpp *dpp = pipe_ctx->plane_res.dpp;
1314 dpp->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
1316 if (stream->out_transfer_func &&
1317 stream->out_transfer_func->type == TF_TYPE_PREDEFINED &&
1318 stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB)
1319 dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_SRGB);
1321 /* dcn10_translate_regamma_to_hw_format takes 750us, only do it when full
1324 else if (cm_helper_translate_curve_to_hw_format(
1325 stream->out_transfer_func,
1326 &dpp->regamma_params, false)) {
1327 dpp->funcs->dpp_program_regamma_pwl(
1329 &dpp->regamma_params, OPP_REGAMMA_USER);
1331 dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_BYPASS);
1336 static void dcn10_pipe_control_lock(
1338 struct pipe_ctx *pipe,
1341 /* use TG master update lock to lock everything on the TG
1342 * therefore only top pipe need to lock
1347 if (dc->debug.sanity_checks)
1348 dcn10_verify_allow_pstate_change_high(dc);
1351 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);
1353 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);
1355 if (dc->debug.sanity_checks)
1356 dcn10_verify_allow_pstate_change_high(dc);
1359 static bool wait_for_reset_trigger_to_occur(
1360 struct dc_context *dc_ctx,
1361 struct timing_generator *tg)
1365 /* To avoid endless loop we wait at most
1366 * frames_to_wait_on_triggered_reset frames for the reset to occur. */
1367 const uint32_t frames_to_wait_on_triggered_reset = 10;
1370 for (i = 0; i < frames_to_wait_on_triggered_reset; i++) {
1372 if (!tg->funcs->is_counter_moving(tg)) {
1373 DC_ERROR("TG counter is not moving!\n");
1377 if (tg->funcs->did_triggered_reset_occur(tg)) {
1379 /* usually occurs at i=1 */
1380 DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",
1385 /* Wait for one frame. */
1386 tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);
1387 tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
1391 DC_ERROR("GSL: Timeout on reset trigger!\n");
1396 static void dcn10_enable_timing_synchronization(
1400 struct pipe_ctx *grouped_pipes[])
1402 struct dc_context *dc_ctx = dc->ctx;
1405 DC_SYNC_INFO("Setting up OTG reset trigger\n");
1407 for (i = 1; i < group_size; i++)
1408 grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger(
1409 grouped_pipes[i]->stream_res.tg,
1410 grouped_pipes[0]->stream_res.tg->inst);
1412 DC_SYNC_INFO("Waiting for trigger\n");
1414 /* Need to get only check 1 pipe for having reset as all the others are
1415 * synchronized. Look at last pipe programmed to reset.
1418 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[1]->stream_res.tg);
1419 for (i = 1; i < group_size; i++)
1420 grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(
1421 grouped_pipes[i]->stream_res.tg);
1423 DC_SYNC_INFO("Sync complete\n");
1426 static void dcn10_enable_per_frame_crtc_position_reset(
1429 struct pipe_ctx *grouped_pipes[])
1431 struct dc_context *dc_ctx = dc->ctx;
1434 DC_SYNC_INFO("Setting up\n");
1435 for (i = 0; i < group_size; i++)
1436 if (grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset)
1437 grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset(
1438 grouped_pipes[i]->stream_res.tg,
1440 &grouped_pipes[i]->stream->triggered_crtc_reset);
1442 DC_SYNC_INFO("Waiting for trigger\n");
1444 for (i = 0; i < group_size; i++)
1445 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
1447 DC_SYNC_INFO("Multi-display sync is complete\n");
1450 /*static void print_rq_dlg_ttu(
1452 struct pipe_ctx *pipe_ctx)
1454 DC_LOG_BANDWIDTH_CALCS(core_dc->ctx->logger,
1455 "\n============== DML TTU Output parameters [%d] ==============\n"
1456 "qos_level_low_wm: %d, \n"
1457 "qos_level_high_wm: %d, \n"
1458 "min_ttu_vblank: %d, \n"
1459 "qos_level_flip: %d, \n"
1460 "refcyc_per_req_delivery_l: %d, \n"
1461 "qos_level_fixed_l: %d, \n"
1462 "qos_ramp_disable_l: %d, \n"
1463 "refcyc_per_req_delivery_pre_l: %d, \n"
1464 "refcyc_per_req_delivery_c: %d, \n"
1465 "qos_level_fixed_c: %d, \n"
1466 "qos_ramp_disable_c: %d, \n"
1467 "refcyc_per_req_delivery_pre_c: %d\n"
1468 "=============================================================\n",
1470 pipe_ctx->ttu_regs.qos_level_low_wm,
1471 pipe_ctx->ttu_regs.qos_level_high_wm,
1472 pipe_ctx->ttu_regs.min_ttu_vblank,
1473 pipe_ctx->ttu_regs.qos_level_flip,
1474 pipe_ctx->ttu_regs.refcyc_per_req_delivery_l,
1475 pipe_ctx->ttu_regs.qos_level_fixed_l,
1476 pipe_ctx->ttu_regs.qos_ramp_disable_l,
1477 pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_l,
1478 pipe_ctx->ttu_regs.refcyc_per_req_delivery_c,
1479 pipe_ctx->ttu_regs.qos_level_fixed_c,
1480 pipe_ctx->ttu_regs.qos_ramp_disable_c,
1481 pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_c
1484 DC_LOG_BANDWIDTH_CALCS(core_dc->ctx->logger,
1485 "\n============== DML DLG Output parameters [%d] ==============\n"
1486 "refcyc_h_blank_end: %d, \n"
1487 "dlg_vblank_end: %d, \n"
1488 "min_dst_y_next_start: %d, \n"
1489 "refcyc_per_htotal: %d, \n"
1490 "refcyc_x_after_scaler: %d, \n"
1491 "dst_y_after_scaler: %d, \n"
1492 "dst_y_prefetch: %d, \n"
1493 "dst_y_per_vm_vblank: %d, \n"
1494 "dst_y_per_row_vblank: %d, \n"
1495 "ref_freq_to_pix_freq: %d, \n"
1496 "vratio_prefetch: %d, \n"
1497 "refcyc_per_pte_group_vblank_l: %d, \n"
1498 "refcyc_per_meta_chunk_vblank_l: %d, \n"
1499 "dst_y_per_pte_row_nom_l: %d, \n"
1500 "refcyc_per_pte_group_nom_l: %d, \n",
1502 pipe_ctx->dlg_regs.refcyc_h_blank_end,
1503 pipe_ctx->dlg_regs.dlg_vblank_end,
1504 pipe_ctx->dlg_regs.min_dst_y_next_start,
1505 pipe_ctx->dlg_regs.refcyc_per_htotal,
1506 pipe_ctx->dlg_regs.refcyc_x_after_scaler,
1507 pipe_ctx->dlg_regs.dst_y_after_scaler,
1508 pipe_ctx->dlg_regs.dst_y_prefetch,
1509 pipe_ctx->dlg_regs.dst_y_per_vm_vblank,
1510 pipe_ctx->dlg_regs.dst_y_per_row_vblank,
1511 pipe_ctx->dlg_regs.ref_freq_to_pix_freq,
1512 pipe_ctx->dlg_regs.vratio_prefetch,
1513 pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_l,
1514 pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_l,
1515 pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_l,
1516 pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_l
1519 DC_LOG_BANDWIDTH_CALCS(core_dc->ctx->logger,
1520 "\ndst_y_per_meta_row_nom_l: %d, \n"
1521 "refcyc_per_meta_chunk_nom_l: %d, \n"
1522 "refcyc_per_line_delivery_pre_l: %d, \n"
1523 "refcyc_per_line_delivery_l: %d, \n"
1524 "vratio_prefetch_c: %d, \n"
1525 "refcyc_per_pte_group_vblank_c: %d, \n"
1526 "refcyc_per_meta_chunk_vblank_c: %d, \n"
1527 "dst_y_per_pte_row_nom_c: %d, \n"
1528 "refcyc_per_pte_group_nom_c: %d, \n"
1529 "dst_y_per_meta_row_nom_c: %d, \n"
1530 "refcyc_per_meta_chunk_nom_c: %d, \n"
1531 "refcyc_per_line_delivery_pre_c: %d, \n"
1532 "refcyc_per_line_delivery_c: %d \n"
1533 "========================================================\n",
1534 pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_l,
1535 pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_l,
1536 pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_l,
1537 pipe_ctx->dlg_regs.refcyc_per_line_delivery_l,
1538 pipe_ctx->dlg_regs.vratio_prefetch_c,
1539 pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_c,
1540 pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_c,
1541 pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_c,
1542 pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_c,
1543 pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_c,
1544 pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_c,
1545 pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_c,
1546 pipe_ctx->dlg_regs.refcyc_per_line_delivery_c
1549 DC_LOG_BANDWIDTH_CALCS(core_dc->ctx->logger,
1550 "\n============== DML RQ Output parameters [%d] ==============\n"
1552 "min_chunk_size: %d \n"
1553 "meta_chunk_size: %d \n"
1554 "min_meta_chunk_size: %d \n"
1555 "dpte_group_size: %d \n"
1556 "mpte_group_size: %d \n"
1557 "swath_height: %d \n"
1558 "pte_row_height_linear: %d \n"
1559 "========================================================\n",
1561 pipe_ctx->rq_regs.rq_regs_l.chunk_size,
1562 pipe_ctx->rq_regs.rq_regs_l.min_chunk_size,
1563 pipe_ctx->rq_regs.rq_regs_l.meta_chunk_size,
1564 pipe_ctx->rq_regs.rq_regs_l.min_meta_chunk_size,
1565 pipe_ctx->rq_regs.rq_regs_l.dpte_group_size,
1566 pipe_ctx->rq_regs.rq_regs_l.mpte_group_size,
1567 pipe_ctx->rq_regs.rq_regs_l.swath_height,
1568 pipe_ctx->rq_regs.rq_regs_l.pte_row_height_linear
1573 static void mmhub_read_vm_system_aperture_settings(struct dcn10_hubp *hubp1,
1574 struct vm_system_aperture_param *apt,
1575 struct dce_hwseq *hws)
1577 PHYSICAL_ADDRESS_LOC physical_page_number;
1578 uint32_t logical_addr_low;
1579 uint32_t logical_addr_high;
1581 REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
1582 PHYSICAL_PAGE_NUMBER_MSB, &physical_page_number.high_part);
1583 REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
1584 PHYSICAL_PAGE_NUMBER_LSB, &physical_page_number.low_part);
1586 REG_GET(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1587 LOGICAL_ADDR, &logical_addr_low);
1589 REG_GET(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1590 LOGICAL_ADDR, &logical_addr_high);
1592 apt->sys_default.quad_part = physical_page_number.quad_part << 12;
1593 apt->sys_low.quad_part = (int64_t)logical_addr_low << 18;
1594 apt->sys_high.quad_part = (int64_t)logical_addr_high << 18;
1597 /* Temporary read settings, future will get values from kmd directly */
1598 static void mmhub_read_vm_context0_settings(struct dcn10_hubp *hubp1,
1599 struct vm_context0_param *vm0,
1600 struct dce_hwseq *hws)
1602 PHYSICAL_ADDRESS_LOC fb_base;
1603 PHYSICAL_ADDRESS_LOC fb_offset;
1604 uint32_t fb_base_value;
1605 uint32_t fb_offset_value;
1607 REG_GET(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, &fb_base_value);
1608 REG_GET(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, &fb_offset_value);
1610 REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
1611 PAGE_DIRECTORY_ENTRY_HI32, &vm0->pte_base.high_part);
1612 REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
1613 PAGE_DIRECTORY_ENTRY_LO32, &vm0->pte_base.low_part);
1615 REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
1616 LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_start.high_part);
1617 REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
1618 LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_start.low_part);
1620 REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
1621 LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_end.high_part);
1622 REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
1623 LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_end.low_part);
1625 REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
1626 PHYSICAL_PAGE_ADDR_HI4, &vm0->fault_default.high_part);
1627 REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
1628 PHYSICAL_PAGE_ADDR_LO32, &vm0->fault_default.low_part);
1631 * The values in VM_CONTEXT0_PAGE_TABLE_BASE_ADDR is in UMA space.
1632 * Therefore we need to do
1633 * DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
1634 * - DCHUBBUB_SDPIF_FB_OFFSET + DCHUBBUB_SDPIF_FB_BASE
1636 fb_base.quad_part = (uint64_t)fb_base_value << 24;
1637 fb_offset.quad_part = (uint64_t)fb_offset_value << 24;
1638 vm0->pte_base.quad_part += fb_base.quad_part;
1639 vm0->pte_base.quad_part -= fb_offset.quad_part;
1643 void dcn10_program_pte_vm(struct dce_hwseq *hws, struct hubp *hubp)
1645 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
1646 struct vm_system_aperture_param apt = { {{ 0 } } };
1647 struct vm_context0_param vm0 = { { { 0 } } };
1649 mmhub_read_vm_system_aperture_settings(hubp1, &apt, hws);
1650 mmhub_read_vm_context0_settings(hubp1, &vm0, hws);
1652 hubp->funcs->hubp_set_vm_system_aperture_settings(hubp, &apt);
1653 hubp->funcs->hubp_set_vm_context0_settings(hubp, &vm0);
1656 static void dcn10_enable_plane(
1658 struct pipe_ctx *pipe_ctx,
1659 struct dc_state *context)
1661 struct dce_hwseq *hws = dc->hwseq;
1663 if (dc->debug.sanity_checks) {
1664 dcn10_verify_allow_pstate_change_high(dc);
1667 undo_DEGVIDCN10_253_wa(dc);
1669 power_on_plane(dc->hwseq,
1670 pipe_ctx->plane_res.hubp->inst);
1672 /* enable DCFCLK current DCHUB */
1673 pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);
1675 /* make sure OPP_PIPE_CLOCK_EN = 1 */
1676 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
1677 pipe_ctx->stream_res.opp,
1680 /* TODO: enable/disable in dm as per update type.
1682 DC_LOG_DC(dc->ctx->logger,
1683 "Pipe:%d 0x%x: addr hi:0x%x, "
1686 " %d; dst: %d, %d, %d, %d;\n",
1689 plane_state->address.grph.addr.high_part,
1690 plane_state->address.grph.addr.low_part,
1691 plane_state->src_rect.x,
1692 plane_state->src_rect.y,
1693 plane_state->src_rect.width,
1694 plane_state->src_rect.height,
1695 plane_state->dst_rect.x,
1696 plane_state->dst_rect.y,
1697 plane_state->dst_rect.width,
1698 plane_state->dst_rect.height);
1700 DC_LOG_DC(dc->ctx->logger,
1701 "Pipe %d: width, height, x, y format:%d\n"
1702 "viewport:%d, %d, %d, %d\n"
1703 "recout: %d, %d, %d, %d\n",
1705 plane_state->format,
1706 pipe_ctx->plane_res.scl_data.viewport.width,
1707 pipe_ctx->plane_res.scl_data.viewport.height,
1708 pipe_ctx->plane_res.scl_data.viewport.x,
1709 pipe_ctx->plane_res.scl_data.viewport.y,
1710 pipe_ctx->plane_res.scl_data.recout.width,
1711 pipe_ctx->plane_res.scl_data.recout.height,
1712 pipe_ctx->plane_res.scl_data.recout.x,
1713 pipe_ctx->plane_res.scl_data.recout.y);
1714 print_rq_dlg_ttu(dc, pipe_ctx);
1717 if (dc->config.gpu_vm_support)
1718 dcn10_program_pte_vm(hws, pipe_ctx->plane_res.hubp);
1720 if (dc->debug.sanity_checks) {
1721 dcn10_verify_allow_pstate_change_high(dc);
1725 static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
1728 struct dpp_grph_csc_adjustment adjust;
1729 memset(&adjust, 0, sizeof(adjust));
1730 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
1733 if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
1734 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
1735 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
1736 adjust.temperature_matrix[i] =
1737 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
1740 pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp, &adjust);
1743 static void dcn10_program_output_csc(struct dc *dc,
1744 struct pipe_ctx *pipe_ctx,
1745 enum dc_color_space colorspace,
1749 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
1750 if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment != NULL)
1751 pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, matrix);
1753 if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default != NULL)
1754 pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default(pipe_ctx->plane_res.dpp, colorspace);
1758 bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
1760 if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible)
1762 if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
1767 bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
1769 if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible)
1771 if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
1776 bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
1778 if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible)
1780 if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
1782 if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
1787 bool is_rgb_cspace(enum dc_color_space output_color_space)
1789 switch (output_color_space) {
1790 case COLOR_SPACE_SRGB:
1791 case COLOR_SPACE_SRGB_LIMITED:
1792 case COLOR_SPACE_2020_RGB_FULLRANGE:
1793 case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
1794 case COLOR_SPACE_ADOBERGB:
1796 case COLOR_SPACE_YCBCR601:
1797 case COLOR_SPACE_YCBCR709:
1798 case COLOR_SPACE_YCBCR601_LIMITED:
1799 case COLOR_SPACE_YCBCR709_LIMITED:
1800 case COLOR_SPACE_2020_YCBCR:
1803 /* Add a case to switch */
1804 BREAK_TO_DEBUGGER();
1809 void dcn10_get_surface_visual_confirm_color(
1810 const struct pipe_ctx *pipe_ctx,
1811 struct tg_color *color)
1813 uint32_t color_value = MAX_TG_COLOR_VALUE;
1815 switch (pipe_ctx->plane_res.scl_data.format) {
1816 case PIXEL_FORMAT_ARGB8888:
1817 /* set boarder color to red */
1818 color->color_r_cr = color_value;
1821 case PIXEL_FORMAT_ARGB2101010:
1822 /* set boarder color to blue */
1823 color->color_b_cb = color_value;
1825 case PIXEL_FORMAT_420BPP8:
1826 /* set boarder color to green */
1827 color->color_g_y = color_value;
1829 case PIXEL_FORMAT_420BPP10:
1830 /* set boarder color to yellow */
1831 color->color_g_y = color_value;
1832 color->color_r_cr = color_value;
1834 case PIXEL_FORMAT_FP16:
1835 /* set boarder color to white */
1836 color->color_r_cr = color_value;
1837 color->color_b_cb = color_value;
1838 color->color_g_y = color_value;
1845 void dcn10_get_hdr_visual_confirm_color(
1846 struct pipe_ctx *pipe_ctx,
1847 struct tg_color *color)
1849 uint32_t color_value = MAX_TG_COLOR_VALUE;
1851 // Determine the overscan color based on the top-most (desktop) plane's context
1852 struct pipe_ctx *top_pipe_ctx = pipe_ctx;
1854 while (top_pipe_ctx->top_pipe != NULL)
1855 top_pipe_ctx = top_pipe_ctx->top_pipe;
1857 switch (top_pipe_ctx->plane_res.scl_data.format) {
1858 case PIXEL_FORMAT_ARGB2101010:
1859 if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_PQ) {
1860 /* HDR10, ARGB2101010 - set boarder color to red */
1861 color->color_r_cr = color_value;
1864 case PIXEL_FORMAT_FP16:
1865 if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_PQ) {
1866 /* HDR10, FP16 - set boarder color to blue */
1867 color->color_b_cb = color_value;
1868 } else if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22) {
1869 /* FreeSync 2 HDR - set boarder color to green */
1870 color->color_g_y = color_value;
1874 /* SDR - set boarder color to Gray */
1875 color->color_r_cr = color_value/2;
1876 color->color_b_cb = color_value/2;
1877 color->color_g_y = color_value/2;
1882 static uint16_t fixed_point_to_int_frac(
1883 struct fixed31_32 arg,
1884 uint8_t integer_bits,
1885 uint8_t fractional_bits)
1888 int32_t divisor = 1 << fractional_bits;
1892 uint16_t d = (uint16_t)dc_fixpt_floor(
1896 if (d <= (uint16_t)(1 << integer_bits) - (1 / (uint16_t)divisor))
1897 numerator = (uint16_t)dc_fixpt_floor(
1902 numerator = dc_fixpt_floor(
1905 1LL << integer_bits),
1912 result = (uint16_t)numerator;
1914 result = (uint16_t)(
1915 (1 << (integer_bits + fractional_bits + 1)) + numerator);
1917 if ((result != 0) && dc_fixpt_lt(
1918 arg, dc_fixpt_zero))
1919 result |= 1 << (integer_bits + fractional_bits);
1924 void dcn10_build_prescale_params(struct dc_bias_and_scale *bias_and_scale,
1925 const struct dc_plane_state *plane_state)
1927 if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
1928 && plane_state->format != SURFACE_PIXEL_FORMAT_INVALID
1929 && plane_state->input_csc_color_matrix.enable_adjustment
1930 && plane_state->coeff_reduction_factor.value != 0) {
1931 bias_and_scale->scale_blue = fixed_point_to_int_frac(
1932 dc_fixpt_mul(plane_state->coeff_reduction_factor,
1933 dc_fixpt_from_fraction(256, 255)),
1936 bias_and_scale->scale_red = bias_and_scale->scale_blue;
1937 bias_and_scale->scale_green = bias_and_scale->scale_blue;
1939 bias_and_scale->scale_blue = 0x2000;
1940 bias_and_scale->scale_red = 0x2000;
1941 bias_and_scale->scale_green = 0x2000;
1945 static void update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state)
1947 struct dc_bias_and_scale bns_params = {0};
1949 // program the input csc
1950 dpp->funcs->dpp_setup(dpp,
1951 plane_state->format,
1952 EXPANSION_MODE_ZERO,
1953 plane_state->input_csc_color_matrix,
1954 plane_state->color_space);
1956 //set scale and bias registers
1957 dcn10_build_prescale_params(&bns_params, plane_state);
1958 if (dpp->funcs->dpp_program_bias_and_scale)
1959 dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
1962 static void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
1964 struct hubp *hubp = pipe_ctx->plane_res.hubp;
1965 struct mpcc_blnd_cfg blnd_cfg = {{0}};
1966 bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
1968 struct mpcc *new_mpcc;
1969 struct mpc *mpc = dc->res_pool->mpc;
1970 struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);
1972 if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) {
1973 dcn10_get_hdr_visual_confirm_color(
1974 pipe_ctx, &blnd_cfg.black_color);
1975 } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) {
1976 dcn10_get_surface_visual_confirm_color(
1977 pipe_ctx, &blnd_cfg.black_color);
1979 color_space_to_black_color(
1980 dc, pipe_ctx->stream->output_color_space,
1981 &blnd_cfg.black_color);
1984 if (per_pixel_alpha)
1985 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;
1987 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA;
1989 blnd_cfg.overlap_only = false;
1990 blnd_cfg.global_gain = 0xff;
1992 if (pipe_ctx->plane_state->global_alpha)
1993 blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value;
1995 blnd_cfg.global_alpha = 0xff;
1997 /* DCN1.0 has output CM before MPC which seems to screw with
1998 * pre-multiplied alpha.
2000 blnd_cfg.pre_multiplied_alpha = is_rgb_cspace(
2001 pipe_ctx->stream->output_color_space)
2007 * Note: currently there is a bug in init_hw such that
2008 * on resume from hibernate, BIOS sets up MPCC0, and
2009 * we do mpcc_remove but the mpcc cannot go to idle
2010 * after remove. This cause us to pick mpcc1 here,
2011 * which causes a pstate hang for yet unknown reason.
2013 mpcc_id = hubp->inst;
2015 /* If there is no full update, don't need to touch MPC tree*/
2016 if (!pipe_ctx->plane_state->update_flags.bits.full_update) {
2017 mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id);
2021 /* check if this MPCC is already being used */
2022 new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id);
2023 /* remove MPCC if being used */
2024 if (new_mpcc != NULL)
2025 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc);
2027 if (dc->debug.sanity_checks)
2028 mpc->funcs->assert_mpcc_idle_before_connect(
2029 dc->res_pool->mpc, mpcc_id);
2031 /* Call MPC to insert new plane */
2032 new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,
2040 ASSERT(new_mpcc != NULL);
2042 hubp->opp_id = pipe_ctx->stream_res.opp->inst;
2043 hubp->mpcc_id = mpcc_id;
2046 static void update_scaler(struct pipe_ctx *pipe_ctx)
2048 bool per_pixel_alpha =
2049 pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
2051 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = per_pixel_alpha;
2052 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
2053 /* scaler configuration */
2054 pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(
2055 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);
2058 void update_dchubp_dpp(
2060 struct pipe_ctx *pipe_ctx,
2061 struct dc_state *context)
2063 struct hubp *hubp = pipe_ctx->plane_res.hubp;
2064 struct dpp *dpp = pipe_ctx->plane_res.dpp;
2065 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2066 union plane_size size = plane_state->plane_size;
2067 unsigned int compat_level = 0;
2069 /* depends on DML calculation, DPP clock value may change dynamically */
2070 /* If request max dpp clk is lower than current dispclk, no need to
2073 if (plane_state->update_flags.bits.full_update) {
2074 bool should_divided_by_2 = context->bw_ctx.bw.dcn.clk.dppclk_khz <=
2075 dc->clk_mgr->clks.dispclk_khz / 2;
2077 dpp->funcs->dpp_dppclk_control(
2079 should_divided_by_2,
2082 if (dc->res_pool->dccg)
2083 dc->res_pool->dccg->funcs->update_dpp_dto(
2086 pipe_ctx->plane_res.bw.dppclk_khz);
2088 dc->clk_mgr->clks.dppclk_khz = should_divided_by_2 ?
2089 dc->clk_mgr->clks.dispclk_khz / 2 :
2090 dc->clk_mgr->clks.dispclk_khz;
2093 /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG
2094 * VTG is within DCHUBBUB which is commond block share by each pipe HUBP.
2095 * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG
2097 if (plane_state->update_flags.bits.full_update) {
2098 hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst);
2100 hubp->funcs->hubp_setup(
2102 &pipe_ctx->dlg_regs,
2103 &pipe_ctx->ttu_regs,
2105 &pipe_ctx->pipe_dlg_param);
2106 hubp->funcs->hubp_setup_interdependent(
2108 &pipe_ctx->dlg_regs,
2109 &pipe_ctx->ttu_regs);
2112 size.grph.surface_size = pipe_ctx->plane_res.scl_data.viewport;
2114 if (plane_state->update_flags.bits.full_update ||
2115 plane_state->update_flags.bits.bpp_change)
2116 update_dpp(dpp, plane_state);
2118 if (plane_state->update_flags.bits.full_update ||
2119 plane_state->update_flags.bits.per_pixel_alpha_change ||
2120 plane_state->update_flags.bits.global_alpha_change)
2121 dc->hwss.update_mpcc(dc, pipe_ctx);
2123 if (plane_state->update_flags.bits.full_update ||
2124 plane_state->update_flags.bits.per_pixel_alpha_change ||
2125 plane_state->update_flags.bits.global_alpha_change ||
2126 plane_state->update_flags.bits.scaling_change ||
2127 plane_state->update_flags.bits.position_change) {
2128 update_scaler(pipe_ctx);
2131 if (plane_state->update_flags.bits.full_update ||
2132 plane_state->update_flags.bits.scaling_change ||
2133 plane_state->update_flags.bits.position_change) {
2134 hubp->funcs->mem_program_viewport(
2136 &pipe_ctx->plane_res.scl_data.viewport,
2137 &pipe_ctx->plane_res.scl_data.viewport_c);
2140 if (pipe_ctx->stream->cursor_attributes.address.quad_part != 0) {
2141 dc->hwss.set_cursor_position(pipe_ctx);
2142 dc->hwss.set_cursor_attribute(pipe_ctx);
2144 if (dc->hwss.set_cursor_sdr_white_level)
2145 dc->hwss.set_cursor_sdr_white_level(pipe_ctx);
2148 if (plane_state->update_flags.bits.full_update) {
2150 program_gamut_remap(pipe_ctx);
2152 dc->hwss.program_output_csc(dc,
2154 pipe_ctx->stream->output_color_space,
2155 pipe_ctx->stream->csc_color_matrix.matrix,
2159 if (plane_state->update_flags.bits.full_update ||
2160 plane_state->update_flags.bits.pixel_format_change ||
2161 plane_state->update_flags.bits.horizontal_mirror_change ||
2162 plane_state->update_flags.bits.rotation_change ||
2163 plane_state->update_flags.bits.swizzle_change ||
2164 plane_state->update_flags.bits.dcc_change ||
2165 plane_state->update_flags.bits.bpp_change ||
2166 plane_state->update_flags.bits.scaling_change ||
2167 plane_state->update_flags.bits.plane_size_change) {
2168 hubp->funcs->hubp_program_surface_config(
2170 plane_state->format,
2171 &plane_state->tiling_info,
2173 plane_state->rotation,
2175 plane_state->horizontal_mirror,
2179 hubp->power_gated = false;
2181 dc->hwss.update_plane_addr(dc, pipe_ctx);
2183 if (is_pipe_tree_visible(pipe_ctx))
2184 hubp->funcs->set_blank(hubp, false);
2187 static void dcn10_blank_pixel_data(
2189 struct pipe_ctx *pipe_ctx,
2192 enum dc_color_space color_space;
2193 struct tg_color black_color = {0};
2194 struct stream_resource *stream_res = &pipe_ctx->stream_res;
2195 struct dc_stream_state *stream = pipe_ctx->stream;
2197 /* program otg blank color */
2198 color_space = stream->output_color_space;
2199 color_space_to_black_color(dc, color_space, &black_color);
2202 * The way 420 is packed, 2 channels carry Y component, 1 channel
2203 * alternate between Cb and Cr, so both channels need the pixel
2206 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
2207 black_color.color_r_cr = black_color.color_g_y;
2210 if (stream_res->tg->funcs->set_blank_color)
2211 stream_res->tg->funcs->set_blank_color(
2216 if (stream_res->tg->funcs->set_blank)
2217 stream_res->tg->funcs->set_blank(stream_res->tg, blank);
2218 if (stream_res->abm) {
2219 stream_res->abm->funcs->set_pipe(stream_res->abm, stream_res->tg->inst + 1);
2220 stream_res->abm->funcs->set_abm_level(stream_res->abm, stream->abm_level);
2223 if (stream_res->abm)
2224 stream_res->abm->funcs->set_abm_immediate_disable(stream_res->abm);
2225 if (stream_res->tg->funcs->set_blank)
2226 stream_res->tg->funcs->set_blank(stream_res->tg, blank);
2230 void set_hdr_multiplier(struct pipe_ctx *pipe_ctx)
2232 struct fixed31_32 multiplier = dc_fixpt_from_fraction(
2233 pipe_ctx->plane_state->sdr_white_level, 80);
2234 uint32_t hw_mult = 0x1f000; // 1.0 default multiplier
2235 struct custom_float_format fmt;
2237 fmt.exponenta_bits = 6;
2238 fmt.mantissa_bits = 12;
2241 if (pipe_ctx->plane_state->sdr_white_level > 80)
2242 convert_to_custom_float_format(multiplier, &fmt, &hw_mult);
2244 pipe_ctx->plane_res.dpp->funcs->dpp_set_hdr_multiplier(
2245 pipe_ctx->plane_res.dpp, hw_mult);
2248 void dcn10_program_pipe(
2250 struct pipe_ctx *pipe_ctx,
2251 struct dc_state *context)
2253 if (pipe_ctx->plane_state->update_flags.bits.full_update)
2254 dcn10_enable_plane(dc, pipe_ctx, context);
2256 update_dchubp_dpp(dc, pipe_ctx, context);
2258 set_hdr_multiplier(pipe_ctx);
2260 if (pipe_ctx->plane_state->update_flags.bits.full_update ||
2261 pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
2262 pipe_ctx->plane_state->update_flags.bits.gamma_change)
2263 dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state);
2265 /* dcn10_translate_regamma_to_hw_format takes 750us to finish
2266 * only do gamma programming for full update.
2267 * TODO: This can be further optimized/cleaned up
2268 * Always call this for now since it does memcmp inside before
2269 * doing heavy calculation and programming
2271 if (pipe_ctx->plane_state->update_flags.bits.full_update)
2272 dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);
2275 static void program_all_pipe_in_tree(
2277 struct pipe_ctx *pipe_ctx,
2278 struct dc_state *context)
2280 if (pipe_ctx->top_pipe == NULL) {
2281 bool blank = !is_pipe_tree_visible(pipe_ctx);
2283 pipe_ctx->stream_res.tg->funcs->program_global_sync(
2284 pipe_ctx->stream_res.tg,
2285 pipe_ctx->pipe_dlg_param.vready_offset,
2286 pipe_ctx->pipe_dlg_param.vstartup_start,
2287 pipe_ctx->pipe_dlg_param.vupdate_offset,
2288 pipe_ctx->pipe_dlg_param.vupdate_width);
2290 pipe_ctx->stream_res.tg->funcs->set_vtg_params(
2291 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
2293 dc->hwss.blank_pixel_data(dc, pipe_ctx, blank);
2297 if (pipe_ctx->plane_state != NULL)
2298 dcn10_program_pipe(dc, pipe_ctx, context);
2300 if (pipe_ctx->bottom_pipe != NULL && pipe_ctx->bottom_pipe != pipe_ctx)
2301 program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context);
2304 struct pipe_ctx *find_top_pipe_for_stream(
2306 struct dc_state *context,
2307 const struct dc_stream_state *stream)
2311 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2312 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2313 struct pipe_ctx *old_pipe_ctx =
2314 &dc->current_state->res_ctx.pipe_ctx[i];
2316 if (!pipe_ctx->plane_state && !old_pipe_ctx->plane_state)
2319 if (pipe_ctx->stream != stream)
2322 if (!pipe_ctx->top_pipe)
2328 static void dcn10_apply_ctx_for_surface(
2330 const struct dc_stream_state *stream,
2332 struct dc_state *context)
2335 struct timing_generator *tg;
2336 bool removed_pipe[4] = { false };
2337 bool interdependent_update = false;
2338 struct pipe_ctx *top_pipe_to_program =
2339 find_top_pipe_for_stream(dc, context, stream);
2340 DC_LOGGER_INIT(dc->ctx->logger);
2342 if (!top_pipe_to_program)
2345 tg = top_pipe_to_program->stream_res.tg;
2347 interdependent_update = top_pipe_to_program->plane_state &&
2348 top_pipe_to_program->plane_state->update_flags.bits.full_update;
2350 if (interdependent_update)
2351 lock_all_pipes(dc, context, true);
2353 dcn10_pipe_control_lock(dc, top_pipe_to_program, true);
2355 if (num_planes == 0) {
2356 /* OTG blank before remove all front end */
2357 dc->hwss.blank_pixel_data(dc, top_pipe_to_program, true);
2360 /* Disconnect unused mpcc */
2361 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2362 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2363 struct pipe_ctx *old_pipe_ctx =
2364 &dc->current_state->res_ctx.pipe_ctx[i];
2366 * Powergate reused pipes that are not powergated
2367 * fairly hacky right now, using opp_id as indicator
2368 * TODO: After move dc_post to dc_update, this will
2371 if (pipe_ctx->plane_state && !old_pipe_ctx->plane_state) {
2372 if (old_pipe_ctx->stream_res.tg == tg &&
2373 old_pipe_ctx->plane_res.hubp &&
2374 old_pipe_ctx->plane_res.hubp->opp_id != 0xf)
2375 dcn10_disable_plane(dc, old_pipe_ctx);
2378 if ((!pipe_ctx->plane_state ||
2379 pipe_ctx->stream_res.tg != old_pipe_ctx->stream_res.tg) &&
2380 old_pipe_ctx->plane_state &&
2381 old_pipe_ctx->stream_res.tg == tg) {
2383 dc->hwss.plane_atomic_disconnect(dc, old_pipe_ctx);
2384 removed_pipe[i] = true;
2386 DC_LOG_DC("Reset mpcc for pipe %d\n",
2387 old_pipe_ctx->pipe_idx);
2392 program_all_pipe_in_tree(dc, top_pipe_to_program, context);
2394 if (interdependent_update)
2395 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2396 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2397 /* Skip inactive pipes and ones already updated */
2398 if (!pipe_ctx->stream || pipe_ctx->stream == stream ||
2399 !pipe_ctx->plane_state || !tg->funcs->is_tg_enabled(tg))
2402 pipe_ctx->plane_res.hubp->funcs->hubp_setup_interdependent(
2403 pipe_ctx->plane_res.hubp,
2404 &pipe_ctx->dlg_regs,
2405 &pipe_ctx->ttu_regs);
2408 if (interdependent_update)
2409 lock_all_pipes(dc, context, false);
2411 dcn10_pipe_control_lock(dc, top_pipe_to_program, false);
2413 if (num_planes == 0)
2414 false_optc_underflow_wa(dc, stream, tg);
2416 for (i = 0; i < dc->res_pool->pipe_count; i++)
2417 if (removed_pipe[i])
2418 dcn10_disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
2420 if (dc->hwseq->wa.DEGVIDCN10_254)
2421 hubbub1_wm_change_req_wa(dc->res_pool->hubbub);
2424 static void dcn10_stereo_hw_frame_pack_wa(struct dc *dc, struct dc_state *context)
2428 for (i = 0; i < context->stream_count; i++) {
2429 if (context->streams[i]->timing.timing_3d_format
2430 == TIMING_3D_FORMAT_HW_FRAME_PACKING) {
2434 hubbub1_allow_self_refresh_control(dc->res_pool->hubbub, false);
2440 static void dcn10_prepare_bandwidth(
2442 struct dc_state *context)
2444 struct hubbub *hubbub = dc->res_pool->hubbub;
2446 if (dc->debug.sanity_checks)
2447 dcn10_verify_allow_pstate_change_high(dc);
2449 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
2450 if (context->stream_count == 0)
2451 context->bw_ctx.bw.dcn.clk.phyclk_khz = 0;
2453 dc->clk_mgr->funcs->update_clocks(
2459 hubbub->funcs->program_watermarks(hubbub,
2460 &context->bw_ctx.bw.dcn.watermarks,
2461 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
2463 dcn10_stereo_hw_frame_pack_wa(dc, context);
2465 if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE)
2466 dcn_bw_notify_pplib_of_wm_ranges(dc);
2468 if (dc->debug.sanity_checks)
2469 dcn10_verify_allow_pstate_change_high(dc);
2472 static void dcn10_optimize_bandwidth(
2474 struct dc_state *context)
2476 struct hubbub *hubbub = dc->res_pool->hubbub;
2478 if (dc->debug.sanity_checks)
2479 dcn10_verify_allow_pstate_change_high(dc);
2481 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
2482 if (context->stream_count == 0)
2483 context->bw_ctx.bw.dcn.clk.phyclk_khz = 0;
2485 dc->clk_mgr->funcs->update_clocks(
2491 hubbub->funcs->program_watermarks(hubbub,
2492 &context->bw_ctx.bw.dcn.watermarks,
2493 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
2495 dcn10_stereo_hw_frame_pack_wa(dc, context);
2497 if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE)
2498 dcn_bw_notify_pplib_of_wm_ranges(dc);
2500 if (dc->debug.sanity_checks)
2501 dcn10_verify_allow_pstate_change_high(dc);
2504 static void set_drr(struct pipe_ctx **pipe_ctx,
2505 int num_pipes, int vmin, int vmax)
2508 struct drr_params params = {0};
2509 // DRR should set trigger event to monitor surface update event
2510 unsigned int event_triggers = 0x80;
2512 params.vertical_total_max = vmax;
2513 params.vertical_total_min = vmin;
2515 /* TODO: If multiple pipes are to be supported, you need
2516 * some GSL stuff. Static screen triggers may be programmed differently
2519 for (i = 0; i < num_pipes; i++) {
2520 pipe_ctx[i]->stream_res.tg->funcs->set_drr(
2521 pipe_ctx[i]->stream_res.tg, ¶ms);
2522 if (vmax != 0 && vmin != 0)
2523 pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control(
2524 pipe_ctx[i]->stream_res.tg,
2529 static void get_position(struct pipe_ctx **pipe_ctx,
2531 struct crtc_position *position)
2535 /* TODO: handle pipes > 1
2537 for (i = 0; i < num_pipes; i++)
2538 pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);
2541 static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
2542 int num_pipes, const struct dc_static_screen_events *events)
2545 unsigned int value = 0;
2547 if (events->surface_update)
2549 if (events->cursor_update)
2551 if (events->force_trigger)
2554 for (i = 0; i < num_pipes; i++)
2555 pipe_ctx[i]->stream_res.tg->funcs->
2556 set_static_screen_control(pipe_ctx[i]->stream_res.tg, value);
2559 static void dcn10_config_stereo_parameters(
2560 struct dc_stream_state *stream, struct crtc_stereo_flags *flags)
2562 enum view_3d_format view_format = stream->view_format;
2563 enum dc_timing_3d_format timing_3d_format =\
2564 stream->timing.timing_3d_format;
2565 bool non_stereo_timing = false;
2567 if (timing_3d_format == TIMING_3D_FORMAT_NONE ||
2568 timing_3d_format == TIMING_3D_FORMAT_SIDE_BY_SIDE ||
2569 timing_3d_format == TIMING_3D_FORMAT_TOP_AND_BOTTOM)
2570 non_stereo_timing = true;
2572 if (non_stereo_timing == false &&
2573 view_format == VIEW_3D_FORMAT_FRAME_SEQUENTIAL) {
2575 flags->PROGRAM_STEREO = 1;
2576 flags->PROGRAM_POLARITY = 1;
2577 if (timing_3d_format == TIMING_3D_FORMAT_INBAND_FA ||
2578 timing_3d_format == TIMING_3D_FORMAT_DP_HDMI_INBAND_FA ||
2579 timing_3d_format == TIMING_3D_FORMAT_SIDEBAND_FA) {
2580 enum display_dongle_type dongle = \
2581 stream->link->ddc->dongle_type;
2582 if (dongle == DISPLAY_DONGLE_DP_VGA_CONVERTER ||
2583 dongle == DISPLAY_DONGLE_DP_DVI_CONVERTER ||
2584 dongle == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
2585 flags->DISABLE_STEREO_DP_SYNC = 1;
2587 flags->RIGHT_EYE_POLARITY =\
2588 stream->timing.flags.RIGHT_EYE_3D_POLARITY;
2589 if (timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
2590 flags->FRAME_PACKED = 1;
2596 static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc)
2598 struct crtc_stereo_flags flags = { 0 };
2599 struct dc_stream_state *stream = pipe_ctx->stream;
2601 dcn10_config_stereo_parameters(stream, &flags);
2603 pipe_ctx->stream_res.opp->funcs->opp_program_stereo(
2604 pipe_ctx->stream_res.opp,
2605 flags.PROGRAM_STEREO == 1 ? true:false,
2608 pipe_ctx->stream_res.tg->funcs->program_stereo(
2609 pipe_ctx->stream_res.tg,
2616 static struct hubp *get_hubp_by_inst(struct resource_pool *res_pool, int mpcc_inst)
2620 for (i = 0; i < res_pool->pipe_count; i++) {
2621 if (res_pool->hubps[i]->inst == mpcc_inst)
2622 return res_pool->hubps[i];
2628 static void dcn10_wait_for_mpcc_disconnect(
2630 struct resource_pool *res_pool,
2631 struct pipe_ctx *pipe_ctx)
2635 if (dc->debug.sanity_checks) {
2636 dcn10_verify_allow_pstate_change_high(dc);
2639 if (!pipe_ctx->stream_res.opp)
2642 for (mpcc_inst = 0; mpcc_inst < MAX_PIPES; mpcc_inst++) {
2643 if (pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst]) {
2644 struct hubp *hubp = get_hubp_by_inst(res_pool, mpcc_inst);
2646 res_pool->mpc->funcs->wait_for_idle(res_pool->mpc, mpcc_inst);
2647 pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst] = false;
2648 hubp->funcs->set_blank(hubp, true);
2652 if (dc->debug.sanity_checks) {
2653 dcn10_verify_allow_pstate_change_high(dc);
2658 static bool dcn10_dummy_display_power_gating(
2660 uint8_t controller_id,
2661 struct dc_bios *dcb,
2662 enum pipe_gating_control power_gating)
2667 static void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx)
2669 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2670 struct timing_generator *tg = pipe_ctx->stream_res.tg;
2673 if (plane_state == NULL)
2676 flip_pending = pipe_ctx->plane_res.hubp->funcs->hubp_is_flip_pending(
2677 pipe_ctx->plane_res.hubp);
2679 plane_state->status.is_flip_pending = plane_state->status.is_flip_pending || flip_pending;
2682 plane_state->status.current_address = plane_state->status.requested_address;
2684 if (plane_state->status.current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2685 tg->funcs->is_stereo_left_eye) {
2686 plane_state->status.is_right_eye =
2687 !tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);
2691 static void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data)
2693 if (hws->ctx->dc->res_pool->hubbub != NULL) {
2694 struct hubp *hubp = hws->ctx->dc->res_pool->hubps[0];
2696 if (hubp->funcs->hubp_update_dchub)
2697 hubp->funcs->hubp_update_dchub(hubp, dh_data);
2699 hubbub1_update_dchub(hws->ctx->dc->res_pool->hubbub, dh_data);
2703 static void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)
2705 struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;
2706 struct hubp *hubp = pipe_ctx->plane_res.hubp;
2707 struct dpp *dpp = pipe_ctx->plane_res.dpp;
2708 struct dc_cursor_mi_param param = {
2709 .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10,
2710 .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz,
2711 .viewport = pipe_ctx->plane_res.scl_data.viewport,
2712 .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz,
2713 .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert,
2714 .rotation = pipe_ctx->plane_state->rotation,
2715 .mirror = pipe_ctx->plane_state->horizontal_mirror
2717 uint32_t x_plane = pipe_ctx->plane_state->dst_rect.x;
2718 uint32_t y_plane = pipe_ctx->plane_state->dst_rect.y;
2719 uint32_t x_offset = min(x_plane, pos_cpy.x);
2720 uint32_t y_offset = min(y_plane, pos_cpy.y);
2722 pos_cpy.x -= x_offset;
2723 pos_cpy.y -= y_offset;
2724 pos_cpy.x_hotspot += (x_plane - x_offset);
2725 pos_cpy.y_hotspot += (y_plane - y_offset);
2727 if (pipe_ctx->plane_state->address.type
2728 == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
2729 pos_cpy.enable = false;
2731 hubp->funcs->set_cursor_position(hubp, &pos_cpy, ¶m);
2732 dpp->funcs->set_cursor_position(dpp, &pos_cpy, ¶m, hubp->curs_attr.width, hubp->curs_attr.height);
2735 static void dcn10_set_cursor_attribute(struct pipe_ctx *pipe_ctx)
2737 struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;
2739 pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes(
2740 pipe_ctx->plane_res.hubp, attributes);
2741 pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes(
2742 pipe_ctx->plane_res.dpp, attributes->color_format);
2745 static void dcn10_set_cursor_sdr_white_level(struct pipe_ctx *pipe_ctx)
2747 uint32_t sdr_white_level = pipe_ctx->stream->cursor_attributes.sdr_white_level;
2748 struct fixed31_32 multiplier;
2749 struct dpp_cursor_attributes opt_attr = { 0 };
2750 uint32_t hw_scale = 0x3c00; // 1.0 default multiplier
2751 struct custom_float_format fmt;
2753 if (!pipe_ctx->plane_res.dpp->funcs->set_optional_cursor_attributes)
2756 fmt.exponenta_bits = 5;
2757 fmt.mantissa_bits = 10;
2760 if (sdr_white_level > 80) {
2761 multiplier = dc_fixpt_from_fraction(sdr_white_level, 80);
2762 convert_to_custom_float_format(multiplier, &fmt, &hw_scale);
2765 opt_attr.scale = hw_scale;
2768 pipe_ctx->plane_res.dpp->funcs->set_optional_cursor_attributes(
2769 pipe_ctx->plane_res.dpp, &opt_attr);
2773 * apply_front_porch_workaround TODO FPGA still need?
2775 * This is a workaround for a bug that has existed since R5xx and has not been
2776 * fixed keep Front porch at minimum 2 for Interlaced mode or 1 for progressive.
2778 static void apply_front_porch_workaround(
2779 struct dc_crtc_timing *timing)
2781 if (timing->flags.INTERLACE == 1) {
2782 if (timing->v_front_porch < 2)
2783 timing->v_front_porch = 2;
2785 if (timing->v_front_porch < 1)
2786 timing->v_front_porch = 1;
2790 int get_vupdate_offset_from_vsync(struct pipe_ctx *pipe_ctx)
2792 const struct dc_crtc_timing *dc_crtc_timing = &pipe_ctx->stream->timing;
2793 struct dc_crtc_timing patched_crtc_timing;
2794 int vesa_sync_start;
2796 int interlace_factor;
2797 int vertical_line_start;
2799 patched_crtc_timing = *dc_crtc_timing;
2800 apply_front_porch_workaround(&patched_crtc_timing);
2802 interlace_factor = patched_crtc_timing.flags.INTERLACE ? 2 : 1;
2804 vesa_sync_start = patched_crtc_timing.v_addressable +
2805 patched_crtc_timing.v_border_bottom +
2806 patched_crtc_timing.v_front_porch;
2808 asic_blank_end = (patched_crtc_timing.v_total -
2810 patched_crtc_timing.v_border_top)
2813 vertical_line_start = asic_blank_end -
2814 pipe_ctx->pipe_dlg_param.vstartup_start + 1;
2816 return vertical_line_start;
2819 void lock_all_pipes(struct dc *dc,
2820 struct dc_state *context,
2823 struct pipe_ctx *pipe_ctx;
2824 struct timing_generator *tg;
2827 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2828 pipe_ctx = &context->res_ctx.pipe_ctx[i];
2829 tg = pipe_ctx->stream_res.tg;
2831 * Only lock the top pipe's tg to prevent redundant
2832 * (un)locking. Also skip if pipe is disabled.
2834 if (pipe_ctx->top_pipe ||
2835 !pipe_ctx->stream || !pipe_ctx->plane_state ||
2836 !tg->funcs->is_tg_enabled(tg))
2840 tg->funcs->lock(tg);
2842 tg->funcs->unlock(tg);
2846 static void calc_vupdate_position(
2847 struct pipe_ctx *pipe_ctx,
2848 uint32_t *start_line,
2851 const struct dc_crtc_timing *dc_crtc_timing = &pipe_ctx->stream->timing;
2852 int vline_int_offset_from_vupdate =
2853 pipe_ctx->stream->periodic_interrupt0.lines_offset;
2854 int vupdate_offset_from_vsync = get_vupdate_offset_from_vsync(pipe_ctx);
2857 if (vline_int_offset_from_vupdate > 0)
2858 vline_int_offset_from_vupdate--;
2859 else if (vline_int_offset_from_vupdate < 0)
2860 vline_int_offset_from_vupdate++;
2862 start_position = vline_int_offset_from_vupdate + vupdate_offset_from_vsync;
2864 if (start_position >= 0)
2865 *start_line = start_position;
2867 *start_line = dc_crtc_timing->v_total + start_position - 1;
2869 *end_line = *start_line + 2;
2871 if (*end_line >= dc_crtc_timing->v_total)
2875 static void cal_vline_position(
2876 struct pipe_ctx *pipe_ctx,
2877 enum vline_select vline,
2878 uint32_t *start_line,
2881 enum vertical_interrupt_ref_point ref_point = INVALID_POINT;
2883 if (vline == VLINE0)
2884 ref_point = pipe_ctx->stream->periodic_interrupt0.ref_point;
2885 else if (vline == VLINE1)
2886 ref_point = pipe_ctx->stream->periodic_interrupt1.ref_point;
2888 switch (ref_point) {
2889 case START_V_UPDATE:
2890 calc_vupdate_position(
2896 // Suppose to do nothing because vsync is 0;
2904 static void dcn10_setup_periodic_interrupt(
2905 struct pipe_ctx *pipe_ctx,
2906 enum vline_select vline)
2908 struct timing_generator *tg = pipe_ctx->stream_res.tg;
2910 if (vline == VLINE0) {
2911 uint32_t start_line = 0;
2912 uint32_t end_line = 0;
2914 cal_vline_position(pipe_ctx, vline, &start_line, &end_line);
2916 tg->funcs->setup_vertical_interrupt0(tg, start_line, end_line);
2918 } else if (vline == VLINE1) {
2919 pipe_ctx->stream_res.tg->funcs->setup_vertical_interrupt1(
2921 pipe_ctx->stream->periodic_interrupt1.lines_offset);
2925 static void dcn10_setup_vupdate_interrupt(struct pipe_ctx *pipe_ctx)
2927 struct timing_generator *tg = pipe_ctx->stream_res.tg;
2928 int start_line = get_vupdate_offset_from_vsync(pipe_ctx);
2930 if (start_line < 0) {
2935 if (tg->funcs->setup_vertical_interrupt2)
2936 tg->funcs->setup_vertical_interrupt2(tg, start_line);
2939 static void dcn10_unblank_stream(struct pipe_ctx *pipe_ctx,
2940 struct dc_link_settings *link_settings)
2942 struct encoder_unblank_param params = { { 0 } };
2943 struct dc_stream_state *stream = pipe_ctx->stream;
2944 struct dc_link *link = stream->link;
2946 /* only 3 items below are used by unblank */
2947 params.timing = pipe_ctx->stream->timing;
2949 params.link_settings.link_rate = link_settings->link_rate;
2951 if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
2952 if (params.timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
2953 params.timing.pix_clk_100hz /= 2;
2954 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, ¶ms);
2957 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
2958 link->dc->hwss.edp_backlight_control(link, true);
2962 static void dcn10_send_immediate_sdp_message(struct pipe_ctx *pipe_ctx,
2963 const uint8_t *custom_sdp_message,
2964 unsigned int sdp_message_size)
2966 if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
2967 pipe_ctx->stream_res.stream_enc->funcs->send_immediate_sdp_message(
2968 pipe_ctx->stream_res.stream_enc,
2974 static const struct hw_sequencer_funcs dcn10_funcs = {
2975 .program_gamut_remap = program_gamut_remap,
2976 .init_hw = dcn10_init_hw,
2977 .init_pipes = dcn10_init_pipes,
2978 .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
2979 .apply_ctx_for_surface = dcn10_apply_ctx_for_surface,
2980 .update_plane_addr = dcn10_update_plane_addr,
2981 .plane_atomic_disconnect = hwss1_plane_atomic_disconnect,
2982 .update_dchub = dcn10_update_dchub,
2983 .update_mpcc = dcn10_update_mpcc,
2984 .update_pending_status = dcn10_update_pending_status,
2985 .set_input_transfer_func = dcn10_set_input_transfer_func,
2986 .set_output_transfer_func = dcn10_set_output_transfer_func,
2987 .program_output_csc = dcn10_program_output_csc,
2988 .power_down = dce110_power_down,
2989 .enable_accelerated_mode = dce110_enable_accelerated_mode,
2990 .enable_timing_synchronization = dcn10_enable_timing_synchronization,
2991 .enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,
2992 .update_info_frame = dce110_update_info_frame,
2993 .send_immediate_sdp_message = dcn10_send_immediate_sdp_message,
2994 .enable_stream = dce110_enable_stream,
2995 .disable_stream = dce110_disable_stream,
2996 .unblank_stream = dcn10_unblank_stream,
2997 .blank_stream = dce110_blank_stream,
2998 .enable_audio_stream = dce110_enable_audio_stream,
2999 .disable_audio_stream = dce110_disable_audio_stream,
3000 .enable_display_power_gating = dcn10_dummy_display_power_gating,
3001 .disable_plane = dcn10_disable_plane,
3002 .blank_pixel_data = dcn10_blank_pixel_data,
3003 .pipe_control_lock = dcn10_pipe_control_lock,
3004 .prepare_bandwidth = dcn10_prepare_bandwidth,
3005 .optimize_bandwidth = dcn10_optimize_bandwidth,
3006 .reset_hw_ctx_wrap = dcn10_reset_hw_ctx_wrap,
3007 .enable_stream_timing = dcn10_enable_stream_timing,
3009 .get_position = get_position,
3010 .set_static_screen_control = set_static_screen_control,
3011 .setup_stereo = dcn10_setup_stereo,
3012 .set_avmute = dce110_set_avmute,
3013 .log_hw_state = dcn10_log_hw_state,
3014 .get_hw_state = dcn10_get_hw_state,
3015 .clear_status_bits = dcn10_clear_status_bits,
3016 .wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
3017 .edp_backlight_control = hwss_edp_backlight_control,
3018 .edp_power_control = hwss_edp_power_control,
3019 .edp_wait_for_hpd_ready = hwss_edp_wait_for_hpd_ready,
3020 .set_cursor_position = dcn10_set_cursor_position,
3021 .set_cursor_attribute = dcn10_set_cursor_attribute,
3022 .set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,
3023 .disable_stream_gating = NULL,
3024 .enable_stream_gating = NULL,
3025 .setup_periodic_interrupt = dcn10_setup_periodic_interrupt,
3026 .setup_vupdate_interrupt = dcn10_setup_vupdate_interrupt
3030 void dcn10_hw_sequencer_construct(struct dc *dc)
3032 dc->hwss = dcn10_funcs;