drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27 #include "core_types.h"
  28 #include "resource.h"
  29 #include "custom_float.h"
  30 #include "dcn10_hw_sequencer.h"
  31 #include "dce110/dce110_hw_sequencer.h"
  32 #include "dce/dce_hwseq.h"
  33 #include "abm.h"
  34 #include "dmcu.h"
  35 #include "dcn10_optc.h"
  36 #include "dcn10/dcn10_dpp.h"
  37 #include "dcn10/dcn10_mpc.h"
  38 #include "timing_generator.h"
  39 #include "opp.h"
  40 #include "ipp.h"
  41 #include "mpc.h"
  42 #include "reg_helper.h"
  43 #include "custom_float.h"
  44 #include "dcn10_hubp.h"
  45 #include "dcn10_hubbub.h"
  46 #include "dcn10_cm_common.h"
  47
  48 #define CTX \
  49         hws->ctx
  50 #define REG(reg)\
  51         hws->regs->reg
  52
  53 #undef FN
  54 #define FN(reg_name, field_name) \
  55         hws->shifts->field_name, hws->masks->field_name
  56
  57 #define DTN_INFO_MICRO_SEC(ref_cycle) \
  58         print_microsec(dc_ctx, ref_cycle)
  59
  60 void print_microsec(struct dc_context *dc_ctx, uint32_t ref_cycle)
  61 {
  62         static const uint32_t ref_clk_mhz = 48;
  63         static const unsigned int frac = 10;
  64         uint32_t us_x10 = (ref_cycle * frac) / ref_clk_mhz;
  65
  66         DTN_INFO("%d.%d \t ",
  67                         us_x10 / frac,
  68                         us_x10 % frac);
  69 }
  70
  71
  72 static void log_mpc_crc(struct dc *dc)
  73 {
  74         struct dc_context *dc_ctx = dc->ctx;
  75         struct dce_hwseq *hws = dc->hwseq;
  76
  77         if (REG(MPC_CRC_RESULT_GB))
  78                 DTN_INFO("MPC_CRC_RESULT_GB:%d MPC_CRC_RESULT_C:%d MPC_CRC_RESULT_AR:%d\n",
  79                 REG_READ(MPC_CRC_RESULT_GB), REG_READ(MPC_CRC_RESULT_C), REG_READ(MPC_CRC_RESULT_AR));
  80         if (REG(DPP_TOP0_DPP_CRC_VAL_B_A))
  81                 DTN_INFO("DPP_TOP0_DPP_CRC_VAL_B_A:%d DPP_TOP0_DPP_CRC_VAL_R_G:%d\n",
  82                 REG_READ(DPP_TOP0_DPP_CRC_VAL_B_A), REG_READ(DPP_TOP0_DPP_CRC_VAL_R_G));
  83 }
  84
  85 void dcn10_log_hubbub_state(struct dc *dc)
  86 {
  87         struct dc_context *dc_ctx = dc->ctx;
  88         struct dcn_hubbub_wm wm;
  89         int i;
  90
  91         hubbub1_wm_read_state(dc->res_pool->hubbub, &wm);
  92
  93         DTN_INFO("HUBBUB WM: \t data_urgent \t pte_meta_urgent \t "
  94                         "sr_enter \t sr_exit \t dram_clk_change \n");
  95
  96         for (i = 0; i < 4; i++) {
  97                 struct dcn_hubbub_wm_set *s;
  98
  99                 s = &wm.sets[i];
 100                 DTN_INFO("WM_Set[%d]:\t ", s->wm_set);
 101                 DTN_INFO_MICRO_SEC(s->data_urgent);
 102                 DTN_INFO_MICRO_SEC(s->pte_meta_urgent);
 103                 DTN_INFO_MICRO_SEC(s->sr_enter);
 104                 DTN_INFO_MICRO_SEC(s->sr_exit);
 105                 DTN_INFO_MICRO_SEC(s->dram_clk_chanage);
 106                 DTN_INFO("\n");
 107         }
 108
 109         DTN_INFO("\n");
 110 }
 111
 112 void dcn10_log_hw_state(struct dc *dc)
 113 {
 114         struct dc_context *dc_ctx = dc->ctx;
 115         struct resource_pool *pool = dc->res_pool;
 116         int i;
 117
 118         DTN_INFO_BEGIN();
 119
 120         dcn10_log_hubbub_state(dc);
 121
 122         DTN_INFO("HUBP:\t format \t addr_hi \t width \t height \t "
 123                         "rotation \t mirror \t  sw_mode \t "
 124                         "dcc_en \t blank_en \t ttu_dis \t underflow \t "
 125                         "min_ttu_vblank \t qos_low_wm \t qos_high_wm \n");
 126
 127         for (i = 0; i < pool->pipe_count; i++) {
 128                 struct hubp *hubp = pool->hubps[i];
 129                 struct dcn_hubp_state s;
 130
 131                 hubp1_read_state(TO_DCN10_HUBP(hubp), &s);
 132
 133                 DTN_INFO("[%d]:\t %xh \t %xh \t %d \t %d \t "
 134                                 "%xh \t %xh \t %xh \t "
 135                                 "%d \t %d \t %d \t %xh \t",
 136                                 i,
 137                                 s.pixel_format,
 138                                 s.inuse_addr_hi,
 139                                 s.viewport_width,
 140                                 s.viewport_height,
 141                                 s.rotation_angle,
 142                                 s.h_mirror_en,
 143                                 s.sw_mode,
 144                                 s.dcc_en,
 145                                 s.blank_en,
 146                                 s.ttu_disable,
 147                                 s.underflow_status);
 148                 DTN_INFO_MICRO_SEC(s.min_ttu_vblank);
 149                 DTN_INFO_MICRO_SEC(s.qos_level_low_wm);
 150                 DTN_INFO_MICRO_SEC(s.qos_level_high_wm);
 151                 DTN_INFO("\n");
 152         }
 153         DTN_INFO("\n");
 154
 155         DTN_INFO("OTG:\t v_bs \t v_be \t v_ss \t v_se \t vpol \t vmax \t vmin \t "
 156                         "h_bs \t h_be \t h_ss \t h_se \t hpol \t htot \t vtot \t underflow\n");
 157
 158         for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
 159                 struct timing_generator *tg = pool->timing_generators[i];
 160                 struct dcn_otg_state s = {0};
 161
 162                 optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s);
 163
 164                 //only print if OTG master is enabled
 165                 if ((s.otg_enabled & 1) == 0)
 166                         continue;
 167
 168                 DTN_INFO("[%d]:\t %d \t %d \t %d \t %d \t "
 169                                 "%d \t %d \t %d \t %d \t %d \t %d \t "
 170                                 "%d \t %d \t %d \t %d \t %d \t ",
 171                                 i,
 172                                 s.v_blank_start,
 173                                 s.v_blank_end,
 174                                 s.v_sync_a_start,
 175                                 s.v_sync_a_end,
 176                                 s.v_sync_a_pol,
 177                                 s.v_total_max,
 178                                 s.v_total_min,
 179                                 s.h_blank_start,
 180                                 s.h_blank_end,
 181                                 s.h_sync_a_start,
 182                                 s.h_sync_a_end,
 183                                 s.h_sync_a_pol,
 184                                 s.h_total,
 185                                 s.v_total,
 186                                 s.underflow_occurred_status);
 187                 DTN_INFO("\n");
 188         }
 189         DTN_INFO("\n");
 190
 191         log_mpc_crc(dc);
 192
 193         DTN_INFO_END();
 194 }
 195
 196 static void enable_dppclk(
 197         struct dce_hwseq *hws,
 198         uint8_t plane_id,
 199         uint32_t requested_pix_clk,
 200         bool dppclk_div)
 201 {
 202         dm_logger_write(hws->ctx->logger, LOG_SURFACE,
 203                         "dppclk_rate_control for pipe %d programed to %d\n",
 204                         plane_id,
 205                         dppclk_div);
 206
 207         if (hws->shifts->DPPCLK_RATE_CONTROL)
 208                 REG_UPDATE_2(DPP_CONTROL[plane_id],
 209                         DPPCLK_RATE_CONTROL, dppclk_div,
 210                         DPP_CLOCK_ENABLE, 1);
 211         else
 212                 REG_UPDATE(DPP_CONTROL[plane_id],
 213                         DPP_CLOCK_ENABLE, 1);
 214 }
 215
 216 static void enable_power_gating_plane(
 217         struct dce_hwseq *hws,
 218         bool enable)
 219 {
 220         bool force_on = 1; /* disable power gating */
 221
 222         if (enable)
 223                 force_on = 0;
 224
 225         /* DCHUBP0/1/2/3 */
 226         REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on);
 227         REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on);
 228         REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on);
 229         REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on);
 230
 231         /* DPP0/1/2/3 */
 232         REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on);
 233         REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on);
 234         REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on);
 235         REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);
 236 }
 237
 238 static void disable_vga(
 239         struct dce_hwseq *hws)
 240 {
 241         REG_WRITE(D1VGA_CONTROL, 0);
 242         REG_WRITE(D2VGA_CONTROL, 0);
 243         REG_WRITE(D3VGA_CONTROL, 0);
 244         REG_WRITE(D4VGA_CONTROL, 0);
 245 }
 246
 247 static void dpp_pg_control(
 248                 struct dce_hwseq *hws,
 249                 unsigned int dpp_inst,
 250                 bool power_on)
 251 {
 252         uint32_t power_gate = power_on ? 0 : 1;
 253         uint32_t pwr_status = power_on ? 0 : 2;
 254
 255         if (hws->ctx->dc->debug.disable_dpp_power_gate)
 256                 return;
 257
 258         switch (dpp_inst) {
 259         case 0: /* DPP0 */
 260                 REG_UPDATE(DOMAIN1_PG_CONFIG,
 261                                 DOMAIN1_POWER_GATE, power_gate);
 262
 263                 REG_WAIT(DOMAIN1_PG_STATUS,
 264                                 DOMAIN1_PGFSM_PWR_STATUS, pwr_status,
 265                                 1, 1000);
 266                 break;
 267         case 1: /* DPP1 */
 268                 REG_UPDATE(DOMAIN3_PG_CONFIG,
 269                                 DOMAIN3_POWER_GATE, power_gate);
 270
 271                 REG_WAIT(DOMAIN3_PG_STATUS,
 272                                 DOMAIN3_PGFSM_PWR_STATUS, pwr_status,
 273                                 1, 1000);
 274                 break;
 275         case 2: /* DPP2 */
 276                 REG_UPDATE(DOMAIN5_PG_CONFIG,
 277                                 DOMAIN5_POWER_GATE, power_gate);
 278
 279                 REG_WAIT(DOMAIN5_PG_STATUS,
 280                                 DOMAIN5_PGFSM_PWR_STATUS, pwr_status,
 281                                 1, 1000);
 282                 break;
 283         case 3: /* DPP3 */
 284                 REG_UPDATE(DOMAIN7_PG_CONFIG,
 285                                 DOMAIN7_POWER_GATE, power_gate);
 286
 287                 REG_WAIT(DOMAIN7_PG_STATUS,
 288                                 DOMAIN7_PGFSM_PWR_STATUS, pwr_status,
 289                                 1, 1000);
 290                 break;
 291         default:
 292                 BREAK_TO_DEBUGGER();
 293                 break;
 294         }
 295 }
 296
 297 static void hubp_pg_control(
 298                 struct dce_hwseq *hws,
 299                 unsigned int hubp_inst,
 300                 bool power_on)
 301 {
 302         uint32_t power_gate = power_on ? 0 : 1;
 303         uint32_t pwr_status = power_on ? 0 : 2;
 304
 305         if (hws->ctx->dc->debug.disable_hubp_power_gate)
 306                 return;
 307
 308         switch (hubp_inst) {
 309         case 0: /* DCHUBP0 */
 310                 REG_UPDATE(DOMAIN0_PG_CONFIG,
 311                                 DOMAIN0_POWER_GATE, power_gate);
 312
 313                 REG_WAIT(DOMAIN0_PG_STATUS,
 314                                 DOMAIN0_PGFSM_PWR_STATUS, pwr_status,
 315                                 1, 1000);
 316                 break;
 317         case 1: /* DCHUBP1 */
 318                 REG_UPDATE(DOMAIN2_PG_CONFIG,
 319                                 DOMAIN2_POWER_GATE, power_gate);
 320
 321                 REG_WAIT(DOMAIN2_PG_STATUS,
 322                                 DOMAIN2_PGFSM_PWR_STATUS, pwr_status,
 323                                 1, 1000);
 324                 break;
 325         case 2: /* DCHUBP2 */
 326                 REG_UPDATE(DOMAIN4_PG_CONFIG,
 327                                 DOMAIN4_POWER_GATE, power_gate);
 328
 329                 REG_WAIT(DOMAIN4_PG_STATUS,
 330                                 DOMAIN4_PGFSM_PWR_STATUS, pwr_status,
 331                                 1, 1000);
 332                 break;
 333         case 3: /* DCHUBP3 */
 334                 REG_UPDATE(DOMAIN6_PG_CONFIG,
 335                                 DOMAIN6_POWER_GATE, power_gate);
 336
 337                 REG_WAIT(DOMAIN6_PG_STATUS,
 338                                 DOMAIN6_PGFSM_PWR_STATUS, pwr_status,
 339                                 1, 1000);
 340                 break;
 341         default:
 342                 BREAK_TO_DEBUGGER();
 343                 break;
 344         }
 345 }
 346
 347 static void power_on_plane(
 348         struct dce_hwseq *hws,
 349         int plane_id)
 350 {
 351         if (REG(DC_IP_REQUEST_CNTL)) {
 352                 REG_SET(DC_IP_REQUEST_CNTL, 0,
 353                                 IP_REQUEST_EN, 1);
 354                 dpp_pg_control(hws, plane_id, true);
 355                 hubp_pg_control(hws, plane_id, true);
 356                 REG_SET(DC_IP_REQUEST_CNTL, 0,
 357                                 IP_REQUEST_EN, 0);
 358                 dm_logger_write(hws->ctx->logger, LOG_DEBUG,
 359                                 "Un-gated front end for pipe %d\n", plane_id);
 360         }
 361 }
 362
 363 static void undo_DEGVIDCN10_253_wa(struct dc *dc)
 364 {
 365         struct dce_hwseq *hws = dc->hwseq;
 366         struct hubp *hubp = dc->res_pool->hubps[0];
 367
 368         if (!hws->wa_state.DEGVIDCN10_253_applied)
 369                 return;
 370
 371         hubp->funcs->set_blank(hubp, true);
 372
 373         REG_SET(DC_IP_REQUEST_CNTL, 0,
 374                         IP_REQUEST_EN, 1);
 375
 376         hubp_pg_control(hws, 0, false);
 377         REG_SET(DC_IP_REQUEST_CNTL, 0,
 378                         IP_REQUEST_EN, 0);
 379
 380         hws->wa_state.DEGVIDCN10_253_applied = false;
 381 }
 382
 383 static void apply_DEGVIDCN10_253_wa(struct dc *dc)
 384 {
 385         struct dce_hwseq *hws = dc->hwseq;
 386         struct hubp *hubp = dc->res_pool->hubps[0];
 387         int i;
 388
 389         if (dc->debug.disable_stutter)
 390                 return;
 391
 392         if (!hws->wa.DEGVIDCN10_253)
 393                 return;
 394
 395         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 396                 if (!dc->res_pool->hubps[i]->power_gated)
 397                         return;
 398         }
 399
 400         /* all pipe power gated, apply work around to enable stutter. */
 401
 402         REG_SET(DC_IP_REQUEST_CNTL, 0,
 403                         IP_REQUEST_EN, 1);
 404
 405         hubp_pg_control(hws, 0, true);
 406         REG_SET(DC_IP_REQUEST_CNTL, 0,
 407                         IP_REQUEST_EN, 0);
 408
 409         hubp->funcs->set_hubp_blank_en(hubp, false);
 410         hws->wa_state.DEGVIDCN10_253_applied = true;
 411 }
 412
 413 static void bios_golden_init(struct dc *dc)
 414 {
 415         struct dc_bios *bp = dc->ctx->dc_bios;
 416         int i;
 417
 418         /* initialize dcn global */
 419         bp->funcs->enable_disp_power_gating(bp,
 420                         CONTROLLER_ID_D0, ASIC_PIPE_INIT);
 421
 422         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 423                 /* initialize dcn per pipe */
 424                 bp->funcs->enable_disp_power_gating(bp,
 425                                 CONTROLLER_ID_D0 + i, ASIC_PIPE_DISABLE);
 426         }
 427 }
 428
 429 static void false_optc_underflow_wa(
 430                 struct dc *dc,
 431                 const struct dc_stream_state *stream,
 432                 struct timing_generator *tg)
 433 {
 434         int i;
 435         bool underflow;
 436
 437         if (!dc->hwseq->wa.false_optc_underflow)
 438                 return;
 439
 440         underflow = tg->funcs->is_optc_underflow_occurred(tg);
 441
 442         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 443                 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
 444
 445                 if (old_pipe_ctx->stream != stream)
 446                         continue;
 447
 448                 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, old_pipe_ctx);
 449         }
 450
 451         tg->funcs->set_blank_data_double_buffer(tg, true);
 452
 453         if (tg->funcs->is_optc_underflow_occurred(tg) && !underflow)
 454                 tg->funcs->clear_optc_underflow(tg);
 455 }
 456
 457 static enum dc_status dcn10_prog_pixclk_crtc_otg(
 458                 struct pipe_ctx *pipe_ctx,
 459                 struct dc_state *context,
 460                 struct dc *dc)
 461 {
 462         struct dc_stream_state *stream = pipe_ctx->stream;
 463         enum dc_color_space color_space;
 464         struct tg_color black_color = {0};
 465
 466         /* by upper caller loop, pipe0 is parent pipe and be called first.
 467          * back end is set up by for pipe0. Other children pipe share back end
 468          * with pipe 0. No program is needed.
 469          */
 470         if (pipe_ctx->top_pipe != NULL)
 471                 return DC_OK;
 472
 473         /* TODO check if timing_changed, disable stream if timing changed */
 474
 475         /* HW program guide assume display already disable
 476          * by unplug sequence. OTG assume stop.
 477          */
 478         pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true);
 479
 480         if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
 481                         pipe_ctx->clock_source,
 482                         &pipe_ctx->stream_res.pix_clk_params,
 483                         &pipe_ctx->pll_settings)) {
 484                 BREAK_TO_DEBUGGER();
 485                 return DC_ERROR_UNEXPECTED;
 486         }
 487         pipe_ctx->stream_res.tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset;
 488         pipe_ctx->stream_res.tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start;
 489         pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset;
 490         pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_width = pipe_ctx->pipe_dlg_param.vupdate_width;
 491
 492         pipe_ctx->stream_res.tg->dlg_otg_param.signal =  pipe_ctx->stream->signal;
 493
 494         pipe_ctx->stream_res.tg->funcs->program_timing(
 495                         pipe_ctx->stream_res.tg,
 496                         &stream->timing,
 497                         true);
 498
 499 #if 0 /* move to after enable_crtc */
 500         /* TODO: OPP FMT, ABM. etc. should be done here. */
 501         /* or FPGA now. instance 0 only. TODO: move to opp.c */
 502
 503         inst_offset = reg_offsets[pipe_ctx->stream_res.tg->inst].fmt;
 504
 505         pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
 506                                 pipe_ctx->stream_res.opp,
 507                                 &stream->bit_depth_params,
 508                                 &stream->clamping);
 509 #endif
 510         /* program otg blank color */
 511         color_space = stream->output_color_space;
 512         color_space_to_black_color(dc, color_space, &black_color);
 513
 514         if (pipe_ctx->stream_res.tg->funcs->set_blank_color)
 515                 pipe_ctx->stream_res.tg->funcs->set_blank_color(
 516                                 pipe_ctx->stream_res.tg,
 517                                 &black_color);
 518
 519         if (pipe_ctx->stream_res.tg->funcs->is_blanked &&
 520                         !pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg)) {
 521                 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);
 522                 hwss_wait_for_blank_complete(pipe_ctx->stream_res.tg);
 523                 false_optc_underflow_wa(dc, pipe_ctx->stream, pipe_ctx->stream_res.tg);
 524         }
 525
 526         /* VTG is  within DCHUB command block. DCFCLK is always on */
 527         if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {
 528                 BREAK_TO_DEBUGGER();
 529                 return DC_ERROR_UNEXPECTED;
 530         }
 531
 532         /* TODO program crtc source select for non-virtual signal*/
 533         /* TODO program FMT */
 534         /* TODO setup link_enc */
 535         /* TODO set stream attributes */
 536         /* TODO program audio */
 537         /* TODO enable stream if timing changed */
 538         /* TODO unblank stream if DP */
 539
 540         return DC_OK;
 541 }
 542
 543 static void reset_back_end_for_pipe(
 544                 struct dc *dc,
 545                 struct pipe_ctx *pipe_ctx,
 546                 struct dc_state *context)
 547 {
 548         int i;
 549
 550         if (pipe_ctx->stream_res.stream_enc == NULL) {
 551                 pipe_ctx->stream = NULL;
 552                 return;
 553         }
 554
 555         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
 556                 /* DPMS may already disable */
 557                 if (!pipe_ctx->stream->dpms_off)
 558                         core_link_disable_stream(pipe_ctx, FREE_ACQUIRED_RESOURCE);
 559         }
 560
 561         /* by upper caller loop, parent pipe: pipe0, will be reset last.
 562          * back end share by all pipes and will be disable only when disable
 563          * parent pipe.
 564          */
 565         if (pipe_ctx->top_pipe == NULL) {
 566                 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
 567
 568                 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
 569         }
 570
 571         for (i = 0; i < dc->res_pool->pipe_count; i++)
 572                 if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx)
 573                         break;
 574
 575         if (i == dc->res_pool->pipe_count)
 576                 return;
 577
 578         pipe_ctx->stream = NULL;
 579         dm_logger_write(dc->ctx->logger, LOG_DEBUG,
 580                                         "Reset back end for pipe %d, tg:%d\n",
 581                                         pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
 582 }
 583
 584 static void dcn10_verify_allow_pstate_change_high(struct dc *dc)
 585 {
 586         static bool should_log_hw_state; /* prevent hw state log by default */
 587
 588         if (!hubbub1_verify_allow_pstate_change_high(dc->res_pool->hubbub)) {
 589                 if (should_log_hw_state) {
 590                         dcn10_log_hw_state(dc);
 591                 }
 592
 593                 BREAK_TO_DEBUGGER();
 594         }
 595 }
 596
 597 /* trigger HW to start disconnect plane from stream on the next vsync */
 598 static void plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx)
 599 {
 600         struct hubp *hubp = pipe_ctx->plane_res.hubp;
 601         int dpp_id = pipe_ctx->plane_res.dpp->inst;
 602         struct mpc *mpc = dc->res_pool->mpc;
 603         int opp_id;
 604         struct mpc_tree *mpc_tree_params;
 605         struct mpcc *mpcc_to_remove = NULL;
 606
 607         /* look at tree rather than mi here to know if we already reset */
 608         for (opp_id = 0; opp_id < dc->res_pool->pipe_count; opp_id++) {
 609                 struct output_pixel_processor *opp = dc->res_pool->opps[opp_id];
 610
 611                 mpc_tree_params = &(opp->mpc_tree_params);
 612                 mpcc_to_remove = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, dpp_id);
 613                 if (mpcc_to_remove != NULL)
 614                         break;
 615         }
 616
 617         /*Already reset*/
 618         if (opp_id == dc->res_pool->pipe_count)
 619                 return;
 620
 621         mpc->funcs->remove_mpcc(mpc, mpc_tree_params, mpcc_to_remove);
 622         dc->res_pool->opps[opp_id]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
 623
 624         dc->optimized_required = true;
 625
 626         if (hubp->funcs->hubp_disconnect)
 627                 hubp->funcs->hubp_disconnect(hubp);
 628
 629         if (dc->debug.sanity_checks)
 630                 dcn10_verify_allow_pstate_change_high(dc);
 631 }
 632
 633 static void plane_atomic_power_down(struct dc *dc, struct pipe_ctx *pipe_ctx)
 634 {
 635         struct dce_hwseq *hws = dc->hwseq;
 636         struct dpp *dpp = pipe_ctx->plane_res.dpp;
 637
 638         if (REG(DC_IP_REQUEST_CNTL)) {
 639                 REG_SET(DC_IP_REQUEST_CNTL, 0,
 640                                 IP_REQUEST_EN, 1);
 641                 dpp_pg_control(hws, dpp->inst, false);
 642                 hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, false);
 643                 dpp->funcs->dpp_reset(dpp);
 644                 REG_SET(DC_IP_REQUEST_CNTL, 0,
 645                                 IP_REQUEST_EN, 0);
 646                 dm_logger_write(dc->ctx->logger, LOG_DEBUG,
 647                                 "Power gated front end %d\n", pipe_ctx->pipe_idx);
 648         }
 649 }
 650
 651 /* disable HW used by plane.
 652  * note:  cannot disable until disconnect is complete
 653  */
 654 static void plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
 655 {
 656         struct dce_hwseq *hws = dc->hwseq;
 657         struct hubp *hubp = pipe_ctx->plane_res.hubp;
 658         int opp_id = hubp->opp_id;
 659         int dpp_id = pipe_ctx->plane_res.dpp->inst;
 660
 661         dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);
 662
 663         hubp->funcs->hubp_clk_cntl(hubp, false);
 664
 665         REG_UPDATE(DPP_CONTROL[dpp_id],
 666                         DPP_CLOCK_ENABLE, 0);
 667
 668         if (opp_id != 0xf && dc->res_pool->opps[opp_id]->mpc_tree_params.opp_list == NULL)
 669                 REG_UPDATE(OPP_PIPE_CONTROL[opp_id],
 670                                 OPP_PIPE_CLOCK_EN, 0);
 671
 672         hubp->power_gated = true;
 673         dc->optimized_required = false; /* We're powering off, no need to optimize */
 674
 675         plane_atomic_power_down(dc, pipe_ctx);
 676
 677         pipe_ctx->stream = NULL;
 678         memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res));
 679         memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res));
 680         pipe_ctx->top_pipe = NULL;
 681         pipe_ctx->bottom_pipe = NULL;
 682         pipe_ctx->plane_state = NULL;
 683 }
 684
 685 static void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
 686 {
 687         if (dc->res_pool->hubps[pipe_ctx->pipe_idx]->power_gated)
 688                 return;
 689
 690         plane_atomic_disable(dc, pipe_ctx);
 691
 692         apply_DEGVIDCN10_253_wa(dc);
 693
 694         dm_logger_write(dc->ctx->logger, LOG_DC,
 695                                         "Power down front end %d\n",
 696                                         pipe_ctx->pipe_idx);
 697 }
 698
 699 static void dcn10_init_hw(struct dc *dc)
 700 {
 701         int i;
 702         struct abm *abm = dc->res_pool->abm;
 703         struct dmcu *dmcu = dc->res_pool->dmcu;
 704         struct dce_hwseq *hws = dc->hwseq;
 705         struct dc_bios *dcb = dc->ctx->dc_bios;
 706         struct dc_state  *context = dc->current_state;
 707
 708         if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
 709                 REG_WRITE(REFCLK_CNTL, 0);
 710                 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
 711                 REG_WRITE(DIO_MEM_PWR_CTRL, 0);
 712
 713                 if (!dc->debug.disable_clock_gate) {
 714                         /* enable all DCN clock gating */
 715                         REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
 716
 717                         REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
 718
 719                         REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
 720                 }
 721
 722                 enable_power_gating_plane(dc->hwseq, true);
 723                 return;
 724         }
 725         /* end of FPGA. Below if real ASIC */
 726
 727         if (!dcb->funcs->is_accelerated_mode(dcb)) {
 728                 bios_golden_init(dc);
 729                 disable_vga(dc->hwseq);
 730         }
 731
 732         for (i = 0; i < dc->link_count; i++) {
 733                 /* Power up AND update implementation according to the
 734                  * required signal (which may be different from the
 735                  * default signal on connector).
 736                  */
 737                 struct dc_link *link = dc->links[i];
 738
 739                 if (link->link_enc->connector.id == CONNECTOR_ID_EDP)
 740                         dc->hwss.edp_power_control(link, true);
 741
 742                 link->link_enc->funcs->hw_init(link->link_enc);
 743         }
 744
 745         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 746                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
 747
 748                 if (tg->funcs->is_tg_enabled(tg))
 749                         tg->funcs->lock(tg);
 750         }
 751
 752         /* Blank controller using driver code instead of
 753          * command table.
 754          */
 755         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 756                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
 757
 758                 if (tg->funcs->is_tg_enabled(tg)) {
 759                         tg->funcs->set_blank(tg, true);
 760                         hwss_wait_for_blank_complete(tg);
 761                 }
 762         }
 763
 764         /* Reset all MPCC muxes */
 765         dc->res_pool->mpc->funcs->mpc_init(dc->res_pool->mpc);
 766
 767         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 768                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
 769                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
 770                 struct hubp *hubp = dc->res_pool->hubps[i];
 771                 struct dpp *dpp = dc->res_pool->dpps[i];
 772
 773                 pipe_ctx->stream_res.tg = tg;
 774                 pipe_ctx->pipe_idx = i;
 775
 776                 pipe_ctx->plane_res.hubp = hubp;
 777                 pipe_ctx->plane_res.dpp = dpp;
 778                 pipe_ctx->plane_res.mpcc_inst = dpp->inst;
 779                 hubp->mpcc_id = dpp->inst;
 780                 hubp->opp_id = 0xf;
 781                 hubp->power_gated = false;
 782
 783                 dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
 784                 dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
 785                 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
 786                 pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
 787
 788                 plane_atomic_disconnect(dc, pipe_ctx);
 789         }
 790
 791         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 792                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
 793
 794                 if (tg->funcs->is_tg_enabled(tg))
 795                         tg->funcs->unlock(tg);
 796         }
 797
 798         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 799                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
 800                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
 801
 802                 dcn10_disable_plane(dc, pipe_ctx);
 803
 804                 pipe_ctx->stream_res.tg = NULL;
 805                 pipe_ctx->plane_res.hubp = NULL;
 806
 807                 tg->funcs->tg_init(tg);
 808         }
 809
 810         for (i = 0; i < dc->res_pool->audio_count; i++) {
 811                 struct audio *audio = dc->res_pool->audios[i];
 812
 813                 audio->funcs->hw_init(audio);
 814         }
 815
 816         if (abm != NULL) {
 817                 abm->funcs->init_backlight(abm);
 818                 abm->funcs->abm_init(abm);
 819         }
 820
 821         if (dmcu != NULL)
 822                 dmcu->funcs->dmcu_init(dmcu);
 823
 824         /* power AFMT HDMI memory TODO: may move to dis/en output save power*/
 825         REG_WRITE(DIO_MEM_PWR_CTRL, 0);
 826
 827         if (!dc->debug.disable_clock_gate) {
 828                 /* enable all DCN clock gating */
 829                 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
 830
 831                 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
 832
 833                 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
 834         }
 835
 836         enable_power_gating_plane(dc->hwseq, true);
 837 }
 838
 839 static void reset_hw_ctx_wrap(
 840                 struct dc *dc,
 841                 struct dc_state *context)
 842 {
 843         int i;
 844
 845         /* Reset Back End*/
 846         for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
 847                 struct pipe_ctx *pipe_ctx_old =
 848                         &dc->current_state->res_ctx.pipe_ctx[i];
 849                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
 850
 851                 if (!pipe_ctx_old->stream)
 852                         continue;
 853
 854                 if (pipe_ctx_old->top_pipe)
 855                         continue;
 856
 857                 if (!pipe_ctx->stream ||
 858                                 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
 859                         struct clock_source *old_clk = pipe_ctx_old->clock_source;
 860
 861                         reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
 862                         if (old_clk)
 863                                 old_clk->funcs->cs_power_down(old_clk);
 864                 }
 865         }
 866
 867 }
 868
 869 static bool patch_address_for_sbs_tb_stereo(
 870                 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr)
 871 {
 872         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
 873         bool sec_split = pipe_ctx->top_pipe &&
 874                         pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
 875         if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
 876                 (pipe_ctx->stream->timing.timing_3d_format ==
 877                  TIMING_3D_FORMAT_SIDE_BY_SIDE ||
 878                  pipe_ctx->stream->timing.timing_3d_format ==
 879                  TIMING_3D_FORMAT_TOP_AND_BOTTOM)) {
 880                 *addr = plane_state->address.grph_stereo.left_addr;
 881                 plane_state->address.grph_stereo.left_addr =
 882                 plane_state->address.grph_stereo.right_addr;
 883                 return true;
 884         } else {
 885                 if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE &&
 886                         plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) {
 887                         plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO;
 888                         plane_state->address.grph_stereo.right_addr =
 889                         plane_state->address.grph_stereo.left_addr;
 890                 }
 891         }
 892         return false;
 893 }
 894
 895
 896
 897 static void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)
 898 {
 899         bool addr_patched = false;
 900         PHYSICAL_ADDRESS_LOC addr;
 901         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
 902
 903         if (plane_state == NULL)
 904                 return;
 905         addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);
 906         pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(
 907                         pipe_ctx->plane_res.hubp,
 908                         &plane_state->address,
 909                         plane_state->flip_immediate);
 910         plane_state->status.requested_address = plane_state->address;
 911         if (addr_patched)
 912                 pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;
 913 }
 914
 915 static bool dcn10_set_input_transfer_func(struct pipe_ctx *pipe_ctx,
 916                                           const struct dc_plane_state *plane_state)
 917 {
 918         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
 919         const struct dc_transfer_func *tf = NULL;
 920         bool result = true;
 921
 922         if (dpp_base == NULL)
 923                 return false;
 924
 925         if (plane_state->in_transfer_func)
 926                 tf = plane_state->in_transfer_func;
 927
 928         if (plane_state->gamma_correction && dce_use_lut(plane_state->format))
 929                 dpp_base->funcs->dpp_program_input_lut(dpp_base, plane_state->gamma_correction);
 930
 931         if (tf == NULL)
 932                 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
 933         else if (tf->type == TF_TYPE_PREDEFINED) {
 934                 switch (tf->tf) {
 935                 case TRANSFER_FUNCTION_SRGB:
 936                         dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_sRGB);
 937                         break;
 938                 case TRANSFER_FUNCTION_BT709:
 939                         dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_xvYCC);
 940                         break;
 941                 case TRANSFER_FUNCTION_LINEAR:
 942                         dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
 943                         break;
 944                 case TRANSFER_FUNCTION_PQ:
 945                 default:
 946                         result = false;
 947                         break;
 948                 }
 949         } else if (tf->type == TF_TYPE_BYPASS) {
 950                 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
 951         } else {
 952                 /*TF_TYPE_DISTRIBUTED_POINTS*/
 953                 result = false;
 954         }
 955
 956         return result;
 957 }
 958
 959
 960
 961
 962
 963 static bool
 964 dcn10_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
 965                                const struct dc_stream_state *stream)
 966 {
 967         struct dpp *dpp = pipe_ctx->plane_res.dpp;
 968
 969         if (dpp == NULL)
 970                 return false;
 971
 972         dpp->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
 973
 974         if (stream->out_transfer_func &&
 975             stream->out_transfer_func->type == TF_TYPE_PREDEFINED &&
 976             stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB)
 977                 dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_SRGB);
 978
 979         /* dcn10_translate_regamma_to_hw_format takes 750us, only do it when full
 980          * update.
 981          */
 982         else if (cm_helper_translate_curve_to_hw_format(
 983                         stream->out_transfer_func,
 984                         &dpp->regamma_params, false)) {
 985                 dpp->funcs->dpp_program_regamma_pwl(
 986                                 dpp,
 987                                 &dpp->regamma_params, OPP_REGAMMA_USER);
 988         } else
 989                 dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_BYPASS);
 990
 991         return true;
 992 }
 993
 994 static void dcn10_pipe_control_lock(
 995         struct dc *dc,
 996         struct pipe_ctx *pipe,
 997         bool lock)
 998 {
 999         struct hubp *hubp = NULL;
1000         hubp = dc->res_pool->hubps[pipe->pipe_idx];
1001         /* use TG master update lock to lock everything on the TG
1002          * therefore only top pipe need to lock
1003          */
1004         if (pipe->top_pipe)
1005                 return;
1006
1007         if (dc->debug.sanity_checks)
1008                 dcn10_verify_allow_pstate_change_high(dc);
1009
1010         if (lock)
1011                 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);
1012         else
1013                 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);
1014
1015         if (dc->debug.sanity_checks)
1016                 dcn10_verify_allow_pstate_change_high(dc);
1017 }
1018
1019 static bool wait_for_reset_trigger_to_occur(
1020         struct dc_context *dc_ctx,
1021         struct timing_generator *tg)
1022 {
1023         bool rc = false;
1024
1025         /* To avoid endless loop we wait at most
1026          * frames_to_wait_on_triggered_reset frames for the reset to occur. */
1027         const uint32_t frames_to_wait_on_triggered_reset = 10;
1028         int i;
1029
1030         for (i = 0; i < frames_to_wait_on_triggered_reset; i++) {
1031
1032                 if (!tg->funcs->is_counter_moving(tg)) {
1033                         DC_ERROR("TG counter is not moving!\n");
1034                         break;
1035                 }
1036
1037                 if (tg->funcs->did_triggered_reset_occur(tg)) {
1038                         rc = true;
1039                         /* usually occurs at i=1 */
1040                         DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",
1041                                         i);
1042                         break;
1043                 }
1044
1045                 /* Wait for one frame. */
1046                 tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);
1047                 tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
1048         }
1049
1050         if (false == rc)
1051                 DC_ERROR("GSL: Timeout on reset trigger!\n");
1052
1053         return rc;
1054 }
1055
1056 static void dcn10_enable_timing_synchronization(
1057         struct dc *dc,
1058         int group_index,
1059         int group_size,
1060         struct pipe_ctx *grouped_pipes[])
1061 {
1062         struct dc_context *dc_ctx = dc->ctx;
1063         int i;
1064
1065         DC_SYNC_INFO("Setting up OTG reset trigger\n");
1066
1067         for (i = 1; i < group_size; i++)
1068                 grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger(
1069                                 grouped_pipes[i]->stream_res.tg,
1070                                 grouped_pipes[0]->stream_res.tg->inst);
1071
1072         DC_SYNC_INFO("Waiting for trigger\n");
1073
1074         /* Need to get only check 1 pipe for having reset as all the others are
1075          * synchronized. Look at last pipe programmed to reset.
1076          */
1077
1078         wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[1]->stream_res.tg);
1079         for (i = 1; i < group_size; i++)
1080                 grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(
1081                                 grouped_pipes[i]->stream_res.tg);
1082
1083         DC_SYNC_INFO("Sync complete\n");
1084 }
1085
1086 static void dcn10_enable_per_frame_crtc_position_reset(
1087         struct dc *dc,
1088         int group_size,
1089         struct pipe_ctx *grouped_pipes[])
1090 {
1091         struct dc_context *dc_ctx = dc->ctx;
1092         int i;
1093
1094         DC_SYNC_INFO("Setting up\n");
1095         for (i = 0; i < group_size; i++)
1096                 grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset(
1097                                 grouped_pipes[i]->stream_res.tg,
1098                                 grouped_pipes[i]->stream->triggered_crtc_reset.event_source->status.primary_otg_inst,
1099                                 &grouped_pipes[i]->stream->triggered_crtc_reset);
1100
1101         DC_SYNC_INFO("Waiting for trigger\n");
1102
1103         for (i = 0; i < group_size; i++)
1104                 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
1105
1106         DC_SYNC_INFO("Multi-display sync is complete\n");
1107 }
1108
1109 /*static void print_rq_dlg_ttu(
1110                 struct dc *core_dc,
1111                 struct pipe_ctx *pipe_ctx)
1112 {
1113         dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
1114                         "\n============== DML TTU Output parameters [%d] ==============\n"
1115                         "qos_level_low_wm: %d, \n"
1116                         "qos_level_high_wm: %d, \n"
1117                         "min_ttu_vblank: %d, \n"
1118                         "qos_level_flip: %d, \n"
1119                         "refcyc_per_req_delivery_l: %d, \n"
1120                         "qos_level_fixed_l: %d, \n"
1121                         "qos_ramp_disable_l: %d, \n"
1122                         "refcyc_per_req_delivery_pre_l: %d, \n"
1123                         "refcyc_per_req_delivery_c: %d, \n"
1124                         "qos_level_fixed_c: %d, \n"
1125                         "qos_ramp_disable_c: %d, \n"
1126                         "refcyc_per_req_delivery_pre_c: %d\n"
1127                         "=============================================================\n",
1128                         pipe_ctx->pipe_idx,
1129                         pipe_ctx->ttu_regs.qos_level_low_wm,
1130                         pipe_ctx->ttu_regs.qos_level_high_wm,
1131                         pipe_ctx->ttu_regs.min_ttu_vblank,
1132                         pipe_ctx->ttu_regs.qos_level_flip,
1133                         pipe_ctx->ttu_regs.refcyc_per_req_delivery_l,
1134                         pipe_ctx->ttu_regs.qos_level_fixed_l,
1135                         pipe_ctx->ttu_regs.qos_ramp_disable_l,
1136                         pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_l,
1137                         pipe_ctx->ttu_regs.refcyc_per_req_delivery_c,
1138                         pipe_ctx->ttu_regs.qos_level_fixed_c,
1139                         pipe_ctx->ttu_regs.qos_ramp_disable_c,
1140                         pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_c
1141                         );
1142
1143         dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
1144                         "\n============== DML DLG Output parameters [%d] ==============\n"
1145                         "refcyc_h_blank_end: %d, \n"
1146                         "dlg_vblank_end: %d, \n"
1147                         "min_dst_y_next_start: %d, \n"
1148                         "refcyc_per_htotal: %d, \n"
1149                         "refcyc_x_after_scaler: %d, \n"
1150                         "dst_y_after_scaler: %d, \n"
1151                         "dst_y_prefetch: %d, \n"
1152                         "dst_y_per_vm_vblank: %d, \n"
1153                         "dst_y_per_row_vblank: %d, \n"
1154                         "ref_freq_to_pix_freq: %d, \n"
1155                         "vratio_prefetch: %d, \n"
1156                         "refcyc_per_pte_group_vblank_l: %d, \n"
1157                         "refcyc_per_meta_chunk_vblank_l: %d, \n"
1158                         "dst_y_per_pte_row_nom_l: %d, \n"
1159                         "refcyc_per_pte_group_nom_l: %d, \n",
1160                         pipe_ctx->pipe_idx,
1161                         pipe_ctx->dlg_regs.refcyc_h_blank_end,
1162                         pipe_ctx->dlg_regs.dlg_vblank_end,
1163                         pipe_ctx->dlg_regs.min_dst_y_next_start,
1164                         pipe_ctx->dlg_regs.refcyc_per_htotal,
1165                         pipe_ctx->dlg_regs.refcyc_x_after_scaler,
1166                         pipe_ctx->dlg_regs.dst_y_after_scaler,
1167                         pipe_ctx->dlg_regs.dst_y_prefetch,
1168                         pipe_ctx->dlg_regs.dst_y_per_vm_vblank,
1169                         pipe_ctx->dlg_regs.dst_y_per_row_vblank,
1170                         pipe_ctx->dlg_regs.ref_freq_to_pix_freq,
1171                         pipe_ctx->dlg_regs.vratio_prefetch,
1172                         pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_l,
1173                         pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_l,
1174                         pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_l,
1175                         pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_l
1176                         );
1177
1178         dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
1179                         "\ndst_y_per_meta_row_nom_l: %d, \n"
1180                         "refcyc_per_meta_chunk_nom_l: %d, \n"
1181                         "refcyc_per_line_delivery_pre_l: %d, \n"
1182                         "refcyc_per_line_delivery_l: %d, \n"
1183                         "vratio_prefetch_c: %d, \n"
1184                         "refcyc_per_pte_group_vblank_c: %d, \n"
1185                         "refcyc_per_meta_chunk_vblank_c: %d, \n"
1186                         "dst_y_per_pte_row_nom_c: %d, \n"
1187                         "refcyc_per_pte_group_nom_c: %d, \n"
1188                         "dst_y_per_meta_row_nom_c: %d, \n"
1189                         "refcyc_per_meta_chunk_nom_c: %d, \n"
1190                         "refcyc_per_line_delivery_pre_c: %d, \n"
1191                         "refcyc_per_line_delivery_c: %d \n"
1192                         "========================================================\n",
1193                         pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_l,
1194                         pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_l,
1195                         pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_l,
1196                         pipe_ctx->dlg_regs.refcyc_per_line_delivery_l,
1197                         pipe_ctx->dlg_regs.vratio_prefetch_c,
1198                         pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_c,
1199                         pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_c,
1200                         pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_c,
1201                         pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_c,
1202                         pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_c,
1203                         pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_c,
1204                         pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_c,
1205                         pipe_ctx->dlg_regs.refcyc_per_line_delivery_c
1206                         );
1207
1208         dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
1209                         "\n============== DML RQ Output parameters [%d] ==============\n"
1210                         "chunk_size: %d \n"
1211                         "min_chunk_size: %d \n"
1212                         "meta_chunk_size: %d \n"
1213                         "min_meta_chunk_size: %d \n"
1214                         "dpte_group_size: %d \n"
1215                         "mpte_group_size: %d \n"
1216                         "swath_height: %d \n"
1217                         "pte_row_height_linear: %d \n"
1218                         "========================================================\n",
1219                         pipe_ctx->pipe_idx,
1220                         pipe_ctx->rq_regs.rq_regs_l.chunk_size,
1221                         pipe_ctx->rq_regs.rq_regs_l.min_chunk_size,
1222                         pipe_ctx->rq_regs.rq_regs_l.meta_chunk_size,
1223                         pipe_ctx->rq_regs.rq_regs_l.min_meta_chunk_size,
1224                         pipe_ctx->rq_regs.rq_regs_l.dpte_group_size,
1225                         pipe_ctx->rq_regs.rq_regs_l.mpte_group_size,
1226                         pipe_ctx->rq_regs.rq_regs_l.swath_height,
1227                         pipe_ctx->rq_regs.rq_regs_l.pte_row_height_linear
1228                         );
1229 }
1230 */
1231
1232 static void mmhub_read_vm_system_aperture_settings(struct dcn10_hubp *hubp1,
1233                 struct vm_system_aperture_param *apt,
1234                 struct dce_hwseq *hws)
1235 {
1236         PHYSICAL_ADDRESS_LOC physical_page_number;
1237         uint32_t logical_addr_low;
1238         uint32_t logical_addr_high;
1239
1240         REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
1241                         PHYSICAL_PAGE_NUMBER_MSB, &physical_page_number.high_part);
1242         REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
1243                         PHYSICAL_PAGE_NUMBER_LSB, &physical_page_number.low_part);
1244
1245         REG_GET(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1246                         LOGICAL_ADDR, &logical_addr_low);
1247
1248         REG_GET(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1249                         LOGICAL_ADDR, &logical_addr_high);
1250
1251         apt->sys_default.quad_part =  physical_page_number.quad_part << 12;
1252         apt->sys_low.quad_part =  (int64_t)logical_addr_low << 18;
1253         apt->sys_high.quad_part =  (int64_t)logical_addr_high << 18;
1254 }
1255
1256 /* Temporary read settings, future will get values from kmd directly */
1257 static void mmhub_read_vm_context0_settings(struct dcn10_hubp *hubp1,
1258                 struct vm_context0_param *vm0,
1259                 struct dce_hwseq *hws)
1260 {
1261         PHYSICAL_ADDRESS_LOC fb_base;
1262         PHYSICAL_ADDRESS_LOC fb_offset;
1263         uint32_t fb_base_value;
1264         uint32_t fb_offset_value;
1265
1266         REG_GET(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, &fb_base_value);
1267         REG_GET(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, &fb_offset_value);
1268
1269         REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
1270                         PAGE_DIRECTORY_ENTRY_HI32, &vm0->pte_base.high_part);
1271         REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
1272                         PAGE_DIRECTORY_ENTRY_LO32, &vm0->pte_base.low_part);
1273
1274         REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
1275                         LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_start.high_part);
1276         REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
1277                         LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_start.low_part);
1278
1279         REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
1280                         LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_end.high_part);
1281         REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
1282                         LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_end.low_part);
1283
1284         REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
1285                         PHYSICAL_PAGE_ADDR_HI4, &vm0->fault_default.high_part);
1286         REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
1287                         PHYSICAL_PAGE_ADDR_LO32, &vm0->fault_default.low_part);
1288
1289         /*
1290          * The values in VM_CONTEXT0_PAGE_TABLE_BASE_ADDR is in UMA space.
1291          * Therefore we need to do
1292          * DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
1293          * - DCHUBBUB_SDPIF_FB_OFFSET + DCHUBBUB_SDPIF_FB_BASE
1294          */
1295         fb_base.quad_part = (uint64_t)fb_base_value << 24;
1296         fb_offset.quad_part = (uint64_t)fb_offset_value << 24;
1297         vm0->pte_base.quad_part += fb_base.quad_part;
1298         vm0->pte_base.quad_part -= fb_offset.quad_part;
1299 }
1300
1301
1302 static void dcn10_program_pte_vm(struct dce_hwseq *hws, struct hubp *hubp)
1303 {
1304         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
1305         struct vm_system_aperture_param apt = { {{ 0 } } };
1306         struct vm_context0_param vm0 = { { { 0 } } };
1307
1308         mmhub_read_vm_system_aperture_settings(hubp1, &apt, hws);
1309         mmhub_read_vm_context0_settings(hubp1, &vm0, hws);
1310
1311         hubp->funcs->hubp_set_vm_system_aperture_settings(hubp, &apt);
1312         hubp->funcs->hubp_set_vm_context0_settings(hubp, &vm0);
1313 }
1314
1315 static void dcn10_enable_plane(
1316         struct dc *dc,
1317         struct pipe_ctx *pipe_ctx,
1318         struct dc_state *context)
1319 {
1320         struct dce_hwseq *hws = dc->hwseq;
1321
1322         if (dc->debug.sanity_checks) {
1323                 dcn10_verify_allow_pstate_change_high(dc);
1324         }
1325
1326         undo_DEGVIDCN10_253_wa(dc);
1327
1328         power_on_plane(dc->hwseq,
1329                 pipe_ctx->plane_res.hubp->inst);
1330
1331         /* enable DCFCLK current DCHUB */
1332         pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);
1333
1334         /* make sure OPP_PIPE_CLOCK_EN = 1 */
1335         REG_UPDATE(OPP_PIPE_CONTROL[pipe_ctx->stream_res.tg->inst],
1336                         OPP_PIPE_CLOCK_EN, 1);
1337
1338 /* TODO: enable/disable in dm as per update type.
1339         if (plane_state) {
1340                 dm_logger_write(dc->ctx->logger, LOG_DC,
1341                                 "Pipe:%d 0x%x: addr hi:0x%x, "
1342                                 "addr low:0x%x, "
1343                                 "src: %d, %d, %d,"
1344                                 " %d; dst: %d, %d, %d, %d;\n",
1345                                 pipe_ctx->pipe_idx,
1346                                 plane_state,
1347                                 plane_state->address.grph.addr.high_part,
1348                                 plane_state->address.grph.addr.low_part,
1349                                 plane_state->src_rect.x,
1350                                 plane_state->src_rect.y,
1351                                 plane_state->src_rect.width,
1352                                 plane_state->src_rect.height,
1353                                 plane_state->dst_rect.x,
1354                                 plane_state->dst_rect.y,
1355                                 plane_state->dst_rect.width,
1356                                 plane_state->dst_rect.height);
1357
1358                 dm_logger_write(dc->ctx->logger, LOG_DC,
1359                                 "Pipe %d: width, height, x, y         format:%d\n"
1360                                 "viewport:%d, %d, %d, %d\n"
1361                                 "recout:  %d, %d, %d, %d\n",
1362                                 pipe_ctx->pipe_idx,
1363                                 plane_state->format,
1364                                 pipe_ctx->plane_res.scl_data.viewport.width,
1365                                 pipe_ctx->plane_res.scl_data.viewport.height,
1366                                 pipe_ctx->plane_res.scl_data.viewport.x,
1367                                 pipe_ctx->plane_res.scl_data.viewport.y,
1368                                 pipe_ctx->plane_res.scl_data.recout.width,
1369                                 pipe_ctx->plane_res.scl_data.recout.height,
1370                                 pipe_ctx->plane_res.scl_data.recout.x,
1371                                 pipe_ctx->plane_res.scl_data.recout.y);
1372                 print_rq_dlg_ttu(dc, pipe_ctx);
1373         }
1374 */
1375         if (dc->config.gpu_vm_support)
1376                 dcn10_program_pte_vm(hws, pipe_ctx->plane_res.hubp);
1377
1378         if (dc->debug.sanity_checks) {
1379                 dcn10_verify_allow_pstate_change_high(dc);
1380         }
1381 }
1382
1383 static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
1384 {
1385         int i = 0;
1386         struct dpp_grph_csc_adjustment adjust;
1387         memset(&adjust, 0, sizeof(adjust));
1388         adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
1389
1390
1391         if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
1392                 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
1393                 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
1394                         adjust.temperature_matrix[i] =
1395                                 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
1396         }
1397
1398         pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp, &adjust);
1399 }
1400
1401
1402 static void program_csc_matrix(struct pipe_ctx *pipe_ctx,
1403                 enum dc_color_space colorspace,
1404                 uint16_t *matrix)
1405 {
1406         if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
1407                         if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment != NULL)
1408                                 pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, matrix);
1409         } else {
1410                 if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default != NULL)
1411                         pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default(pipe_ctx->plane_res.dpp, colorspace);
1412         }
1413 }
1414
1415 static void program_output_csc(struct dc *dc,
1416                 struct pipe_ctx *pipe_ctx,
1417                 enum dc_color_space colorspace,
1418                 uint16_t *matrix,
1419                 int opp_id)
1420 {
1421         if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment != NULL)
1422                 program_csc_matrix(pipe_ctx,
1423                                 colorspace,
1424                                 matrix);
1425 }
1426
1427 static bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
1428 {
1429         if (pipe_ctx->plane_state->visible)
1430                 return true;
1431         if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
1432                 return true;
1433         return false;
1434 }
1435
1436 static bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
1437 {
1438         if (pipe_ctx->plane_state->visible)
1439                 return true;
1440         if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
1441                 return true;
1442         return false;
1443 }
1444
1445 static bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
1446 {
1447         if (pipe_ctx->plane_state->visible)
1448                 return true;
1449         if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
1450                 return true;
1451         if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
1452                 return true;
1453         return false;
1454 }
1455
1456 static bool is_rgb_cspace(enum dc_color_space output_color_space)
1457 {
1458         switch (output_color_space) {
1459         case COLOR_SPACE_SRGB:
1460         case COLOR_SPACE_SRGB_LIMITED:
1461         case COLOR_SPACE_2020_RGB_FULLRANGE:
1462         case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
1463         case COLOR_SPACE_ADOBERGB:
1464                 return true;
1465         case COLOR_SPACE_YCBCR601:
1466         case COLOR_SPACE_YCBCR709:
1467         case COLOR_SPACE_YCBCR601_LIMITED:
1468         case COLOR_SPACE_YCBCR709_LIMITED:
1469         case COLOR_SPACE_2020_YCBCR:
1470                 return false;
1471         default:
1472                 /* Add a case to switch */
1473                 BREAK_TO_DEBUGGER();
1474                 return false;
1475         }
1476 }
1477
1478 static void dcn10_get_surface_visual_confirm_color(
1479                 const struct pipe_ctx *pipe_ctx,
1480                 struct tg_color *color)
1481 {
1482         uint32_t color_value = MAX_TG_COLOR_VALUE;
1483
1484         switch (pipe_ctx->plane_res.scl_data.format) {
1485         case PIXEL_FORMAT_ARGB8888:
1486                 /* set boarder color to red */
1487                 color->color_r_cr = color_value;
1488                 break;
1489
1490         case PIXEL_FORMAT_ARGB2101010:
1491                 /* set boarder color to blue */
1492                 color->color_b_cb = color_value;
1493                 break;
1494         case PIXEL_FORMAT_420BPP8:
1495                 /* set boarder color to green */
1496                 color->color_g_y = color_value;
1497                 break;
1498         case PIXEL_FORMAT_420BPP10:
1499                 /* set boarder color to yellow */
1500                 color->color_g_y = color_value;
1501                 color->color_r_cr = color_value;
1502                 break;
1503         case PIXEL_FORMAT_FP16:
1504                 /* set boarder color to white */
1505                 color->color_r_cr = color_value;
1506                 color->color_b_cb = color_value;
1507                 color->color_g_y = color_value;
1508                 break;
1509         default:
1510                 break;
1511         }
1512 }
1513
1514 static uint16_t fixed_point_to_int_frac(
1515         struct fixed31_32 arg,
1516         uint8_t integer_bits,
1517         uint8_t fractional_bits)
1518 {
1519         int32_t numerator;
1520         int32_t divisor = 1 << fractional_bits;
1521
1522         uint16_t result;
1523
1524         uint16_t d = (uint16_t)dal_fixed31_32_floor(
1525                 dal_fixed31_32_abs(
1526                         arg));
1527
1528         if (d <= (uint16_t)(1 << integer_bits) - (1 / (uint16_t)divisor))
1529                 numerator = (uint16_t)dal_fixed31_32_floor(
1530                         dal_fixed31_32_mul_int(
1531                                 arg,
1532                                 divisor));
1533         else {
1534                 numerator = dal_fixed31_32_floor(
1535                         dal_fixed31_32_sub(
1536                                 dal_fixed31_32_from_int(
1537                                         1LL << integer_bits),
1538                                 dal_fixed31_32_recip(
1539                                         dal_fixed31_32_from_int(
1540                                                 divisor))));
1541         }
1542
1543         if (numerator >= 0)
1544                 result = (uint16_t)numerator;
1545         else
1546                 result = (uint16_t)(
1547                 (1 << (integer_bits + fractional_bits + 1)) + numerator);
1548
1549         if ((result != 0) && dal_fixed31_32_lt(
1550                 arg, dal_fixed31_32_zero))
1551                 result |= 1 << (integer_bits + fractional_bits);
1552
1553         return result;
1554 }
1555
1556 void build_prescale_params(struct  dc_bias_and_scale *bias_and_scale,
1557                 const struct dc_plane_state *plane_state)
1558 {
1559         if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
1560                         && plane_state->format != SURFACE_PIXEL_FORMAT_INVALID
1561                         && plane_state->input_csc_color_matrix.enable_adjustment
1562                         && plane_state->coeff_reduction_factor.value != 0) {
1563                 bias_and_scale->scale_blue = fixed_point_to_int_frac(
1564                         dal_fixed31_32_mul(plane_state->coeff_reduction_factor,
1565                                         dal_fixed31_32_from_fraction(256, 255)),
1566                                 2,
1567                                 13);
1568                 bias_and_scale->scale_red = bias_and_scale->scale_blue;
1569                 bias_and_scale->scale_green = bias_and_scale->scale_blue;
1570         } else {
1571                 bias_and_scale->scale_blue = 0x2000;
1572                 bias_and_scale->scale_red = 0x2000;
1573                 bias_and_scale->scale_green = 0x2000;
1574         }
1575 }
1576
1577 static void update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state)
1578 {
1579         struct dc_bias_and_scale bns_params = {0};
1580
1581         // program the input csc
1582         dpp->funcs->dpp_setup(dpp,
1583                         plane_state->format,
1584                         EXPANSION_MODE_ZERO,
1585                         plane_state->input_csc_color_matrix,
1586                         COLOR_SPACE_YCBCR601_LIMITED);
1587
1588         //set scale and bias registers
1589         build_prescale_params(&bns_params, plane_state);
1590         if (dpp->funcs->dpp_program_bias_and_scale)
1591                 dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
1592 }
1593
1594 static void update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
1595 {
1596         struct hubp *hubp = pipe_ctx->plane_res.hubp;
1597         struct mpcc_blnd_cfg blnd_cfg;
1598         bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
1599         int mpcc_id;
1600         struct mpcc *new_mpcc;
1601         struct mpc *mpc = dc->res_pool->mpc;
1602         struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);
1603
1604         /* TODO: proper fix once fpga works */
1605
1606         if (dc->debug.surface_visual_confirm)
1607                 dcn10_get_surface_visual_confirm_color(
1608                                 pipe_ctx, &blnd_cfg.black_color);
1609         else
1610                 color_space_to_black_color(
1611                         dc, pipe_ctx->stream->output_color_space,
1612                         &blnd_cfg.black_color);
1613
1614         if (per_pixel_alpha)
1615                 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;
1616         else
1617                 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA;
1618
1619         blnd_cfg.overlap_only = false;
1620         blnd_cfg.global_alpha = 0xff;
1621         blnd_cfg.global_gain = 0xff;
1622
1623         /* DCN1.0 has output CM before MPC which seems to screw with
1624          * pre-multiplied alpha.
1625          */
1626         blnd_cfg.pre_multiplied_alpha = is_rgb_cspace(
1627                         pipe_ctx->stream->output_color_space)
1628                                         && per_pixel_alpha;
1629
1630         /*
1631          * TODO: remove hack
1632          * Note: currently there is a bug in init_hw such that
1633          * on resume from hibernate, BIOS sets up MPCC0, and
1634          * we do mpcc_remove but the mpcc cannot go to idle
1635          * after remove. This cause us to pick mpcc1 here,
1636          * which causes a pstate hang for yet unknown reason.
1637          */
1638         mpcc_id = hubp->inst;
1639
1640         /* check if this MPCC is already being used */
1641         new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id);
1642         /* remove MPCC if being used */
1643         if (new_mpcc != NULL)
1644                 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc);
1645         else
1646                 if (dc->debug.sanity_checks)
1647                         mpc->funcs->assert_mpcc_idle_before_connect(
1648                                         dc->res_pool->mpc, mpcc_id);
1649
1650         /* Call MPC to insert new plane */
1651         new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,
1652                         mpc_tree_params,
1653                         &blnd_cfg,
1654                         NULL,
1655                         NULL,
1656                         hubp->inst,
1657                         mpcc_id);
1658
1659         ASSERT(new_mpcc != NULL);
1660
1661         hubp->opp_id = pipe_ctx->stream_res.opp->inst;
1662         hubp->mpcc_id = mpcc_id;
1663 }
1664
1665 static void update_scaler(struct pipe_ctx *pipe_ctx)
1666 {
1667         bool per_pixel_alpha =
1668                         pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
1669
1670         /* TODO: proper fix once fpga works */
1671
1672         pipe_ctx->plane_res.scl_data.lb_params.alpha_en = per_pixel_alpha;
1673         pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
1674         /* scaler configuration */
1675         pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(
1676                         pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);
1677 }
1678
1679 static void update_dchubp_dpp(
1680         struct dc *dc,
1681         struct pipe_ctx *pipe_ctx,
1682         struct dc_state *context)
1683 {
1684         struct hubp *hubp = pipe_ctx->plane_res.hubp;
1685         struct dpp *dpp = pipe_ctx->plane_res.dpp;
1686         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1687         union plane_size size = plane_state->plane_size;
1688
1689         /* depends on DML calculation, DPP clock value may change dynamically */
1690         if (plane_state->update_flags.bits.full_update) {
1691                 enable_dppclk(
1692                         dc->hwseq,
1693                         pipe_ctx->plane_res.dpp->inst,
1694                         pipe_ctx->stream_res.pix_clk_params.requested_pix_clk,
1695                         context->bw.dcn.calc_clk.dppclk_div);
1696                 dc->current_state->bw.dcn.cur_clk.dppclk_div =
1697                                 context->bw.dcn.calc_clk.dppclk_div;
1698                 context->bw.dcn.cur_clk.dppclk_div = context->bw.dcn.calc_clk.dppclk_div;
1699         }
1700
1701         /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG
1702          * VTG is within DCHUBBUB which is commond block share by each pipe HUBP.
1703          * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG
1704          */
1705         if (plane_state->update_flags.bits.full_update) {
1706                 hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst);
1707
1708                 hubp->funcs->hubp_setup(
1709                         hubp,
1710                         &pipe_ctx->dlg_regs,
1711                         &pipe_ctx->ttu_regs,
1712                         &pipe_ctx->rq_regs,
1713                         &pipe_ctx->pipe_dlg_param);
1714         }
1715
1716         size.grph.surface_size = pipe_ctx->plane_res.scl_data.viewport;
1717
1718         if (plane_state->update_flags.bits.full_update ||
1719                 plane_state->update_flags.bits.bpp_change)
1720                 update_dpp(dpp, plane_state);
1721
1722         if (plane_state->update_flags.bits.full_update ||
1723                 plane_state->update_flags.bits.per_pixel_alpha_change)
1724                 update_mpcc(dc, pipe_ctx);
1725
1726         if (plane_state->update_flags.bits.full_update ||
1727                 plane_state->update_flags.bits.per_pixel_alpha_change ||
1728                 plane_state->update_flags.bits.scaling_change ||
1729                 plane_state->update_flags.bits.position_change) {
1730                 update_scaler(pipe_ctx);
1731         }
1732
1733         if (plane_state->update_flags.bits.full_update ||
1734                 plane_state->update_flags.bits.scaling_change ||
1735                 plane_state->update_flags.bits.position_change) {
1736                 hubp->funcs->mem_program_viewport(
1737                         hubp,
1738                         &pipe_ctx->plane_res.scl_data.viewport,
1739                         &pipe_ctx->plane_res.scl_data.viewport_c);
1740         }
1741
1742         if (plane_state->update_flags.bits.full_update) {
1743                 /*gamut remap*/
1744                 program_gamut_remap(pipe_ctx);
1745
1746                 program_output_csc(dc,
1747                                 pipe_ctx,
1748                                 pipe_ctx->stream->output_color_space,
1749                                 pipe_ctx->stream->csc_color_matrix.matrix,
1750                                 hubp->opp_id);
1751         }
1752
1753         if (plane_state->update_flags.bits.full_update ||
1754                 plane_state->update_flags.bits.horizontal_mirror_change ||
1755                 plane_state->update_flags.bits.rotation_change ||
1756                 plane_state->update_flags.bits.swizzle_change ||
1757                 plane_state->update_flags.bits.dcc_change ||
1758                 plane_state->update_flags.bits.bpp_change ||
1759                 plane_state->update_flags.bits.scaling_change) {
1760                 hubp->funcs->hubp_program_surface_config(
1761                         hubp,
1762                         plane_state->format,
1763                         &plane_state->tiling_info,
1764                         &size,
1765                         plane_state->rotation,
1766                         &plane_state->dcc,
1767                         plane_state->horizontal_mirror);
1768         }
1769
1770         hubp->power_gated = false;
1771
1772         dc->hwss.update_plane_addr(dc, pipe_ctx);
1773
1774         if (is_pipe_tree_visible(pipe_ctx))
1775                 hubp->funcs->set_blank(hubp, false);
1776 }
1777
1778
1779 static void program_all_pipe_in_tree(
1780                 struct dc *dc,
1781                 struct pipe_ctx *pipe_ctx,
1782                 struct dc_state *context)
1783 {
1784
1785         if (pipe_ctx->top_pipe == NULL) {
1786
1787                 pipe_ctx->stream_res.tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset;
1788                 pipe_ctx->stream_res.tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start;
1789                 pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset;
1790                 pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_width = pipe_ctx->pipe_dlg_param.vupdate_width;
1791                 pipe_ctx->stream_res.tg->dlg_otg_param.signal =  pipe_ctx->stream->signal;
1792
1793                 pipe_ctx->stream_res.tg->funcs->program_global_sync(
1794                                 pipe_ctx->stream_res.tg);
1795
1796                 if (pipe_ctx->stream_res.tg->funcs->set_blank)
1797                         pipe_ctx->stream_res.tg->funcs->set_blank(
1798                                         pipe_ctx->stream_res.tg,
1799                                         !is_pipe_tree_visible(pipe_ctx));
1800         }
1801
1802         if (pipe_ctx->plane_state != NULL) {
1803                 if (pipe_ctx->plane_state->update_flags.bits.full_update)
1804                         dcn10_enable_plane(dc, pipe_ctx, context);
1805
1806                 update_dchubp_dpp(dc, pipe_ctx, context);
1807
1808                 if (pipe_ctx->plane_state->update_flags.bits.full_update ||
1809                                 pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
1810                                 pipe_ctx->plane_state->update_flags.bits.gamma_change)
1811                         dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state);
1812
1813                 /* dcn10_translate_regamma_to_hw_format takes 750us to finish
1814                  * only do gamma programming for full update.
1815                  * TODO: This can be further optimized/cleaned up
1816                  * Always call this for now since it does memcmp inside before
1817                  * doing heavy calculation and programming
1818                  */
1819                 if (pipe_ctx->plane_state->update_flags.bits.full_update)
1820                         dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);
1821         }
1822
1823         if (pipe_ctx->bottom_pipe != NULL && pipe_ctx->bottom_pipe != pipe_ctx)
1824                 program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context);
1825 }
1826
1827 static void dcn10_pplib_apply_display_requirements(
1828         struct dc *dc,
1829         struct dc_state *context)
1830 {
1831         struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
1832
1833         pp_display_cfg->all_displays_in_sync = false;/*todo*/
1834         pp_display_cfg->nb_pstate_switch_disable = false;
1835         pp_display_cfg->min_engine_clock_khz = context->bw.dcn.cur_clk.dcfclk_khz;
1836         pp_display_cfg->min_memory_clock_khz = context->bw.dcn.cur_clk.fclk_khz;
1837         pp_display_cfg->min_engine_clock_deep_sleep_khz = context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz;
1838         pp_display_cfg->min_dcfc_deep_sleep_clock_khz = context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz;
1839         pp_display_cfg->avail_mclk_switch_time_us =
1840                         context->bw.dcn.cur_clk.dram_ccm_us > 0 ? context->bw.dcn.cur_clk.dram_ccm_us : 0;
1841         pp_display_cfg->avail_mclk_switch_time_in_disp_active_us =
1842                         context->bw.dcn.cur_clk.min_active_dram_ccm_us > 0 ? context->bw.dcn.cur_clk.min_active_dram_ccm_us : 0;
1843         pp_display_cfg->min_dcfclock_khz = context->bw.dcn.cur_clk.dcfclk_khz;
1844         pp_display_cfg->disp_clk_khz = context->bw.dcn.cur_clk.dispclk_khz;
1845         dce110_fill_display_configs(context, pp_display_cfg);
1846
1847         if (memcmp(&dc->prev_display_config, pp_display_cfg, sizeof(
1848                         struct dm_pp_display_configuration)) !=  0)
1849                 dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
1850
1851         dc->prev_display_config = *pp_display_cfg;
1852 }
1853
1854 static void optimize_shared_resources(struct dc *dc)
1855 {
1856         if (dc->current_state->stream_count == 0) {
1857                 /* S0i2 message */
1858                 dcn10_pplib_apply_display_requirements(dc, dc->current_state);
1859         }
1860
1861         if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE)
1862                 dcn_bw_notify_pplib_of_wm_ranges(dc);
1863 }
1864
1865 static void ready_shared_resources(struct dc *dc, struct dc_state *context)
1866 {
1867         /* S0i2 message */
1868         if (dc->current_state->stream_count == 0 &&
1869                         context->stream_count != 0)
1870                 dcn10_pplib_apply_display_requirements(dc, context);
1871 }
1872
1873 static struct pipe_ctx *find_top_pipe_for_stream(
1874                 struct dc *dc,
1875                 struct dc_state *context,
1876                 const struct dc_stream_state *stream)
1877 {
1878         int i;
1879
1880         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1881                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1882                 struct pipe_ctx *old_pipe_ctx =
1883                                 &dc->current_state->res_ctx.pipe_ctx[i];
1884
1885                 if (!pipe_ctx->plane_state && !old_pipe_ctx->plane_state)
1886                         continue;
1887
1888                 if (pipe_ctx->stream != stream)
1889                         continue;
1890
1891                 if (!pipe_ctx->top_pipe)
1892                         return pipe_ctx;
1893         }
1894         return NULL;
1895 }
1896
1897 static void dcn10_apply_ctx_for_surface(
1898                 struct dc *dc,
1899                 const struct dc_stream_state *stream,
1900                 int num_planes,
1901                 struct dc_state *context)
1902 {
1903         int i;
1904         struct timing_generator *tg;
1905         struct output_pixel_processor *opp;
1906         bool removed_pipe[4] = { false };
1907         unsigned int ref_clk_mhz = dc->res_pool->ref_clock_inKhz/1000;
1908         bool program_water_mark = false;
1909
1910         struct pipe_ctx *top_pipe_to_program =
1911                         find_top_pipe_for_stream(dc, context, stream);
1912
1913         if (!top_pipe_to_program)
1914                 return;
1915
1916         opp = top_pipe_to_program->stream_res.opp;
1917
1918         tg = top_pipe_to_program->stream_res.tg;
1919
1920         dcn10_pipe_control_lock(dc, top_pipe_to_program, true);
1921
1922         if (num_planes == 0) {
1923
1924                 /* OTG blank before remove all front end */
1925                 if (tg->funcs->set_blank)
1926                         tg->funcs->set_blank(tg, true);
1927         }
1928
1929         /* Disconnect unused mpcc */
1930         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1931                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1932                 struct pipe_ctx *old_pipe_ctx =
1933                                 &dc->current_state->res_ctx.pipe_ctx[i];
1934                 /*
1935                  * Powergate reused pipes that are not powergated
1936                  * fairly hacky right now, using opp_id as indicator
1937                  * TODO: After move dc_post to dc_update, this will
1938                  * be removed.
1939                  */
1940                 if (pipe_ctx->plane_state && !old_pipe_ctx->plane_state) {
1941                         if (old_pipe_ctx->stream_res.tg == tg &&
1942                                 old_pipe_ctx->plane_res.hubp &&
1943                                 old_pipe_ctx->plane_res.hubp->opp_id != 0xf) {
1944                                 dcn10_disable_plane(dc, pipe_ctx);
1945                                 /*
1946                                  * power down fe will unlock when calling reset, need
1947                                  * to lock it back here. Messy, need rework.
1948                                  */
1949                                 pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg);
1950                         }
1951                 }
1952
1953                 if (!pipe_ctx->plane_state &&
1954                         old_pipe_ctx->plane_state &&
1955                         old_pipe_ctx->stream_res.tg == tg) {
1956
1957                         plane_atomic_disconnect(dc, old_pipe_ctx);
1958                         removed_pipe[i] = true;
1959
1960                         dm_logger_write(dc->ctx->logger, LOG_DC,
1961                                         "Reset mpcc for pipe %d\n",
1962                                         old_pipe_ctx->pipe_idx);
1963                 }
1964         }
1965
1966         if (num_planes > 0)
1967                 program_all_pipe_in_tree(dc, top_pipe_to_program, context);
1968
1969         dcn10_pipe_control_lock(dc, top_pipe_to_program, false);
1970
1971         if (num_planes == 0)
1972                 false_optc_underflow_wa(dc, stream, tg);
1973
1974         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1975                 struct pipe_ctx *old_pipe_ctx =
1976                                 &dc->current_state->res_ctx.pipe_ctx[i];
1977                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1978
1979                 if (pipe_ctx->stream == stream &&
1980                                 pipe_ctx->plane_state &&
1981                         pipe_ctx->plane_state->update_flags.bits.full_update)
1982                         program_water_mark = true;
1983
1984                 if (removed_pipe[i])
1985                         dcn10_disable_plane(dc, old_pipe_ctx);
1986         }
1987
1988         if (program_water_mark) {
1989                 if (dc->debug.sanity_checks) {
1990                         /* pstate stuck check after watermark update */
1991                         dcn10_verify_allow_pstate_change_high(dc);
1992                 }
1993
1994                 /* watermark is for all pipes */
1995                 hubbub1_program_watermarks(dc->res_pool->hubbub,
1996                                 &context->bw.dcn.watermarks, ref_clk_mhz);
1997
1998                 if (dc->debug.sanity_checks) {
1999                         /* pstate stuck check after watermark update */
2000                         dcn10_verify_allow_pstate_change_high(dc);
2001                 }
2002         }
2003 /*      dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS,
2004                         "\n============== Watermark parameters ==============\n"
2005                         "a.urgent_ns: %d \n"
2006                         "a.cstate_enter_plus_exit: %d \n"
2007                         "a.cstate_exit: %d \n"
2008                         "a.pstate_change: %d \n"
2009                         "a.pte_meta_urgent: %d \n"
2010                         "b.urgent_ns: %d \n"
2011                         "b.cstate_enter_plus_exit: %d \n"
2012                         "b.cstate_exit: %d \n"
2013                         "b.pstate_change: %d \n"
2014                         "b.pte_meta_urgent: %d \n",
2015                         context->bw.dcn.watermarks.a.urgent_ns,
2016                         context->bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns,
2017                         context->bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns,
2018                         context->bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns,
2019                         context->bw.dcn.watermarks.a.pte_meta_urgent_ns,
2020                         context->bw.dcn.watermarks.b.urgent_ns,
2021                         context->bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns,
2022                         context->bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns,
2023                         context->bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns,
2024                         context->bw.dcn.watermarks.b.pte_meta_urgent_ns
2025                         );
2026         dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS,
2027                         "\nc.urgent_ns: %d \n"
2028                         "c.cstate_enter_plus_exit: %d \n"
2029                         "c.cstate_exit: %d \n"
2030                         "c.pstate_change: %d \n"
2031                         "c.pte_meta_urgent: %d \n"
2032                         "d.urgent_ns: %d \n"
2033                         "d.cstate_enter_plus_exit: %d \n"
2034                         "d.cstate_exit: %d \n"
2035                         "d.pstate_change: %d \n"
2036                         "d.pte_meta_urgent: %d \n"
2037                         "========================================================\n",
2038                         context->bw.dcn.watermarks.c.urgent_ns,
2039                         context->bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns,
2040                         context->bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns,
2041                         context->bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns,
2042                         context->bw.dcn.watermarks.c.pte_meta_urgent_ns,
2043                         context->bw.dcn.watermarks.d.urgent_ns,
2044                         context->bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns,
2045                         context->bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns,
2046                         context->bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns,
2047                         context->bw.dcn.watermarks.d.pte_meta_urgent_ns
2048                         );
2049 */
2050 }
2051
2052 static void dcn10_set_bandwidth(
2053                 struct dc *dc,
2054                 struct dc_state *context,
2055                 bool decrease_allowed)
2056 {
2057         struct pp_smu_display_requirement_rv *smu_req_cur =
2058                         &dc->res_pool->pp_smu_req;
2059         struct pp_smu_display_requirement_rv smu_req = *smu_req_cur;
2060         struct pp_smu_funcs_rv *pp_smu = dc->res_pool->pp_smu;
2061
2062         if (dc->debug.sanity_checks) {
2063                 dcn10_verify_allow_pstate_change_high(dc);
2064         }
2065
2066         if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
2067                 return;
2068
2069         if (decrease_allowed || context->bw.dcn.calc_clk.dispclk_khz
2070                         > dc->current_state->bw.dcn.cur_clk.dispclk_khz) {
2071                 dc->res_pool->display_clock->funcs->set_clock(
2072                                 dc->res_pool->display_clock,
2073                                 context->bw.dcn.calc_clk.dispclk_khz);
2074                 dc->current_state->bw.dcn.cur_clk.dispclk_khz =
2075                                 context->bw.dcn.calc_clk.dispclk_khz;
2076         }
2077         if (decrease_allowed || context->bw.dcn.calc_clk.dcfclk_khz
2078                         > dc->current_state->bw.dcn.cur_clk.dcfclk_khz) {
2079                 smu_req.hard_min_dcefclk_khz =
2080                                 context->bw.dcn.calc_clk.dcfclk_khz;
2081         }
2082         if (decrease_allowed || context->bw.dcn.calc_clk.fclk_khz
2083                         > dc->current_state->bw.dcn.cur_clk.fclk_khz) {
2084                 smu_req.hard_min_fclk_khz = context->bw.dcn.calc_clk.fclk_khz;
2085         }
2086         if (decrease_allowed || context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz
2087                         > dc->current_state->bw.dcn.cur_clk.dcfclk_deep_sleep_khz) {
2088                 dc->current_state->bw.dcn.calc_clk.dcfclk_deep_sleep_khz =
2089                                 context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz;
2090                 context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz =
2091                                 context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz;
2092         }
2093
2094         smu_req.display_count = context->stream_count;
2095
2096         if (pp_smu->set_display_requirement)
2097                 pp_smu->set_display_requirement(&pp_smu->pp_smu, &smu_req);
2098
2099         *smu_req_cur = smu_req;
2100
2101         /* Decrease in freq is increase in period so opposite comparison for dram_ccm */
2102         if (decrease_allowed || context->bw.dcn.calc_clk.dram_ccm_us
2103                         < dc->current_state->bw.dcn.cur_clk.dram_ccm_us) {
2104                 dc->current_state->bw.dcn.calc_clk.dram_ccm_us =
2105                                 context->bw.dcn.calc_clk.dram_ccm_us;
2106                 context->bw.dcn.cur_clk.dram_ccm_us =
2107                                 context->bw.dcn.calc_clk.dram_ccm_us;
2108         }
2109         if (decrease_allowed || context->bw.dcn.calc_clk.min_active_dram_ccm_us
2110                         < dc->current_state->bw.dcn.cur_clk.min_active_dram_ccm_us) {
2111                 dc->current_state->bw.dcn.calc_clk.min_active_dram_ccm_us =
2112                                 context->bw.dcn.calc_clk.min_active_dram_ccm_us;
2113                 context->bw.dcn.cur_clk.min_active_dram_ccm_us =
2114                                 context->bw.dcn.calc_clk.min_active_dram_ccm_us;
2115         }
2116         dcn10_pplib_apply_display_requirements(dc, context);
2117
2118         if (dc->debug.sanity_checks) {
2119                 dcn10_verify_allow_pstate_change_high(dc);
2120         }
2121
2122         /* need to fix this function.  not doing the right thing here */
2123 }
2124
2125 static void set_drr(struct pipe_ctx **pipe_ctx,
2126                 int num_pipes, int vmin, int vmax)
2127 {
2128         int i = 0;
2129         struct drr_params params = {0};
2130
2131         params.vertical_total_max = vmax;
2132         params.vertical_total_min = vmin;
2133
2134         /* TODO: If multiple pipes are to be supported, you need
2135          * some GSL stuff
2136          */
2137         for (i = 0; i < num_pipes; i++) {
2138                 pipe_ctx[i]->stream_res.tg->funcs->set_drr(pipe_ctx[i]->stream_res.tg, &params);
2139         }
2140 }
2141
2142 static void get_position(struct pipe_ctx **pipe_ctx,
2143                 int num_pipes,
2144                 struct crtc_position *position)
2145 {
2146         int i = 0;
2147
2148         /* TODO: handle pipes > 1
2149          */
2150         for (i = 0; i < num_pipes; i++)
2151                 pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);
2152 }
2153
2154 static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
2155                 int num_pipes, const struct dc_static_screen_events *events)
2156 {
2157         unsigned int i;
2158         unsigned int value = 0;
2159
2160         if (events->surface_update)
2161                 value |= 0x80;
2162         if (events->cursor_update)
2163                 value |= 0x2;
2164
2165         for (i = 0; i < num_pipes; i++)
2166                 pipe_ctx[i]->stream_res.tg->funcs->
2167                         set_static_screen_control(pipe_ctx[i]->stream_res.tg, value);
2168 }
2169
2170 static void set_plane_config(
2171         const struct dc *dc,
2172         struct pipe_ctx *pipe_ctx,
2173         struct resource_context *res_ctx)
2174 {
2175         /* TODO */
2176         program_gamut_remap(pipe_ctx);
2177 }
2178
2179 static void dcn10_config_stereo_parameters(
2180                 struct dc_stream_state *stream, struct crtc_stereo_flags *flags)
2181 {
2182         enum view_3d_format view_format = stream->view_format;
2183         enum dc_timing_3d_format timing_3d_format =\
2184                         stream->timing.timing_3d_format;
2185         bool non_stereo_timing = false;
2186
2187         if (timing_3d_format == TIMING_3D_FORMAT_NONE ||
2188                 timing_3d_format == TIMING_3D_FORMAT_SIDE_BY_SIDE ||
2189                 timing_3d_format == TIMING_3D_FORMAT_TOP_AND_BOTTOM)
2190                 non_stereo_timing = true;
2191
2192         if (non_stereo_timing == false &&
2193                 view_format == VIEW_3D_FORMAT_FRAME_SEQUENTIAL) {
2194
2195                 flags->PROGRAM_STEREO         = 1;
2196                 flags->PROGRAM_POLARITY       = 1;
2197                 if (timing_3d_format == TIMING_3D_FORMAT_INBAND_FA ||
2198                         timing_3d_format == TIMING_3D_FORMAT_DP_HDMI_INBAND_FA ||
2199                         timing_3d_format == TIMING_3D_FORMAT_SIDEBAND_FA) {
2200                         enum display_dongle_type dongle = \
2201                                         stream->sink->link->ddc->dongle_type;
2202                         if (dongle == DISPLAY_DONGLE_DP_VGA_CONVERTER ||
2203                                 dongle == DISPLAY_DONGLE_DP_DVI_CONVERTER ||
2204                                 dongle == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
2205                                 flags->DISABLE_STEREO_DP_SYNC = 1;
2206                 }
2207                 flags->RIGHT_EYE_POLARITY =\
2208                                 stream->timing.flags.RIGHT_EYE_3D_POLARITY;
2209                 if (timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
2210                         flags->FRAME_PACKED = 1;
2211         }
2212
2213         return;
2214 }
2215
2216 static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc)
2217 {
2218         struct crtc_stereo_flags flags = { 0 };
2219         struct dc_stream_state *stream = pipe_ctx->stream;
2220
2221         dcn10_config_stereo_parameters(stream, &flags);
2222
2223         pipe_ctx->stream_res.opp->funcs->opp_program_stereo(
2224                 pipe_ctx->stream_res.opp,
2225                 flags.PROGRAM_STEREO == 1 ? true:false,
2226                 &stream->timing);
2227
2228         pipe_ctx->stream_res.tg->funcs->program_stereo(
2229                 pipe_ctx->stream_res.tg,
2230                 &stream->timing,
2231                 &flags);
2232
2233         return;
2234 }
2235
2236 static struct hubp *get_hubp_by_inst(struct resource_pool *res_pool, int mpcc_inst)
2237 {
2238         int i;
2239
2240         for (i = 0; i < res_pool->pipe_count; i++) {
2241                 if (res_pool->hubps[i]->inst == mpcc_inst)
2242                         return res_pool->hubps[i];
2243         }
2244         ASSERT(false);
2245         return NULL;
2246 }
2247
2248 static void dcn10_wait_for_mpcc_disconnect(
2249                 struct dc *dc,
2250                 struct resource_pool *res_pool,
2251                 struct pipe_ctx *pipe_ctx)
2252 {
2253         int mpcc_inst;
2254
2255         if (dc->debug.sanity_checks) {
2256                 dcn10_verify_allow_pstate_change_high(dc);
2257         }
2258
2259         if (!pipe_ctx->stream_res.opp)
2260                 return;
2261
2262         for (mpcc_inst = 0; mpcc_inst < MAX_PIPES; mpcc_inst++) {
2263                 if (pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst]) {
2264                         struct hubp *hubp = get_hubp_by_inst(res_pool, mpcc_inst);
2265
2266                         res_pool->mpc->funcs->wait_for_idle(res_pool->mpc, mpcc_inst);
2267                         pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst] = false;
2268                         hubp->funcs->set_blank(hubp, true);
2269                         /*dm_logger_write(dc->ctx->logger, LOG_ERROR,
2270                                         "[debug_mpo: wait_for_mpcc finished waiting on mpcc %d]\n",
2271                                         i);*/
2272                 }
2273         }
2274
2275         if (dc->debug.sanity_checks) {
2276                 dcn10_verify_allow_pstate_change_high(dc);
2277         }
2278
2279 }
2280
2281 static bool dcn10_dummy_display_power_gating(
2282         struct dc *dc,
2283         uint8_t controller_id,
2284         struct dc_bios *dcb,
2285         enum pipe_gating_control power_gating)
2286 {
2287         return true;
2288 }
2289
2290 void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx)
2291 {
2292         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2293         struct timing_generator *tg = pipe_ctx->stream_res.tg;
2294
2295         if (plane_state == NULL)
2296                 return;
2297
2298         plane_state->status.is_flip_pending =
2299                         pipe_ctx->plane_res.hubp->funcs->hubp_is_flip_pending(
2300                                         pipe_ctx->plane_res.hubp);
2301
2302         plane_state->status.current_address = pipe_ctx->plane_res.hubp->current_address;
2303         if (pipe_ctx->plane_res.hubp->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2304                         tg->funcs->is_stereo_left_eye) {
2305                 plane_state->status.is_right_eye =
2306                                 !tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);
2307         }
2308 }
2309
2310 void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data)
2311 {
2312         if (hws->ctx->dc->res_pool->hubbub != NULL)
2313                 hubbub1_update_dchub(hws->ctx->dc->res_pool->hubbub, dh_data);
2314 }
2315
2316 static const struct hw_sequencer_funcs dcn10_funcs = {
2317         .program_gamut_remap = program_gamut_remap,
2318         .program_csc_matrix = program_csc_matrix,
2319         .init_hw = dcn10_init_hw,
2320         .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
2321         .apply_ctx_for_surface = dcn10_apply_ctx_for_surface,
2322         .set_plane_config = set_plane_config,
2323         .update_plane_addr = dcn10_update_plane_addr,
2324         .update_dchub = dcn10_update_dchub,
2325         .update_pending_status = dcn10_update_pending_status,
2326         .set_input_transfer_func = dcn10_set_input_transfer_func,
2327         .set_output_transfer_func = dcn10_set_output_transfer_func,
2328         .power_down = dce110_power_down,
2329         .enable_accelerated_mode = dce110_enable_accelerated_mode,
2330         .enable_timing_synchronization = dcn10_enable_timing_synchronization,
2331         .enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,
2332         .update_info_frame = dce110_update_info_frame,
2333         .enable_stream = dce110_enable_stream,
2334         .disable_stream = dce110_disable_stream,
2335         .unblank_stream = dce110_unblank_stream,
2336         .enable_display_power_gating = dcn10_dummy_display_power_gating,
2337         .disable_plane = dcn10_disable_plane,
2338         .pipe_control_lock = dcn10_pipe_control_lock,
2339         .set_bandwidth = dcn10_set_bandwidth,
2340         .reset_hw_ctx_wrap = reset_hw_ctx_wrap,
2341         .prog_pixclk_crtc_otg = dcn10_prog_pixclk_crtc_otg,
2342         .set_drr = set_drr,
2343         .get_position = get_position,
2344         .set_static_screen_control = set_static_screen_control,
2345         .setup_stereo = dcn10_setup_stereo,
2346         .set_avmute = dce110_set_avmute,
2347         .log_hw_state = dcn10_log_hw_state,
2348         .wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
2349         .ready_shared_resources = ready_shared_resources,
2350         .optimize_shared_resources = optimize_shared_resources,
2351         .pplib_apply_display_requirements =
2352                         dcn10_pplib_apply_display_requirements,
2353         .edp_backlight_control = hwss_edp_backlight_control,
2354         .edp_power_control = hwss_edp_power_control,
2355         .edp_wait_for_hpd_ready = hwss_edp_wait_for_hpd_ready,
2356 };
2357
2358
2359 void dcn10_hw_sequencer_construct(struct dc *dc)
2360 {
2361         dc->hwss = dcn10_funcs;
2362 }
2363