drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 #include "dm_services.h"
  26 #include "dce_calcs.h"
  27 #include "reg_helper.h"
  28 #include "basics/conversion.h"
  29 #include "dcn10_hubp.h"
  30
  31 #define REG(reg)\
  32         hubp1->hubp_regs->reg
  33
  34 #define CTX \
  35         hubp1->base.ctx
  36
  37 #undef FN
  38 #define FN(reg_name, field_name) \
  39         hubp1->hubp_shift->field_name, hubp1->hubp_mask->field_name
  40
  41 void hubp1_set_blank(struct hubp *hubp, bool blank)
  42 {
  43         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
  44         uint32_t blank_en = blank ? 1 : 0;
  45
  46         REG_UPDATE_2(DCHUBP_CNTL,
  47                         HUBP_BLANK_EN, blank_en,
  48                         HUBP_TTU_DISABLE, blank_en);
  49
  50         if (blank) {
  51                 uint32_t reg_val = REG_READ(DCHUBP_CNTL);
  52
  53                 if (reg_val) {
  54                         /* init sequence workaround: in case HUBP is
  55                          * power gated, this wait would timeout.
  56                          *
  57                          * we just wrote reg_val to non-0, if it stay 0
  58                          * it means HUBP is gated
  59                          */
  60                         REG_WAIT(DCHUBP_CNTL,
  61                                         HUBP_NO_OUTSTANDING_REQ, 1,
  62                                         1, 200);
  63                 }
  64
  65                 hubp->mpcc_id = 0xf;
  66                 hubp->opp_id = 0xf;
  67         }
  68 }
  69
  70 static void hubp1_disconnect(struct hubp *hubp)
  71 {
  72         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
  73
  74         REG_UPDATE(DCHUBP_CNTL,
  75                         HUBP_TTU_DISABLE, 1);
  76 }
  77
  78 static void hubp1_set_hubp_blank_en(struct hubp *hubp, bool blank)
  79 {
  80         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
  81         uint32_t blank_en = blank ? 1 : 0;
  82
  83         REG_UPDATE(DCHUBP_CNTL, HUBP_BLANK_EN, blank_en);
  84 }
  85
  86 static void hubp1_vready_workaround(struct hubp *hubp,
  87                 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)
  88 {
  89         uint32_t value = 0;
  90         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
  91
  92         /* set HBUBREQ_DEBUG_DB[12] = 1 */
  93         value = REG_READ(HUBPREQ_DEBUG_DB);
  94
  95         /* hack mode disable */
  96         value |= 0x100;
  97         value &= ~0x1000;
  98
  99         if ((pipe_dest->vstartup_start - 2*(pipe_dest->vready_offset+pipe_dest->vupdate_width
 100                 + pipe_dest->vupdate_offset) / pipe_dest->htotal) <= pipe_dest->vblank_end) {
 101                 /* if (eco_fix_needed(otg_global_sync_timing)
 102                  * set HBUBREQ_DEBUG_DB[12] = 1 */
 103                 value |= 0x1000;
 104         }
 105
 106         REG_WRITE(HUBPREQ_DEBUG_DB, value);
 107 }
 108
 109 void hubp1_program_tiling(
 110         struct hubp *hubp,
 111         const union dc_tiling_info *info,
 112         const enum surface_pixel_format pixel_format)
 113 {
 114         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
 115
 116         REG_UPDATE_6(DCSURF_ADDR_CONFIG,
 117                         NUM_PIPES, log_2(info->gfx9.num_pipes),
 118                         NUM_BANKS, log_2(info->gfx9.num_banks),
 119                         PIPE_INTERLEAVE, info->gfx9.pipe_interleave,
 120                         NUM_SE, log_2(info->gfx9.num_shader_engines),
 121                         NUM_RB_PER_SE, log_2(info->gfx9.num_rb_per_se),
 122                         MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags));
 123
 124         REG_UPDATE_4(DCSURF_TILING_CONFIG,
 125                         SW_MODE, info->gfx9.swizzle,
 126                         META_LINEAR, info->gfx9.meta_linear,
 127                         RB_ALIGNED, info->gfx9.rb_aligned,
 128                         PIPE_ALIGNED, info->gfx9.pipe_aligned);
 129 }
 130
 131 void hubp1_program_size_and_rotation(
 132         struct hubp *hubp,
 133         enum dc_rotation_angle rotation,
 134         enum surface_pixel_format format,
 135         const union plane_size *plane_size,
 136         struct dc_plane_dcc_param *dcc,
 137         bool horizontal_mirror)
 138 {
 139         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
 140         uint32_t pitch, meta_pitch, pitch_c, meta_pitch_c, mirror;
 141
 142         /* Program data and meta surface pitch (calculation from addrlib)
 143          * 444 or 420 luma
 144          */
 145         if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
 146                 pitch = plane_size->video.luma_pitch - 1;
 147                 meta_pitch = dcc->video.meta_pitch_l - 1;
 148                 pitch_c = plane_size->video.chroma_pitch - 1;
 149                 meta_pitch_c = dcc->video.meta_pitch_c - 1;
 150         } else {
 151                 pitch = plane_size->grph.surface_pitch - 1;
 152                 meta_pitch = dcc->grph.meta_pitch - 1;
 153                 pitch_c = 0;
 154                 meta_pitch_c = 0;
 155         }
 156
 157         if (!dcc->enable) {
 158                 meta_pitch = 0;
 159                 meta_pitch_c = 0;
 160         }
 161
 162         REG_UPDATE_2(DCSURF_SURFACE_PITCH,
 163                         PITCH, pitch, META_PITCH, meta_pitch);
 164
 165         if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
 166                 REG_UPDATE_2(DCSURF_SURFACE_PITCH_C,
 167                         PITCH_C, pitch_c, META_PITCH_C, meta_pitch_c);
 168
 169         if (horizontal_mirror)
 170                 mirror = 1;
 171         else
 172                 mirror = 0;
 173
 174
 175         /* Program rotation angle and horz mirror - no mirror */
 176         if (rotation == ROTATION_ANGLE_0)
 177                 REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
 178                                 ROTATION_ANGLE, 0,
 179                                 H_MIRROR_EN, mirror);
 180         else if (rotation == ROTATION_ANGLE_90)
 181                 REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
 182                                 ROTATION_ANGLE, 1,
 183                                 H_MIRROR_EN, mirror);
 184         else if (rotation == ROTATION_ANGLE_180)
 185                 REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
 186                                 ROTATION_ANGLE, 2,
 187                                 H_MIRROR_EN, mirror);
 188         else if (rotation == ROTATION_ANGLE_270)
 189                 REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
 190                                 ROTATION_ANGLE, 3,
 191                                 H_MIRROR_EN, mirror);
 192 }
 193
 194 void hubp1_program_pixel_format(
 195         struct hubp *hubp,
 196         enum surface_pixel_format format)
 197 {
 198         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
 199         uint32_t red_bar = 3;
 200         uint32_t blue_bar = 2;
 201
 202         /* swap for ABGR format */
 203         if (format == SURFACE_PIXEL_FORMAT_GRPH_ABGR8888
 204                         || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010
 205                         || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS
 206                         || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) {
 207                 red_bar = 2;
 208                 blue_bar = 3;
 209         }
 210
 211         REG_UPDATE_2(HUBPRET_CONTROL,
 212                         CROSSBAR_SRC_CB_B, blue_bar,
 213                         CROSSBAR_SRC_CR_R, red_bar);
 214
 215         /* Mapping is same as ipp programming (cnvc) */
 216
 217         switch (format) {
 218         case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
 219                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 220                                 SURFACE_PIXEL_FORMAT, 1);
 221                 break;
 222         case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
 223                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 224                                 SURFACE_PIXEL_FORMAT, 3);
 225                 break;
 226         case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
 227         case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
 228                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 229                                 SURFACE_PIXEL_FORMAT, 8);
 230                 break;
 231         case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
 232         case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
 233         case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
 234                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 235                                 SURFACE_PIXEL_FORMAT, 10);
 236                 break;
 237         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
 238                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 239                                 SURFACE_PIXEL_FORMAT, 22);
 240                 break;
 241         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
 242         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:/*we use crossbar already*/
 243                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 244                                 SURFACE_PIXEL_FORMAT, 24);
 245                 break;
 246
 247         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
 248                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 249                                 SURFACE_PIXEL_FORMAT, 65);
 250                 break;
 251         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
 252                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 253                                 SURFACE_PIXEL_FORMAT, 64);
 254                 break;
 255         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
 256                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 257                                 SURFACE_PIXEL_FORMAT, 67);
 258                 break;
 259         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
 260                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 261                                 SURFACE_PIXEL_FORMAT, 66);
 262                 break;
 263         default:
 264                 BREAK_TO_DEBUGGER();
 265                 break;
 266         }
 267
 268         /* don't see the need of program the xbar in DCN 1.0 */
 269 }
 270
 271 bool hubp1_program_surface_flip_and_addr(
 272         struct hubp *hubp,
 273         const struct dc_plane_address *address,
 274         bool flip_immediate)
 275 {
 276         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
 277
 278         /* program flip type */
 279         REG_SET(DCSURF_FLIP_CONTROL, 0,
 280                         SURFACE_FLIP_TYPE, flip_immediate);
 281
 282         /* HW automatically latch rest of address register on write to
 283          * DCSURF_PRIMARY_SURFACE_ADDRESS if SURFACE_UPDATE_LOCK is not used
 284          *
 285          * program high first and then the low addr, order matters!
 286          */
 287         switch (address->type) {
 288         case PLN_ADDR_TYPE_GRAPHICS:
 289                 /* DCN1.0 does not support const color
 290                  * TODO: program DCHUBBUB_RET_PATH_DCC_CFGx_0/1
 291                  * base on address->grph.dcc_const_color
 292                  * x = 0, 2, 4, 6 for pipe 0, 1, 2, 3 for rgb and luma
 293                  * x = 1, 3, 5, 7 for pipe 0, 1, 2, 3 for chroma
 294                  */
 295
 296                 if (address->grph.addr.quad_part == 0)
 297                         break;
 298
 299                 REG_UPDATE(DCSURF_SURFACE_CONTROL,
 300                                 PRIMARY_SURFACE_TMZ, address->tmz_surface);
 301
 302                 if (address->grph.meta_addr.quad_part != 0) {
 303                         REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
 304                                         PRIMARY_META_SURFACE_ADDRESS_HIGH,
 305                                         address->grph.meta_addr.high_part);
 306
 307                         REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
 308                                         PRIMARY_META_SURFACE_ADDRESS,
 309                                         address->grph.meta_addr.low_part);
 310                 }
 311
 312                 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
 313                                 PRIMARY_SURFACE_ADDRESS_HIGH,
 314                                 address->grph.addr.high_part);
 315
 316                 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
 317                                 PRIMARY_SURFACE_ADDRESS,
 318                                 address->grph.addr.low_part);
 319                 break;
 320         case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE:
 321                 if (address->video_progressive.luma_addr.quad_part == 0
 322                         || address->video_progressive.chroma_addr.quad_part == 0)
 323                         break;
 324
 325                 REG_UPDATE(DCSURF_SURFACE_CONTROL,
 326                                 PRIMARY_SURFACE_TMZ, address->tmz_surface);
 327
 328                 if (address->video_progressive.luma_meta_addr.quad_part != 0) {
 329                         REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0,
 330                                 PRIMARY_META_SURFACE_ADDRESS_HIGH_C,
 331                                 address->video_progressive.chroma_meta_addr.high_part);
 332
 333                         REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0,
 334                                 PRIMARY_META_SURFACE_ADDRESS_C,
 335                                 address->video_progressive.chroma_meta_addr.low_part);
 336
 337                         REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
 338                                 PRIMARY_META_SURFACE_ADDRESS_HIGH,
 339                                 address->video_progressive.luma_meta_addr.high_part);
 340
 341                         REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
 342                                 PRIMARY_META_SURFACE_ADDRESS,
 343                                 address->video_progressive.luma_meta_addr.low_part);
 344                 }
 345
 346                 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,
 347                         PRIMARY_SURFACE_ADDRESS_HIGH_C,
 348                         address->video_progressive.chroma_addr.high_part);
 349
 350                 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,
 351                         PRIMARY_SURFACE_ADDRESS_C,
 352                         address->video_progressive.chroma_addr.low_part);
 353
 354                 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
 355                         PRIMARY_SURFACE_ADDRESS_HIGH,
 356                         address->video_progressive.luma_addr.high_part);
 357
 358                 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
 359                         PRIMARY_SURFACE_ADDRESS,
 360                         address->video_progressive.luma_addr.low_part);
 361                 break;
 362         case PLN_ADDR_TYPE_GRPH_STEREO:
 363                 if (address->grph_stereo.left_addr.quad_part == 0)
 364                         break;
 365                 if (address->grph_stereo.right_addr.quad_part == 0)
 366                         break;
 367
 368                 REG_UPDATE(DCSURF_SURFACE_CONTROL,
 369                                 PRIMARY_SURFACE_TMZ, address->tmz_surface);
 370
 371                 if (address->grph_stereo.right_meta_addr.quad_part != 0) {
 372
 373                         REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0,
 374                                         SECONDARY_META_SURFACE_ADDRESS_HIGH,
 375                                         address->grph_stereo.right_meta_addr.high_part);
 376
 377                         REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0,
 378                                         SECONDARY_META_SURFACE_ADDRESS,
 379                                         address->grph_stereo.right_meta_addr.low_part);
 380                 }
 381                 if (address->grph_stereo.left_meta_addr.quad_part != 0) {
 382
 383                         REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
 384                                         PRIMARY_META_SURFACE_ADDRESS_HIGH,
 385                                         address->grph_stereo.left_meta_addr.high_part);
 386
 387                         REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
 388                                         PRIMARY_META_SURFACE_ADDRESS,
 389                                         address->grph_stereo.left_meta_addr.low_part);
 390                 }
 391
 392                 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0,
 393                                 SECONDARY_SURFACE_ADDRESS_HIGH,
 394                                 address->grph_stereo.right_addr.high_part);
 395
 396                 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0,
 397                                 SECONDARY_SURFACE_ADDRESS,
 398                                 address->grph_stereo.right_addr.low_part);
 399
 400                 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
 401                                 PRIMARY_SURFACE_ADDRESS_HIGH,
 402                                 address->grph_stereo.left_addr.high_part);
 403
 404                 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
 405                                 PRIMARY_SURFACE_ADDRESS,
 406                                 address->grph_stereo.left_addr.low_part);
 407                 break;
 408         default:
 409                 BREAK_TO_DEBUGGER();
 410                 break;
 411         }
 412
 413         hubp->request_address = *address;
 414
 415         if (flip_immediate)
 416                 hubp->current_address = *address;
 417
 418         return true;
 419 }
 420
 421 void hubp1_dcc_control(struct hubp *hubp, bool enable,
 422                 bool independent_64b_blks)
 423 {
 424         uint32_t dcc_en = enable ? 1 : 0;
 425         uint32_t dcc_ind_64b_blk = independent_64b_blks ? 1 : 0;
 426         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
 427
 428         REG_UPDATE_2(DCSURF_SURFACE_CONTROL,
 429                         PRIMARY_SURFACE_DCC_EN, dcc_en,
 430                         PRIMARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk);
 431 }
 432
 433 void hubp1_program_surface_config(
 434         struct hubp *hubp,
 435         enum surface_pixel_format format,
 436         union dc_tiling_info *tiling_info,
 437         union plane_size *plane_size,
 438         enum dc_rotation_angle rotation,
 439         struct dc_plane_dcc_param *dcc,
 440         bool horizontal_mirror)
 441 {
 442         hubp1_dcc_control(hubp, dcc->enable, dcc->grph.independent_64b_blks);
 443         hubp1_program_tiling(hubp, tiling_info, format);
 444         hubp1_program_size_and_rotation(
 445                         hubp, rotation, format, plane_size, dcc, horizontal_mirror);
 446         hubp1_program_pixel_format(hubp, format);
 447 }
 448
 449 void hubp1_program_requestor(
 450                 struct hubp *hubp,
 451                 struct _vcs_dpi_display_rq_regs_st *rq_regs)
 452 {
 453         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
 454
 455         REG_UPDATE(HUBPRET_CONTROL,
 456                         DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address);
 457         REG_SET_4(DCN_EXPANSION_MODE, 0,
 458                         DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode,
 459                         PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode,
 460                         MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode,
 461                         CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode);
 462         REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0,
 463                 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size,
 464                 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size,
 465                 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size,
 466                 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size,
 467                 DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size,
 468                 MPTE_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size,
 469                 SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height,
 470                 PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear);
 471         REG_SET_8(DCHUBP_REQ_SIZE_CONFIG_C, 0,
 472                 CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size,
 473                 MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size,
 474                 META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size,
 475                 MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size,
 476                 DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size,
 477                 MPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.mpte_group_size,
 478                 SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height,
 479                 PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear);
 480 }
 481
 482
 483 void hubp1_program_deadline(
 484                 struct hubp *hubp,
 485                 struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
 486                 struct _vcs_dpi_display_ttu_regs_st *ttu_attr)
 487 {
 488         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
 489
 490         /* DLG - Per hubp */
 491         REG_SET_2(BLANK_OFFSET_0, 0,
 492                 REFCYC_H_BLANK_END, dlg_attr->refcyc_h_blank_end,
 493                 DLG_V_BLANK_END, dlg_attr->dlg_vblank_end);
 494
 495         REG_SET(BLANK_OFFSET_1, 0,
 496                 MIN_DST_Y_NEXT_START, dlg_attr->min_dst_y_next_start);
 497
 498         REG_SET(DST_DIMENSIONS, 0,
 499                 REFCYC_PER_HTOTAL, dlg_attr->refcyc_per_htotal);
 500
 501         REG_SET_2(DST_AFTER_SCALER, 0,
 502                 REFCYC_X_AFTER_SCALER, dlg_attr->refcyc_x_after_scaler,
 503                 DST_Y_AFTER_SCALER, dlg_attr->dst_y_after_scaler);
 504
 505         if (REG(PREFETCH_SETTINS))
 506                 REG_SET_2(PREFETCH_SETTINS, 0,
 507                         DST_Y_PREFETCH, dlg_attr->dst_y_prefetch,
 508                         VRATIO_PREFETCH, dlg_attr->vratio_prefetch);
 509         else
 510                 REG_SET_2(PREFETCH_SETTINGS, 0,
 511                         DST_Y_PREFETCH, dlg_attr->dst_y_prefetch,
 512                         VRATIO_PREFETCH, dlg_attr->vratio_prefetch);
 513
 514         REG_SET_2(VBLANK_PARAMETERS_0, 0,
 515                 DST_Y_PER_VM_VBLANK, dlg_attr->dst_y_per_vm_vblank,
 516                 DST_Y_PER_ROW_VBLANK, dlg_attr->dst_y_per_row_vblank);
 517
 518         REG_SET(REF_FREQ_TO_PIX_FREQ, 0,
 519                 REF_FREQ_TO_PIX_FREQ, dlg_attr->ref_freq_to_pix_freq);
 520
 521         /* DLG - Per luma/chroma */
 522         REG_SET(VBLANK_PARAMETERS_1, 0,
 523                 REFCYC_PER_PTE_GROUP_VBLANK_L, dlg_attr->refcyc_per_pte_group_vblank_l);
 524
 525         REG_SET(VBLANK_PARAMETERS_3, 0,
 526                 REFCYC_PER_META_CHUNK_VBLANK_L, dlg_attr->refcyc_per_meta_chunk_vblank_l);
 527
 528         REG_SET(NOM_PARAMETERS_0, 0,
 529                 DST_Y_PER_PTE_ROW_NOM_L, dlg_attr->dst_y_per_pte_row_nom_l);
 530
 531         REG_SET(NOM_PARAMETERS_1, 0,
 532                 REFCYC_PER_PTE_GROUP_NOM_L, dlg_attr->refcyc_per_pte_group_nom_l);
 533
 534         REG_SET(NOM_PARAMETERS_4, 0,
 535                 DST_Y_PER_META_ROW_NOM_L, dlg_attr->dst_y_per_meta_row_nom_l);
 536
 537         REG_SET(NOM_PARAMETERS_5, 0,
 538                 REFCYC_PER_META_CHUNK_NOM_L, dlg_attr->refcyc_per_meta_chunk_nom_l);
 539
 540         REG_SET_2(PER_LINE_DELIVERY_PRE, 0,
 541                 REFCYC_PER_LINE_DELIVERY_PRE_L, dlg_attr->refcyc_per_line_delivery_pre_l,
 542                 REFCYC_PER_LINE_DELIVERY_PRE_C, dlg_attr->refcyc_per_line_delivery_pre_c);
 543
 544         REG_SET_2(PER_LINE_DELIVERY, 0,
 545                 REFCYC_PER_LINE_DELIVERY_L, dlg_attr->refcyc_per_line_delivery_l,
 546                 REFCYC_PER_LINE_DELIVERY_C, dlg_attr->refcyc_per_line_delivery_c);
 547
 548         if (REG(PREFETCH_SETTINS_C))
 549                 REG_SET(PREFETCH_SETTINS_C, 0,
 550                         VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c);
 551         else
 552                 REG_SET(PREFETCH_SETTINGS_C, 0,
 553                         VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c);
 554
 555         REG_SET(VBLANK_PARAMETERS_2, 0,
 556                 REFCYC_PER_PTE_GROUP_VBLANK_C, dlg_attr->refcyc_per_pte_group_vblank_c);
 557
 558         REG_SET(VBLANK_PARAMETERS_4, 0,
 559                 REFCYC_PER_META_CHUNK_VBLANK_C, dlg_attr->refcyc_per_meta_chunk_vblank_c);
 560
 561         REG_SET(NOM_PARAMETERS_2, 0,
 562                 DST_Y_PER_PTE_ROW_NOM_C, dlg_attr->dst_y_per_pte_row_nom_c);
 563
 564         REG_SET(NOM_PARAMETERS_3, 0,
 565                 REFCYC_PER_PTE_GROUP_NOM_C, dlg_attr->refcyc_per_pte_group_nom_c);
 566
 567         REG_SET(NOM_PARAMETERS_6, 0,
 568                 DST_Y_PER_META_ROW_NOM_C, dlg_attr->dst_y_per_meta_row_nom_c);
 569
 570         REG_SET(NOM_PARAMETERS_7, 0,
 571                 REFCYC_PER_META_CHUNK_NOM_C, dlg_attr->refcyc_per_meta_chunk_nom_c);
 572
 573         /* TTU - per hubp */
 574         REG_SET_2(DCN_TTU_QOS_WM, 0,
 575                 QoS_LEVEL_LOW_WM, ttu_attr->qos_level_low_wm,
 576                 QoS_LEVEL_HIGH_WM, ttu_attr->qos_level_high_wm);
 577
 578         REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0,
 579                 MIN_TTU_VBLANK, ttu_attr->min_ttu_vblank,
 580                 QoS_LEVEL_FLIP, ttu_attr->qos_level_flip);
 581
 582         /* TTU - per luma/chroma */
 583         /* Assumed surf0 is luma and 1 is chroma */
 584
 585         REG_SET_3(DCN_SURF0_TTU_CNTL0, 0,
 586                 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_l,
 587                 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_l,
 588                 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_l);
 589
 590         REG_SET(DCN_SURF0_TTU_CNTL1, 0,
 591                 REFCYC_PER_REQ_DELIVERY_PRE,
 592                 ttu_attr->refcyc_per_req_delivery_pre_l);
 593
 594         REG_SET_3(DCN_SURF1_TTU_CNTL0, 0,
 595                 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_c,
 596                 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_c,
 597                 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_c);
 598
 599         REG_SET(DCN_SURF1_TTU_CNTL1, 0,
 600                 REFCYC_PER_REQ_DELIVERY_PRE,
 601                 ttu_attr->refcyc_per_req_delivery_pre_c);
 602 }
 603
 604 static void hubp1_setup(
 605                 struct hubp *hubp,
 606                 struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
 607                 struct _vcs_dpi_display_ttu_regs_st *ttu_attr,
 608                 struct _vcs_dpi_display_rq_regs_st *rq_regs,
 609                 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)
 610 {
 611         /* otg is locked when this func is called. Register are double buffered.
 612          * disable the requestors is not needed
 613          */
 614         hubp1_program_requestor(hubp, rq_regs);
 615         hubp1_program_deadline(hubp, dlg_attr, ttu_attr);
 616         hubp1_vready_workaround(hubp, pipe_dest);
 617 }
 618
 619 bool hubp1_is_flip_pending(struct hubp *hubp)
 620 {
 621         uint32_t flip_pending = 0;
 622         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
 623         struct dc_plane_address earliest_inuse_address;
 624
 625         REG_GET(DCSURF_FLIP_CONTROL,
 626                         SURFACE_FLIP_PENDING, &flip_pending);
 627
 628         REG_GET(DCSURF_SURFACE_EARLIEST_INUSE,
 629                         SURFACE_EARLIEST_INUSE_ADDRESS, &earliest_inuse_address.grph.addr.low_part);
 630
 631         REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH,
 632                         SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &earliest_inuse_address.grph.addr.high_part);
 633
 634         if (flip_pending)
 635                 return true;
 636
 637         if (earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part)
 638                 return true;
 639
 640         hubp->current_address = hubp->request_address;
 641         return false;
 642 }
 643
 644 uint32_t aperture_default_system = 1;
 645 uint32_t context0_default_system; /* = 0;*/
 646
 647 static void hubp1_set_vm_system_aperture_settings(struct hubp *hubp,
 648                 struct vm_system_aperture_param *apt)
 649 {
 650         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
 651         PHYSICAL_ADDRESS_LOC mc_vm_apt_default;
 652         PHYSICAL_ADDRESS_LOC mc_vm_apt_low;
 653         PHYSICAL_ADDRESS_LOC mc_vm_apt_high;
 654
 655         mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12;
 656         mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 12;
 657         mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 12;
 658
 659         REG_SET_2(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 0,
 660                 MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, aperture_default_system, /* 1 = system physical memory */
 661                 MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mc_vm_apt_default.high_part);
 662         REG_SET(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 0,
 663                 MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mc_vm_apt_default.low_part);
 664
 665         REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, 0,
 666                         MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, mc_vm_apt_low.high_part);
 667         REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, 0,
 668                         MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, mc_vm_apt_low.low_part);
 669
 670         REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, 0,
 671                         MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, mc_vm_apt_high.high_part);
 672         REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, 0,
 673                         MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, mc_vm_apt_high.low_part);
 674 }
 675
 676 static void hubp1_set_vm_context0_settings(struct hubp *hubp,
 677                 const struct vm_context0_param *vm0)
 678 {
 679         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
 680         /* pte base */
 681         REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, 0,
 682                         VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, vm0->pte_base.high_part);
 683         REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, 0,
 684                         VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, vm0->pte_base.low_part);
 685
 686         /* pte start */
 687         REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, 0,
 688                         VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, vm0->pte_start.high_part);
 689         REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, 0,
 690                         VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, vm0->pte_start.low_part);
 691
 692         /* pte end */
 693         REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, 0,
 694                         VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, vm0->pte_end.high_part);
 695         REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, 0,
 696                         VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, vm0->pte_end.low_part);
 697
 698         /* fault handling */
 699         REG_SET_2(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, 0,
 700                         VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, vm0->fault_default.high_part,
 701                         VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM, context0_default_system);
 702         REG_SET(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, 0,
 703                         VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, vm0->fault_default.low_part);
 704
 705         /* control: enable VM PTE*/
 706         REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0,
 707                         ENABLE_L1_TLB, 1,
 708                         SYSTEM_ACCESS_MODE, 3);
 709 }
 710
 711 void min_set_viewport(
 712         struct hubp *hubp,
 713         const struct rect *viewport,
 714         const struct rect *viewport_c)
 715 {
 716         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
 717
 718         REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0,
 719                   PRI_VIEWPORT_WIDTH, viewport->width,
 720                   PRI_VIEWPORT_HEIGHT, viewport->height);
 721
 722         REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0,
 723                   PRI_VIEWPORT_X_START, viewport->x,
 724                   PRI_VIEWPORT_Y_START, viewport->y);
 725
 726         /*for stereo*/
 727         REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0,
 728                   SEC_VIEWPORT_WIDTH, viewport->width,
 729                   SEC_VIEWPORT_HEIGHT, viewport->height);
 730
 731         REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0,
 732                   SEC_VIEWPORT_X_START, viewport->x,
 733                   SEC_VIEWPORT_Y_START, viewport->y);
 734
 735         /* DC supports NV12 only at the moment */
 736         REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0,
 737                   PRI_VIEWPORT_WIDTH_C, viewport_c->width,
 738                   PRI_VIEWPORT_HEIGHT_C, viewport_c->height);
 739
 740         REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0,
 741                   PRI_VIEWPORT_X_START_C, viewport_c->x,
 742                   PRI_VIEWPORT_Y_START_C, viewport_c->y);
 743 }
 744
 745 void hubp1_read_state(struct dcn10_hubp *hubp1,
 746                 struct dcn_hubp_state *s)
 747 {
 748         REG_GET(DCSURF_SURFACE_CONFIG,
 749                         SURFACE_PIXEL_FORMAT, &s->pixel_format);
 750
 751         REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH,
 752                         SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &s->inuse_addr_hi);
 753
 754         REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION,
 755                         PRI_VIEWPORT_WIDTH, &s->viewport_width,
 756                         PRI_VIEWPORT_HEIGHT, &s->viewport_height);
 757
 758         REG_GET_2(DCSURF_SURFACE_CONFIG,
 759                         ROTATION_ANGLE, &s->rotation_angle,
 760                         H_MIRROR_EN, &s->h_mirror_en);
 761
 762         REG_GET(DCSURF_TILING_CONFIG,
 763                         SW_MODE, &s->sw_mode);
 764
 765         REG_GET(DCSURF_SURFACE_CONTROL,
 766                         PRIMARY_SURFACE_DCC_EN, &s->dcc_en);
 767
 768         REG_GET_3(DCHUBP_CNTL,
 769                         HUBP_BLANK_EN, &s->blank_en,
 770                         HUBP_TTU_DISABLE, &s->ttu_disable,
 771                         HUBP_UNDERFLOW_STATUS, &s->underflow_status);
 772
 773         REG_GET(DCN_GLOBAL_TTU_CNTL,
 774                         MIN_TTU_VBLANK, &s->min_ttu_vblank);
 775
 776         REG_GET_2(DCN_TTU_QOS_WM,
 777                         QoS_LEVEL_LOW_WM, &s->qos_level_low_wm,
 778                         QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm);
 779 }
 780
 781 enum cursor_pitch hubp1_get_cursor_pitch(unsigned int pitch)
 782 {
 783         enum cursor_pitch hw_pitch;
 784
 785         switch (pitch) {
 786         case 64:
 787                 hw_pitch = CURSOR_PITCH_64_PIXELS;
 788                 break;
 789         case 128:
 790                 hw_pitch = CURSOR_PITCH_128_PIXELS;
 791                 break;
 792         case 256:
 793                 hw_pitch = CURSOR_PITCH_256_PIXELS;
 794                 break;
 795         default:
 796                 DC_ERR("Invalid cursor pitch of %d. "
 797                                 "Only 64/128/256 is supported on DCN.\n", pitch);
 798                 hw_pitch = CURSOR_PITCH_64_PIXELS;
 799                 break;
 800         }
 801         return hw_pitch;
 802 }
 803
 804 static enum cursor_lines_per_chunk hubp1_get_lines_per_chunk(
 805                 unsigned int cur_width,
 806                 enum dc_cursor_color_format format)
 807 {
 808         enum cursor_lines_per_chunk line_per_chunk;
 809
 810         if (format == CURSOR_MODE_MONO)
 811                 /* impl B. expansion in CUR Buffer reader */
 812                 line_per_chunk = CURSOR_LINE_PER_CHUNK_16;
 813         else if (cur_width <= 32)
 814                 line_per_chunk = CURSOR_LINE_PER_CHUNK_16;
 815         else if (cur_width <= 64)
 816                 line_per_chunk = CURSOR_LINE_PER_CHUNK_8;
 817         else if (cur_width <= 128)
 818                 line_per_chunk = CURSOR_LINE_PER_CHUNK_4;
 819         else
 820                 line_per_chunk = CURSOR_LINE_PER_CHUNK_2;
 821
 822         return line_per_chunk;
 823 }
 824
 825 void hubp1_cursor_set_attributes(
 826                 struct hubp *hubp,
 827                 const struct dc_cursor_attributes *attr)
 828 {
 829         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
 830         enum cursor_pitch hw_pitch = hubp1_get_cursor_pitch(attr->pitch);
 831         enum cursor_lines_per_chunk lpc = hubp1_get_lines_per_chunk(
 832                         attr->width, attr->color_format);
 833
 834         hubp->curs_attr = *attr;
 835
 836         REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH,
 837                         CURSOR_SURFACE_ADDRESS_HIGH, attr->address.high_part);
 838         REG_UPDATE(CURSOR_SURFACE_ADDRESS,
 839                         CURSOR_SURFACE_ADDRESS, attr->address.low_part);
 840
 841         REG_UPDATE_2(CURSOR_SIZE,
 842                         CURSOR_WIDTH, attr->width,
 843                         CURSOR_HEIGHT, attr->height);
 844
 845         REG_UPDATE_3(CURSOR_CONTROL,
 846                         CURSOR_MODE, attr->color_format,
 847                         CURSOR_PITCH, hw_pitch,
 848                         CURSOR_LINES_PER_CHUNK, lpc);
 849
 850         REG_SET_2(CURSOR_SETTINS, 0,
 851                         /* no shift of the cursor HDL schedule */
 852                         CURSOR0_DST_Y_OFFSET, 0,
 853                          /* used to shift the cursor chunk request deadline */
 854                         CURSOR0_CHUNK_HDL_ADJUST, 3);
 855 }
 856
 857 void hubp1_cursor_set_position(
 858                 struct hubp *hubp,
 859                 const struct dc_cursor_position *pos,
 860                 const struct dc_cursor_mi_param *param)
 861 {
 862         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
 863         int src_x_offset = pos->x - pos->x_hotspot - param->viewport_x_start;
 864         uint32_t cur_en = pos->enable ? 1 : 0;
 865         uint32_t dst_x_offset = (src_x_offset >= 0) ? src_x_offset : 0;
 866
 867         /*
 868          * Guard aganst cursor_set_position() from being called with invalid
 869          * attributes
 870          *
 871          * TODO: Look at combining cursor_set_position() and
 872          * cursor_set_attributes() into cursor_update()
 873          */
 874         if (hubp->curs_attr.address.quad_part == 0)
 875                 return;
 876
 877         dst_x_offset *= param->ref_clk_khz;
 878         dst_x_offset /= param->pixel_clk_khz;
 879
 880         ASSERT(param->h_scale_ratio.value);
 881
 882         if (param->h_scale_ratio.value)
 883                 dst_x_offset = dal_fixed31_32_floor(dal_fixed31_32_div(
 884                                 dal_fixed31_32_from_int(dst_x_offset),
 885                                 param->h_scale_ratio));
 886
 887         if (src_x_offset >= (int)param->viewport_width)
 888                 cur_en = 0;  /* not visible beyond right edge*/
 889
 890         if (src_x_offset + (int)hubp->curs_attr.width < 0)
 891                 cur_en = 0;  /* not visible beyond left edge*/
 892
 893         if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0)
 894                 hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr);
 895
 896         REG_UPDATE(CURSOR_CONTROL,
 897                         CURSOR_ENABLE, cur_en);
 898
 899         REG_SET_2(CURSOR_POSITION, 0,
 900                         CURSOR_X_POSITION, pos->x,
 901                         CURSOR_Y_POSITION, pos->y);
 902
 903         REG_SET_2(CURSOR_HOT_SPOT, 0,
 904                         CURSOR_HOT_SPOT_X, pos->x_hotspot,
 905                         CURSOR_HOT_SPOT_Y, pos->y_hotspot);
 906
 907         REG_SET(CURSOR_DST_OFFSET, 0,
 908                         CURSOR_DST_X_OFFSET, dst_x_offset);
 909         /* TODO Handle surface pixel formats other than 4:4:4 */
 910 }
 911
 912 static struct hubp_funcs dcn10_hubp_funcs = {
 913         .hubp_program_surface_flip_and_addr =
 914                         hubp1_program_surface_flip_and_addr,
 915         .hubp_program_surface_config =
 916                         hubp1_program_surface_config,
 917         .hubp_is_flip_pending = hubp1_is_flip_pending,
 918         .hubp_setup = hubp1_setup,
 919         .hubp_set_vm_system_aperture_settings = hubp1_set_vm_system_aperture_settings,
 920         .hubp_set_vm_context0_settings = hubp1_set_vm_context0_settings,
 921         .set_blank = hubp1_set_blank,
 922         .dcc_control = hubp1_dcc_control,
 923         .mem_program_viewport = min_set_viewport,
 924         .set_hubp_blank_en = hubp1_set_hubp_blank_en,
 925         .set_cursor_attributes  = hubp1_cursor_set_attributes,
 926         .set_cursor_position    = hubp1_cursor_set_position,
 927         .hubp_disconnect = hubp1_disconnect,
 928 };
 929
 930 /*****************************************/
 931 /* Constructor, Destructor               */
 932 /*****************************************/
 933
 934 void dcn10_hubp_construct(
 935         struct dcn10_hubp *hubp1,
 936         struct dc_context *ctx,
 937         uint32_t inst,
 938         const struct dcn_mi_registers *hubp_regs,
 939         const struct dcn_mi_shift *hubp_shift,
 940         const struct dcn_mi_mask *hubp_mask)
 941 {
 942         hubp1->base.funcs = &dcn10_hubp_funcs;
 943         hubp1->base.ctx = ctx;
 944         hubp1->hubp_regs = hubp_regs;
 945         hubp1->hubp_shift = hubp_shift;
 946         hubp1->hubp_mask = hubp_mask;
 947         hubp1->base.inst = inst;
 948         hubp1->base.opp_id = 0xf;
 949         hubp1->base.mpcc_id = 0xf;
 950 }
 951
 952