drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27 #include "dcn10_hubp.h"
  28 #include "dcn10_hubbub.h"
  29 #include "reg_helper.h"
  30
  31 #define CTX \
  32         hubbub1->base.ctx
  33 #define DC_LOGGER \
  34         hubbub1->base.ctx->logger
  35 #define REG(reg)\
  36         hubbub1->regs->reg
  37
  38 #undef FN
  39 #define FN(reg_name, field_name) \
  40         hubbub1->shifts->field_name, hubbub1->masks->field_name
  41
  42 void hubbub1_wm_read_state(struct hubbub *hubbub,
  43                 struct dcn_hubbub_wm *wm)
  44 {
  45         struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub);
  46         struct dcn_hubbub_wm_set *s;
  47
  48         memset(wm, 0, sizeof(struct dcn_hubbub_wm));
  49
  50         s = &wm->sets[0];
  51         s->wm_set = 0;
  52         s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A);
  53         s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A);
  54         if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A)) {
  55                 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A);
  56                 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A);
  57         }
  58         s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A);
  59
  60         s = &wm->sets[1];
  61         s->wm_set = 1;
  62         s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B);
  63         s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B);
  64         if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B)) {
  65                 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B);
  66                 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B);
  67         }
  68         s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B);
  69
  70         s = &wm->sets[2];
  71         s->wm_set = 2;
  72         s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C);
  73         s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C);
  74         if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C)) {
  75                 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C);
  76                 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C);
  77         }
  78         s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C);
  79
  80         s = &wm->sets[3];
  81         s->wm_set = 3;
  82         s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D);
  83         s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D);
  84         if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D)) {
  85                 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D);
  86                 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D);
  87         }
  88         s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D);
  89 }
  90
  91 void hubbub1_disable_allow_self_refresh(struct hubbub *hubbub)
  92 {
  93         struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub);
  94         REG_UPDATE(DCHUBBUB_ARB_DRAM_STATE_CNTL,
  95                         DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, 0);
  96 }
  97
  98 bool hububu1_is_allow_self_refresh_enabled(struct hubbub *hubbub)
  99 {
 100         struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub);
 101         uint32_t enable = 0;
 102
 103         REG_GET(DCHUBBUB_ARB_DRAM_STATE_CNTL,
 104                         DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, &enable);
 105
 106         return enable ? true : false;
 107 }
 108
 109
 110 bool hubbub1_verify_allow_pstate_change_high(
 111         struct hubbub *hubbub)
 112 {
 113         struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub);
 114
 115         /* pstate latency is ~20us so if we wait over 40us and pstate allow
 116          * still not asserted, we are probably stuck and going to hang
 117          *
 118          * TODO: Figure out why it takes ~100us on linux
 119          * pstate takes around ~100us on linux. Unknown currently as to
 120          * why it takes that long on linux
 121          */
 122         static unsigned int pstate_wait_timeout_us = 200;
 123         static unsigned int pstate_wait_expected_timeout_us = 40;
 124         static unsigned int max_sampled_pstate_wait_us; /* data collection */
 125         static bool forced_pstate_allow; /* help with revert wa */
 126
 127         unsigned int debug_data;
 128         unsigned int i;
 129
 130         if (forced_pstate_allow) {
 131                 /* we hacked to force pstate allow to prevent hang last time
 132                  * we verify_allow_pstate_change_high.  so disable force
 133                  * here so we can check status
 134                  */
 135                 REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL,
 136                              DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE, 0,
 137                              DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, 0);
 138                 forced_pstate_allow = false;
 139         }
 140
 141         /* RV2:
 142          * dchubbubdebugind, at: 0xB
 143          * description
 144          * 0:     Pipe0 Plane0 Allow Pstate Change
 145          * 1:     Pipe0 Plane1 Allow Pstate Change
 146          * 2:     Pipe0 Cursor0 Allow Pstate Change
 147          * 3:     Pipe0 Cursor1 Allow Pstate Change
 148          * 4:     Pipe1 Plane0 Allow Pstate Change
 149          * 5:     Pipe1 Plane1 Allow Pstate Change
 150          * 6:     Pipe1 Cursor0 Allow Pstate Change
 151          * 7:     Pipe1 Cursor1 Allow Pstate Change
 152          * 8:     Pipe2 Plane0 Allow Pstate Change
 153          * 9:     Pipe2 Plane1 Allow Pstate Change
 154          * 10:    Pipe2 Cursor0 Allow Pstate Change
 155          * 11:    Pipe2 Cursor1 Allow Pstate Change
 156          * 12:    Pipe3 Plane0 Allow Pstate Change
 157          * 13:    Pipe3 Plane1 Allow Pstate Change
 158          * 14:    Pipe3 Cursor0 Allow Pstate Change
 159          * 15:    Pipe3 Cursor1 Allow Pstate Change
 160          * 16:    Pipe4 Plane0 Allow Pstate Change
 161          * 17:    Pipe4 Plane1 Allow Pstate Change
 162          * 18:    Pipe4 Cursor0 Allow Pstate Change
 163          * 19:    Pipe4 Cursor1 Allow Pstate Change
 164          * 20:    Pipe5 Plane0 Allow Pstate Change
 165          * 21:    Pipe5 Plane1 Allow Pstate Change
 166          * 22:    Pipe5 Cursor0 Allow Pstate Change
 167          * 23:    Pipe5 Cursor1 Allow Pstate Change
 168          * 24:    Pipe6 Plane0 Allow Pstate Change
 169          * 25:    Pipe6 Plane1 Allow Pstate Change
 170          * 26:    Pipe6 Cursor0 Allow Pstate Change
 171          * 27:    Pipe6 Cursor1 Allow Pstate Change
 172          * 28:    WB0 Allow Pstate Change
 173          * 29:    WB1 Allow Pstate Change
 174          * 30:    Arbiter's allow_pstate_change
 175          * 31:    SOC pstate change request"
 176          *
 177          * RV1:
 178          * dchubbubdebugind, at: 0x7
 179          * description "3-0:   Pipe0 cursor0 QOS
 180          * 7-4:   Pipe1 cursor0 QOS
 181          * 11-8:  Pipe2 cursor0 QOS
 182          * 15-12: Pipe3 cursor0 QOS
 183          * 16:    Pipe0 Plane0 Allow Pstate Change
 184          * 17:    Pipe1 Plane0 Allow Pstate Change
 185          * 18:    Pipe2 Plane0 Allow Pstate Change
 186          * 19:    Pipe3 Plane0 Allow Pstate Change
 187          * 20:    Pipe0 Plane1 Allow Pstate Change
 188          * 21:    Pipe1 Plane1 Allow Pstate Change
 189          * 22:    Pipe2 Plane1 Allow Pstate Change
 190          * 23:    Pipe3 Plane1 Allow Pstate Change
 191          * 24:    Pipe0 cursor0 Allow Pstate Change
 192          * 25:    Pipe1 cursor0 Allow Pstate Change
 193          * 26:    Pipe2 cursor0 Allow Pstate Change
 194          * 27:    Pipe3 cursor0 Allow Pstate Change
 195          * 28:    WB0 Allow Pstate Change
 196          * 29:    WB1 Allow Pstate Change
 197          * 30:    Arbiter's allow_pstate_change
 198          * 31:    SOC pstate change request
 199          */
 200
 201         REG_WRITE(DCHUBBUB_TEST_DEBUG_INDEX, hubbub1->debug_test_index_pstate);
 202
 203         for (i = 0; i < pstate_wait_timeout_us; i++) {
 204                 debug_data = REG_READ(DCHUBBUB_TEST_DEBUG_DATA);
 205
 206                 if (debug_data & (1 << 30)) {
 207
 208                         if (i > pstate_wait_expected_timeout_us)
 209                                 DC_LOG_WARNING("pstate took longer than expected ~%dus\n",
 210                                                 i);
 211
 212                         return true;
 213                 }
 214                 if (max_sampled_pstate_wait_us < i)
 215                         max_sampled_pstate_wait_us = i;
 216
 217                 udelay(1);
 218         }
 219
 220         /* force pstate allow to prevent system hang
 221          * and break to debugger to investigate
 222          */
 223         REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL,
 224                      DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE, 1,
 225                      DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, 1);
 226         forced_pstate_allow = true;
 227
 228         DC_LOG_WARNING("pstate TEST_DEBUG_DATA: 0x%X\n",
 229                         debug_data);
 230
 231         return false;
 232 }
 233
 234 static uint32_t convert_and_clamp(
 235         uint32_t wm_ns,
 236         uint32_t refclk_mhz,
 237         uint32_t clamp_value)
 238 {
 239         uint32_t ret_val = 0;
 240         ret_val = wm_ns * refclk_mhz;
 241         ret_val /= 1000;
 242
 243         if (ret_val > clamp_value)
 244                 ret_val = clamp_value;
 245
 246         return ret_val;
 247 }
 248
 249
 250 void hubbub1_wm_change_req_wa(struct hubbub *hubbub)
 251 {
 252         struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub);
 253
 254         REG_UPDATE_SEQ(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
 255                         DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 0, 1);
 256 }
 257
 258 void hubbub1_program_watermarks(
 259                 struct hubbub *hubbub,
 260                 struct dcn_watermark_set *watermarks,
 261                 unsigned int refclk_mhz,
 262                 bool safe_to_lower)
 263 {
 264         struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub);
 265
 266         uint32_t force_en = hubbub1->base.ctx->dc->debug.disable_stutter ? 1 : 0;
 267         /*
 268          * Need to clamp to max of the register values (i.e. no wrap)
 269          * for dcn1, all wm registers are 21-bit wide
 270          */
 271         uint32_t prog_wm_value;
 272
 273
 274         /* Repeat for water mark set A, B, C and D. */
 275         /* clock state A */
 276         if (safe_to_lower || watermarks->a.urgent_ns > hubbub1->watermarks.a.urgent_ns) {
 277                 hubbub1->watermarks.a.urgent_ns = watermarks->a.urgent_ns;
 278                 prog_wm_value = convert_and_clamp(watermarks->a.urgent_ns,
 279                                 refclk_mhz, 0x1fffff);
 280                 REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, prog_wm_value);
 281
 282                 DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_A calculated =%d\n"
 283                         "HW register value = 0x%x\n",
 284                         watermarks->a.urgent_ns, prog_wm_value);
 285         }
 286
 287         if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A)) {
 288                 if (safe_to_lower || watermarks->a.pte_meta_urgent_ns > hubbub1->watermarks.a.pte_meta_urgent_ns) {
 289                         hubbub1->watermarks.a.pte_meta_urgent_ns = watermarks->a.pte_meta_urgent_ns;
 290                         prog_wm_value = convert_and_clamp(watermarks->a.pte_meta_urgent_ns,
 291                                         refclk_mhz, 0x1fffff);
 292                         REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A, prog_wm_value);
 293                         DC_LOG_BANDWIDTH_CALCS("PTE_META_URGENCY_WATERMARK_A calculated =%d\n"
 294                                 "HW register value = 0x%x\n",
 295                                 watermarks->a.pte_meta_urgent_ns, prog_wm_value);
 296                 }
 297         }
 298
 299         if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A)) {
 300                 if (safe_to_lower || watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns
 301                                 > hubbub1->watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns) {
 302                         hubbub1->watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns =
 303                                         watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns;
 304                         prog_wm_value = convert_and_clamp(
 305                                         watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns,
 306                                         refclk_mhz, 0x1fffff);
 307                         REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, prog_wm_value);
 308                         DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_A calculated =%d\n"
 309                                 "HW register value = 0x%x\n",
 310                                 watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
 311                 }
 312
 313                 if (safe_to_lower || watermarks->a.cstate_pstate.cstate_exit_ns
 314                                 > hubbub1->watermarks.a.cstate_pstate.cstate_exit_ns) {
 315                         hubbub1->watermarks.a.cstate_pstate.cstate_exit_ns =
 316                                         watermarks->a.cstate_pstate.cstate_exit_ns;
 317                         prog_wm_value = convert_and_clamp(
 318                                         watermarks->a.cstate_pstate.cstate_exit_ns,
 319                                         refclk_mhz, 0x1fffff);
 320                         REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value);
 321                         DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_A calculated =%d\n"
 322                                 "HW register value = 0x%x\n",
 323                                 watermarks->a.cstate_pstate.cstate_exit_ns, prog_wm_value);
 324                 }
 325         }
 326
 327         if (safe_to_lower || watermarks->a.cstate_pstate.pstate_change_ns
 328                         > hubbub1->watermarks.a.cstate_pstate.pstate_change_ns) {
 329                 hubbub1->watermarks.a.cstate_pstate.pstate_change_ns =
 330                                 watermarks->a.cstate_pstate.pstate_change_ns;
 331                 prog_wm_value = convert_and_clamp(
 332                                 watermarks->a.cstate_pstate.pstate_change_ns,
 333                                 refclk_mhz, 0x1fffff);
 334                 REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, prog_wm_value);
 335                 DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_A calculated =%d\n"
 336                         "HW register value = 0x%x\n\n",
 337                         watermarks->a.cstate_pstate.pstate_change_ns, prog_wm_value);
 338         }
 339
 340         /* clock state B */
 341         if (safe_to_lower || watermarks->b.urgent_ns > hubbub1->watermarks.b.urgent_ns) {
 342                 hubbub1->watermarks.b.urgent_ns = watermarks->b.urgent_ns;
 343                 prog_wm_value = convert_and_clamp(watermarks->b.urgent_ns,
 344                                 refclk_mhz, 0x1fffff);
 345                 REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, prog_wm_value);
 346
 347                 DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_B calculated =%d\n"
 348                         "HW register value = 0x%x\n",
 349                         watermarks->b.urgent_ns, prog_wm_value);
 350         }
 351
 352         if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B)) {
 353                 if (safe_to_lower || watermarks->b.pte_meta_urgent_ns > hubbub1->watermarks.b.pte_meta_urgent_ns) {
 354                         hubbub1->watermarks.b.pte_meta_urgent_ns = watermarks->b.pte_meta_urgent_ns;
 355                         prog_wm_value = convert_and_clamp(watermarks->b.pte_meta_urgent_ns,
 356                                         refclk_mhz, 0x1fffff);
 357                         REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B, prog_wm_value);
 358                         DC_LOG_BANDWIDTH_CALCS("PTE_META_URGENCY_WATERMARK_B calculated =%d\n"
 359                                 "HW register value = 0x%x\n",
 360                                 watermarks->b.pte_meta_urgent_ns, prog_wm_value);
 361                 }
 362         }
 363
 364         if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B)) {
 365                 if (safe_to_lower || watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns
 366                                 > hubbub1->watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns) {
 367                         hubbub1->watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns =
 368                                         watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns;
 369                         prog_wm_value = convert_and_clamp(
 370                                         watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns,
 371                                         refclk_mhz, 0x1fffff);
 372                         REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, prog_wm_value);
 373                         DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_B calculated =%d\n"
 374                                 "HW register value = 0x%x\n",
 375                                 watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
 376                 }
 377
 378                 if (safe_to_lower || watermarks->b.cstate_pstate.cstate_exit_ns
 379                                 > hubbub1->watermarks.b.cstate_pstate.cstate_exit_ns) {
 380                         hubbub1->watermarks.b.cstate_pstate.cstate_exit_ns =
 381                                         watermarks->b.cstate_pstate.cstate_exit_ns;
 382                         prog_wm_value = convert_and_clamp(
 383                                         watermarks->b.cstate_pstate.cstate_exit_ns,
 384                                         refclk_mhz, 0x1fffff);
 385                         REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, prog_wm_value);
 386                         DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_B calculated =%d\n"
 387                                 "HW register value = 0x%x\n",
 388                                 watermarks->b.cstate_pstate.cstate_exit_ns, prog_wm_value);
 389                 }
 390         }
 391
 392         if (safe_to_lower || watermarks->b.cstate_pstate.pstate_change_ns
 393                         > hubbub1->watermarks.b.cstate_pstate.pstate_change_ns) {
 394                 hubbub1->watermarks.b.cstate_pstate.pstate_change_ns =
 395                                 watermarks->b.cstate_pstate.pstate_change_ns;
 396                 prog_wm_value = convert_and_clamp(
 397                                 watermarks->b.cstate_pstate.pstate_change_ns,
 398                                 refclk_mhz, 0x1fffff);
 399                 REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, prog_wm_value);
 400                 DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_B calculated =%d\n"
 401                         "HW register value = 0x%x\n\n",
 402                         watermarks->b.cstate_pstate.pstate_change_ns, prog_wm_value);
 403         }
 404
 405         /* clock state C */
 406         if (safe_to_lower || watermarks->c.urgent_ns > hubbub1->watermarks.c.urgent_ns) {
 407                 hubbub1->watermarks.c.urgent_ns = watermarks->c.urgent_ns;
 408                 prog_wm_value = convert_and_clamp(watermarks->c.urgent_ns,
 409                                 refclk_mhz, 0x1fffff);
 410                 REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, prog_wm_value);
 411
 412                 DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_C calculated =%d\n"
 413                         "HW register value = 0x%x\n",
 414                         watermarks->c.urgent_ns, prog_wm_value);
 415         }
 416
 417         if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C)) {
 418                 if (safe_to_lower || watermarks->c.pte_meta_urgent_ns > hubbub1->watermarks.c.pte_meta_urgent_ns) {
 419                         hubbub1->watermarks.c.pte_meta_urgent_ns = watermarks->c.pte_meta_urgent_ns;
 420                         prog_wm_value = convert_and_clamp(watermarks->c.pte_meta_urgent_ns,
 421                                         refclk_mhz, 0x1fffff);
 422                         REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C, prog_wm_value);
 423                         DC_LOG_BANDWIDTH_CALCS("PTE_META_URGENCY_WATERMARK_C calculated =%d\n"
 424                                 "HW register value = 0x%x\n",
 425                                 watermarks->c.pte_meta_urgent_ns, prog_wm_value);
 426                 }
 427         }
 428
 429         if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C)) {
 430                 if (safe_to_lower || watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns
 431                                 > hubbub1->watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns) {
 432                         hubbub1->watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns =
 433                                         watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns;
 434                         prog_wm_value = convert_and_clamp(
 435                                         watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns,
 436                                         refclk_mhz, 0x1fffff);
 437                         REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, prog_wm_value);
 438                         DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_C calculated =%d\n"
 439                                 "HW register value = 0x%x\n",
 440                                 watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
 441                 }
 442
 443                 if (safe_to_lower || watermarks->c.cstate_pstate.cstate_exit_ns
 444                                 > hubbub1->watermarks.c.cstate_pstate.cstate_exit_ns) {
 445                         hubbub1->watermarks.c.cstate_pstate.cstate_exit_ns =
 446                                         watermarks->c.cstate_pstate.cstate_exit_ns;
 447                         prog_wm_value = convert_and_clamp(
 448                                         watermarks->c.cstate_pstate.cstate_exit_ns,
 449                                         refclk_mhz, 0x1fffff);
 450                         REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, prog_wm_value);
 451                         DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_C calculated =%d\n"
 452                                 "HW register value = 0x%x\n",
 453                                 watermarks->c.cstate_pstate.cstate_exit_ns, prog_wm_value);
 454                 }
 455         }
 456
 457         if (safe_to_lower || watermarks->c.cstate_pstate.pstate_change_ns
 458                         > hubbub1->watermarks.c.cstate_pstate.pstate_change_ns) {
 459                 hubbub1->watermarks.c.cstate_pstate.pstate_change_ns =
 460                                 watermarks->c.cstate_pstate.pstate_change_ns;
 461                 prog_wm_value = convert_and_clamp(
 462                                 watermarks->c.cstate_pstate.pstate_change_ns,
 463                                 refclk_mhz, 0x1fffff);
 464                 REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, prog_wm_value);
 465                 DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_C calculated =%d\n"
 466                         "HW register value = 0x%x\n\n",
 467                         watermarks->c.cstate_pstate.pstate_change_ns, prog_wm_value);
 468         }
 469
 470         /* clock state D */
 471         if (safe_to_lower || watermarks->d.urgent_ns > hubbub1->watermarks.d.urgent_ns) {
 472                 hubbub1->watermarks.d.urgent_ns = watermarks->d.urgent_ns;
 473                 prog_wm_value = convert_and_clamp(watermarks->d.urgent_ns,
 474                                 refclk_mhz, 0x1fffff);
 475                 REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, prog_wm_value);
 476
 477                 DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_D calculated =%d\n"
 478                         "HW register value = 0x%x\n",
 479                         watermarks->d.urgent_ns, prog_wm_value);
 480         }
 481
 482         if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D)) {
 483                 if (safe_to_lower || watermarks->d.pte_meta_urgent_ns > hubbub1->watermarks.d.pte_meta_urgent_ns) {
 484                         hubbub1->watermarks.d.pte_meta_urgent_ns = watermarks->d.pte_meta_urgent_ns;
 485                         prog_wm_value = convert_and_clamp(watermarks->d.pte_meta_urgent_ns,
 486                                         refclk_mhz, 0x1fffff);
 487                         REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D, prog_wm_value);
 488                         DC_LOG_BANDWIDTH_CALCS("PTE_META_URGENCY_WATERMARK_D calculated =%d\n"
 489                                 "HW register value = 0x%x\n",
 490                                 watermarks->d.pte_meta_urgent_ns, prog_wm_value);
 491                 }
 492         }
 493
 494         if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D)) {
 495                 if (safe_to_lower || watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns
 496                                 > hubbub1->watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns) {
 497                         hubbub1->watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns =
 498                                         watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns;
 499                         prog_wm_value = convert_and_clamp(
 500                                         watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns,
 501                                         refclk_mhz, 0x1fffff);
 502                         REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, prog_wm_value);
 503                         DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_D calculated =%d\n"
 504                                 "HW register value = 0x%x\n",
 505                                 watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
 506                 }
 507
 508                 if (safe_to_lower || watermarks->d.cstate_pstate.cstate_exit_ns
 509                                 > hubbub1->watermarks.d.cstate_pstate.cstate_exit_ns) {
 510                         hubbub1->watermarks.d.cstate_pstate.cstate_exit_ns =
 511                                         watermarks->d.cstate_pstate.cstate_exit_ns;
 512                         prog_wm_value = convert_and_clamp(
 513                                         watermarks->d.cstate_pstate.cstate_exit_ns,
 514                                         refclk_mhz, 0x1fffff);
 515                         REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, prog_wm_value);
 516                         DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_D calculated =%d\n"
 517                                 "HW register value = 0x%x\n",
 518                                 watermarks->d.cstate_pstate.cstate_exit_ns, prog_wm_value);
 519                 }
 520         }
 521
 522         if (safe_to_lower || watermarks->d.cstate_pstate.pstate_change_ns
 523                         > hubbub1->watermarks.d.cstate_pstate.pstate_change_ns) {
 524                 hubbub1->watermarks.d.cstate_pstate.pstate_change_ns =
 525                                 watermarks->d.cstate_pstate.pstate_change_ns;
 526                 prog_wm_value = convert_and_clamp(
 527                                 watermarks->d.cstate_pstate.pstate_change_ns,
 528                                 refclk_mhz, 0x1fffff);
 529                 REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, prog_wm_value);
 530                 DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_D calculated =%d\n"
 531                         "HW register value = 0x%x\n\n",
 532                         watermarks->d.cstate_pstate.pstate_change_ns, prog_wm_value);
 533         }
 534
 535         REG_UPDATE(DCHUBBUB_ARB_SAT_LEVEL,
 536                         DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz);
 537         REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND,
 538                         DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 68);
 539
 540         REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL,
 541                         DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, 0,
 542                         DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, force_en);
 543
 544 #if 0
 545         REG_UPDATE_2(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
 546                         DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, 1,
 547                         DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 1);
 548 #endif
 549 }
 550
 551 void hubbub1_update_dchub(
 552         struct hubbub *hubbub,
 553         struct dchub_init_data *dh_data)
 554 {
 555         struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub);
 556
 557         if (REG(DCHUBBUB_SDPIF_FB_TOP) == 0) {
 558                 ASSERT(false);
 559                 /*should not come here*/
 560                 return;
 561         }
 562         /* TODO: port code from dal2 */
 563         switch (dh_data->fb_mode) {
 564         case FRAME_BUFFER_MODE_ZFB_ONLY:
 565                 /*For ZFB case need to put DCHUB FB BASE and TOP upside down to indicate ZFB mode*/
 566                 REG_UPDATE(DCHUBBUB_SDPIF_FB_TOP,
 567                                 SDPIF_FB_TOP, 0);
 568
 569                 REG_UPDATE(DCHUBBUB_SDPIF_FB_BASE,
 570                                 SDPIF_FB_BASE, 0x0FFFF);
 571
 572                 REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE,
 573                                 SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
 574
 575                 REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT,
 576                                 SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
 577
 578                 REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP,
 579                                 SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr +
 580                                                 dh_data->zfb_size_in_byte - 1) >> 22);
 581                 break;
 582         case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL:
 583                 /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
 584
 585                 REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE,
 586                                 SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
 587
 588                 REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT,
 589                                 SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
 590
 591                 REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP,
 592                                 SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr +
 593                                                 dh_data->zfb_size_in_byte - 1) >> 22);
 594                 break;
 595         case FRAME_BUFFER_MODE_LOCAL_ONLY:
 596                 /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
 597                 REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE,
 598                                 SDPIF_AGP_BASE, 0);
 599
 600                 REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT,
 601                                 SDPIF_AGP_BOT, 0X03FFFF);
 602
 603                 REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP,
 604                                 SDPIF_AGP_TOP, 0);
 605                 break;
 606         default:
 607                 break;
 608         }
 609
 610         dh_data->dchub_initialzied = true;
 611         dh_data->dchub_info_valid = false;
 612 }
 613
 614 void hubbub1_toggle_watermark_change_req(struct hubbub *hubbub)
 615 {
 616         struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub);
 617
 618         uint32_t watermark_change_req;
 619
 620         REG_GET(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
 621                         DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, &watermark_change_req);
 622
 623         if (watermark_change_req)
 624                 watermark_change_req = 0;
 625         else
 626                 watermark_change_req = 1;
 627
 628         REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
 629                         DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, watermark_change_req);
 630 }
 631
 632 void hubbub1_soft_reset(struct hubbub *hubbub, bool reset)
 633 {
 634         struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub);
 635
 636         uint32_t reset_en = reset ? 1 : 0;
 637
 638         REG_UPDATE(DCHUBBUB_SOFT_RESET,
 639                         DCHUBBUB_GLOBAL_SOFT_RESET, reset_en);
 640 }
 641
 642 static bool hubbub1_dcc_support_swizzle(
 643                 enum swizzle_mode_values swizzle,
 644                 unsigned int bytes_per_element,
 645                 enum segment_order *segment_order_horz,
 646                 enum segment_order *segment_order_vert)
 647 {
 648         bool standard_swizzle = false;
 649         bool display_swizzle = false;
 650
 651         switch (swizzle) {
 652         case DC_SW_4KB_S:
 653         case DC_SW_64KB_S:
 654         case DC_SW_VAR_S:
 655         case DC_SW_4KB_S_X:
 656         case DC_SW_64KB_S_X:
 657         case DC_SW_VAR_S_X:
 658                 standard_swizzle = true;
 659                 break;
 660         case DC_SW_4KB_D:
 661         case DC_SW_64KB_D:
 662         case DC_SW_VAR_D:
 663         case DC_SW_4KB_D_X:
 664         case DC_SW_64KB_D_X:
 665         case DC_SW_VAR_D_X:
 666                 display_swizzle = true;
 667                 break;
 668         default:
 669                 break;
 670         }
 671
 672         if (bytes_per_element == 1 && standard_swizzle) {
 673                 *segment_order_horz = segment_order__contiguous;
 674                 *segment_order_vert = segment_order__na;
 675                 return true;
 676         }
 677         if (bytes_per_element == 2 && standard_swizzle) {
 678                 *segment_order_horz = segment_order__non_contiguous;
 679                 *segment_order_vert = segment_order__contiguous;
 680                 return true;
 681         }
 682         if (bytes_per_element == 4 && standard_swizzle) {
 683                 *segment_order_horz = segment_order__non_contiguous;
 684                 *segment_order_vert = segment_order__contiguous;
 685                 return true;
 686         }
 687         if (bytes_per_element == 8 && standard_swizzle) {
 688                 *segment_order_horz = segment_order__na;
 689                 *segment_order_vert = segment_order__contiguous;
 690                 return true;
 691         }
 692         if (bytes_per_element == 8 && display_swizzle) {
 693                 *segment_order_horz = segment_order__contiguous;
 694                 *segment_order_vert = segment_order__non_contiguous;
 695                 return true;
 696         }
 697
 698         return false;
 699 }
 700
 701 static bool hubbub1_dcc_support_pixel_format(
 702                 enum surface_pixel_format format,
 703                 unsigned int *bytes_per_element)
 704 {
 705         /* DML: get_bytes_per_element */
 706         switch (format) {
 707         case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
 708         case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
 709                 *bytes_per_element = 2;
 710                 return true;
 711         case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
 712         case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
 713         case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
 714         case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
 715                 *bytes_per_element = 4;
 716                 return true;
 717         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
 718         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
 719         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
 720                 *bytes_per_element = 8;
 721                 return true;
 722         default:
 723                 return false;
 724         }
 725 }
 726
 727 static void hubbub1_get_blk256_size(unsigned int *blk256_width, unsigned int *blk256_height,
 728                 unsigned int bytes_per_element)
 729 {
 730         /* copied from DML.  might want to refactor DML to leverage from DML */
 731         /* DML : get_blk256_size */
 732         if (bytes_per_element == 1) {
 733                 *blk256_width = 16;
 734                 *blk256_height = 16;
 735         } else if (bytes_per_element == 2) {
 736                 *blk256_width = 16;
 737                 *blk256_height = 8;
 738         } else if (bytes_per_element == 4) {
 739                 *blk256_width = 8;
 740                 *blk256_height = 8;
 741         } else if (bytes_per_element == 8) {
 742                 *blk256_width = 8;
 743                 *blk256_height = 4;
 744         }
 745 }
 746
 747 static void hubbub1_det_request_size(
 748                 unsigned int height,
 749                 unsigned int width,
 750                 unsigned int bpe,
 751                 bool *req128_horz_wc,
 752                 bool *req128_vert_wc)
 753 {
 754         unsigned int detile_buf_size = 164 * 1024;  /* 164KB for DCN1.0 */
 755
 756         unsigned int blk256_height = 0;
 757         unsigned int blk256_width = 0;
 758         unsigned int swath_bytes_horz_wc, swath_bytes_vert_wc;
 759
 760         hubbub1_get_blk256_size(&blk256_width, &blk256_height, bpe);
 761
 762         swath_bytes_horz_wc = height * blk256_height * bpe;
 763         swath_bytes_vert_wc = width * blk256_width * bpe;
 764
 765         *req128_horz_wc = (2 * swath_bytes_horz_wc <= detile_buf_size) ?
 766                         false : /* full 256B request */
 767                         true; /* half 128b request */
 768
 769         *req128_vert_wc = (2 * swath_bytes_vert_wc <= detile_buf_size) ?
 770                         false : /* full 256B request */
 771                         true; /* half 128b request */
 772 }
 773
 774 static bool hubbub1_get_dcc_compression_cap(struct hubbub *hubbub,
 775                 const struct dc_dcc_surface_param *input,
 776                 struct dc_surface_dcc_cap *output)
 777 {
 778         struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub);
 779         struct dc *dc = hubbub1->base.ctx->dc;
 780
 781         /* implement section 1.6.2.1 of DCN1_Programming_Guide.docx */
 782         enum dcc_control dcc_control;
 783         unsigned int bpe;
 784         enum segment_order segment_order_horz, segment_order_vert;
 785         bool req128_horz_wc, req128_vert_wc;
 786
 787         memset(output, 0, sizeof(*output));
 788
 789         if (dc->debug.disable_dcc == DCC_DISABLE)
 790                 return false;
 791
 792         if (!hubbub1->base.funcs->dcc_support_pixel_format(input->format, &bpe))
 793                 return false;
 794
 795         if (!hubbub1->base.funcs->dcc_support_swizzle(input->swizzle_mode, bpe,
 796                         &segment_order_horz, &segment_order_vert))
 797                 return false;
 798
 799         hubbub1_det_request_size(input->surface_size.height,  input->surface_size.width,
 800                         bpe, &req128_horz_wc, &req128_vert_wc);
 801
 802         if (!req128_horz_wc && !req128_vert_wc) {
 803                 dcc_control = dcc_control__256_256_xxx;
 804         } else if (input->scan == SCAN_DIRECTION_HORIZONTAL) {
 805                 if (!req128_horz_wc)
 806                         dcc_control = dcc_control__256_256_xxx;
 807                 else if (segment_order_horz == segment_order__contiguous)
 808                         dcc_control = dcc_control__128_128_xxx;
 809                 else
 810                         dcc_control = dcc_control__256_64_64;
 811         } else if (input->scan == SCAN_DIRECTION_VERTICAL) {
 812                 if (!req128_vert_wc)
 813                         dcc_control = dcc_control__256_256_xxx;
 814                 else if (segment_order_vert == segment_order__contiguous)
 815                         dcc_control = dcc_control__128_128_xxx;
 816                 else
 817                         dcc_control = dcc_control__256_64_64;
 818         } else {
 819                 if ((req128_horz_wc &&
 820                         segment_order_horz == segment_order__non_contiguous) ||
 821                         (req128_vert_wc &&
 822                         segment_order_vert == segment_order__non_contiguous))
 823                         /* access_dir not known, must use most constraining */
 824                         dcc_control = dcc_control__256_64_64;
 825                 else
 826                         /* reg128 is true for either horz and vert
 827                          * but segment_order is contiguous
 828                          */
 829                         dcc_control = dcc_control__128_128_xxx;
 830         }
 831
 832         if (dc->debug.disable_dcc == DCC_HALF_REQ_DISALBE &&
 833                 dcc_control != dcc_control__256_256_xxx)
 834                 return false;
 835
 836         switch (dcc_control) {
 837         case dcc_control__256_256_xxx:
 838                 output->grph.rgb.max_uncompressed_blk_size = 256;
 839                 output->grph.rgb.max_compressed_blk_size = 256;
 840                 output->grph.rgb.independent_64b_blks = false;
 841                 break;
 842         case dcc_control__128_128_xxx:
 843                 output->grph.rgb.max_uncompressed_blk_size = 128;
 844                 output->grph.rgb.max_compressed_blk_size = 128;
 845                 output->grph.rgb.independent_64b_blks = false;
 846                 break;
 847         case dcc_control__256_64_64:
 848                 output->grph.rgb.max_uncompressed_blk_size = 256;
 849                 output->grph.rgb.max_compressed_blk_size = 64;
 850                 output->grph.rgb.independent_64b_blks = true;
 851                 break;
 852         }
 853
 854         output->capable = true;
 855         output->const_color_support = false;
 856
 857         return true;
 858 }
 859
 860 static const struct hubbub_funcs hubbub1_funcs = {
 861         .update_dchub = hubbub1_update_dchub,
 862         .dcc_support_swizzle = hubbub1_dcc_support_swizzle,
 863         .dcc_support_pixel_format = hubbub1_dcc_support_pixel_format,
 864         .get_dcc_compression_cap = hubbub1_get_dcc_compression_cap,
 865         .wm_read_state = hubbub1_wm_read_state,
 866 };
 867
 868 void hubbub1_construct(struct hubbub *hubbub,
 869         struct dc_context *ctx,
 870         const struct dcn_hubbub_registers *hubbub_regs,
 871         const struct dcn_hubbub_shift *hubbub_shift,
 872         const struct dcn_hubbub_mask *hubbub_mask)
 873 {
 874         struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub);
 875
 876         hubbub1->base.ctx = ctx;
 877
 878         hubbub1->base.funcs = &hubbub1_funcs;
 879
 880         hubbub1->regs = hubbub_regs;
 881         hubbub1->shifts = hubbub_shift;
 882         hubbub1->masks = hubbub_mask;
 883
 884         hubbub1->debug_test_index_pstate = 0x7;
 885 #if defined(CONFIG_DRM_AMD_DC_DCN1_01)
 886         if (ctx->dce_version == DCN_VERSION_1_01)
 887                 hubbub1->debug_test_index_pstate = 0xB;
 888 #endif
 889 }
 890