drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27
  28 #include "core_types.h"
  29
  30 #include "reg_helper.h"
  31 #include "dcn10_dpp.h"
  32 #include "basics/conversion.h"
  33
  34 #define NUM_PHASES    64
  35 #define HORZ_MAX_TAPS 8
  36 #define VERT_MAX_TAPS 8
  37
  38 #define BLACK_OFFSET_RGB_Y 0x0
  39 #define BLACK_OFFSET_CBCR  0x8000
  40
  41 #define REG(reg)\
  42         dpp->tf_regs->reg
  43
  44 #define CTX \
  45         dpp->base.ctx
  46
  47 #undef FN
  48 #define FN(reg_name, field_name) \
  49         dpp->tf_shift->field_name, dpp->tf_mask->field_name
  50
  51 enum pixel_format_description {
  52         PIXEL_FORMAT_FIXED = 0,
  53         PIXEL_FORMAT_FIXED16,
  54         PIXEL_FORMAT_FLOAT
  55
  56 };
  57
  58 enum dcn10_coef_filter_type_sel {
  59         SCL_COEF_LUMA_VERT_FILTER = 0,
  60         SCL_COEF_LUMA_HORZ_FILTER = 1,
  61         SCL_COEF_CHROMA_VERT_FILTER = 2,
  62         SCL_COEF_CHROMA_HORZ_FILTER = 3,
  63         SCL_COEF_ALPHA_VERT_FILTER = 4,
  64         SCL_COEF_ALPHA_HORZ_FILTER = 5
  65 };
  66
  67 enum dscl_autocal_mode {
  68         AUTOCAL_MODE_OFF = 0,
  69
  70         /* Autocal calculate the scaling ratio and initial phase and the
  71          * DSCL_MODE_SEL must be set to 1
  72          */
  73         AUTOCAL_MODE_AUTOSCALE = 1,
  74         /* Autocal perform auto centering without replication and the
  75          * DSCL_MODE_SEL must be set to 0
  76          */
  77         AUTOCAL_MODE_AUTOCENTER = 2,
  78         /* Autocal perform auto centering and auto replication and the
  79          * DSCL_MODE_SEL must be set to 0
  80          */
  81         AUTOCAL_MODE_AUTOREPLICATE = 3
  82 };
  83
  84 enum dscl_mode_sel {
  85         DSCL_MODE_SCALING_444_BYPASS = 0,
  86         DSCL_MODE_SCALING_444_RGB_ENABLE = 1,
  87         DSCL_MODE_SCALING_444_YCBCR_ENABLE = 2,
  88         DSCL_MODE_SCALING_420_YCBCR_ENABLE = 3,
  89         DSCL_MODE_SCALING_420_LUMA_BYPASS = 4,
  90         DSCL_MODE_SCALING_420_CHROMA_BYPASS = 5,
  91         DSCL_MODE_DSCL_BYPASS = 6
  92 };
  93
  94 enum gamut_remap_select {
  95         GAMUT_REMAP_BYPASS = 0,
  96         GAMUT_REMAP_COEFF,
  97         GAMUT_REMAP_COMA_COEFF,
  98         GAMUT_REMAP_COMB_COEFF
  99 };
 100
 101 /* Program gamut remap in bypass mode */
 102 void dpp_set_gamut_remap_bypass(struct dcn10_dpp *dpp)
 103 {
 104         REG_SET(CM_GAMUT_REMAP_CONTROL, 0,
 105                         CM_GAMUT_REMAP_MODE, 0);
 106         /* Gamut remap in bypass */
 107 }
 108
 109 #define IDENTITY_RATIO(ratio) (dal_fixed31_32_u2d19(ratio) == (1 << 19))
 110
 111
 112 bool dpp_get_optimal_number_of_taps(
 113                 struct dpp *dpp,
 114                 struct scaler_data *scl_data,
 115                 const struct scaling_taps *in_taps)
 116 {
 117         uint32_t pixel_width;
 118
 119         if (scl_data->viewport.width > scl_data->recout.width)
 120                 pixel_width = scl_data->recout.width;
 121         else
 122                 pixel_width = scl_data->viewport.width;
 123
 124         /* TODO: add lb check */
 125
 126         /* No support for programming ratio of 4, drop to 3.99999.. */
 127         if (scl_data->ratios.horz.value == (4ll << 32))
 128                 scl_data->ratios.horz.value--;
 129         if (scl_data->ratios.vert.value == (4ll << 32))
 130                 scl_data->ratios.vert.value--;
 131         if (scl_data->ratios.horz_c.value == (4ll << 32))
 132                 scl_data->ratios.horz_c.value--;
 133         if (scl_data->ratios.vert_c.value == (4ll << 32))
 134                 scl_data->ratios.vert_c.value--;
 135
 136         /* Set default taps if none are provided */
 137         if (in_taps->h_taps == 0)
 138                 scl_data->taps.h_taps = 4;
 139         else
 140                 scl_data->taps.h_taps = in_taps->h_taps;
 141         if (in_taps->v_taps == 0)
 142                 scl_data->taps.v_taps = 4;
 143         else
 144                 scl_data->taps.v_taps = in_taps->v_taps;
 145         if (in_taps->v_taps_c == 0)
 146                 scl_data->taps.v_taps_c = 2;
 147         else
 148                 scl_data->taps.v_taps_c = in_taps->v_taps_c;
 149         if (in_taps->h_taps_c == 0)
 150                 scl_data->taps.h_taps_c = 2;
 151         /* Only 1 and even h_taps_c are supported by hw */
 152         else if ((in_taps->h_taps_c % 2) != 0 && in_taps->h_taps_c != 1)
 153                 scl_data->taps.h_taps_c = in_taps->h_taps_c - 1;
 154         else
 155                 scl_data->taps.h_taps_c = in_taps->h_taps_c;
 156
 157         if (!dpp->ctx->dc->debug.always_scale) {
 158                 if (IDENTITY_RATIO(scl_data->ratios.horz))
 159                         scl_data->taps.h_taps = 1;
 160                 if (IDENTITY_RATIO(scl_data->ratios.vert))
 161                         scl_data->taps.v_taps = 1;
 162                 /*
 163                  * Spreadsheet doesn't handle taps_c is one properly,
 164                  * need to force Chroma to always be scaled to pass
 165                  * bandwidth validation.
 166                  */
 167         }
 168
 169         return true;
 170 }
 171
 172 void dpp_reset(struct dpp *dpp_base)
 173 {
 174         struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 175
 176         dpp->filter_h_c = NULL;
 177         dpp->filter_v_c = NULL;
 178         dpp->filter_h = NULL;
 179         dpp->filter_v = NULL;
 180
 181         memset(&dpp->scl_data, 0, sizeof(dpp->scl_data));
 182         memset(&dpp->pwl_data, 0, sizeof(dpp->pwl_data));
 183 }
 184
 185
 186
 187 static void dpp1_cm_set_regamma_pwl(
 188         struct dpp *dpp_base, const struct pwl_params *params, enum opp_regamma mode)
 189 {
 190         struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 191         uint32_t re_mode;
 192
 193         switch (mode) {
 194         case OPP_REGAMMA_BYPASS:
 195                 re_mode = 0;
 196                 break;
 197         case OPP_REGAMMA_SRGB:
 198                 re_mode = 1;
 199                 break;
 200         case OPP_REGAMMA_3_6:
 201                 re_mode = 2;
 202                 break;
 203         case OPP_REGAMMA_USER:
 204                 re_mode = dpp->is_write_to_ram_a_safe ? 4 : 3;
 205                 if (memcmp(&dpp->pwl_data, params, sizeof(*params)) == 0)
 206                         break;
 207
 208                 dpp1_cm_power_on_regamma_lut(dpp_base, true);
 209                 dpp1_cm_configure_regamma_lut(dpp_base, dpp->is_write_to_ram_a_safe);
 210
 211                 if (dpp->is_write_to_ram_a_safe)
 212                         dpp1_cm_program_regamma_luta_settings(dpp_base, params);
 213                 else
 214                         dpp1_cm_program_regamma_lutb_settings(dpp_base, params);
 215
 216                 dpp1_cm_program_regamma_lut(
 217                                 dpp_base, params->rgb_resulted, params->hw_points_num);
 218                 dpp->pwl_data = *params;
 219
 220                 re_mode = dpp->is_write_to_ram_a_safe ? 3 : 4;
 221                 dpp->is_write_to_ram_a_safe = !dpp->is_write_to_ram_a_safe;
 222                 break;
 223         default:
 224                 break;
 225         }
 226         REG_SET(CM_RGAM_CONTROL, 0, CM_RGAM_LUT_MODE, re_mode);
 227 }
 228
 229 static void dpp1_setup_format_flags(enum surface_pixel_format input_format,\
 230                                                 enum pixel_format_description *fmt)
 231 {
 232
 233         if (input_format == SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F ||
 234                 input_format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F)
 235                 *fmt = PIXEL_FORMAT_FLOAT;
 236         else if (input_format == SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616)
 237                 *fmt = PIXEL_FORMAT_FIXED16;
 238         else
 239                 *fmt = PIXEL_FORMAT_FIXED;
 240 }
 241
 242 static void dpp1_set_degamma_format_float(
 243                 struct dpp *dpp_base,
 244                 bool is_float)
 245 {
 246         struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 247
 248         if (is_float) {
 249                 REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 3);
 250                 REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, 1);
 251         } else {
 252                 REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 2);
 253                 REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, 0);
 254         }
 255 }
 256
 257 void dpp1_cnv_setup (
 258                 struct dpp *dpp_base,
 259                 enum surface_pixel_format format,
 260                 enum expansion_mode mode,
 261                 struct csc_transform input_csc_color_matrix,
 262                 enum dc_color_space input_color_space)
 263 {
 264         uint32_t pixel_format;
 265         uint32_t alpha_en;
 266         enum pixel_format_description fmt ;
 267         enum dc_color_space color_space;
 268         enum dcn10_input_csc_select select;
 269         bool is_float;
 270         struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 271         bool force_disable_cursor = false;
 272         struct out_csc_color_matrix tbl_entry;
 273         int i = 0;
 274
 275         dpp1_setup_format_flags(format, &fmt);
 276         alpha_en = 1;
 277         pixel_format = 0;
 278         color_space = COLOR_SPACE_SRGB;
 279         select = INPUT_CSC_SELECT_BYPASS;
 280         is_float = false;
 281
 282         switch (fmt) {
 283         case PIXEL_FORMAT_FIXED:
 284         case PIXEL_FORMAT_FIXED16:
 285         /*when output is float then FORMAT_CONTROL__OUTPUT_FP=1*/
 286                 REG_SET_3(FORMAT_CONTROL, 0,
 287                         CNVC_BYPASS, 0,
 288                         FORMAT_EXPANSION_MODE, mode,
 289                         OUTPUT_FP, 0);
 290                 break;
 291         case PIXEL_FORMAT_FLOAT:
 292                 REG_SET_3(FORMAT_CONTROL, 0,
 293                         CNVC_BYPASS, 0,
 294                         FORMAT_EXPANSION_MODE, mode,
 295                         OUTPUT_FP, 1);
 296                 is_float = true;
 297                 break;
 298         default:
 299
 300                 break;
 301         }
 302
 303         dpp1_set_degamma_format_float(dpp_base, is_float);
 304
 305         switch (format) {
 306         case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
 307                 pixel_format = 1;
 308                 break;
 309         case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
 310                 pixel_format = 3;
 311                 alpha_en = 0;
 312                 break;
 313         case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
 314         case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
 315                 pixel_format = 8;
 316                 break;
 317         case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
 318         case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
 319                 pixel_format = 10;
 320                 break;
 321         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
 322                 force_disable_cursor = false;
 323                 pixel_format = 65;
 324                 color_space = COLOR_SPACE_YCBCR709;
 325                 select = INPUT_CSC_SELECT_ICSC;
 326                 break;
 327         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
 328                 force_disable_cursor = true;
 329                 pixel_format = 64;
 330                 color_space = COLOR_SPACE_YCBCR709;
 331                 select = INPUT_CSC_SELECT_ICSC;
 332                 break;
 333         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
 334                 force_disable_cursor = true;
 335                 pixel_format = 67;
 336                 color_space = COLOR_SPACE_YCBCR709;
 337                 select = INPUT_CSC_SELECT_ICSC;
 338                 break;
 339         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
 340                 force_disable_cursor = true;
 341                 pixel_format = 66;
 342                 color_space = COLOR_SPACE_YCBCR709;
 343                 select = INPUT_CSC_SELECT_ICSC;
 344                 break;
 345         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
 346                 pixel_format = 22;
 347                 break;
 348         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
 349                 pixel_format = 24;
 350                 break;
 351         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
 352                 pixel_format = 25;
 353                 break;
 354         default:
 355                 break;
 356         }
 357         REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0,
 358                         CNVC_SURFACE_PIXEL_FORMAT, pixel_format);
 359         REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en);
 360
 361         // if input adjustments exist, program icsc with those values
 362
 363         if (input_csc_color_matrix.enable_adjustment
 364                                 == true) {
 365                 for (i = 0; i < 12; i++)
 366                         tbl_entry.regval[i] = input_csc_color_matrix.matrix[i];
 367
 368                 tbl_entry.color_space = input_color_space;
 369
 370                 if (color_space >= COLOR_SPACE_YCBCR601)
 371                         select = INPUT_CSC_SELECT_ICSC;
 372                 else
 373                         select = INPUT_CSC_SELECT_BYPASS;
 374
 375                 dpp1_program_input_csc(dpp_base, color_space, select, &tbl_entry);
 376         } else
 377                 dpp1_program_input_csc(dpp_base, color_space, select, NULL);
 378
 379         if (force_disable_cursor) {
 380                 REG_UPDATE(CURSOR_CONTROL,
 381                                 CURSOR_ENABLE, 0);
 382                 REG_UPDATE(CURSOR0_CONTROL,
 383                                 CUR0_ENABLE, 0);
 384         }
 385 }
 386
 387 void dpp1_set_cursor_attributes(
 388                 struct dpp *dpp_base,
 389                 const struct dc_cursor_attributes *attr)
 390 {
 391         struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 392         enum dc_cursor_color_format color_format = attr->color_format;
 393
 394         REG_UPDATE_2(CURSOR0_CONTROL,
 395                         CUR0_MODE, color_format,
 396                         CUR0_EXPANSION_MODE, 0);
 397
 398         if (color_format == CURSOR_MODE_MONO) {
 399                 /* todo: clarify what to program these to */
 400                 REG_UPDATE(CURSOR0_COLOR0,
 401                                 CUR0_COLOR0, 0x00000000);
 402                 REG_UPDATE(CURSOR0_COLOR1,
 403                                 CUR0_COLOR1, 0xFFFFFFFF);
 404         }
 405
 406         /* TODO: Fixed vs float */
 407
 408         REG_UPDATE_3(FORMAT_CONTROL,
 409                                 CNVC_BYPASS, 0,
 410                                 FORMAT_CONTROL__ALPHA_EN, 1,
 411                                 FORMAT_EXPANSION_MODE, 0);
 412 }
 413
 414
 415 void dpp1_set_cursor_position(
 416                 struct dpp *dpp_base,
 417                 const struct dc_cursor_position *pos,
 418                 const struct dc_cursor_mi_param *param,
 419                 uint32_t width)
 420 {
 421         struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 422         int src_x_offset = pos->x - pos->x_hotspot - param->viewport_x_start;
 423         uint32_t cur_en = pos->enable ? 1 : 0;
 424
 425         if (src_x_offset >= (int)param->viewport_width)
 426                 cur_en = 0;  /* not visible beyond right edge*/
 427
 428         if (src_x_offset + (int)width < 0)
 429                 cur_en = 0;  /* not visible beyond left edge*/
 430
 431         REG_UPDATE(CURSOR0_CONTROL,
 432                         CUR0_ENABLE, cur_en);
 433
 434 }
 435
 436 static const struct dpp_funcs dcn10_dpp_funcs = {
 437                 .dpp_reset = dpp_reset,
 438                 .dpp_set_scaler = dpp1_dscl_set_scaler_manual_scale,
 439                 .dpp_get_optimal_number_of_taps = dpp_get_optimal_number_of_taps,
 440                 .dpp_set_gamut_remap = dpp1_cm_set_gamut_remap,
 441                 .dpp_set_csc_adjustment = dpp1_cm_set_output_csc_adjustment,
 442                 .dpp_set_csc_default = dpp1_cm_set_output_csc_default,
 443                 .dpp_power_on_regamma_lut = dpp1_cm_power_on_regamma_lut,
 444                 .dpp_program_regamma_lut = dpp1_cm_program_regamma_lut,
 445                 .dpp_configure_regamma_lut = dpp1_cm_configure_regamma_lut,
 446                 .dpp_program_regamma_lutb_settings = dpp1_cm_program_regamma_lutb_settings,
 447                 .dpp_program_regamma_luta_settings = dpp1_cm_program_regamma_luta_settings,
 448                 .dpp_program_regamma_pwl = dpp1_cm_set_regamma_pwl,
 449                 .dpp_program_bias_and_scale = dpp1_program_bias_and_scale,
 450                 .dpp_set_degamma = dpp1_set_degamma,
 451                 .dpp_program_input_lut          = dpp1_program_input_lut,
 452                 .dpp_program_degamma_pwl        = dpp1_set_degamma_pwl,
 453                 .dpp_setup                      = dpp1_cnv_setup,
 454                 .dpp_full_bypass                = dpp1_full_bypass,
 455                 .set_cursor_attributes = dpp1_set_cursor_attributes,
 456                 .set_cursor_position = dpp1_set_cursor_position,
 457 };
 458
 459 static struct dpp_caps dcn10_dpp_cap = {
 460         .dscl_data_proc_format = DSCL_DATA_PRCESSING_FIXED_FORMAT,
 461         .dscl_calc_lb_num_partitions = dpp1_dscl_calc_lb_num_partitions,
 462 };
 463
 464 /*****************************************/
 465 /* Constructor, Destructor               */
 466 /*****************************************/
 467
 468 void dpp1_construct(
 469         struct dcn10_dpp *dpp,
 470         struct dc_context *ctx,
 471         uint32_t inst,
 472         const struct dcn_dpp_registers *tf_regs,
 473         const struct dcn_dpp_shift *tf_shift,
 474         const struct dcn_dpp_mask *tf_mask)
 475 {
 476         dpp->base.ctx = ctx;
 477
 478         dpp->base.inst = inst;
 479         dpp->base.funcs = &dcn10_dpp_funcs;
 480         dpp->base.caps = &dcn10_dpp_cap;
 481
 482         dpp->tf_regs = tf_regs;
 483         dpp->tf_shift = tf_shift;
 484         dpp->tf_mask = tf_mask;
 485
 486         dpp->lb_pixel_depth_supported =
 487                 LB_PIXEL_DEPTH_18BPP |
 488                 LB_PIXEL_DEPTH_24BPP |
 489                 LB_PIXEL_DEPTH_30BPP;
 490
 491         dpp->lb_bits_per_entry = LB_BITS_PER_ENTRY;
 492         dpp->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x1404*/
 493 }