2 * Copyright 2012-15 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <linux/slab.h>
28 #include "dce/dce_8_0_d.h"
29 #include "dce/dce_8_0_sh_mask.h"
31 #include "dm_services.h"
33 #include "link_encoder.h"
34 #include "stream_encoder.h"
37 #include "include/irq_service_interface.h"
38 #include "irq/dce80/irq_service_dce80.h"
39 #include "dce110/dce110_timing_generator.h"
40 #include "dce110/dce110_resource.h"
41 #include "dce80/dce80_timing_generator.h"
42 #include "dce/dce_mem_input.h"
43 #include "dce/dce_link_encoder.h"
44 #include "dce/dce_stream_encoder.h"
45 #include "dce/dce_ipp.h"
46 #include "dce/dce_transform.h"
47 #include "dce/dce_opp.h"
48 #include "dce/dce_clock_source.h"
49 #include "dce/dce_audio.h"
50 #include "dce/dce_hwseq.h"
51 #include "dce80/dce80_hw_sequencer.h"
52 #include "dce100/dce100_resource.h"
53 #include "dce/dce_panel_cntl.h"
55 #include "reg_helper.h"
57 #include "dce/dce_dmcu.h"
58 #include "dce/dce_aux.h"
59 #include "dce/dce_abm.h"
60 #include "dce/dce_i2c.h"
61 /* TODO remove this include */
63 #include "dce80_resource.h"
65 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
66 #include "gmc/gmc_7_1_d.h"
67 #include "gmc/gmc_7_1_sh_mask.h"
70 #ifndef mmDP_DPHY_INTERNAL_CTRL
71 #define mmDP_DPHY_INTERNAL_CTRL 0x1CDE
72 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x1CDE
73 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x1FDE
74 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x42DE
75 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x45DE
76 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x48DE
77 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4BDE
78 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x4EDE
82 #ifndef mmBIOS_SCRATCH_2
83 #define mmBIOS_SCRATCH_2 0x05CB
84 #define mmBIOS_SCRATCH_3 0x05CC
85 #define mmBIOS_SCRATCH_6 0x05CF
88 #ifndef mmDP_DPHY_FAST_TRAINING
89 #define mmDP_DPHY_FAST_TRAINING 0x1CCE
90 #define mmDP0_DP_DPHY_FAST_TRAINING 0x1CCE
91 #define mmDP1_DP_DPHY_FAST_TRAINING 0x1FCE
92 #define mmDP2_DP_DPHY_FAST_TRAINING 0x42CE
93 #define mmDP3_DP_DPHY_FAST_TRAINING 0x45CE
94 #define mmDP4_DP_DPHY_FAST_TRAINING 0x48CE
95 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4BCE
96 #define mmDP6_DP_DPHY_FAST_TRAINING 0x4ECE
100 #ifndef mmHPD_DC_HPD_CONTROL
101 #define mmHPD_DC_HPD_CONTROL 0x189A
102 #define mmHPD0_DC_HPD_CONTROL 0x189A
103 #define mmHPD1_DC_HPD_CONTROL 0x18A2
104 #define mmHPD2_DC_HPD_CONTROL 0x18AA
105 #define mmHPD3_DC_HPD_CONTROL 0x18B2
106 #define mmHPD4_DC_HPD_CONTROL 0x18BA
107 #define mmHPD5_DC_HPD_CONTROL 0x18C2
110 #define DCE11_DIG_FE_CNTL 0x4a00
111 #define DCE11_DIG_BE_CNTL 0x4a47
112 #define DCE11_DP_SEC 0x4ac3
114 static const struct dce110_timing_generator_offsets dce80_tg_offsets[] = {
116 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
117 .dcp = (mmGRPH_CONTROL - mmGRPH_CONTROL),
118 .dmif = (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL
119 - mmDPG_WATERMARK_MASK_CONTROL),
122 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
123 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
124 .dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL
125 - mmDPG_WATERMARK_MASK_CONTROL),
128 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
129 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
130 .dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL
131 - mmDPG_WATERMARK_MASK_CONTROL),
134 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
135 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
136 .dmif = (mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL
137 - mmDPG_WATERMARK_MASK_CONTROL),
140 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
141 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
142 .dmif = (mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL
143 - mmDPG_WATERMARK_MASK_CONTROL),
146 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
147 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
148 .dmif = (mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL
149 - mmDPG_WATERMARK_MASK_CONTROL),
153 /* set register offset */
154 #define SR(reg_name)\
155 .reg_name = mm ## reg_name
157 /* set register offset with instance */
158 #define SRI(reg_name, block, id)\
159 .reg_name = mm ## block ## id ## _ ## reg_name
161 #define ipp_regs(id)\
163 IPP_COMMON_REG_LIST_DCE_BASE(id)\
166 static const struct dce_ipp_registers ipp_regs[] = {
175 static const struct dce_ipp_shift ipp_shift = {
176 IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
179 static const struct dce_ipp_mask ipp_mask = {
180 IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
183 #define transform_regs(id)\
185 XFM_COMMON_REG_LIST_DCE80(id)\
188 static const struct dce_transform_registers xfm_regs[] = {
197 static const struct dce_transform_shift xfm_shift = {
198 XFM_COMMON_MASK_SH_LIST_DCE80(__SHIFT)
201 static const struct dce_transform_mask xfm_mask = {
202 XFM_COMMON_MASK_SH_LIST_DCE80(_MASK)
205 #define aux_regs(id)\
210 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
219 #define hpd_regs(id)\
224 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
233 #define link_regs(id)\
235 LE_DCE80_REG_LIST(id)\
238 static const struct dce110_link_enc_registers link_enc_regs[] = {
248 #define stream_enc_regs(id)\
250 SE_COMMON_REG_LIST_DCE_BASE(id),\
254 static const struct dce110_stream_enc_registers stream_enc_regs[] = {
264 static const struct dce_stream_encoder_shift se_shift = {
265 SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT)
268 static const struct dce_stream_encoder_mask se_mask = {
269 SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK)
272 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
273 { DCE_PANEL_CNTL_REG_LIST() }
276 static const struct dce_panel_cntl_shift panel_cntl_shift = {
277 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
280 static const struct dce_panel_cntl_mask panel_cntl_mask = {
281 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
284 #define opp_regs(id)\
286 OPP_DCE_80_REG_LIST(id),\
289 static const struct dce_opp_registers opp_regs[] = {
298 static const struct dce_opp_shift opp_shift = {
299 OPP_COMMON_MASK_SH_LIST_DCE_80(__SHIFT)
302 static const struct dce_opp_mask opp_mask = {
303 OPP_COMMON_MASK_SH_LIST_DCE_80(_MASK)
306 static const struct dce110_aux_registers_shift aux_shift = {
307 DCE10_AUX_MASK_SH_LIST(__SHIFT)
310 static const struct dce110_aux_registers_mask aux_mask = {
311 DCE10_AUX_MASK_SH_LIST(_MASK)
314 #define aux_engine_regs(id)\
316 AUX_COMMON_REG_LIST(id), \
317 .AUX_RESET_MASK = 0 \
320 static const struct dce110_aux_registers aux_engine_regs[] = {
329 #define audio_regs(id)\
331 AUD_COMMON_REG_LIST(id)\
334 static const struct dce_audio_registers audio_regs[] = {
344 static const struct dce_audio_shift audio_shift = {
345 AUD_COMMON_MASK_SH_LIST(__SHIFT)
348 static const struct dce_audio_mask audio_mask = {
349 AUD_COMMON_MASK_SH_LIST(_MASK)
352 #define clk_src_regs(id)\
354 CS_COMMON_REG_LIST_DCE_80(id),\
358 static const struct dce110_clk_src_regs clk_src_regs[] = {
364 static const struct dce110_clk_src_shift cs_shift = {
365 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
368 static const struct dce110_clk_src_mask cs_mask = {
369 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
372 static const struct bios_registers bios_regs = {
373 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3,
374 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
377 static const struct resource_caps res_cap = {
378 .num_timing_generator = 6,
380 .num_stream_encoder = 6,
385 static const struct resource_caps res_cap_81 = {
386 .num_timing_generator = 4,
388 .num_stream_encoder = 7,
393 static const struct resource_caps res_cap_83 = {
394 .num_timing_generator = 2,
396 .num_stream_encoder = 6,
401 static const struct dc_plane_cap plane_cap = {
402 .type = DC_PLANE_TYPE_DCE_RGB,
404 .pixel_format_support = {
410 .max_upscale_factor = {
416 .max_downscale_factor = {
423 static const struct dce_dmcu_registers dmcu_regs = {
424 DMCU_DCE80_REG_LIST()
427 static const struct dce_dmcu_shift dmcu_shift = {
428 DMCU_MASK_SH_LIST_DCE80(__SHIFT)
431 static const struct dce_dmcu_mask dmcu_mask = {
432 DMCU_MASK_SH_LIST_DCE80(_MASK)
434 static const struct dce_abm_registers abm_regs = {
435 ABM_DCE110_COMMON_REG_LIST()
438 static const struct dce_abm_shift abm_shift = {
439 ABM_MASK_SH_LIST_DCE110(__SHIFT)
442 static const struct dce_abm_mask abm_mask = {
443 ABM_MASK_SH_LIST_DCE110(_MASK)
447 #define REG(reg) mm ## reg
449 #ifndef mmCC_DC_HDMI_STRAPS
450 #define mmCC_DC_HDMI_STRAPS 0x1918
451 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
452 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
453 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
454 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
457 static int map_transmitter_id_to_phy_instance(
458 enum transmitter transmitter)
460 switch (transmitter) {
461 case TRANSMITTER_UNIPHY_A:
463 case TRANSMITTER_UNIPHY_B:
465 case TRANSMITTER_UNIPHY_C:
467 case TRANSMITTER_UNIPHY_D:
469 case TRANSMITTER_UNIPHY_E:
471 case TRANSMITTER_UNIPHY_F:
473 case TRANSMITTER_UNIPHY_G:
481 static void read_dce_straps(
482 struct dc_context *ctx,
483 struct resource_straps *straps)
485 REG_GET_2(CC_DC_HDMI_STRAPS,
486 HDMI_DISABLE, &straps->hdmi_disable,
487 AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
489 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
492 static struct audio *create_audio(
493 struct dc_context *ctx, unsigned int inst)
495 return dce_audio_create(ctx, inst,
496 &audio_regs[inst], &audio_shift, &audio_mask);
499 static struct timing_generator *dce80_timing_generator_create(
500 struct dc_context *ctx,
502 const struct dce110_timing_generator_offsets *offsets)
504 struct dce110_timing_generator *tg110 =
505 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL);
510 dce80_timing_generator_construct(tg110, ctx, instance, offsets);
514 static struct output_pixel_processor *dce80_opp_create(
515 struct dc_context *ctx,
518 struct dce110_opp *opp =
519 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL);
524 dce110_opp_construct(opp,
525 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
529 static struct dce_aux *dce80_aux_engine_create(
530 struct dc_context *ctx,
533 struct aux_engine_dce110 *aux_engine =
534 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
539 dce110_aux_engine_construct(aux_engine, ctx, inst,
540 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
541 &aux_engine_regs[inst],
544 ctx->dc->caps.extended_aux_timeout_support);
546 return &aux_engine->base;
548 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
550 static const struct dce_i2c_registers i2c_hw_regs[] = {
559 static const struct dce_i2c_shift i2c_shifts = {
560 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
563 static const struct dce_i2c_mask i2c_masks = {
564 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
567 static struct dce_i2c_hw *dce80_i2c_hw_create(
568 struct dc_context *ctx,
571 struct dce_i2c_hw *dce_i2c_hw =
572 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
577 dce_i2c_hw_construct(dce_i2c_hw, ctx, inst,
578 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
583 static struct dce_i2c_sw *dce80_i2c_sw_create(
584 struct dc_context *ctx)
586 struct dce_i2c_sw *dce_i2c_sw =
587 kzalloc(sizeof(struct dce_i2c_sw), GFP_KERNEL);
592 dce_i2c_sw_construct(dce_i2c_sw, ctx);
596 static struct stream_encoder *dce80_stream_encoder_create(
597 enum engine_id eng_id,
598 struct dc_context *ctx)
600 struct dce110_stream_encoder *enc110 =
601 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
606 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
607 &stream_enc_regs[eng_id],
608 &se_shift, &se_mask);
609 return &enc110->base;
612 #define SRII(reg_name, block, id)\
613 .reg_name[id] = mm ## block ## id ## _ ## reg_name
615 static const struct dce_hwseq_registers hwseq_reg = {
616 HWSEQ_DCE8_REG_LIST()
619 static const struct dce_hwseq_shift hwseq_shift = {
620 HWSEQ_DCE8_MASK_SH_LIST(__SHIFT)
623 static const struct dce_hwseq_mask hwseq_mask = {
624 HWSEQ_DCE8_MASK_SH_LIST(_MASK)
627 static struct dce_hwseq *dce80_hwseq_create(
628 struct dc_context *ctx)
630 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
634 hws->regs = &hwseq_reg;
635 hws->shifts = &hwseq_shift;
636 hws->masks = &hwseq_mask;
641 static const struct resource_create_funcs res_create_funcs = {
642 .read_dce_straps = read_dce_straps,
643 .create_audio = create_audio,
644 .create_stream_encoder = dce80_stream_encoder_create,
645 .create_hwseq = dce80_hwseq_create,
648 #define mi_inst_regs(id) { \
649 MI_DCE8_REG_LIST(id), \
650 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \
652 static const struct dce_mem_input_registers mi_regs[] = {
661 static const struct dce_mem_input_shift mi_shifts = {
662 MI_DCE8_MASK_SH_LIST(__SHIFT),
663 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT
666 static const struct dce_mem_input_mask mi_masks = {
667 MI_DCE8_MASK_SH_LIST(_MASK),
668 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK
671 static struct mem_input *dce80_mem_input_create(
672 struct dc_context *ctx,
675 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
683 dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
684 dce_mi->wa.single_head_rdreq_dmif_limit = 2;
685 return &dce_mi->base;
688 static void dce80_transform_destroy(struct transform **xfm)
690 kfree(TO_DCE_TRANSFORM(*xfm));
694 static struct transform *dce80_transform_create(
695 struct dc_context *ctx,
698 struct dce_transform *transform =
699 kzalloc(sizeof(struct dce_transform), GFP_KERNEL);
704 dce_transform_construct(transform, ctx, inst,
705 &xfm_regs[inst], &xfm_shift, &xfm_mask);
706 transform->prescaler_on = false;
707 return &transform->base;
710 static const struct encoder_feature_support link_enc_feature = {
711 .max_hdmi_deep_color = COLOR_DEPTH_121212,
712 .max_hdmi_pixel_clock = 297000,
713 .flags.bits.IS_HBR2_CAPABLE = true,
714 .flags.bits.IS_TPS3_CAPABLE = true
717 static struct link_encoder *dce80_link_encoder_create(
718 const struct encoder_init_data *enc_init_data)
720 struct dce110_link_encoder *enc110 =
721 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
728 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
730 dce110_link_encoder_construct(enc110,
733 &link_enc_regs[link_regs_id],
734 &link_enc_aux_regs[enc_init_data->channel - 1],
735 &link_enc_hpd_regs[enc_init_data->hpd_source]);
736 return &enc110->base;
739 static struct panel_cntl *dce80_panel_cntl_create(const struct panel_cntl_init_data *init_data)
741 struct dce_panel_cntl *panel_cntl =
742 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
747 dce_panel_cntl_construct(panel_cntl,
749 &panel_cntl_regs[init_data->inst],
753 return &panel_cntl->base;
756 static struct clock_source *dce80_clock_source_create(
757 struct dc_context *ctx,
758 struct dc_bios *bios,
759 enum clock_source_id id,
760 const struct dce110_clk_src_regs *regs,
763 struct dce110_clk_src *clk_src =
764 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
769 if (dce110_clk_src_construct(clk_src, ctx, bios, id,
770 regs, &cs_shift, &cs_mask)) {
771 clk_src->base.dp_clk_src = dp_clk_src;
772 return &clk_src->base;
780 static void dce80_clock_source_destroy(struct clock_source **clk_src)
782 kfree(TO_DCE110_CLK_SRC(*clk_src));
786 static struct input_pixel_processor *dce80_ipp_create(
787 struct dc_context *ctx, uint32_t inst)
789 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL);
796 dce_ipp_construct(ipp, ctx, inst,
797 &ipp_regs[inst], &ipp_shift, &ipp_mask);
801 static void dce80_resource_destruct(struct dce110_resource_pool *pool)
805 for (i = 0; i < pool->base.pipe_count; i++) {
806 if (pool->base.opps[i] != NULL)
807 dce110_opp_destroy(&pool->base.opps[i]);
809 if (pool->base.transforms[i] != NULL)
810 dce80_transform_destroy(&pool->base.transforms[i]);
812 if (pool->base.ipps[i] != NULL)
813 dce_ipp_destroy(&pool->base.ipps[i]);
815 if (pool->base.mis[i] != NULL) {
816 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
817 pool->base.mis[i] = NULL;
820 if (pool->base.timing_generators[i] != NULL) {
821 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
822 pool->base.timing_generators[i] = NULL;
826 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
827 if (pool->base.engines[i] != NULL)
828 dce110_engine_destroy(&pool->base.engines[i]);
829 if (pool->base.hw_i2cs[i] != NULL) {
830 kfree(pool->base.hw_i2cs[i]);
831 pool->base.hw_i2cs[i] = NULL;
833 if (pool->base.sw_i2cs[i] != NULL) {
834 kfree(pool->base.sw_i2cs[i]);
835 pool->base.sw_i2cs[i] = NULL;
839 for (i = 0; i < pool->base.stream_enc_count; i++) {
840 if (pool->base.stream_enc[i] != NULL)
841 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
844 for (i = 0; i < pool->base.clk_src_count; i++) {
845 if (pool->base.clock_sources[i] != NULL) {
846 dce80_clock_source_destroy(&pool->base.clock_sources[i]);
850 if (pool->base.abm != NULL)
851 dce_abm_destroy(&pool->base.abm);
853 if (pool->base.dmcu != NULL)
854 dce_dmcu_destroy(&pool->base.dmcu);
856 if (pool->base.dp_clock_source != NULL)
857 dce80_clock_source_destroy(&pool->base.dp_clock_source);
859 for (i = 0; i < pool->base.audio_count; i++) {
860 if (pool->base.audios[i] != NULL) {
861 dce_aud_destroy(&pool->base.audios[i]);
865 if (pool->base.irqs != NULL) {
866 dal_irq_service_destroy(&pool->base.irqs);
870 static bool dce80_validate_bandwidth(
872 struct dc_state *context,
876 bool at_least_one_pipe = false;
878 for (i = 0; i < dc->res_pool->pipe_count; i++) {
879 if (context->res_ctx.pipe_ctx[i].stream)
880 at_least_one_pipe = true;
883 if (at_least_one_pipe) {
884 /* TODO implement when needed but for now hardcode max value*/
885 context->bw_ctx.bw.dce.dispclk_khz = 681000;
886 context->bw_ctx.bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ;
888 context->bw_ctx.bw.dce.dispclk_khz = 0;
889 context->bw_ctx.bw.dce.yclk_khz = 0;
895 static bool dce80_validate_surface_sets(
896 struct dc_state *context)
900 for (i = 0; i < context->stream_count; i++) {
901 if (context->stream_status[i].plane_count == 0)
904 if (context->stream_status[i].plane_count > 1)
907 if (context->stream_status[i].plane_states[0]->format
908 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
915 static enum dc_status dce80_validate_global(
917 struct dc_state *context)
919 if (!dce80_validate_surface_sets(context))
920 return DC_FAIL_SURFACE_VALIDATE;
925 static void dce80_destroy_resource_pool(struct resource_pool **pool)
927 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
929 dce80_resource_destruct(dce110_pool);
934 static const struct resource_funcs dce80_res_pool_funcs = {
935 .destroy = dce80_destroy_resource_pool,
936 .link_enc_create = dce80_link_encoder_create,
937 .panel_cntl_create = dce80_panel_cntl_create,
938 .validate_bandwidth = dce80_validate_bandwidth,
939 .validate_plane = dce100_validate_plane,
940 .add_stream_to_ctx = dce100_add_stream_to_ctx,
941 .validate_global = dce80_validate_global,
942 .find_first_free_match_stream_enc_for_link = dce100_find_first_free_match_stream_enc_for_link
945 static bool dce80_construct(
946 uint8_t num_virtual_links,
948 struct dce110_resource_pool *pool)
951 struct dc_context *ctx = dc->ctx;
954 ctx->dc_bios->regs = &bios_regs;
956 pool->base.res_cap = &res_cap;
957 pool->base.funcs = &dce80_res_pool_funcs;
960 /*************************************************
961 * Resource + asic cap harcoding *
962 *************************************************/
963 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
964 pool->base.pipe_count = res_cap.num_timing_generator;
965 pool->base.timing_generator_count = res_cap.num_timing_generator;
966 dc->caps.max_downscale_ratio = 200;
967 dc->caps.i2c_speed_in_khz = 40;
968 dc->caps.i2c_speed_in_khz_hdcp = 40;
969 dc->caps.max_cursor_size = 128;
970 dc->caps.min_horizontal_blanking_period = 80;
971 dc->caps.dual_link_dvi = true;
972 dc->caps.extended_aux_timeout_support = false;
974 /*************************************************
976 *************************************************/
980 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
981 pool->base.dp_clock_source =
982 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
984 pool->base.clock_sources[0] =
985 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
986 pool->base.clock_sources[1] =
987 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
988 pool->base.clock_sources[2] =
989 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
990 pool->base.clk_src_count = 3;
993 pool->base.dp_clock_source =
994 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
996 pool->base.clock_sources[0] =
997 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
998 pool->base.clock_sources[1] =
999 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
1000 pool->base.clk_src_count = 2;
1003 if (pool->base.dp_clock_source == NULL) {
1004 dm_error("DC: failed to create dp clock source!\n");
1005 BREAK_TO_DEBUGGER();
1006 goto res_create_fail;
1009 for (i = 0; i < pool->base.clk_src_count; i++) {
1010 if (pool->base.clock_sources[i] == NULL) {
1011 dm_error("DC: failed to create clock sources!\n");
1012 BREAK_TO_DEBUGGER();
1013 goto res_create_fail;
1017 pool->base.dmcu = dce_dmcu_create(ctx,
1021 if (pool->base.dmcu == NULL) {
1022 dm_error("DC: failed to create dmcu!\n");
1023 BREAK_TO_DEBUGGER();
1024 goto res_create_fail;
1027 pool->base.abm = dce_abm_create(ctx,
1031 if (pool->base.abm == NULL) {
1032 dm_error("DC: failed to create abm!\n");
1033 BREAK_TO_DEBUGGER();
1034 goto res_create_fail;
1038 struct irq_service_init_data init_data;
1039 init_data.ctx = dc->ctx;
1040 pool->base.irqs = dal_irq_service_dce80_create(&init_data);
1041 if (!pool->base.irqs)
1042 goto res_create_fail;
1045 for (i = 0; i < pool->base.pipe_count; i++) {
1046 pool->base.timing_generators[i] = dce80_timing_generator_create(
1047 ctx, i, &dce80_tg_offsets[i]);
1048 if (pool->base.timing_generators[i] == NULL) {
1049 BREAK_TO_DEBUGGER();
1050 dm_error("DC: failed to create tg!\n");
1051 goto res_create_fail;
1054 pool->base.mis[i] = dce80_mem_input_create(ctx, i);
1055 if (pool->base.mis[i] == NULL) {
1056 BREAK_TO_DEBUGGER();
1057 dm_error("DC: failed to create memory input!\n");
1058 goto res_create_fail;
1061 pool->base.ipps[i] = dce80_ipp_create(ctx, i);
1062 if (pool->base.ipps[i] == NULL) {
1063 BREAK_TO_DEBUGGER();
1064 dm_error("DC: failed to create input pixel processor!\n");
1065 goto res_create_fail;
1068 pool->base.transforms[i] = dce80_transform_create(ctx, i);
1069 if (pool->base.transforms[i] == NULL) {
1070 BREAK_TO_DEBUGGER();
1071 dm_error("DC: failed to create transform!\n");
1072 goto res_create_fail;
1075 pool->base.opps[i] = dce80_opp_create(ctx, i);
1076 if (pool->base.opps[i] == NULL) {
1077 BREAK_TO_DEBUGGER();
1078 dm_error("DC: failed to create output pixel processor!\n");
1079 goto res_create_fail;
1083 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1084 pool->base.engines[i] = dce80_aux_engine_create(ctx, i);
1085 if (pool->base.engines[i] == NULL) {
1086 BREAK_TO_DEBUGGER();
1088 "DC:failed to create aux engine!!\n");
1089 goto res_create_fail;
1091 pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i);
1092 if (pool->base.hw_i2cs[i] == NULL) {
1093 BREAK_TO_DEBUGGER();
1095 "DC:failed to create i2c engine!!\n");
1096 goto res_create_fail;
1098 pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx);
1099 if (pool->base.sw_i2cs[i] == NULL) {
1100 BREAK_TO_DEBUGGER();
1102 "DC:failed to create sw i2c!!\n");
1103 goto res_create_fail;
1107 dc->caps.max_planes = pool->base.pipe_count;
1109 for (i = 0; i < dc->caps.max_planes; ++i)
1110 dc->caps.planes[i] = plane_cap;
1112 dc->caps.disable_dp_clk_share = true;
1114 if (!resource_construct(num_virtual_links, dc, &pool->base,
1116 goto res_create_fail;
1118 /* Create hardware sequencer */
1119 dce80_hw_sequencer_construct(dc);
1124 dce80_resource_destruct(pool);
1128 struct resource_pool *dce80_create_resource_pool(
1129 uint8_t num_virtual_links,
1132 struct dce110_resource_pool *pool =
1133 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1138 if (dce80_construct(num_virtual_links, dc, pool))
1141 BREAK_TO_DEBUGGER();
1145 static bool dce81_construct(
1146 uint8_t num_virtual_links,
1148 struct dce110_resource_pool *pool)
1151 struct dc_context *ctx = dc->ctx;
1154 ctx->dc_bios->regs = &bios_regs;
1156 pool->base.res_cap = &res_cap_81;
1157 pool->base.funcs = &dce80_res_pool_funcs;
1160 /*************************************************
1161 * Resource + asic cap harcoding *
1162 *************************************************/
1163 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1164 pool->base.pipe_count = res_cap_81.num_timing_generator;
1165 pool->base.timing_generator_count = res_cap_81.num_timing_generator;
1166 dc->caps.max_downscale_ratio = 200;
1167 dc->caps.i2c_speed_in_khz = 40;
1168 dc->caps.i2c_speed_in_khz_hdcp = 40;
1169 dc->caps.max_cursor_size = 128;
1170 dc->caps.min_horizontal_blanking_period = 80;
1171 dc->caps.is_apu = true;
1173 /*************************************************
1174 * Create resources *
1175 *************************************************/
1179 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
1180 pool->base.dp_clock_source =
1181 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
1183 pool->base.clock_sources[0] =
1184 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
1185 pool->base.clock_sources[1] =
1186 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
1187 pool->base.clock_sources[2] =
1188 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
1189 pool->base.clk_src_count = 3;
1192 pool->base.dp_clock_source =
1193 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
1195 pool->base.clock_sources[0] =
1196 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
1197 pool->base.clock_sources[1] =
1198 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
1199 pool->base.clk_src_count = 2;
1202 if (pool->base.dp_clock_source == NULL) {
1203 dm_error("DC: failed to create dp clock source!\n");
1204 BREAK_TO_DEBUGGER();
1205 goto res_create_fail;
1208 for (i = 0; i < pool->base.clk_src_count; i++) {
1209 if (pool->base.clock_sources[i] == NULL) {
1210 dm_error("DC: failed to create clock sources!\n");
1211 BREAK_TO_DEBUGGER();
1212 goto res_create_fail;
1216 pool->base.dmcu = dce_dmcu_create(ctx,
1220 if (pool->base.dmcu == NULL) {
1221 dm_error("DC: failed to create dmcu!\n");
1222 BREAK_TO_DEBUGGER();
1223 goto res_create_fail;
1226 pool->base.abm = dce_abm_create(ctx,
1230 if (pool->base.abm == NULL) {
1231 dm_error("DC: failed to create abm!\n");
1232 BREAK_TO_DEBUGGER();
1233 goto res_create_fail;
1237 struct irq_service_init_data init_data;
1238 init_data.ctx = dc->ctx;
1239 pool->base.irqs = dal_irq_service_dce80_create(&init_data);
1240 if (!pool->base.irqs)
1241 goto res_create_fail;
1244 for (i = 0; i < pool->base.pipe_count; i++) {
1245 pool->base.timing_generators[i] = dce80_timing_generator_create(
1246 ctx, i, &dce80_tg_offsets[i]);
1247 if (pool->base.timing_generators[i] == NULL) {
1248 BREAK_TO_DEBUGGER();
1249 dm_error("DC: failed to create tg!\n");
1250 goto res_create_fail;
1253 pool->base.mis[i] = dce80_mem_input_create(ctx, i);
1254 if (pool->base.mis[i] == NULL) {
1255 BREAK_TO_DEBUGGER();
1256 dm_error("DC: failed to create memory input!\n");
1257 goto res_create_fail;
1260 pool->base.ipps[i] = dce80_ipp_create(ctx, i);
1261 if (pool->base.ipps[i] == NULL) {
1262 BREAK_TO_DEBUGGER();
1263 dm_error("DC: failed to create input pixel processor!\n");
1264 goto res_create_fail;
1267 pool->base.transforms[i] = dce80_transform_create(ctx, i);
1268 if (pool->base.transforms[i] == NULL) {
1269 BREAK_TO_DEBUGGER();
1270 dm_error("DC: failed to create transform!\n");
1271 goto res_create_fail;
1274 pool->base.opps[i] = dce80_opp_create(ctx, i);
1275 if (pool->base.opps[i] == NULL) {
1276 BREAK_TO_DEBUGGER();
1277 dm_error("DC: failed to create output pixel processor!\n");
1278 goto res_create_fail;
1282 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1283 pool->base.engines[i] = dce80_aux_engine_create(ctx, i);
1284 if (pool->base.engines[i] == NULL) {
1285 BREAK_TO_DEBUGGER();
1287 "DC:failed to create aux engine!!\n");
1288 goto res_create_fail;
1290 pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i);
1291 if (pool->base.hw_i2cs[i] == NULL) {
1292 BREAK_TO_DEBUGGER();
1294 "DC:failed to create i2c engine!!\n");
1295 goto res_create_fail;
1297 pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx);
1298 if (pool->base.sw_i2cs[i] == NULL) {
1299 BREAK_TO_DEBUGGER();
1301 "DC:failed to create sw i2c!!\n");
1302 goto res_create_fail;
1306 dc->caps.max_planes = pool->base.pipe_count;
1308 for (i = 0; i < dc->caps.max_planes; ++i)
1309 dc->caps.planes[i] = plane_cap;
1311 dc->caps.disable_dp_clk_share = true;
1313 if (!resource_construct(num_virtual_links, dc, &pool->base,
1315 goto res_create_fail;
1317 /* Create hardware sequencer */
1318 dce80_hw_sequencer_construct(dc);
1323 dce80_resource_destruct(pool);
1327 struct resource_pool *dce81_create_resource_pool(
1328 uint8_t num_virtual_links,
1331 struct dce110_resource_pool *pool =
1332 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1337 if (dce81_construct(num_virtual_links, dc, pool))
1340 BREAK_TO_DEBUGGER();
1344 static bool dce83_construct(
1345 uint8_t num_virtual_links,
1347 struct dce110_resource_pool *pool)
1350 struct dc_context *ctx = dc->ctx;
1353 ctx->dc_bios->regs = &bios_regs;
1355 pool->base.res_cap = &res_cap_83;
1356 pool->base.funcs = &dce80_res_pool_funcs;
1359 /*************************************************
1360 * Resource + asic cap harcoding *
1361 *************************************************/
1362 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1363 pool->base.pipe_count = res_cap_83.num_timing_generator;
1364 pool->base.timing_generator_count = res_cap_83.num_timing_generator;
1365 dc->caps.max_downscale_ratio = 200;
1366 dc->caps.i2c_speed_in_khz = 40;
1367 dc->caps.i2c_speed_in_khz_hdcp = 40;
1368 dc->caps.max_cursor_size = 128;
1369 dc->caps.min_horizontal_blanking_period = 80;
1370 dc->caps.is_apu = true;
1372 /*************************************************
1373 * Create resources *
1374 *************************************************/
1378 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
1379 pool->base.dp_clock_source =
1380 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
1382 pool->base.clock_sources[0] =
1383 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], false);
1384 pool->base.clock_sources[1] =
1385 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);
1386 pool->base.clk_src_count = 2;
1389 pool->base.dp_clock_source =
1390 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], true);
1392 pool->base.clock_sources[0] =
1393 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);
1394 pool->base.clk_src_count = 1;
1397 if (pool->base.dp_clock_source == NULL) {
1398 dm_error("DC: failed to create dp clock source!\n");
1399 BREAK_TO_DEBUGGER();
1400 goto res_create_fail;
1403 for (i = 0; i < pool->base.clk_src_count; i++) {
1404 if (pool->base.clock_sources[i] == NULL) {
1405 dm_error("DC: failed to create clock sources!\n");
1406 BREAK_TO_DEBUGGER();
1407 goto res_create_fail;
1411 pool->base.dmcu = dce_dmcu_create(ctx,
1415 if (pool->base.dmcu == NULL) {
1416 dm_error("DC: failed to create dmcu!\n");
1417 BREAK_TO_DEBUGGER();
1418 goto res_create_fail;
1421 pool->base.abm = dce_abm_create(ctx,
1425 if (pool->base.abm == NULL) {
1426 dm_error("DC: failed to create abm!\n");
1427 BREAK_TO_DEBUGGER();
1428 goto res_create_fail;
1432 struct irq_service_init_data init_data;
1433 init_data.ctx = dc->ctx;
1434 pool->base.irqs = dal_irq_service_dce80_create(&init_data);
1435 if (!pool->base.irqs)
1436 goto res_create_fail;
1439 for (i = 0; i < pool->base.pipe_count; i++) {
1440 pool->base.timing_generators[i] = dce80_timing_generator_create(
1441 ctx, i, &dce80_tg_offsets[i]);
1442 if (pool->base.timing_generators[i] == NULL) {
1443 BREAK_TO_DEBUGGER();
1444 dm_error("DC: failed to create tg!\n");
1445 goto res_create_fail;
1448 pool->base.mis[i] = dce80_mem_input_create(ctx, i);
1449 if (pool->base.mis[i] == NULL) {
1450 BREAK_TO_DEBUGGER();
1451 dm_error("DC: failed to create memory input!\n");
1452 goto res_create_fail;
1455 pool->base.ipps[i] = dce80_ipp_create(ctx, i);
1456 if (pool->base.ipps[i] == NULL) {
1457 BREAK_TO_DEBUGGER();
1458 dm_error("DC: failed to create input pixel processor!\n");
1459 goto res_create_fail;
1462 pool->base.transforms[i] = dce80_transform_create(ctx, i);
1463 if (pool->base.transforms[i] == NULL) {
1464 BREAK_TO_DEBUGGER();
1465 dm_error("DC: failed to create transform!\n");
1466 goto res_create_fail;
1469 pool->base.opps[i] = dce80_opp_create(ctx, i);
1470 if (pool->base.opps[i] == NULL) {
1471 BREAK_TO_DEBUGGER();
1472 dm_error("DC: failed to create output pixel processor!\n");
1473 goto res_create_fail;
1477 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1478 pool->base.engines[i] = dce80_aux_engine_create(ctx, i);
1479 if (pool->base.engines[i] == NULL) {
1480 BREAK_TO_DEBUGGER();
1482 "DC:failed to create aux engine!!\n");
1483 goto res_create_fail;
1485 pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i);
1486 if (pool->base.hw_i2cs[i] == NULL) {
1487 BREAK_TO_DEBUGGER();
1489 "DC:failed to create i2c engine!!\n");
1490 goto res_create_fail;
1492 pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx);
1493 if (pool->base.sw_i2cs[i] == NULL) {
1494 BREAK_TO_DEBUGGER();
1496 "DC:failed to create sw i2c!!\n");
1497 goto res_create_fail;
1501 dc->caps.max_planes = pool->base.pipe_count;
1503 for (i = 0; i < dc->caps.max_planes; ++i)
1504 dc->caps.planes[i] = plane_cap;
1506 dc->caps.disable_dp_clk_share = true;
1508 if (!resource_construct(num_virtual_links, dc, &pool->base,
1510 goto res_create_fail;
1512 /* Create hardware sequencer */
1513 dce80_hw_sequencer_construct(dc);
1518 dce80_resource_destruct(pool);
1522 struct resource_pool *dce83_create_resource_pool(
1523 uint8_t num_virtual_links,
1526 struct dce110_resource_pool *pool =
1527 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1532 if (dce83_construct(num_virtual_links, dc, pool))
1535 BREAK_TO_DEBUGGER();