drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dce/dce_8_0_d.h"
  27 #include "dce/dce_8_0_sh_mask.h"
  28
  29 #include "dm_services.h"
  30
  31 #include "link_encoder.h"
  32 #include "stream_encoder.h"
  33
  34 #include "resource.h"
  35 #include "include/irq_service_interface.h"
  36 #include "irq/dce80/irq_service_dce80.h"
  37 #include "dce110/dce110_timing_generator.h"
  38 #include "dce110/dce110_resource.h"
  39 #include "dce80/dce80_timing_generator.h"
  40 #include "dce/dce_clk_mgr.h"
  41 #include "dce/dce_mem_input.h"
  42 #include "dce/dce_link_encoder.h"
  43 #include "dce/dce_stream_encoder.h"
  44 #include "dce/dce_ipp.h"
  45 #include "dce/dce_transform.h"
  46 #include "dce/dce_opp.h"
  47 #include "dce/dce_clock_source.h"
  48 #include "dce/dce_audio.h"
  49 #include "dce/dce_hwseq.h"
  50 #include "dce80/dce80_hw_sequencer.h"
  51 #include "dce100/dce100_resource.h"
  52
  53 #include "reg_helper.h"
  54
  55 #include "dce/dce_dmcu.h"
  56 #include "dce/dce_aux.h"
  57 #include "dce/dce_abm.h"
  58 #include "dce/dce_i2c.h"
  59 /* TODO remove this include */
  60
  61 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
  62 #include "gmc/gmc_7_1_d.h"
  63 #include "gmc/gmc_7_1_sh_mask.h"
  64 #endif
  65
  66 #ifndef mmDP_DPHY_INTERNAL_CTRL
  67 #define mmDP_DPHY_INTERNAL_CTRL                         0x1CDE
  68 #define mmDP0_DP_DPHY_INTERNAL_CTRL                     0x1CDE
  69 #define mmDP1_DP_DPHY_INTERNAL_CTRL                     0x1FDE
  70 #define mmDP2_DP_DPHY_INTERNAL_CTRL                     0x42DE
  71 #define mmDP3_DP_DPHY_INTERNAL_CTRL                     0x45DE
  72 #define mmDP4_DP_DPHY_INTERNAL_CTRL                     0x48DE
  73 #define mmDP5_DP_DPHY_INTERNAL_CTRL                     0x4BDE
  74 #define mmDP6_DP_DPHY_INTERNAL_CTRL                     0x4EDE
  75 #endif
  76
  77
  78 #ifndef mmBIOS_SCRATCH_2
  79         #define mmBIOS_SCRATCH_2 0x05CB
  80         #define mmBIOS_SCRATCH_6 0x05CF
  81 #endif
  82
  83 #ifndef mmDP_DPHY_FAST_TRAINING
  84         #define mmDP_DPHY_FAST_TRAINING                         0x1CCE
  85         #define mmDP0_DP_DPHY_FAST_TRAINING                     0x1CCE
  86         #define mmDP1_DP_DPHY_FAST_TRAINING                     0x1FCE
  87         #define mmDP2_DP_DPHY_FAST_TRAINING                     0x42CE
  88         #define mmDP3_DP_DPHY_FAST_TRAINING                     0x45CE
  89         #define mmDP4_DP_DPHY_FAST_TRAINING                     0x48CE
  90         #define mmDP5_DP_DPHY_FAST_TRAINING                     0x4BCE
  91         #define mmDP6_DP_DPHY_FAST_TRAINING                     0x4ECE
  92 #endif
  93
  94
  95 #ifndef mmHPD_DC_HPD_CONTROL
  96         #define mmHPD_DC_HPD_CONTROL                            0x189A
  97         #define mmHPD0_DC_HPD_CONTROL                           0x189A
  98         #define mmHPD1_DC_HPD_CONTROL                           0x18A2
  99         #define mmHPD2_DC_HPD_CONTROL                           0x18AA
 100         #define mmHPD3_DC_HPD_CONTROL                           0x18B2
 101         #define mmHPD4_DC_HPD_CONTROL                           0x18BA
 102         #define mmHPD5_DC_HPD_CONTROL                           0x18C2
 103 #endif
 104
 105 #define DCE11_DIG_FE_CNTL 0x4a00
 106 #define DCE11_DIG_BE_CNTL 0x4a47
 107 #define DCE11_DP_SEC 0x4ac3
 108
 109 static const struct dce110_timing_generator_offsets dce80_tg_offsets[] = {
 110                 {
 111                         .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
 112                         .dcp =  (mmGRPH_CONTROL - mmGRPH_CONTROL),
 113                         .dmif = (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL
 114                                         - mmDPG_WATERMARK_MASK_CONTROL),
 115                 },
 116                 {
 117                         .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
 118                         .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
 119                         .dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL
 120                                         - mmDPG_WATERMARK_MASK_CONTROL),
 121                 },
 122                 {
 123                         .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
 124                         .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
 125                         .dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL
 126                                         - mmDPG_WATERMARK_MASK_CONTROL),
 127                 },
 128                 {
 129                         .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
 130                         .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
 131                         .dmif = (mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL
 132                                         - mmDPG_WATERMARK_MASK_CONTROL),
 133                 },
 134                 {
 135                         .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
 136                         .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
 137                         .dmif = (mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL
 138                                         - mmDPG_WATERMARK_MASK_CONTROL),
 139                 },
 140                 {
 141                         .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
 142                         .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
 143                         .dmif = (mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL
 144                                         - mmDPG_WATERMARK_MASK_CONTROL),
 145                 }
 146 };
 147
 148 /* set register offset */
 149 #define SR(reg_name)\
 150         .reg_name = mm ## reg_name
 151
 152 /* set register offset with instance */
 153 #define SRI(reg_name, block, id)\
 154         .reg_name = mm ## block ## id ## _ ## reg_name
 155
 156
 157 static const struct clk_mgr_registers disp_clk_regs = {
 158                 CLK_COMMON_REG_LIST_DCE_BASE()
 159 };
 160
 161 static const struct clk_mgr_shift disp_clk_shift = {
 162                 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
 163 };
 164
 165 static const struct clk_mgr_mask disp_clk_mask = {
 166                 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
 167 };
 168
 169 #define ipp_regs(id)\
 170 [id] = {\
 171                 IPP_COMMON_REG_LIST_DCE_BASE(id)\
 172 }
 173
 174 static const struct dce_ipp_registers ipp_regs[] = {
 175                 ipp_regs(0),
 176                 ipp_regs(1),
 177                 ipp_regs(2),
 178                 ipp_regs(3),
 179                 ipp_regs(4),
 180                 ipp_regs(5)
 181 };
 182
 183 static const struct dce_ipp_shift ipp_shift = {
 184                 IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
 185 };
 186
 187 static const struct dce_ipp_mask ipp_mask = {
 188                 IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
 189 };
 190
 191 #define transform_regs(id)\
 192 [id] = {\
 193                 XFM_COMMON_REG_LIST_DCE80(id)\
 194 }
 195
 196 static const struct dce_transform_registers xfm_regs[] = {
 197                 transform_regs(0),
 198                 transform_regs(1),
 199                 transform_regs(2),
 200                 transform_regs(3),
 201                 transform_regs(4),
 202                 transform_regs(5)
 203 };
 204
 205 static const struct dce_transform_shift xfm_shift = {
 206                 XFM_COMMON_MASK_SH_LIST_DCE80(__SHIFT)
 207 };
 208
 209 static const struct dce_transform_mask xfm_mask = {
 210                 XFM_COMMON_MASK_SH_LIST_DCE80(_MASK)
 211 };
 212
 213 #define aux_regs(id)\
 214 [id] = {\
 215         AUX_REG_LIST(id)\
 216 }
 217
 218 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
 219         aux_regs(0),
 220         aux_regs(1),
 221         aux_regs(2),
 222         aux_regs(3),
 223         aux_regs(4),
 224         aux_regs(5)
 225 };
 226
 227 #define hpd_regs(id)\
 228 [id] = {\
 229         HPD_REG_LIST(id)\
 230 }
 231
 232 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
 233                 hpd_regs(0),
 234                 hpd_regs(1),
 235                 hpd_regs(2),
 236                 hpd_regs(3),
 237                 hpd_regs(4),
 238                 hpd_regs(5)
 239 };
 240
 241 #define link_regs(id)\
 242 [id] = {\
 243         LE_DCE80_REG_LIST(id)\
 244 }
 245
 246 static const struct dce110_link_enc_registers link_enc_regs[] = {
 247         link_regs(0),
 248         link_regs(1),
 249         link_regs(2),
 250         link_regs(3),
 251         link_regs(4),
 252         link_regs(5),
 253         link_regs(6),
 254 };
 255
 256 #define stream_enc_regs(id)\
 257 [id] = {\
 258         SE_COMMON_REG_LIST_DCE_BASE(id),\
 259         .AFMT_CNTL = 0,\
 260 }
 261
 262 static const struct dce110_stream_enc_registers stream_enc_regs[] = {
 263         stream_enc_regs(0),
 264         stream_enc_regs(1),
 265         stream_enc_regs(2),
 266         stream_enc_regs(3),
 267         stream_enc_regs(4),
 268         stream_enc_regs(5),
 269         stream_enc_regs(6)
 270 };
 271
 272 static const struct dce_stream_encoder_shift se_shift = {
 273                 SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT)
 274 };
 275
 276 static const struct dce_stream_encoder_mask se_mask = {
 277                 SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK)
 278 };
 279
 280 #define opp_regs(id)\
 281 [id] = {\
 282         OPP_DCE_80_REG_LIST(id),\
 283 }
 284
 285 static const struct dce_opp_registers opp_regs[] = {
 286         opp_regs(0),
 287         opp_regs(1),
 288         opp_regs(2),
 289         opp_regs(3),
 290         opp_regs(4),
 291         opp_regs(5)
 292 };
 293
 294 static const struct dce_opp_shift opp_shift = {
 295         OPP_COMMON_MASK_SH_LIST_DCE_80(__SHIFT)
 296 };
 297
 298 static const struct dce_opp_mask opp_mask = {
 299         OPP_COMMON_MASK_SH_LIST_DCE_80(_MASK)
 300 };
 301
 302 #define aux_engine_regs(id)\
 303 [id] = {\
 304         AUX_COMMON_REG_LIST(id), \
 305         .AUX_RESET_MASK = 0 \
 306 }
 307
 308 static const struct dce110_aux_registers aux_engine_regs[] = {
 309                 aux_engine_regs(0),
 310                 aux_engine_regs(1),
 311                 aux_engine_regs(2),
 312                 aux_engine_regs(3),
 313                 aux_engine_regs(4),
 314                 aux_engine_regs(5)
 315 };
 316
 317 #define audio_regs(id)\
 318 [id] = {\
 319         AUD_COMMON_REG_LIST(id)\
 320 }
 321
 322 static const struct dce_audio_registers audio_regs[] = {
 323         audio_regs(0),
 324         audio_regs(1),
 325         audio_regs(2),
 326         audio_regs(3),
 327         audio_regs(4),
 328         audio_regs(5),
 329         audio_regs(6),
 330 };
 331
 332 static const struct dce_audio_shift audio_shift = {
 333                 AUD_COMMON_MASK_SH_LIST(__SHIFT)
 334 };
 335
 336 static const struct dce_aduio_mask audio_mask = {
 337                 AUD_COMMON_MASK_SH_LIST(_MASK)
 338 };
 339
 340 #define clk_src_regs(id)\
 341 [id] = {\
 342         CS_COMMON_REG_LIST_DCE_80(id),\
 343 }
 344
 345
 346 static const struct dce110_clk_src_regs clk_src_regs[] = {
 347         clk_src_regs(0),
 348         clk_src_regs(1),
 349         clk_src_regs(2)
 350 };
 351
 352 static const struct dce110_clk_src_shift cs_shift = {
 353                 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
 354 };
 355
 356 static const struct dce110_clk_src_mask cs_mask = {
 357                 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
 358 };
 359
 360 static const struct bios_registers bios_regs = {
 361         .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
 362 };
 363
 364 static const struct resource_caps res_cap = {
 365                 .num_timing_generator = 6,
 366                 .num_audio = 6,
 367                 .num_stream_encoder = 6,
 368                 .num_pll = 3,
 369                 .num_ddc = 6,
 370 };
 371
 372 static const struct resource_caps res_cap_81 = {
 373                 .num_timing_generator = 4,
 374                 .num_audio = 7,
 375                 .num_stream_encoder = 7,
 376                 .num_pll = 3,
 377                 .num_ddc = 6,
 378 };
 379
 380 static const struct resource_caps res_cap_83 = {
 381                 .num_timing_generator = 2,
 382                 .num_audio = 6,
 383                 .num_stream_encoder = 6,
 384                 .num_pll = 2,
 385                 .num_ddc = 2,
 386 };
 387
 388 static const struct dce_dmcu_registers dmcu_regs = {
 389                 DMCU_DCE80_REG_LIST()
 390 };
 391
 392 static const struct dce_dmcu_shift dmcu_shift = {
 393                 DMCU_MASK_SH_LIST_DCE80(__SHIFT)
 394 };
 395
 396 static const struct dce_dmcu_mask dmcu_mask = {
 397                 DMCU_MASK_SH_LIST_DCE80(_MASK)
 398 };
 399 static const struct dce_abm_registers abm_regs = {
 400                 ABM_DCE110_COMMON_REG_LIST()
 401 };
 402
 403 static const struct dce_abm_shift abm_shift = {
 404                 ABM_MASK_SH_LIST_DCE110(__SHIFT)
 405 };
 406
 407 static const struct dce_abm_mask abm_mask = {
 408                 ABM_MASK_SH_LIST_DCE110(_MASK)
 409 };
 410
 411 #define CTX  ctx
 412 #define REG(reg) mm ## reg
 413
 414 #ifndef mmCC_DC_HDMI_STRAPS
 415 #define mmCC_DC_HDMI_STRAPS 0x1918
 416 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
 417 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
 418 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
 419 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
 420 #endif
 421
 422 static void read_dce_straps(
 423         struct dc_context *ctx,
 424         struct resource_straps *straps)
 425 {
 426         REG_GET_2(CC_DC_HDMI_STRAPS,
 427                         HDMI_DISABLE, &straps->hdmi_disable,
 428                         AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
 429
 430         REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
 431 }
 432
 433 static struct audio *create_audio(
 434                 struct dc_context *ctx, unsigned int inst)
 435 {
 436         return dce_audio_create(ctx, inst,
 437                         &audio_regs[inst], &audio_shift, &audio_mask);
 438 }
 439
 440 static struct timing_generator *dce80_timing_generator_create(
 441                 struct dc_context *ctx,
 442                 uint32_t instance,
 443                 const struct dce110_timing_generator_offsets *offsets)
 444 {
 445         struct dce110_timing_generator *tg110 =
 446                 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL);
 447
 448         if (!tg110)
 449                 return NULL;
 450
 451         dce80_timing_generator_construct(tg110, ctx, instance, offsets);
 452         return &tg110->base;
 453 }
 454
 455 static struct output_pixel_processor *dce80_opp_create(
 456         struct dc_context *ctx,
 457         uint32_t inst)
 458 {
 459         struct dce110_opp *opp =
 460                 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL);
 461
 462         if (!opp)
 463                 return NULL;
 464
 465         dce110_opp_construct(opp,
 466                              ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
 467         return &opp->base;
 468 }
 469
 470 struct aux_engine *dce80_aux_engine_create(
 471         struct dc_context *ctx,
 472         uint32_t inst)
 473 {
 474         struct aux_engine_dce110 *aux_engine =
 475                 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
 476
 477         if (!aux_engine)
 478                 return NULL;
 479
 480         dce110_aux_engine_construct(aux_engine, ctx, inst,
 481                                     SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
 482                                     &aux_engine_regs[inst]);
 483
 484         return &aux_engine->base;
 485 }
 486 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
 487
 488 static const struct dce_i2c_registers i2c_hw_regs[] = {
 489                 i2c_inst_regs(1),
 490                 i2c_inst_regs(2),
 491                 i2c_inst_regs(3),
 492                 i2c_inst_regs(4),
 493                 i2c_inst_regs(5),
 494                 i2c_inst_regs(6),
 495 };
 496
 497 static const struct dce_i2c_shift i2c_shifts = {
 498                 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
 499 };
 500
 501 static const struct dce_i2c_mask i2c_masks = {
 502                 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
 503 };
 504
 505 struct dce_i2c_hw *dce80_i2c_hw_create(
 506         struct dc_context *ctx,
 507         uint32_t inst)
 508 {
 509         struct dce_i2c_hw *dce_i2c_hw =
 510                 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
 511
 512         if (!dce_i2c_hw)
 513                 return NULL;
 514
 515         dce_i2c_hw_construct(dce_i2c_hw, ctx, inst,
 516                                     &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
 517
 518         return dce_i2c_hw;
 519 }
 520
 521 struct dce_i2c_sw *dce80_i2c_sw_create(
 522         struct dc_context *ctx)
 523 {
 524         struct dce_i2c_sw *dce_i2c_sw =
 525                 kzalloc(sizeof(struct dce_i2c_sw), GFP_KERNEL);
 526
 527         if (!dce_i2c_sw)
 528                 return NULL;
 529
 530         dce_i2c_sw_construct(dce_i2c_sw, ctx);
 531
 532         return dce_i2c_sw;
 533 }
 534 static struct stream_encoder *dce80_stream_encoder_create(
 535         enum engine_id eng_id,
 536         struct dc_context *ctx)
 537 {
 538         struct dce110_stream_encoder *enc110 =
 539                 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
 540
 541         if (!enc110)
 542                 return NULL;
 543
 544         dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
 545                                         &stream_enc_regs[eng_id],
 546                                         &se_shift, &se_mask);
 547         return &enc110->base;
 548 }
 549
 550 #define SRII(reg_name, block, id)\
 551         .reg_name[id] = mm ## block ## id ## _ ## reg_name
 552
 553 static const struct dce_hwseq_registers hwseq_reg = {
 554                 HWSEQ_DCE8_REG_LIST()
 555 };
 556
 557 static const struct dce_hwseq_shift hwseq_shift = {
 558                 HWSEQ_DCE8_MASK_SH_LIST(__SHIFT)
 559 };
 560
 561 static const struct dce_hwseq_mask hwseq_mask = {
 562                 HWSEQ_DCE8_MASK_SH_LIST(_MASK)
 563 };
 564
 565 static struct dce_hwseq *dce80_hwseq_create(
 566         struct dc_context *ctx)
 567 {
 568         struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
 569
 570         if (hws) {
 571                 hws->ctx = ctx;
 572                 hws->regs = &hwseq_reg;
 573                 hws->shifts = &hwseq_shift;
 574                 hws->masks = &hwseq_mask;
 575         }
 576         return hws;
 577 }
 578
 579 static const struct resource_create_funcs res_create_funcs = {
 580         .read_dce_straps = read_dce_straps,
 581         .create_audio = create_audio,
 582         .create_stream_encoder = dce80_stream_encoder_create,
 583         .create_hwseq = dce80_hwseq_create,
 584 };
 585
 586 #define mi_inst_regs(id) { \
 587         MI_DCE8_REG_LIST(id), \
 588         .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \
 589 }
 590 static const struct dce_mem_input_registers mi_regs[] = {
 591                 mi_inst_regs(0),
 592                 mi_inst_regs(1),
 593                 mi_inst_regs(2),
 594                 mi_inst_regs(3),
 595                 mi_inst_regs(4),
 596                 mi_inst_regs(5),
 597 };
 598
 599 static const struct dce_mem_input_shift mi_shifts = {
 600                 MI_DCE8_MASK_SH_LIST(__SHIFT),
 601                 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT
 602 };
 603
 604 static const struct dce_mem_input_mask mi_masks = {
 605                 MI_DCE8_MASK_SH_LIST(_MASK),
 606                 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK
 607 };
 608
 609 static struct mem_input *dce80_mem_input_create(
 610         struct dc_context *ctx,
 611         uint32_t inst)
 612 {
 613         struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
 614                                                GFP_KERNEL);
 615
 616         if (!dce_mi) {
 617                 BREAK_TO_DEBUGGER();
 618                 return NULL;
 619         }
 620
 621         dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
 622         dce_mi->wa.single_head_rdreq_dmif_limit = 2;
 623         return &dce_mi->base;
 624 }
 625
 626 static void dce80_transform_destroy(struct transform **xfm)
 627 {
 628         kfree(TO_DCE_TRANSFORM(*xfm));
 629         *xfm = NULL;
 630 }
 631
 632 static struct transform *dce80_transform_create(
 633         struct dc_context *ctx,
 634         uint32_t inst)
 635 {
 636         struct dce_transform *transform =
 637                 kzalloc(sizeof(struct dce_transform), GFP_KERNEL);
 638
 639         if (!transform)
 640                 return NULL;
 641
 642         dce_transform_construct(transform, ctx, inst,
 643                                 &xfm_regs[inst], &xfm_shift, &xfm_mask);
 644         transform->prescaler_on = false;
 645         return &transform->base;
 646 }
 647
 648 static const struct encoder_feature_support link_enc_feature = {
 649                 .max_hdmi_deep_color = COLOR_DEPTH_121212,
 650                 .max_hdmi_pixel_clock = 297000,
 651                 .flags.bits.IS_HBR2_CAPABLE = true,
 652                 .flags.bits.IS_TPS3_CAPABLE = true
 653 };
 654
 655 struct link_encoder *dce80_link_encoder_create(
 656         const struct encoder_init_data *enc_init_data)
 657 {
 658         struct dce110_link_encoder *enc110 =
 659                 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
 660
 661         if (!enc110)
 662                 return NULL;
 663
 664         dce110_link_encoder_construct(enc110,
 665                                       enc_init_data,
 666                                       &link_enc_feature,
 667                                       &link_enc_regs[enc_init_data->transmitter],
 668                                       &link_enc_aux_regs[enc_init_data->channel - 1],
 669                                       &link_enc_hpd_regs[enc_init_data->hpd_source]);
 670         return &enc110->base;
 671 }
 672
 673 struct clock_source *dce80_clock_source_create(
 674         struct dc_context *ctx,
 675         struct dc_bios *bios,
 676         enum clock_source_id id,
 677         const struct dce110_clk_src_regs *regs,
 678         bool dp_clk_src)
 679 {
 680         struct dce110_clk_src *clk_src =
 681                 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
 682
 683         if (!clk_src)
 684                 return NULL;
 685
 686         if (dce110_clk_src_construct(clk_src, ctx, bios, id,
 687                         regs, &cs_shift, &cs_mask)) {
 688                 clk_src->base.dp_clk_src = dp_clk_src;
 689                 return &clk_src->base;
 690         }
 691
 692         BREAK_TO_DEBUGGER();
 693         return NULL;
 694 }
 695
 696 void dce80_clock_source_destroy(struct clock_source **clk_src)
 697 {
 698         kfree(TO_DCE110_CLK_SRC(*clk_src));
 699         *clk_src = NULL;
 700 }
 701
 702 static struct input_pixel_processor *dce80_ipp_create(
 703         struct dc_context *ctx, uint32_t inst)
 704 {
 705         struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL);
 706
 707         if (!ipp) {
 708                 BREAK_TO_DEBUGGER();
 709                 return NULL;
 710         }
 711
 712         dce_ipp_construct(ipp, ctx, inst,
 713                         &ipp_regs[inst], &ipp_shift, &ipp_mask);
 714         return &ipp->base;
 715 }
 716
 717 static void destruct(struct dce110_resource_pool *pool)
 718 {
 719         unsigned int i;
 720
 721         for (i = 0; i < pool->base.pipe_count; i++) {
 722                 if (pool->base.opps[i] != NULL)
 723                         dce110_opp_destroy(&pool->base.opps[i]);
 724
 725                 if (pool->base.transforms[i] != NULL)
 726                         dce80_transform_destroy(&pool->base.transforms[i]);
 727
 728                 if (pool->base.ipps[i] != NULL)
 729                         dce_ipp_destroy(&pool->base.ipps[i]);
 730
 731                 if (pool->base.mis[i] != NULL) {
 732                         kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
 733                         pool->base.mis[i] = NULL;
 734                 }
 735
 736                 if (pool->base.timing_generators[i] != NULL)    {
 737                         kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
 738                         pool->base.timing_generators[i] = NULL;
 739                 }
 740         }
 741
 742         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
 743                 if (pool->base.engines[i] != NULL)
 744                         dce110_engine_destroy(&pool->base.engines[i]);
 745                 if (pool->base.hw_i2cs[i] != NULL) {
 746                         kfree(pool->base.hw_i2cs[i]);
 747                         pool->base.hw_i2cs[i] = NULL;
 748                 }
 749                 if (pool->base.sw_i2cs[i] != NULL) {
 750                         kfree(pool->base.sw_i2cs[i]);
 751                         pool->base.sw_i2cs[i] = NULL;
 752                 }
 753         }
 754
 755         for (i = 0; i < pool->base.stream_enc_count; i++) {
 756                 if (pool->base.stream_enc[i] != NULL)
 757                         kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
 758         }
 759
 760         for (i = 0; i < pool->base.clk_src_count; i++) {
 761                 if (pool->base.clock_sources[i] != NULL) {
 762                         dce80_clock_source_destroy(&pool->base.clock_sources[i]);
 763                 }
 764         }
 765
 766         if (pool->base.abm != NULL)
 767                         dce_abm_destroy(&pool->base.abm);
 768
 769         if (pool->base.dmcu != NULL)
 770                         dce_dmcu_destroy(&pool->base.dmcu);
 771
 772         if (pool->base.dp_clock_source != NULL)
 773                 dce80_clock_source_destroy(&pool->base.dp_clock_source);
 774
 775         for (i = 0; i < pool->base.audio_count; i++)    {
 776                 if (pool->base.audios[i] != NULL) {
 777                         dce_aud_destroy(&pool->base.audios[i]);
 778                 }
 779         }
 780
 781         if (pool->base.clk_mgr != NULL)
 782                 dce_clk_mgr_destroy(&pool->base.clk_mgr);
 783
 784         if (pool->base.irqs != NULL) {
 785                 dal_irq_service_destroy(&pool->base.irqs);
 786         }
 787 }
 788
 789 bool dce80_validate_bandwidth(
 790         struct dc *dc,
 791         struct dc_state *context)
 792 {
 793         int i;
 794         bool at_least_one_pipe = false;
 795
 796         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 797                 if (context->res_ctx.pipe_ctx[i].stream)
 798                         at_least_one_pipe = true;
 799         }
 800
 801         if (at_least_one_pipe) {
 802                 /* TODO implement when needed but for now hardcode max value*/
 803                 context->bw.dce.dispclk_khz = 681000;
 804                 context->bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ;
 805         } else {
 806                 context->bw.dce.dispclk_khz = 0;
 807                 context->bw.dce.yclk_khz = 0;
 808         }
 809
 810         return true;
 811 }
 812
 813 static bool dce80_validate_surface_sets(
 814                 struct dc_state *context)
 815 {
 816         int i;
 817
 818         for (i = 0; i < context->stream_count; i++) {
 819                 if (context->stream_status[i].plane_count == 0)
 820                         continue;
 821
 822                 if (context->stream_status[i].plane_count > 1)
 823                         return false;
 824
 825                 if (context->stream_status[i].plane_states[0]->format
 826                                 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
 827                         return false;
 828         }
 829
 830         return true;
 831 }
 832
 833 enum dc_status dce80_validate_global(
 834                 struct dc *dc,
 835                 struct dc_state *context)
 836 {
 837         if (!dce80_validate_surface_sets(context))
 838                 return DC_FAIL_SURFACE_VALIDATE;
 839
 840         return DC_OK;
 841 }
 842
 843 static void dce80_destroy_resource_pool(struct resource_pool **pool)
 844 {
 845         struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
 846
 847         destruct(dce110_pool);
 848         kfree(dce110_pool);
 849         *pool = NULL;
 850 }
 851
 852 static const struct resource_funcs dce80_res_pool_funcs = {
 853         .destroy = dce80_destroy_resource_pool,
 854         .link_enc_create = dce80_link_encoder_create,
 855         .validate_bandwidth = dce80_validate_bandwidth,
 856         .validate_plane = dce100_validate_plane,
 857         .add_stream_to_ctx = dce100_add_stream_to_ctx,
 858         .validate_global = dce80_validate_global
 859 };
 860
 861 static bool dce80_construct(
 862         uint8_t num_virtual_links,
 863         struct dc *dc,
 864         struct dce110_resource_pool *pool)
 865 {
 866         unsigned int i;
 867         struct dc_context *ctx = dc->ctx;
 868         struct dc_firmware_info info;
 869         struct dc_bios *bp;
 870
 871         ctx->dc_bios->regs = &bios_regs;
 872
 873         pool->base.res_cap = &res_cap;
 874         pool->base.funcs = &dce80_res_pool_funcs;
 875
 876
 877         /*************************************************
 878          *  Resource + asic cap harcoding                *
 879          *************************************************/
 880         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
 881         pool->base.pipe_count = res_cap.num_timing_generator;
 882         pool->base.timing_generator_count = res_cap.num_timing_generator;
 883         dc->caps.max_downscale_ratio = 200;
 884         dc->caps.i2c_speed_in_khz = 40;
 885         dc->caps.max_cursor_size = 128;
 886         dc->caps.dual_link_dvi = true;
 887
 888         /*************************************************
 889          *  Create resources                             *
 890          *************************************************/
 891
 892         bp = ctx->dc_bios;
 893
 894         if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
 895                 info.external_clock_source_frequency_for_dp != 0) {
 896                 pool->base.dp_clock_source =
 897                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
 898
 899                 pool->base.clock_sources[0] =
 900                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
 901                 pool->base.clock_sources[1] =
 902                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
 903                 pool->base.clock_sources[2] =
 904                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
 905                 pool->base.clk_src_count = 3;
 906
 907         } else {
 908                 pool->base.dp_clock_source =
 909                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
 910
 911                 pool->base.clock_sources[0] =
 912                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
 913                 pool->base.clock_sources[1] =
 914                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
 915                 pool->base.clk_src_count = 2;
 916         }
 917
 918         if (pool->base.dp_clock_source == NULL) {
 919                 dm_error("DC: failed to create dp clock source!\n");
 920                 BREAK_TO_DEBUGGER();
 921                 goto res_create_fail;
 922         }
 923
 924         for (i = 0; i < pool->base.clk_src_count; i++) {
 925                 if (pool->base.clock_sources[i] == NULL) {
 926                         dm_error("DC: failed to create clock sources!\n");
 927                         BREAK_TO_DEBUGGER();
 928                         goto res_create_fail;
 929                 }
 930         }
 931
 932         pool->base.clk_mgr = dce_clk_mgr_create(ctx,
 933                         &disp_clk_regs,
 934                         &disp_clk_shift,
 935                         &disp_clk_mask);
 936         if (pool->base.clk_mgr == NULL) {
 937                 dm_error("DC: failed to create display clock!\n");
 938                 BREAK_TO_DEBUGGER();
 939                 goto res_create_fail;
 940         }
 941
 942         pool->base.dmcu = dce_dmcu_create(ctx,
 943                         &dmcu_regs,
 944                         &dmcu_shift,
 945                         &dmcu_mask);
 946         if (pool->base.dmcu == NULL) {
 947                 dm_error("DC: failed to create dmcu!\n");
 948                 BREAK_TO_DEBUGGER();
 949                 goto res_create_fail;
 950         }
 951
 952         pool->base.abm = dce_abm_create(ctx,
 953                         &abm_regs,
 954                         &abm_shift,
 955                         &abm_mask);
 956         if (pool->base.abm == NULL) {
 957                 dm_error("DC: failed to create abm!\n");
 958                 BREAK_TO_DEBUGGER();
 959                 goto res_create_fail;
 960         }
 961
 962         {
 963                 struct irq_service_init_data init_data;
 964                 init_data.ctx = dc->ctx;
 965                 pool->base.irqs = dal_irq_service_dce80_create(&init_data);
 966                 if (!pool->base.irqs)
 967                         goto res_create_fail;
 968         }
 969
 970         for (i = 0; i < pool->base.pipe_count; i++) {
 971                 pool->base.timing_generators[i] = dce80_timing_generator_create(
 972                                 ctx, i, &dce80_tg_offsets[i]);
 973                 if (pool->base.timing_generators[i] == NULL) {
 974                         BREAK_TO_DEBUGGER();
 975                         dm_error("DC: failed to create tg!\n");
 976                         goto res_create_fail;
 977                 }
 978
 979                 pool->base.mis[i] = dce80_mem_input_create(ctx, i);
 980                 if (pool->base.mis[i] == NULL) {
 981                         BREAK_TO_DEBUGGER();
 982                         dm_error("DC: failed to create memory input!\n");
 983                         goto res_create_fail;
 984                 }
 985
 986                 pool->base.ipps[i] = dce80_ipp_create(ctx, i);
 987                 if (pool->base.ipps[i] == NULL) {
 988                         BREAK_TO_DEBUGGER();
 989                         dm_error("DC: failed to create input pixel processor!\n");
 990                         goto res_create_fail;
 991                 }
 992
 993                 pool->base.transforms[i] = dce80_transform_create(ctx, i);
 994                 if (pool->base.transforms[i] == NULL) {
 995                         BREAK_TO_DEBUGGER();
 996                         dm_error("DC: failed to create transform!\n");
 997                         goto res_create_fail;
 998                 }
 999
1000                 pool->base.opps[i] = dce80_opp_create(ctx, i);
1001                 if (pool->base.opps[i] == NULL) {
1002                         BREAK_TO_DEBUGGER();
1003                         dm_error("DC: failed to create output pixel processor!\n");
1004                         goto res_create_fail;
1005                 }
1006         }
1007
1008         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1009                 pool->base.engines[i] = dce80_aux_engine_create(ctx, i);
1010                 if (pool->base.engines[i] == NULL) {
1011                         BREAK_TO_DEBUGGER();
1012                         dm_error(
1013                                 "DC:failed to create aux engine!!\n");
1014                         goto res_create_fail;
1015                 }
1016                 pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i);
1017                 if (pool->base.hw_i2cs[i] == NULL) {
1018                         BREAK_TO_DEBUGGER();
1019                         dm_error(
1020                                 "DC:failed to create i2c engine!!\n");
1021                         goto res_create_fail;
1022                 }
1023                 pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx);
1024                 if (pool->base.sw_i2cs[i] == NULL) {
1025                         BREAK_TO_DEBUGGER();
1026                         dm_error(
1027                                 "DC:failed to create sw i2c!!\n");
1028                         goto res_create_fail;
1029                 }
1030         }
1031
1032         dc->caps.max_planes =  pool->base.pipe_count;
1033         dc->caps.disable_dp_clk_share = true;
1034
1035         if (!resource_construct(num_virtual_links, dc, &pool->base,
1036                         &res_create_funcs))
1037                 goto res_create_fail;
1038
1039         /* Create hardware sequencer */
1040         dce80_hw_sequencer_construct(dc);
1041
1042         return true;
1043
1044 res_create_fail:
1045         destruct(pool);
1046         return false;
1047 }
1048
1049 struct resource_pool *dce80_create_resource_pool(
1050         uint8_t num_virtual_links,
1051         struct dc *dc)
1052 {
1053         struct dce110_resource_pool *pool =
1054                 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1055
1056         if (!pool)
1057                 return NULL;
1058
1059         if (dce80_construct(num_virtual_links, dc, pool))
1060                 return &pool->base;
1061
1062         BREAK_TO_DEBUGGER();
1063         return NULL;
1064 }
1065
1066 static bool dce81_construct(
1067         uint8_t num_virtual_links,
1068         struct dc *dc,
1069         struct dce110_resource_pool *pool)
1070 {
1071         unsigned int i;
1072         struct dc_context *ctx = dc->ctx;
1073         struct dc_firmware_info info;
1074         struct dc_bios *bp;
1075
1076         ctx->dc_bios->regs = &bios_regs;
1077
1078         pool->base.res_cap = &res_cap_81;
1079         pool->base.funcs = &dce80_res_pool_funcs;
1080
1081
1082         /*************************************************
1083          *  Resource + asic cap harcoding                *
1084          *************************************************/
1085         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1086         pool->base.pipe_count = res_cap_81.num_timing_generator;
1087         pool->base.timing_generator_count = res_cap_81.num_timing_generator;
1088         dc->caps.max_downscale_ratio = 200;
1089         dc->caps.i2c_speed_in_khz = 40;
1090         dc->caps.max_cursor_size = 128;
1091         dc->caps.is_apu = true;
1092
1093         /*************************************************
1094          *  Create resources                             *
1095          *************************************************/
1096
1097         bp = ctx->dc_bios;
1098
1099         if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
1100                 info.external_clock_source_frequency_for_dp != 0) {
1101                 pool->base.dp_clock_source =
1102                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
1103
1104                 pool->base.clock_sources[0] =
1105                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
1106                 pool->base.clock_sources[1] =
1107                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
1108                 pool->base.clock_sources[2] =
1109                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
1110                 pool->base.clk_src_count = 3;
1111
1112         } else {
1113                 pool->base.dp_clock_source =
1114                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
1115
1116                 pool->base.clock_sources[0] =
1117                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
1118                 pool->base.clock_sources[1] =
1119                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
1120                 pool->base.clk_src_count = 2;
1121         }
1122
1123         if (pool->base.dp_clock_source == NULL) {
1124                 dm_error("DC: failed to create dp clock source!\n");
1125                 BREAK_TO_DEBUGGER();
1126                 goto res_create_fail;
1127         }
1128
1129         for (i = 0; i < pool->base.clk_src_count; i++) {
1130                 if (pool->base.clock_sources[i] == NULL) {
1131                         dm_error("DC: failed to create clock sources!\n");
1132                         BREAK_TO_DEBUGGER();
1133                         goto res_create_fail;
1134                 }
1135         }
1136
1137         pool->base.clk_mgr = dce_clk_mgr_create(ctx,
1138                         &disp_clk_regs,
1139                         &disp_clk_shift,
1140                         &disp_clk_mask);
1141         if (pool->base.clk_mgr == NULL) {
1142                 dm_error("DC: failed to create display clock!\n");
1143                 BREAK_TO_DEBUGGER();
1144                 goto res_create_fail;
1145         }
1146
1147         pool->base.dmcu = dce_dmcu_create(ctx,
1148                         &dmcu_regs,
1149                         &dmcu_shift,
1150                         &dmcu_mask);
1151         if (pool->base.dmcu == NULL) {
1152                 dm_error("DC: failed to create dmcu!\n");
1153                 BREAK_TO_DEBUGGER();
1154                 goto res_create_fail;
1155         }
1156
1157         pool->base.abm = dce_abm_create(ctx,
1158                         &abm_regs,
1159                         &abm_shift,
1160                         &abm_mask);
1161         if (pool->base.abm == NULL) {
1162                 dm_error("DC: failed to create abm!\n");
1163                 BREAK_TO_DEBUGGER();
1164                 goto res_create_fail;
1165         }
1166
1167         {
1168                 struct irq_service_init_data init_data;
1169                 init_data.ctx = dc->ctx;
1170                 pool->base.irqs = dal_irq_service_dce80_create(&init_data);
1171                 if (!pool->base.irqs)
1172                         goto res_create_fail;
1173         }
1174
1175         for (i = 0; i < pool->base.pipe_count; i++) {
1176                 pool->base.timing_generators[i] = dce80_timing_generator_create(
1177                                 ctx, i, &dce80_tg_offsets[i]);
1178                 if (pool->base.timing_generators[i] == NULL) {
1179                         BREAK_TO_DEBUGGER();
1180                         dm_error("DC: failed to create tg!\n");
1181                         goto res_create_fail;
1182                 }
1183
1184                 pool->base.mis[i] = dce80_mem_input_create(ctx, i);
1185                 if (pool->base.mis[i] == NULL) {
1186                         BREAK_TO_DEBUGGER();
1187                         dm_error("DC: failed to create memory input!\n");
1188                         goto res_create_fail;
1189                 }
1190
1191                 pool->base.ipps[i] = dce80_ipp_create(ctx, i);
1192                 if (pool->base.ipps[i] == NULL) {
1193                         BREAK_TO_DEBUGGER();
1194                         dm_error("DC: failed to create input pixel processor!\n");
1195                         goto res_create_fail;
1196                 }
1197
1198                 pool->base.transforms[i] = dce80_transform_create(ctx, i);
1199                 if (pool->base.transforms[i] == NULL) {
1200                         BREAK_TO_DEBUGGER();
1201                         dm_error("DC: failed to create transform!\n");
1202                         goto res_create_fail;
1203                 }
1204
1205                 pool->base.opps[i] = dce80_opp_create(ctx, i);
1206                 if (pool->base.opps[i] == NULL) {
1207                         BREAK_TO_DEBUGGER();
1208                         dm_error("DC: failed to create output pixel processor!\n");
1209                         goto res_create_fail;
1210                 }
1211         }
1212
1213         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1214                 pool->base.engines[i] = dce80_aux_engine_create(ctx, i);
1215                 if (pool->base.engines[i] == NULL) {
1216                         BREAK_TO_DEBUGGER();
1217                         dm_error(
1218                                 "DC:failed to create aux engine!!\n");
1219                         goto res_create_fail;
1220                 }
1221                 pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i);
1222                 if (pool->base.hw_i2cs[i] == NULL) {
1223                         BREAK_TO_DEBUGGER();
1224                         dm_error(
1225                                 "DC:failed to create i2c engine!!\n");
1226                         goto res_create_fail;
1227                 }
1228                 pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx);
1229                 if (pool->base.sw_i2cs[i] == NULL) {
1230                         BREAK_TO_DEBUGGER();
1231                         dm_error(
1232                                 "DC:failed to create sw i2c!!\n");
1233                         goto res_create_fail;
1234                 }
1235         }
1236
1237         dc->caps.max_planes =  pool->base.pipe_count;
1238         dc->caps.disable_dp_clk_share = true;
1239
1240         if (!resource_construct(num_virtual_links, dc, &pool->base,
1241                         &res_create_funcs))
1242                 goto res_create_fail;
1243
1244         /* Create hardware sequencer */
1245         dce80_hw_sequencer_construct(dc);
1246
1247         return true;
1248
1249 res_create_fail:
1250         destruct(pool);
1251         return false;
1252 }
1253
1254 struct resource_pool *dce81_create_resource_pool(
1255         uint8_t num_virtual_links,
1256         struct dc *dc)
1257 {
1258         struct dce110_resource_pool *pool =
1259                 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1260
1261         if (!pool)
1262                 return NULL;
1263
1264         if (dce81_construct(num_virtual_links, dc, pool))
1265                 return &pool->base;
1266
1267         BREAK_TO_DEBUGGER();
1268         return NULL;
1269 }
1270
1271 static bool dce83_construct(
1272         uint8_t num_virtual_links,
1273         struct dc *dc,
1274         struct dce110_resource_pool *pool)
1275 {
1276         unsigned int i;
1277         struct dc_context *ctx = dc->ctx;
1278         struct dc_firmware_info info;
1279         struct dc_bios *bp;
1280
1281         ctx->dc_bios->regs = &bios_regs;
1282
1283         pool->base.res_cap = &res_cap_83;
1284         pool->base.funcs = &dce80_res_pool_funcs;
1285
1286
1287         /*************************************************
1288          *  Resource + asic cap harcoding                *
1289          *************************************************/
1290         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1291         pool->base.pipe_count = res_cap_83.num_timing_generator;
1292         pool->base.timing_generator_count = res_cap_83.num_timing_generator;
1293         dc->caps.max_downscale_ratio = 200;
1294         dc->caps.i2c_speed_in_khz = 40;
1295         dc->caps.max_cursor_size = 128;
1296         dc->caps.is_apu = true;
1297
1298         /*************************************************
1299          *  Create resources                             *
1300          *************************************************/
1301
1302         bp = ctx->dc_bios;
1303
1304         if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
1305                 info.external_clock_source_frequency_for_dp != 0) {
1306                 pool->base.dp_clock_source =
1307                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
1308
1309                 pool->base.clock_sources[0] =
1310                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], false);
1311                 pool->base.clock_sources[1] =
1312                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);
1313                 pool->base.clk_src_count = 2;
1314
1315         } else {
1316                 pool->base.dp_clock_source =
1317                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], true);
1318
1319                 pool->base.clock_sources[0] =
1320                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);
1321                 pool->base.clk_src_count = 1;
1322         }
1323
1324         if (pool->base.dp_clock_source == NULL) {
1325                 dm_error("DC: failed to create dp clock source!\n");
1326                 BREAK_TO_DEBUGGER();
1327                 goto res_create_fail;
1328         }
1329
1330         for (i = 0; i < pool->base.clk_src_count; i++) {
1331                 if (pool->base.clock_sources[i] == NULL) {
1332                         dm_error("DC: failed to create clock sources!\n");
1333                         BREAK_TO_DEBUGGER();
1334                         goto res_create_fail;
1335                 }
1336         }
1337
1338         pool->base.clk_mgr = dce_clk_mgr_create(ctx,
1339                         &disp_clk_regs,
1340                         &disp_clk_shift,
1341                         &disp_clk_mask);
1342         if (pool->base.clk_mgr == NULL) {
1343                 dm_error("DC: failed to create display clock!\n");
1344                 BREAK_TO_DEBUGGER();
1345                 goto res_create_fail;
1346         }
1347
1348         pool->base.dmcu = dce_dmcu_create(ctx,
1349                         &dmcu_regs,
1350                         &dmcu_shift,
1351                         &dmcu_mask);
1352         if (pool->base.dmcu == NULL) {
1353                 dm_error("DC: failed to create dmcu!\n");
1354                 BREAK_TO_DEBUGGER();
1355                 goto res_create_fail;
1356         }
1357
1358         pool->base.abm = dce_abm_create(ctx,
1359                         &abm_regs,
1360                         &abm_shift,
1361                         &abm_mask);
1362         if (pool->base.abm == NULL) {
1363                 dm_error("DC: failed to create abm!\n");
1364                 BREAK_TO_DEBUGGER();
1365                 goto res_create_fail;
1366         }
1367
1368         {
1369                 struct irq_service_init_data init_data;
1370                 init_data.ctx = dc->ctx;
1371                 pool->base.irqs = dal_irq_service_dce80_create(&init_data);
1372                 if (!pool->base.irqs)
1373                         goto res_create_fail;
1374         }
1375
1376         for (i = 0; i < pool->base.pipe_count; i++) {
1377                 pool->base.timing_generators[i] = dce80_timing_generator_create(
1378                                 ctx, i, &dce80_tg_offsets[i]);
1379                 if (pool->base.timing_generators[i] == NULL) {
1380                         BREAK_TO_DEBUGGER();
1381                         dm_error("DC: failed to create tg!\n");
1382                         goto res_create_fail;
1383                 }
1384
1385                 pool->base.mis[i] = dce80_mem_input_create(ctx, i);
1386                 if (pool->base.mis[i] == NULL) {
1387                         BREAK_TO_DEBUGGER();
1388                         dm_error("DC: failed to create memory input!\n");
1389                         goto res_create_fail;
1390                 }
1391
1392                 pool->base.ipps[i] = dce80_ipp_create(ctx, i);
1393                 if (pool->base.ipps[i] == NULL) {
1394                         BREAK_TO_DEBUGGER();
1395                         dm_error("DC: failed to create input pixel processor!\n");
1396                         goto res_create_fail;
1397                 }
1398
1399                 pool->base.transforms[i] = dce80_transform_create(ctx, i);
1400                 if (pool->base.transforms[i] == NULL) {
1401                         BREAK_TO_DEBUGGER();
1402                         dm_error("DC: failed to create transform!\n");
1403                         goto res_create_fail;
1404                 }
1405
1406                 pool->base.opps[i] = dce80_opp_create(ctx, i);
1407                 if (pool->base.opps[i] == NULL) {
1408                         BREAK_TO_DEBUGGER();
1409                         dm_error("DC: failed to create output pixel processor!\n");
1410                         goto res_create_fail;
1411                 }
1412         }
1413
1414         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1415                 pool->base.engines[i] = dce80_aux_engine_create(ctx, i);
1416                 if (pool->base.engines[i] == NULL) {
1417                         BREAK_TO_DEBUGGER();
1418                         dm_error(
1419                                 "DC:failed to create aux engine!!\n");
1420                         goto res_create_fail;
1421                 }
1422                 pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i);
1423                 if (pool->base.hw_i2cs[i] == NULL) {
1424                         BREAK_TO_DEBUGGER();
1425                         dm_error(
1426                                 "DC:failed to create i2c engine!!\n");
1427                         goto res_create_fail;
1428                 }
1429                 pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx);
1430                 if (pool->base.sw_i2cs[i] == NULL) {
1431                         BREAK_TO_DEBUGGER();
1432                         dm_error(
1433                                 "DC:failed to create sw i2c!!\n");
1434                         goto res_create_fail;
1435                 }
1436         }
1437
1438         dc->caps.max_planes =  pool->base.pipe_count;
1439         dc->caps.disable_dp_clk_share = true;
1440
1441         if (!resource_construct(num_virtual_links, dc, &pool->base,
1442                         &res_create_funcs))
1443                 goto res_create_fail;
1444
1445         /* Create hardware sequencer */
1446         dce80_hw_sequencer_construct(dc);
1447
1448         return true;
1449
1450 res_create_fail:
1451         destruct(pool);
1452         return false;
1453 }
1454
1455 struct resource_pool *dce83_create_resource_pool(
1456         uint8_t num_virtual_links,
1457         struct dc *dc)
1458 {
1459         struct dce110_resource_pool *pool =
1460                 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1461
1462         if (!pool)
1463                 return NULL;
1464
1465         if (dce83_construct(num_virtual_links, dc, pool))
1466                 return &pool->base;
1467
1468         BREAK_TO_DEBUGGER();
1469         return NULL;
1470 }