drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c

   1 /*
   2 * Copyright 2012-15 Advanced Micro Devices, Inc.cls
   3 *
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: AMD
  24  *
  25  */
  26
  27 #include "dm_services.h"
  28
  29
  30 #include "stream_encoder.h"
  31 #include "resource.h"
  32 #include "include/irq_service_interface.h"
  33 #include "dce120_resource.h"
  34 #include "dce112/dce112_resource.h"
  35
  36 #include "dce110/dce110_resource.h"
  37 #include "../virtual/virtual_stream_encoder.h"
  38 #include "dce120_timing_generator.h"
  39 #include "irq/dce120/irq_service_dce120.h"
  40 #include "dce/dce_opp.h"
  41 #include "dce/dce_clock_source.h"
  42 #include "dce/dce_clocks.h"
  43 #include "dce/dce_ipp.h"
  44 #include "dce/dce_mem_input.h"
  45
  46 #include "dce110/dce110_hw_sequencer.h"
  47 #include "dce120/dce120_hw_sequencer.h"
  48 #include "dce/dce_transform.h"
  49
  50 #include "dce/dce_audio.h"
  51 #include "dce/dce_link_encoder.h"
  52 #include "dce/dce_stream_encoder.h"
  53 #include "dce/dce_hwseq.h"
  54 #include "dce/dce_abm.h"
  55 #include "dce/dce_dmcu.h"
  56 #include "dce/dce_aux.h"
  57 #include "dce/dce_i2c.h"
  58
  59 #include "dce/dce_12_0_offset.h"
  60 #include "dce/dce_12_0_sh_mask.h"
  61 #include "soc15_hw_ip.h"
  62 #include "vega10_ip_offset.h"
  63 #include "nbio/nbio_6_1_offset.h"
  64 #include "reg_helper.h"
  65
  66 #include "dce100/dce100_resource.h"
  67
  68 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
  69         #define mmDP0_DP_DPHY_INTERNAL_CTRL             0x210f
  70         #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
  71         #define mmDP1_DP_DPHY_INTERNAL_CTRL             0x220f
  72         #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
  73         #define mmDP2_DP_DPHY_INTERNAL_CTRL             0x230f
  74         #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
  75         #define mmDP3_DP_DPHY_INTERNAL_CTRL             0x240f
  76         #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
  77         #define mmDP4_DP_DPHY_INTERNAL_CTRL             0x250f
  78         #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
  79         #define mmDP5_DP_DPHY_INTERNAL_CTRL             0x260f
  80         #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
  81         #define mmDP6_DP_DPHY_INTERNAL_CTRL             0x270f
  82         #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
  83 #endif
  84
  85 enum dce120_clk_src_array_id {
  86         DCE120_CLK_SRC_PLL0,
  87         DCE120_CLK_SRC_PLL1,
  88         DCE120_CLK_SRC_PLL2,
  89         DCE120_CLK_SRC_PLL3,
  90         DCE120_CLK_SRC_PLL4,
  91         DCE120_CLK_SRC_PLL5,
  92
  93         DCE120_CLK_SRC_TOTAL
  94 };
  95
  96 static const struct dce110_timing_generator_offsets dce120_tg_offsets[] = {
  97         {
  98                 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
  99         },
 100         {
 101                 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
 102         },
 103         {
 104                 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
 105         },
 106         {
 107                 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
 108         },
 109         {
 110                 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
 111         },
 112         {
 113                 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
 114         }
 115 };
 116
 117 /* begin *********************
 118  * macros to expend register list macro defined in HW object header file */
 119
 120 #define BASE_INNER(seg) \
 121         DCE_BASE__INST0_SEG ## seg
 122
 123 #define NBIO_BASE_INNER(seg) \
 124         NBIF_BASE__INST0_SEG ## seg
 125
 126 #define NBIO_BASE(seg) \
 127         NBIO_BASE_INNER(seg)
 128
 129 /* compile time expand base address. */
 130 #define BASE(seg) \
 131         BASE_INNER(seg)
 132
 133 #define SR(reg_name)\
 134                 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
 135                                         mm ## reg_name
 136
 137 #define SRI(reg_name, block, id)\
 138         .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 139                                         mm ## block ## id ## _ ## reg_name
 140
 141 /* macros to expend register list macro defined in HW object header file
 142  * end *********************/
 143
 144
 145 static const struct dce_dmcu_registers dmcu_regs = {
 146                 DMCU_DCE110_COMMON_REG_LIST()
 147 };
 148
 149 static const struct dce_dmcu_shift dmcu_shift = {
 150                 DMCU_MASK_SH_LIST_DCE110(__SHIFT)
 151 };
 152
 153 static const struct dce_dmcu_mask dmcu_mask = {
 154                 DMCU_MASK_SH_LIST_DCE110(_MASK)
 155 };
 156
 157 static const struct dce_abm_registers abm_regs = {
 158                 ABM_DCE110_COMMON_REG_LIST()
 159 };
 160
 161 static const struct dce_abm_shift abm_shift = {
 162                 ABM_MASK_SH_LIST_DCE110(__SHIFT)
 163 };
 164
 165 static const struct dce_abm_mask abm_mask = {
 166                 ABM_MASK_SH_LIST_DCE110(_MASK)
 167 };
 168
 169 #define ipp_regs(id)\
 170 [id] = {\
 171                 IPP_DCE110_REG_LIST_DCE_BASE(id)\
 172 }
 173
 174 static const struct dce_ipp_registers ipp_regs[] = {
 175                 ipp_regs(0),
 176                 ipp_regs(1),
 177                 ipp_regs(2),
 178                 ipp_regs(3),
 179                 ipp_regs(4),
 180                 ipp_regs(5)
 181 };
 182
 183 static const struct dce_ipp_shift ipp_shift = {
 184                 IPP_DCE120_MASK_SH_LIST_SOC_BASE(__SHIFT)
 185 };
 186
 187 static const struct dce_ipp_mask ipp_mask = {
 188                 IPP_DCE120_MASK_SH_LIST_SOC_BASE(_MASK)
 189 };
 190
 191 #define transform_regs(id)\
 192 [id] = {\
 193                 XFM_COMMON_REG_LIST_DCE110(id)\
 194 }
 195
 196 static const struct dce_transform_registers xfm_regs[] = {
 197                 transform_regs(0),
 198                 transform_regs(1),
 199                 transform_regs(2),
 200                 transform_regs(3),
 201                 transform_regs(4),
 202                 transform_regs(5)
 203 };
 204
 205 static const struct dce_transform_shift xfm_shift = {
 206                 XFM_COMMON_MASK_SH_LIST_SOC_BASE(__SHIFT)
 207 };
 208
 209 static const struct dce_transform_mask xfm_mask = {
 210                 XFM_COMMON_MASK_SH_LIST_SOC_BASE(_MASK)
 211 };
 212
 213 #define aux_regs(id)\
 214 [id] = {\
 215         AUX_REG_LIST(id)\
 216 }
 217
 218 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
 219                 aux_regs(0),
 220                 aux_regs(1),
 221                 aux_regs(2),
 222                 aux_regs(3),
 223                 aux_regs(4),
 224                 aux_regs(5)
 225 };
 226
 227 #define hpd_regs(id)\
 228 [id] = {\
 229         HPD_REG_LIST(id)\
 230 }
 231
 232 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
 233                 hpd_regs(0),
 234                 hpd_regs(1),
 235                 hpd_regs(2),
 236                 hpd_regs(3),
 237                 hpd_regs(4),
 238                 hpd_regs(5)
 239 };
 240
 241 #define link_regs(id)\
 242 [id] = {\
 243         LE_DCE120_REG_LIST(id), \
 244         SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
 245 }
 246
 247 static const struct dce110_link_enc_registers link_enc_regs[] = {
 248         link_regs(0),
 249         link_regs(1),
 250         link_regs(2),
 251         link_regs(3),
 252         link_regs(4),
 253         link_regs(5),
 254         link_regs(6),
 255 };
 256
 257
 258 #define stream_enc_regs(id)\
 259 [id] = {\
 260         SE_COMMON_REG_LIST(id),\
 261         .TMDS_CNTL = 0,\
 262 }
 263
 264 static const struct dce110_stream_enc_registers stream_enc_regs[] = {
 265         stream_enc_regs(0),
 266         stream_enc_regs(1),
 267         stream_enc_regs(2),
 268         stream_enc_regs(3),
 269         stream_enc_regs(4),
 270         stream_enc_regs(5)
 271 };
 272
 273 static const struct dce_stream_encoder_shift se_shift = {
 274                 SE_COMMON_MASK_SH_LIST_DCE120(__SHIFT)
 275 };
 276
 277 static const struct dce_stream_encoder_mask se_mask = {
 278                 SE_COMMON_MASK_SH_LIST_DCE120(_MASK)
 279 };
 280
 281 #define opp_regs(id)\
 282 [id] = {\
 283         OPP_DCE_120_REG_LIST(id),\
 284 }
 285
 286 static const struct dce_opp_registers opp_regs[] = {
 287         opp_regs(0),
 288         opp_regs(1),
 289         opp_regs(2),
 290         opp_regs(3),
 291         opp_regs(4),
 292         opp_regs(5)
 293 };
 294
 295 static const struct dce_opp_shift opp_shift = {
 296         OPP_COMMON_MASK_SH_LIST_DCE_120(__SHIFT)
 297 };
 298
 299 static const struct dce_opp_mask opp_mask = {
 300         OPP_COMMON_MASK_SH_LIST_DCE_120(_MASK)
 301 };
 302  #define aux_engine_regs(id)\
 303 [id] = {\
 304         AUX_COMMON_REG_LIST(id), \
 305         .AUX_RESET_MASK = 0 \
 306 }
 307
 308 static const struct dce110_aux_registers aux_engine_regs[] = {
 309                 aux_engine_regs(0),
 310                 aux_engine_regs(1),
 311                 aux_engine_regs(2),
 312                 aux_engine_regs(3),
 313                 aux_engine_regs(4),
 314                 aux_engine_regs(5)
 315 };
 316
 317 #define audio_regs(id)\
 318 [id] = {\
 319         AUD_COMMON_REG_LIST(id)\
 320 }
 321
 322 static const struct dce_audio_registers audio_regs[] = {
 323         audio_regs(0),
 324         audio_regs(1),
 325         audio_regs(2),
 326         audio_regs(3),
 327         audio_regs(4),
 328         audio_regs(5)
 329 };
 330
 331 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
 332                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
 333                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
 334                 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
 335
 336 static const struct dce_audio_shift audio_shift = {
 337                 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
 338 };
 339
 340 static const struct dce_aduio_mask audio_mask = {
 341                 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
 342 };
 343
 344 #define clk_src_regs(index, id)\
 345 [index] = {\
 346         CS_COMMON_REG_LIST_DCE_112(id),\
 347 }
 348
 349 static const struct dce110_clk_src_regs clk_src_regs[] = {
 350         clk_src_regs(0, A),
 351         clk_src_regs(1, B),
 352         clk_src_regs(2, C),
 353         clk_src_regs(3, D),
 354         clk_src_regs(4, E),
 355         clk_src_regs(5, F)
 356 };
 357
 358 static const struct dce110_clk_src_shift cs_shift = {
 359                 CS_COMMON_MASK_SH_LIST_DCE_112(__SHIFT)
 360 };
 361
 362 static const struct dce110_clk_src_mask cs_mask = {
 363                 CS_COMMON_MASK_SH_LIST_DCE_112(_MASK)
 364 };
 365
 366 struct output_pixel_processor *dce120_opp_create(
 367         struct dc_context *ctx,
 368         uint32_t inst)
 369 {
 370         struct dce110_opp *opp =
 371                 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL);
 372
 373         if (!opp)
 374                 return NULL;
 375
 376         dce110_opp_construct(opp,
 377                              ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
 378         return &opp->base;
 379 }
 380 struct aux_engine *dce120_aux_engine_create(
 381         struct dc_context *ctx,
 382         uint32_t inst)
 383 {
 384         struct aux_engine_dce110 *aux_engine =
 385                 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
 386
 387         if (!aux_engine)
 388                 return NULL;
 389
 390         dce110_aux_engine_construct(aux_engine, ctx, inst,
 391                                     SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
 392                                     &aux_engine_regs[inst]);
 393
 394         return &aux_engine->base;
 395 }
 396 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
 397
 398 static const struct dce_i2c_registers i2c_hw_regs[] = {
 399                 i2c_inst_regs(1),
 400                 i2c_inst_regs(2),
 401                 i2c_inst_regs(3),
 402                 i2c_inst_regs(4),
 403                 i2c_inst_regs(5),
 404                 i2c_inst_regs(6),
 405 };
 406
 407 static const struct dce_i2c_shift i2c_shifts = {
 408                 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
 409 };
 410
 411 static const struct dce_i2c_mask i2c_masks = {
 412                 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
 413 };
 414
 415 struct dce_i2c_hw *dce120_i2c_hw_create(
 416         struct dc_context *ctx,
 417         uint32_t inst)
 418 {
 419         struct dce_i2c_hw *dce_i2c_hw =
 420                 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
 421
 422         if (!dce_i2c_hw)
 423                 return NULL;
 424
 425         dce112_i2c_hw_construct(dce_i2c_hw, ctx, inst,
 426                                     &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
 427
 428         return dce_i2c_hw;
 429 }
 430 static const struct bios_registers bios_regs = {
 431         .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 + NBIO_BASE(mmBIOS_SCRATCH_6_BASE_IDX)
 432 };
 433
 434 static const struct resource_caps res_cap = {
 435                 .num_timing_generator = 6,
 436                 .num_audio = 7,
 437                 .num_stream_encoder = 6,
 438                 .num_pll = 6,
 439                 .num_ddc = 6,
 440 };
 441
 442 static const struct dc_debug_options debug_defaults = {
 443                 .disable_clock_gate = true,
 444 };
 445
 446 struct clock_source *dce120_clock_source_create(
 447         struct dc_context *ctx,
 448         struct dc_bios *bios,
 449         enum clock_source_id id,
 450         const struct dce110_clk_src_regs *regs,
 451         bool dp_clk_src)
 452 {
 453         struct dce110_clk_src *clk_src =
 454                 kzalloc(sizeof(*clk_src), GFP_KERNEL);
 455
 456         if (!clk_src)
 457                 return NULL;
 458
 459         if (dce112_clk_src_construct(clk_src, ctx, bios, id,
 460                                      regs, &cs_shift, &cs_mask)) {
 461                 clk_src->base.dp_clk_src = dp_clk_src;
 462                 return &clk_src->base;
 463         }
 464
 465         BREAK_TO_DEBUGGER();
 466         return NULL;
 467 }
 468
 469 void dce120_clock_source_destroy(struct clock_source **clk_src)
 470 {
 471         kfree(TO_DCE110_CLK_SRC(*clk_src));
 472         *clk_src = NULL;
 473 }
 474
 475
 476 bool dce120_hw_sequencer_create(struct dc *dc)
 477 {
 478         /* All registers used by dce11.2 match those in dce11 in offset and
 479          * structure
 480          */
 481         dce120_hw_sequencer_construct(dc);
 482
 483         /*TODO  Move to separate file and Override what is needed */
 484
 485         return true;
 486 }
 487
 488 static struct timing_generator *dce120_timing_generator_create(
 489                 struct dc_context *ctx,
 490                 uint32_t instance,
 491                 const struct dce110_timing_generator_offsets *offsets)
 492 {
 493         struct dce110_timing_generator *tg110 =
 494                 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL);
 495
 496         if (!tg110)
 497                 return NULL;
 498
 499         dce120_timing_generator_construct(tg110, ctx, instance, offsets);
 500         return &tg110->base;
 501 }
 502
 503 static void dce120_transform_destroy(struct transform **xfm)
 504 {
 505         kfree(TO_DCE_TRANSFORM(*xfm));
 506         *xfm = NULL;
 507 }
 508
 509 static void destruct(struct dce110_resource_pool *pool)
 510 {
 511         unsigned int i;
 512
 513         for (i = 0; i < pool->base.pipe_count; i++) {
 514                 if (pool->base.opps[i] != NULL)
 515                         dce110_opp_destroy(&pool->base.opps[i]);
 516
 517                 if (pool->base.transforms[i] != NULL)
 518                         dce120_transform_destroy(&pool->base.transforms[i]);
 519
 520                 if (pool->base.ipps[i] != NULL)
 521                         dce_ipp_destroy(&pool->base.ipps[i]);
 522
 523                 if (pool->base.mis[i] != NULL) {
 524                         kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
 525                         pool->base.mis[i] = NULL;
 526                 }
 527
 528                 if (pool->base.irqs != NULL) {
 529                         dal_irq_service_destroy(&pool->base.irqs);
 530                 }
 531
 532                 if (pool->base.timing_generators[i] != NULL) {
 533                         kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
 534                         pool->base.timing_generators[i] = NULL;
 535                 }
 536
 537                 if (pool->base.engines[i] != NULL)
 538                         dce110_engine_destroy(&pool->base.engines[i]);
 539                 if (pool->base.hw_i2cs[i] != NULL) {
 540                         kfree(pool->base.hw_i2cs[i]);
 541                         pool->base.hw_i2cs[i] = NULL;
 542                 }
 543                 if (pool->base.sw_i2cs[i] != NULL) {
 544                         kfree(pool->base.sw_i2cs[i]);
 545                         pool->base.sw_i2cs[i] = NULL;
 546                 }
 547         }
 548
 549         for (i = 0; i < pool->base.audio_count; i++) {
 550                 if (pool->base.audios[i])
 551                         dce_aud_destroy(&pool->base.audios[i]);
 552         }
 553
 554         for (i = 0; i < pool->base.stream_enc_count; i++) {
 555                 if (pool->base.stream_enc[i] != NULL)
 556                         kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
 557         }
 558
 559         for (i = 0; i < pool->base.clk_src_count; i++) {
 560                 if (pool->base.clock_sources[i] != NULL)
 561                         dce120_clock_source_destroy(
 562                                 &pool->base.clock_sources[i]);
 563         }
 564
 565         if (pool->base.dp_clock_source != NULL)
 566                 dce120_clock_source_destroy(&pool->base.dp_clock_source);
 567
 568         if (pool->base.abm != NULL)
 569                 dce_abm_destroy(&pool->base.abm);
 570
 571         if (pool->base.dmcu != NULL)
 572                 dce_dmcu_destroy(&pool->base.dmcu);
 573
 574         if (pool->base.dccg != NULL)
 575                 dce_dccg_destroy(&pool->base.dccg);
 576 }
 577
 578 static void read_dce_straps(
 579         struct dc_context *ctx,
 580         struct resource_straps *straps)
 581 {
 582         uint32_t reg_val = dm_read_reg_soc15(ctx, mmCC_DC_MISC_STRAPS, 0);
 583
 584         straps->audio_stream_number = get_reg_field_value(reg_val,
 585                                                           CC_DC_MISC_STRAPS,
 586                                                           AUDIO_STREAM_NUMBER);
 587         straps->hdmi_disable = get_reg_field_value(reg_val,
 588                                                    CC_DC_MISC_STRAPS,
 589                                                    HDMI_DISABLE);
 590
 591         reg_val = dm_read_reg_soc15(ctx, mmDC_PINSTRAPS, 0);
 592         straps->dc_pinstraps_audio = get_reg_field_value(reg_val,
 593                                                          DC_PINSTRAPS,
 594                                                          DC_PINSTRAPS_AUDIO);
 595 }
 596
 597 static struct audio *create_audio(
 598                 struct dc_context *ctx, unsigned int inst)
 599 {
 600         return dce_audio_create(ctx, inst,
 601                         &audio_regs[inst], &audio_shift, &audio_mask);
 602 }
 603
 604 static const struct encoder_feature_support link_enc_feature = {
 605                 .max_hdmi_deep_color = COLOR_DEPTH_121212,
 606                 .max_hdmi_pixel_clock = 600000,
 607                 .ycbcr420_supported = true,
 608                 .flags.bits.IS_HBR2_CAPABLE = true,
 609                 .flags.bits.IS_HBR3_CAPABLE = true,
 610                 .flags.bits.IS_TPS3_CAPABLE = true,
 611                 .flags.bits.IS_TPS4_CAPABLE = true,
 612                 .flags.bits.IS_YCBCR_CAPABLE = true
 613 };
 614
 615 static struct link_encoder *dce120_link_encoder_create(
 616         const struct encoder_init_data *enc_init_data)
 617 {
 618         struct dce110_link_encoder *enc110 =
 619                 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
 620
 621         if (!enc110)
 622                 return NULL;
 623
 624         dce110_link_encoder_construct(enc110,
 625                                       enc_init_data,
 626                                       &link_enc_feature,
 627                                       &link_enc_regs[enc_init_data->transmitter],
 628                                       &link_enc_aux_regs[enc_init_data->channel - 1],
 629                                       &link_enc_hpd_regs[enc_init_data->hpd_source]);
 630
 631         return &enc110->base;
 632 }
 633
 634 static struct input_pixel_processor *dce120_ipp_create(
 635         struct dc_context *ctx, uint32_t inst)
 636 {
 637         struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL);
 638
 639         if (!ipp) {
 640                 BREAK_TO_DEBUGGER();
 641                 return NULL;
 642         }
 643
 644         dce_ipp_construct(ipp, ctx, inst,
 645                         &ipp_regs[inst], &ipp_shift, &ipp_mask);
 646         return &ipp->base;
 647 }
 648
 649 static struct stream_encoder *dce120_stream_encoder_create(
 650         enum engine_id eng_id,
 651         struct dc_context *ctx)
 652 {
 653         struct dce110_stream_encoder *enc110 =
 654                 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
 655
 656         if (!enc110)
 657                 return NULL;
 658
 659         dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
 660                                         &stream_enc_regs[eng_id],
 661                                         &se_shift, &se_mask);
 662         return &enc110->base;
 663 }
 664
 665 #define SRII(reg_name, block, id)\
 666         .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 667                                         mm ## block ## id ## _ ## reg_name
 668
 669 static const struct dce_hwseq_registers hwseq_reg = {
 670                 HWSEQ_DCE120_REG_LIST()
 671 };
 672
 673 static const struct dce_hwseq_shift hwseq_shift = {
 674                 HWSEQ_DCE12_MASK_SH_LIST(__SHIFT)
 675 };
 676
 677 static const struct dce_hwseq_mask hwseq_mask = {
 678                 HWSEQ_DCE12_MASK_SH_LIST(_MASK)
 679 };
 680
 681 static struct dce_hwseq *dce120_hwseq_create(
 682         struct dc_context *ctx)
 683 {
 684         struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
 685
 686         if (hws) {
 687                 hws->ctx = ctx;
 688                 hws->regs = &hwseq_reg;
 689                 hws->shifts = &hwseq_shift;
 690                 hws->masks = &hwseq_mask;
 691         }
 692         return hws;
 693 }
 694
 695 static const struct resource_create_funcs res_create_funcs = {
 696         .read_dce_straps = read_dce_straps,
 697         .create_audio = create_audio,
 698         .create_stream_encoder = dce120_stream_encoder_create,
 699         .create_hwseq = dce120_hwseq_create,
 700 };
 701
 702 #define mi_inst_regs(id) { MI_DCE12_REG_LIST(id) }
 703 static const struct dce_mem_input_registers mi_regs[] = {
 704                 mi_inst_regs(0),
 705                 mi_inst_regs(1),
 706                 mi_inst_regs(2),
 707                 mi_inst_regs(3),
 708                 mi_inst_regs(4),
 709                 mi_inst_regs(5),
 710 };
 711
 712 static const struct dce_mem_input_shift mi_shifts = {
 713                 MI_DCE12_MASK_SH_LIST(__SHIFT)
 714 };
 715
 716 static const struct dce_mem_input_mask mi_masks = {
 717                 MI_DCE12_MASK_SH_LIST(_MASK)
 718 };
 719
 720 static struct mem_input *dce120_mem_input_create(
 721         struct dc_context *ctx,
 722         uint32_t inst)
 723 {
 724         struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
 725                                                GFP_KERNEL);
 726
 727         if (!dce_mi) {
 728                 BREAK_TO_DEBUGGER();
 729                 return NULL;
 730         }
 731
 732         dce120_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
 733         return &dce_mi->base;
 734 }
 735
 736 static struct transform *dce120_transform_create(
 737         struct dc_context *ctx,
 738         uint32_t inst)
 739 {
 740         struct dce_transform *transform =
 741                 kzalloc(sizeof(struct dce_transform), GFP_KERNEL);
 742
 743         if (!transform)
 744                 return NULL;
 745
 746         dce_transform_construct(transform, ctx, inst,
 747                                 &xfm_regs[inst], &xfm_shift, &xfm_mask);
 748         transform->lb_memory_size = 0x1404; /*5124*/
 749         return &transform->base;
 750 }
 751
 752 static void dce120_destroy_resource_pool(struct resource_pool **pool)
 753 {
 754         struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
 755
 756         destruct(dce110_pool);
 757         kfree(dce110_pool);
 758         *pool = NULL;
 759 }
 760
 761 static const struct resource_funcs dce120_res_pool_funcs = {
 762         .destroy = dce120_destroy_resource_pool,
 763         .link_enc_create = dce120_link_encoder_create,
 764         .validate_bandwidth = dce112_validate_bandwidth,
 765         .validate_plane = dce100_validate_plane,
 766         .add_stream_to_ctx = dce112_add_stream_to_ctx
 767 };
 768
 769 static void bw_calcs_data_update_from_pplib(struct dc *dc)
 770 {
 771         struct dm_pp_clock_levels_with_latency eng_clks = {0};
 772         struct dm_pp_clock_levels_with_latency mem_clks = {0};
 773         struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0};
 774         int i;
 775         unsigned int clk;
 776         unsigned int latency;
 777
 778         /*do system clock*/
 779         if (!dm_pp_get_clock_levels_by_type_with_latency(
 780                                 dc->ctx,
 781                                 DM_PP_CLOCK_TYPE_ENGINE_CLK,
 782                                 &eng_clks) || eng_clks.num_levels == 0) {
 783
 784                 eng_clks.num_levels = 8;
 785                 clk = 300000;
 786
 787                 for (i = 0; i < eng_clks.num_levels; i++) {
 788                         eng_clks.data[i].clocks_in_khz = clk;
 789                         clk += 100000;
 790                 }
 791         }
 792
 793         /* convert all the clock fro kHz to fix point mHz  TODO: wloop data */
 794         dc->bw_vbios->high_sclk = bw_frc_to_fixed(
 795                 eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000);
 796         dc->bw_vbios->mid1_sclk  = bw_frc_to_fixed(
 797                 eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000);
 798         dc->bw_vbios->mid2_sclk  = bw_frc_to_fixed(
 799                 eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000);
 800         dc->bw_vbios->mid3_sclk  = bw_frc_to_fixed(
 801                 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000);
 802         dc->bw_vbios->mid4_sclk  = bw_frc_to_fixed(
 803                 eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000);
 804         dc->bw_vbios->mid5_sclk  = bw_frc_to_fixed(
 805                 eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000);
 806         dc->bw_vbios->mid6_sclk  = bw_frc_to_fixed(
 807                 eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000);
 808         dc->bw_vbios->low_sclk  = bw_frc_to_fixed(
 809                         eng_clks.data[0].clocks_in_khz, 1000);
 810
 811         /*do memory clock*/
 812         if (!dm_pp_get_clock_levels_by_type_with_latency(
 813                         dc->ctx,
 814                         DM_PP_CLOCK_TYPE_MEMORY_CLK,
 815                         &mem_clks) || mem_clks.num_levels == 0) {
 816
 817                 mem_clks.num_levels = 3;
 818                 clk = 250000;
 819                 latency = 45;
 820
 821                 for (i = 0; i < eng_clks.num_levels; i++) {
 822                         mem_clks.data[i].clocks_in_khz = clk;
 823                         mem_clks.data[i].latency_in_us = latency;
 824                         clk += 500000;
 825                         latency -= 5;
 826                 }
 827
 828         }
 829
 830         /* we don't need to call PPLIB for validation clock since they
 831          * also give us the highest sclk and highest mclk (UMA clock).
 832          * ALSO always convert UMA clock (from PPLIB)  to YCLK (HW formula):
 833          * YCLK = UMACLK*m_memoryTypeMultiplier
 834          */
 835         dc->bw_vbios->low_yclk = bw_frc_to_fixed(
 836                 mem_clks.data[0].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 1000);
 837         dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
 838                 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER,
 839                 1000);
 840         dc->bw_vbios->high_yclk = bw_frc_to_fixed(
 841                 mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER,
 842                 1000);
 843
 844         /* Now notify PPLib/SMU about which Watermarks sets they should select
 845          * depending on DPM state they are in. And update BW MGR GFX Engine and
 846          * Memory clock member variables for Watermarks calculations for each
 847          * Watermark Set
 848          */
 849         clk_ranges.num_wm_sets = 4;
 850         clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A;
 851         clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz =
 852                         eng_clks.data[0].clocks_in_khz;
 853         clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz =
 854                         eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1;
 855         clk_ranges.wm_clk_ranges[0].wm_min_mem_clk_in_khz =
 856                         mem_clks.data[0].clocks_in_khz;
 857         clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz =
 858                         mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1;
 859
 860         clk_ranges.wm_clk_ranges[1].wm_set_id = WM_SET_B;
 861         clk_ranges.wm_clk_ranges[1].wm_min_eng_clk_in_khz =
 862                         eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
 863         /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
 864         clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000;
 865         clk_ranges.wm_clk_ranges[1].wm_min_mem_clk_in_khz =
 866                         mem_clks.data[0].clocks_in_khz;
 867         clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz =
 868                         mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1;
 869
 870         clk_ranges.wm_clk_ranges[2].wm_set_id = WM_SET_C;
 871         clk_ranges.wm_clk_ranges[2].wm_min_eng_clk_in_khz =
 872                         eng_clks.data[0].clocks_in_khz;
 873         clk_ranges.wm_clk_ranges[2].wm_max_eng_clk_in_khz =
 874                         eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1;
 875         clk_ranges.wm_clk_ranges[2].wm_min_mem_clk_in_khz =
 876                         mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
 877         /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
 878         clk_ranges.wm_clk_ranges[2].wm_max_mem_clk_in_khz = 5000000;
 879
 880         clk_ranges.wm_clk_ranges[3].wm_set_id = WM_SET_D;
 881         clk_ranges.wm_clk_ranges[3].wm_min_eng_clk_in_khz =
 882                         eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
 883         /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
 884         clk_ranges.wm_clk_ranges[3].wm_max_eng_clk_in_khz = 5000000;
 885         clk_ranges.wm_clk_ranges[3].wm_min_mem_clk_in_khz =
 886                         mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
 887         /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
 888         clk_ranges.wm_clk_ranges[3].wm_max_mem_clk_in_khz = 5000000;
 889
 890         /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
 891         dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges);
 892 }
 893
 894 static uint32_t read_pipe_fuses(struct dc_context *ctx)
 895 {
 896         uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0);
 897         /* VG20 support max 6 pipes */
 898         value = value & 0x3f;
 899         return value;
 900 }
 901
 902 static bool construct(
 903         uint8_t num_virtual_links,
 904         struct dc *dc,
 905         struct dce110_resource_pool *pool)
 906 {
 907         unsigned int i;
 908         int j;
 909         struct dc_context *ctx = dc->ctx;
 910         struct irq_service_init_data irq_init_data;
 911         bool harvest_enabled = ASICREV_IS_VEGA20_P(ctx->asic_id.hw_internal_rev);
 912         uint32_t pipe_fuses;
 913
 914         ctx->dc_bios->regs = &bios_regs;
 915
 916         pool->base.res_cap = &res_cap;
 917         pool->base.funcs = &dce120_res_pool_funcs;
 918
 919         /* TODO: Fill more data from GreenlandAsicCapability.cpp */
 920         pool->base.pipe_count = res_cap.num_timing_generator;
 921         pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
 922         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
 923
 924         dc->caps.max_downscale_ratio = 200;
 925         dc->caps.i2c_speed_in_khz = 100;
 926         dc->caps.max_cursor_size = 128;
 927         dc->caps.dual_link_dvi = true;
 928         dc->caps.psp_setup_panel_mode = true;
 929
 930         dc->debug = debug_defaults;
 931
 932         /*************************************************
 933          *  Create resources                             *
 934          *************************************************/
 935
 936         pool->base.clock_sources[DCE120_CLK_SRC_PLL0] =
 937                         dce120_clock_source_create(ctx, ctx->dc_bios,
 938                                 CLOCK_SOURCE_COMBO_PHY_PLL0,
 939                                 &clk_src_regs[0], false);
 940         pool->base.clock_sources[DCE120_CLK_SRC_PLL1] =
 941                         dce120_clock_source_create(ctx, ctx->dc_bios,
 942                                 CLOCK_SOURCE_COMBO_PHY_PLL1,
 943                                 &clk_src_regs[1], false);
 944         pool->base.clock_sources[DCE120_CLK_SRC_PLL2] =
 945                         dce120_clock_source_create(ctx, ctx->dc_bios,
 946                                 CLOCK_SOURCE_COMBO_PHY_PLL2,
 947                                 &clk_src_regs[2], false);
 948         pool->base.clock_sources[DCE120_CLK_SRC_PLL3] =
 949                         dce120_clock_source_create(ctx, ctx->dc_bios,
 950                                 CLOCK_SOURCE_COMBO_PHY_PLL3,
 951                                 &clk_src_regs[3], false);
 952         pool->base.clock_sources[DCE120_CLK_SRC_PLL4] =
 953                         dce120_clock_source_create(ctx, ctx->dc_bios,
 954                                 CLOCK_SOURCE_COMBO_PHY_PLL4,
 955                                 &clk_src_regs[4], false);
 956         pool->base.clock_sources[DCE120_CLK_SRC_PLL5] =
 957                         dce120_clock_source_create(ctx, ctx->dc_bios,
 958                                 CLOCK_SOURCE_COMBO_PHY_PLL5,
 959                                 &clk_src_regs[5], false);
 960         pool->base.clk_src_count = DCE120_CLK_SRC_TOTAL;
 961
 962         pool->base.dp_clock_source =
 963                         dce120_clock_source_create(ctx, ctx->dc_bios,
 964                                 CLOCK_SOURCE_ID_DP_DTO,
 965                                 &clk_src_regs[0], true);
 966
 967         for (i = 0; i < pool->base.clk_src_count; i++) {
 968                 if (pool->base.clock_sources[i] == NULL) {
 969                         dm_error("DC: failed to create clock sources!\n");
 970                         BREAK_TO_DEBUGGER();
 971                         goto clk_src_create_fail;
 972                 }
 973         }
 974
 975         pool->base.dccg = dce120_dccg_create(ctx);
 976         if (pool->base.dccg == NULL) {
 977                 dm_error("DC: failed to create display clock!\n");
 978                 BREAK_TO_DEBUGGER();
 979                 goto dccg_create_fail;
 980         }
 981
 982         pool->base.dmcu = dce_dmcu_create(ctx,
 983                         &dmcu_regs,
 984                         &dmcu_shift,
 985                         &dmcu_mask);
 986         if (pool->base.dmcu == NULL) {
 987                 dm_error("DC: failed to create dmcu!\n");
 988                 BREAK_TO_DEBUGGER();
 989                 goto res_create_fail;
 990         }
 991
 992         pool->base.abm = dce_abm_create(ctx,
 993                         &abm_regs,
 994                         &abm_shift,
 995                         &abm_mask);
 996         if (pool->base.abm == NULL) {
 997                 dm_error("DC: failed to create abm!\n");
 998                 BREAK_TO_DEBUGGER();
 999                 goto res_create_fail;
1000         }
1001
1002
1003         irq_init_data.ctx = dc->ctx;
1004         pool->base.irqs = dal_irq_service_dce120_create(&irq_init_data);
1005         if (!pool->base.irqs)
1006                 goto irqs_create_fail;
1007
1008         /* retrieve valid pipe fuses */
1009         if (harvest_enabled)
1010                 pipe_fuses = read_pipe_fuses(ctx);
1011
1012         /* index to valid pipe resource */
1013         j = 0;
1014         for (i = 0; i < pool->base.pipe_count; i++) {
1015                 if (harvest_enabled) {
1016                         if ((pipe_fuses & (1 << i)) != 0) {
1017                                 dm_error("DC: skip invalid pipe %d!\n", i);
1018                                 continue;
1019                         }
1020                 }
1021
1022                 pool->base.timing_generators[j] =
1023                                 dce120_timing_generator_create(
1024                                         ctx,
1025                                         i,
1026                                         &dce120_tg_offsets[i]);
1027                 if (pool->base.timing_generators[j] == NULL) {
1028                         BREAK_TO_DEBUGGER();
1029                         dm_error("DC: failed to create tg!\n");
1030                         goto controller_create_fail;
1031                 }
1032
1033                 pool->base.mis[j] = dce120_mem_input_create(ctx, i);
1034
1035                 if (pool->base.mis[j] == NULL) {
1036                         BREAK_TO_DEBUGGER();
1037                         dm_error(
1038                                 "DC: failed to create memory input!\n");
1039                         goto controller_create_fail;
1040                 }
1041
1042                 pool->base.ipps[j] = dce120_ipp_create(ctx, i);
1043                 if (pool->base.ipps[i] == NULL) {
1044                         BREAK_TO_DEBUGGER();
1045                         dm_error(
1046                                 "DC: failed to create input pixel processor!\n");
1047                         goto controller_create_fail;
1048                 }
1049
1050                 pool->base.transforms[j] = dce120_transform_create(ctx, i);
1051                 if (pool->base.transforms[i] == NULL) {
1052                         BREAK_TO_DEBUGGER();
1053                         dm_error(
1054                                 "DC: failed to create transform!\n");
1055                         goto res_create_fail;
1056                 }
1057
1058                 pool->base.opps[j] = dce120_opp_create(
1059                         ctx,
1060                         i);
1061                 if (pool->base.opps[j] == NULL) {
1062                         BREAK_TO_DEBUGGER();
1063                         dm_error(
1064                                 "DC: failed to create output pixel processor!\n");
1065                 }
1066
1067                 /* check next valid pipe */
1068                 j++;
1069         }
1070
1071         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1072                 pool->base.engines[i] = dce120_aux_engine_create(ctx, i);
1073                 if (pool->base.engines[i] == NULL) {
1074                         BREAK_TO_DEBUGGER();
1075                         dm_error(
1076                                 "DC:failed to create aux engine!!\n");
1077                         goto res_create_fail;
1078                 }
1079                 pool->base.hw_i2cs[i] = dce120_i2c_hw_create(ctx, i);
1080                 if (pool->base.hw_i2cs[i] == NULL) {
1081                         BREAK_TO_DEBUGGER();
1082                         dm_error(
1083                                 "DC:failed to create i2c engine!!\n");
1084                         goto res_create_fail;
1085                 }
1086                 pool->base.sw_i2cs[i] = NULL;
1087         }
1088
1089         /* valid pipe num */
1090         pool->base.pipe_count = j;
1091         pool->base.timing_generator_count = j;
1092
1093         if (!resource_construct(num_virtual_links, dc, &pool->base,
1094                          &res_create_funcs))
1095                 goto res_create_fail;
1096
1097         /* Create hardware sequencer */
1098         if (!dce120_hw_sequencer_create(dc))
1099                 goto controller_create_fail;
1100
1101         dc->caps.max_planes =  pool->base.pipe_count;
1102
1103         bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);
1104
1105         bw_calcs_data_update_from_pplib(dc);
1106
1107         return true;
1108
1109 irqs_create_fail:
1110 controller_create_fail:
1111 dccg_create_fail:
1112 clk_src_create_fail:
1113 res_create_fail:
1114
1115         destruct(pool);
1116
1117         return false;
1118 }
1119
1120 struct resource_pool *dce120_create_resource_pool(
1121         uint8_t num_virtual_links,
1122         struct dc *dc)
1123 {
1124         struct dce110_resource_pool *pool =
1125                 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1126
1127         if (!pool)
1128                 return NULL;
1129
1130         if (construct(num_virtual_links, dc, pool))
1131                 return &pool->base;
1132
1133         BREAK_TO_DEBUGGER();
1134         return NULL;
1135 }